CN103633995A - Frequency divider circuit - Google Patents
Frequency divider circuit Download PDFInfo
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- CN103633995A CN103633995A CN201210305614.1A CN201210305614A CN103633995A CN 103633995 A CN103633995 A CN 103633995A CN 201210305614 A CN201210305614 A CN 201210305614A CN 103633995 A CN103633995 A CN 103633995A
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Abstract
The invention provides a frequency divider circuit. The frequency divider circuit comprises N triggers, N groups of switches and a controller. The output end of the ith trigger is connected with the input end of the i+1th trigger, wherein 1</=i</=N and N is a positive integer greater than or equal to 1. Each group of switch comprises a first switch and a second switch. The output end of the controller is connected with the input end of the first trigger. The input end of the controller is respectively connected with the other end of each second switch in N groups of switches, the other end of each first switch in even switch groups and the other end of each first switch in odd switch groups. The controller is used for carrying out control turn-on and turn-off selection on each second switch according to input frequency dividing parameters in a first mode, and carrying out control turn-on and turn-off selection on each first switch according to input frequency dividing parameters in a second mode. The frequency divider circuit can realize the function of frequency dividing of any positive integer, and has the advantages of simple structure and small scale.
Description
Technical field
The present invention relates to digital circuit technique field, particularly a kind of divider circuit.
Background technology
Conventionally, as shown in Figure 1, this frequency-halving circuit comprises d type flip flop 1 and inverter A to frequency-halving circuit.When initial state is 00, through two clock signal C K, state reverts to initial state, has completed the function of two divided-frequency.As shown in Figure 2, this three frequency division circuit comprises the first d type flip flop 1, the second d type flip flop 2 and NAND gate B to three frequency division circuit.When initial state is 00, the output state of the first d type flip flop 1 and the second d type flip flop 2 circulates between 10-11-01, and therefore, 10 state, reducing after three clock signal C K, has completed the function of three frequency division.And another kind of three frequency division circuit is as shown in Figure 3, to use with door C and replace NAND gate B, it realizes the function of three frequency division and the three frequency division circuit in Fig. 2 is similar.On this basis, some comparatively complicated frequency dividing circuits are successively suggested.
As shown in Figure 4, existing 2
nfrequency dividing circuit comprises n d type flip flop (1,2,3 equally ... n), and by n d type flip flop cascade to realize 2
n(n>=1) frequency division, this frequency dividing circuit can only realize 2
nfrequency division, can not realize arbitrary integer frequency division.
In addition, patent CN200710161515 also discloses a kind of arbitrary integer divider circuit, as shown in Figure 5.This divider circuit comprises frequency dividing circuit 50, control switching circuit 52, frequency division selector 503 and odd even selector 505.Wherein, frequency dividing circuit 50 is for realizing odd and even number frequency division, and control switching circuit 52 is controlled this divider circuit and carried out Fractional-N frequency or N+0.5 frequency division, and odd number or even number are decided by odd even selector 505.When selecting signal SEL to be " 0 ", input pulse CK is selected in order to control frequency division selector 503, is now even frequency division; When selecting signal SEL to be " 1 ", anti-phase input pulse CKb is selected in order to control frequency division selector 503, is now frequency division by odd integers.This divider circuit also needs two inversion clock input CK and CKb, and the link of two DFF.Yet this divider circuit is realized odd and even number frequency division by control switching circuit 52, circuit scale is large, realizes complexity, and does not have rule to follow, and is inconvenient to remember.
Therefore the shortcoming that, prior art exists is that (1) is realized the frequency dividing circuit of even number, frequency division by odd integers and often by various Programming with Pascal Language, realized, or by IC(Integrated Circuit, integrated circuit) and expanded circuit realize, implementation more complicated, circuit scale is larger; (2) the topological structure irregularities that existing fraction frequency device presents, and be inconvenient to remember and design.
Summary of the invention
Object of the present invention is intended at least solve one of above-mentioned technological deficiency.
For this reason, the object of the invention is to propose a kind of divider circuit, can realize the function of any positive integer frequency division, and circuit structure is simple, small scale.
For achieving the above object, embodiments of the invention have proposed a kind of divider circuit, comprise: N trigger, each trigger in a described N trigger comprises input, output and clock signal input terminal, and the clock signal input terminal of described each trigger is all connected, and the described output of i trigger is connected with the described input of i+1 trigger, wherein, 1≤i≤N, N is more than or equal to 1 positive integer, N organizes switch, and every group of switch in described N group switch comprises the first switch and second switch, and described the first switch in i group switch and one end of second switch are all connected with the output of described i trigger, and controller, the output of described controller is connected with the input of first trigger in a described N trigger, the first input end of described controller is connected with the other end that described N organizes the second switch in switch, the second input of described controller is connected with the other end of the first switch of even number set switch in described N group switch, the 3rd input of described controller is connected with the other end of the first switch of odd number group switch in described N group switch, described controller for selecting to control turn-on and turn-off to control all or part of the starting working in a described N trigger according to the frequency division parameter of input to the second switch of described N group switch under first mode, and according to the frequency division parameter of input, the first switch in described N group switch is selected to control turn-on and turn-off to control all or part of the starting working in a described N trigger under the second pattern.
According to the divider circuit of the embodiment of the present invention, can by the regularity of circuit topological structure, construct as required the fraction frequency device of any positive integer frequency division value, and circuit structure is simple, small scale, convenient memory.
The aspect that the present invention is additional and advantage in the following description part provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Accompanying drawing explanation
Above-mentioned and/or the additional aspect of the present invention and advantage will become from the following description of the accompanying drawings of embodiments and obviously and easily understand, wherein:
Fig. 1 is common frequency-halving circuit schematic diagram;
Fig. 2 is a kind of common three frequency division circuit diagram;
Fig. 3 is another kind of common three frequency division circuit diagram;
Fig. 4 is existing a kind of 2
nthe circuit diagram of frequency division;
Fig. 5 is the circuit diagram of existing a kind of arbitrary integer frequency division;
Fig. 6-Figure 13 is respectively the schematic diagram that frequency division value is five, seven, nine, 11,13,15,17,19 divider circuit;
Figure 14 is the universal circuit schematic diagram of odd divider;
Figure 15-Figure 23 is respectively the schematic diagram that frequency division value is four, six, eight, ten, 12,14,16,18,20 divider circuit;
Figure 24 is the universal circuit schematic diagram of even number divider;
Figure 25 A is according to the schematic diagram of the divider circuit of the embodiment of the present invention;
Figure 25 B is the schematic diagram of the divider circuit of a specific embodiment according to the present invention; And
Figure 26 is the schematic diagram of the divider circuit of an example according to the present invention.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Below by the embodiment being described with reference to the drawings, be exemplary, only for explaining the present invention, and can not be interpreted as limitation of the present invention.
Disclosing below provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts of specific examples and setting are described.Certainly, they are only example, and object does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and object clearly, itself do not indicate the relation between discussed various embodiment and/or setting.In addition, the various specific technique the invention provides and the example of material, but those of ordinary skills can recognize the property of can be applicable to of other techniques and/or the use of other materials.In addition, First Characteristic described below Second Characteristic it " on " structure can comprise that the first and second Characteristics creations are for the direct embodiment of contact, also can comprise the embodiment of other Characteristics creation between the first and second features, such the first and second features may not be direct contacts.
In description of the invention, it should be noted that, unless otherwise prescribed and limit, term " installation ", " being connected ", " connection " should be interpreted broadly, for example, can be mechanical connection or electrical connection, also can be the connection of two element internals, can be to be directly connected, and also can indirectly be connected by intermediary, for the ordinary skill in the art, can understand as the case may be the concrete meaning of above-mentioned term.
With reference to description and accompanying drawing below, these and other aspects of embodiments of the invention will be known.These describe and accompanying drawing in, specifically disclose some specific implementations in embodiments of the invention, represent to implement some modes of the principle of embodiments of the invention, still should be appreciated that the scope of embodiments of the invention is not limited.On the contrary, embodiments of the invention comprise spirit and all changes within the scope of intension, modification and the equivalent that falls into additional claims.
The divider circuit proposing according to the embodiment of the present invention is described with reference to the accompanying drawings.
As shown in Fig. 2, Fig. 6-Figure 13, frequency division value is, in three, five, seven, nine, 11,13,15,17,19 divider circuit, to include NAND gate B.Correspondingly, when frequency division value is three, as shown in Figure 2, corresponding divider circuit also comprises the first d type flip flop 1 and the second d type flip flop 2.Wherein, after being connected, the clock signal input terminal ck of the clock signal input terminal ck of the first d type flip flop 1 and the second d type flip flop 2 is jointly connected clock signal unit 100, after being connected, the Q end of the first d type flip flop 1 and the D end of the second d type flip flop 2 be jointly connected to the second input b of NAND gate B, the Q end of the second d type flip flop 2 is connected with the first input end a of NAND gate B, and the output of NAND gate B is connected with the D end of the first d type flip flop 1.The rest may be inferred, and when frequency division value is five, as shown in Figure 6, corresponding divider circuit also comprises the first d type flip flop 1, the second d type flip flop 2 and 3d flip-flop 3; When frequency division value is seven, as shown in Figure 7, corresponding divider circuit also comprises the first d type flip flop 1, the second d type flip flop 2,3d flip-flop 3 and four d flip-flop 4; When frequency division value is nine, as shown in Figure 8, corresponding divider circuit also comprises the first d type flip flop 1, the second d type flip flop 2,3d flip-flop 3, four d flip-flop 4 and the 5th d type flip flop 5; When frequency division value was ten a period of time, as shown in Figure 9, corresponding divider circuit also comprises the first d type flip flop 1, the second d type flip flop 2,3d flip-flop 3, four d flip-flop 4, the 5th d type flip flop 5 and the 6th d type flip flop 6; When frequency division value is 13, as shown in figure 10, corresponding divider circuit also comprises the first d type flip flop 1, the second d type flip flop 2,3d flip-flop 3, four d flip-flop 4, the 5th d type flip flop 5, the 6th d type flip flop 6 and the 7th d type flip flop 7; When frequency division value is 15, as shown in figure 11, corresponding divider circuit also comprises the first d type flip flop 1, the second d type flip flop 2,3d flip-flop 3, four d flip-flop 4, the 5th d type flip flop 5, the 6th d type flip flop 6, the 7th d type flip flop 7 and the 8th d type flip flop 8; When frequency division value is 17, as shown in figure 12, corresponding divider circuit also comprises the first d type flip flop 1, the second d type flip flop 2,3d flip-flop 3, four d flip-flop 4, the 5th d type flip flop 5, the 6th d type flip flop 6, the 7th d type flip flop 7, the 8th d type flip flop 8 and the 9th d type flip flop 9; When frequency division value is 19, as shown in figure 13, corresponding divider circuit also comprises the first d type flip flop 1, the second d type flip flop 2,3d flip-flop 3, four d flip-flop 4, the 5th d type flip flop 5, the 6th d type flip flop 6, the 7th d type flip flop 7, the 8th d type flip flop 8, the 9th d type flip flop 9 and the tenth d type flip flop 10.Therefore, according to above-mentioned topological structure rule, can conclude the universal architecture that has summed up odd divider, as shown in figure 14, frequency division value=3+2 (n-2)=2n-1, wherein, n >=2, n is the number of the d type flip flop of frequency divider cascade.
Wherein, when n=2, frequency division value equals three, and as shown in Figure 2, the operation principle of this divider circuit is as follows:
The Q that supposes initial state the first d type flip flop 1 holds the Q end that is output as the ' 0 ', second d type flip flop 2 to be output as ' 0 ', and like this, the input of the D of the first d type flip flop end is exactly ' 1 '; After the upper edge of first clock signal C K is come, the Q end that the Q end of the first d type flip flop 1 is output as the ' 1 ', second d type flip flop 2 is output as ' 0 ', and like this, it is exactly ' 1 ' that the D of the first d type flip flop 1 end is inputted; After the upper edge of second clock signal C K is come, the Q end that the Q end of the first d type flip flop 1 is output as the ' 1 ', second d type flip flop 2 is output as ' 1 ', and like this, it is exactly ' 0 ' that the D of the first d type flip flop 1 end is inputted; After the upper edge of the 3rd clock signal C K is come, the Q end that the Q end of the first d type flip flop 1 is output as the ' 0 ', second d type flip flop 2 is output as ' 1 ', and like this, it is exactly ' 1 ' that the D of the first d type flip flop 1 end is inputted; After the upper edge of the 4th clock signal C K is come, the Q end that the Q end of the first d type flip flop 1 is output as the ' 1 ', second d type flip flop 2 is output as ' 0 ', and like this, it is exactly ' 1 ' that the D of the first d type flip flop 1 end is inputted.So at this moment can find out, after three clock signal C K, the Q that the Q of the first d type flip flop 1 end is output as the ' 1 ', second d type flip flop 2 holds the D that is output as the ' 0 ', first d type flip flop 1 to hold ' 1 ' the state exactly of inputting to reappear.That is to say, this circuit is the circuit of three frequency division, and the output state of the Q end of its first d type flip flop 1 and the Q end of the second d type flip flop is as shown in table 1 below.
Table 1
| The Q end of the first d |
The Q end of the second d |
|
| |
0 | 0 |
| The upper edge of clock signal C K | 1 | 0 |
| The upper edge of clock signal C K | 1 | 1 |
| The upper edge of clock signal C K | 0 | 1 |
| The upper edge of |
1 | 0 |
Therefore, as can be seen from Table 1, when initial state is 00, the output state of the first d type flip flop 1 and the second d type flip flop 2 circulates between 10-11-01, and 10 state, reducing after three clock signal C K, has completed the function of three frequency division.Be understandable that, when initial state is worth for other, it is also the same analyzing.
Certainly, the rest may be inferred, when frequency division value is other numerical value for example five, seven ..., the operation principle of corresponding divider circuit is also to analyze as described above, this is no longer going to repeat them.
As shown in Fig. 1, Figure 15-Figure 23, frequency division value is, in two, four, six, eight, ten, 12,14,16,18,20 divider circuit, to include inverter A.Correspondingly, when frequency division value is two, as shown in Figure 1, corresponding divider circuit also comprises the first d type flip flop 1.Wherein, the clock signal input terminal ck of the first d type flip flop 1 is connected with clock signal unit 100, and the Q end of the first d type flip flop 1 is connected with the input of inverter A, and the D end of the first d type flip flop 1 is connected with the output of inverter A.The rest may be inferred, and when frequency division value is four, as shown in figure 15, corresponding divider circuit also comprises the first d type flip flop 1 and the second d type flip flop 2; When frequency division value is six, as shown in figure 16, corresponding divider circuit also comprises the first d type flip flop 1, the second d type flip flop 2 and 3d flip-flop 3; When frequency division value is eight, as shown in figure 17, corresponding divider circuit also comprises the first d type flip flop 1, the second d type flip flop 2,3d flip-flop 3 and four d flip-flop 4; When frequency division value is ten, as shown in figure 18, corresponding divider circuit also comprises the first d type flip flop 1, the second d type flip flop 2,3d flip-flop 3, four d flip-flop 4 and the 5th d type flip flop 5; When frequency division value is 12, as shown in figure 19, corresponding divider circuit also comprises the first d type flip flop 1, the second d type flip flop 2,3d flip-flop 3, four d flip-flop 4, the 5th d type flip flop 5 and the 6th d type flip flop 6; When frequency division value is 14, as shown in figure 20, corresponding divider circuit also comprises the first d type flip flop 1, the second d type flip flop 2,3d flip-flop 3, four d flip-flop 4, the 5th d type flip flop 5, the 6th d type flip flop 6 and the 7th d type flip flop 7; When frequency division value is 16, as shown in figure 21, corresponding divider circuit also comprises the first d type flip flop 1, the second d type flip flop 2,3d flip-flop 3, four d flip-flop 4, the 5th d type flip flop 5, the 6th d type flip flop 6, the 7th d type flip flop 7 and the 8th d type flip flop 8; When frequency division value is 18, as shown in figure 22, corresponding divider circuit also comprises the first d type flip flop 1, the second d type flip flop 2,3d flip-flop 3, four d flip-flop 4, the 5th d type flip flop 5, the 6th d type flip flop 6, the 7th d type flip flop 7, the 8th d type flip flop 8 and the 9th d type flip flop 9; When frequency division value is 20, as shown in figure 23, corresponding divider circuit also comprises the first d type flip flop 1, the second d type flip flop 2,3d flip-flop 3, four d flip-flop 4, the 5th d type flip flop 5, the 6th d type flip flop 6, the 7th d type flip flop 7, the 8th d type flip flop 8 and the 9th d type flip flop 9 and the tenth d type flip flop 10.Therefore, according to above-mentioned topological structure rule, can conclude the universal architecture that has summed up even number divider, as shown in figure 24, frequency division value=2n, wherein, n >=1, n is the number of the d type flip flop of frequency divider cascade.
Wherein, when n=1, frequency division value equals two, and as shown in Figure 1, the operation principle of this divider circuit is as follows:
First the Q end of supposing initial state the first d type flip flop 1 is output as ' 0 ', and like this, the input of the D of the first d type flip flop 1 end is exactly ' 1 '; After the upper edge of first clock signal C K is come, the Q end of the first d type flip flop 1 is output as ' 1 ', and like this, the input of the D of the first d type flip flop 1 end is exactly ' 0 '; After the upper edge of second clock signal C K is come, the Q end of the first d type flip flop 1 is output as ' 0 ', and like this, the input of the D of the first d type flip flop 1 end is exactly ' 1 '.So can draw, through two clock signal C K, the state of the first d type flip flop 1 is got back to initial state, so completed the function of two divided-frequency, the state of the first d type flip flop 1 is as shown in table 2 below.
Table 2
| The Q end state of the first d |
The D end state of the first d |
|
| |
0 | 1 |
| The upper edge of |
1 | 0 |
| The upper edge of |
0 | 1 |
Therefore, as can be seen from Table 1, when initial state is 01, through two clock signal C K, state reverts to initial state, has completed the function of two divided-frequency.Be understandable that, when initial state is worth for other, it is also the same analyzing.
Similarly, certainly, the rest may be inferred, when frequency division value is other numerical value for example four, six ..., the operation principle of corresponding divider circuit is also to analyze as described above, this is no longer going to repeat them.
Based on the above-mentioned analysis to the circuit of the circuit of odd divider and even number divider, the divider circuit that the embodiment of the present invention proposes, switch and the control of some gate circuits by one group of necessity combine the universal architecture of the universal architecture of odd divider and even number divider, can realize easily programmable frequency divider.As shown in Figure 25 A, the divider circuit that the embodiment of the present invention proposes comprises N trigger (1,2,3 ... n), N group switch 200 and controller 300.
Wherein, N trigger (1,2,3 ... n) each trigger in comprises input D end, output Q end and clock signal input terminal ck end, and the clock signal input terminal ck of each trigger end is all connected to one, the output Q end of i trigger is connected with the input D end of i+1 trigger, wherein, 1≤i≤N, N is more than or equal to 1 positive integer.And, every group of switch in N group switch 200 comprises the first switch (S1_1, S2_1, S3_1 ... Sn_1) and second switch (S1_2, S2_2, S3_2 ... Sn_2), the first switches Si _ 1 and in i group switch and one end of second switch Si_2 are all connected with the output Q end of i trigger.The output of a controller 300 and N trigger (1, 2, 3 ... the input D end of first trigger 1 n) is connected, and the first input end a ' of controller 300 and N organize the second switch (S1_2 in switch 200, S2_2, S3_2 ... Sn_2) the other end is connected, the first switch (S2_1 of even number set switch in the second input b ' of controller 300 and N group switch 200, S4_1, S6_1 ...) the other end be connected, the first switch (S1_1 of odd number group switch in the 3rd input c ' of controller 300 and N group switch 200, S3_1, S5_1 ...) the other end be connected, controller 300 for being the second switch (S1_2 of frequency division value to N group switch 200 according to the frequency division parameter of input under first mode, S2_2, S3_2 ... Sn2) select to control turn-on and turn-off to control N trigger (1, 2, 3 ... n) all or part of the starting working in, and according to the frequency division parameter of input, N is organized to the first switch (S1_1 in switch 200 under the second pattern, S2_1, S3_1 ... Sn_1) select to control turn-on and turn-off to control N trigger (1, 2, 3 ... n) all or part of the starting working in, thus can realize any even number and any function of frequency division by odd integers.
Wherein, described first mode is even frequency division pattern, and described the second pattern is frequency division by odd integers pattern.
In one embodiment of the invention, as shown in Figure 25 B, controller 300 comprises inverter A and the 3rd switch S
even.Wherein, the input of inverter A (being the first input end a ' of controller 300) is organized second switch (S1_2, S2_2, the S3_2 in switch 200 with N respectively ... Sn_2) the other end is connected, the 3rd switch S
evenone end be connected with the output of inverter A, the 3rd switch S
eventhe input D end of the other end and first trigger 1 be connected, and pass through the 3rd switch S
evenselection enters even frequency division pattern.
In this embodiment, as shown in Figure 25 B, controller 300 also comprises NAND gate B and the 4th switch S
odd.Wherein, the first input end of NAND gate B (being the second input b ' of controller 300) is organized respectively the first switch (S2_1, S4_1, the S6_1 of even number set switch in switch 200 with N ...) the other end be connected, the second input of NAND gate B (being the 3rd input c ' of controller 300) is organized respectively the first switch (S1_1, S3_1, the S5_1 of odd number group switch in switch 200 with N ...) the other end be connected, the 4th switch S
oddone end be connected with the output of NAND gate B, the 4th switch S
oddthe input D end of the other end and first trigger 1 be connected, by the 4th switch S
oddselection enters frequency division by odd integers pattern.
Be understandable that, in embodiments of the present invention, controller 300 can be single-chip microcomputer or MCU(Micro Control Unit, micro-control unit) etc., also comprise control section (not shown), for controlling N group switch 200, the 3rd switch S
evenwith the 4th switch S
oddturn-on and turn-off correspondingly, thus realize any odd number and the frequency division of even number arbitrarily.
In one embodiment of the invention, as shown in Figure 25 A and Figure 25 B, described divider circuit also comprises clock signal unit 100.Clock signal unit 100 is connected with the clock signal input terminal ck end of each trigger respectively, for to each trigger input clock pulse control signal,, after arriving in the upper edge of each clock pulse control signal, controls trigger and overturns.
In an embodiment of the present invention, described trigger is d type flip flop.
That is to say, according to actual needs, controller 300 is controlled closed correct switch just can realize the frequency division of any positive integer.When needs frequency division by odd integers, the 4th switch S
oddthis odd number feedback network of controlling is opened, then the first switch (S1_1, S2_1, the S3_1 based in the closed N group of frequency division by odd integers circuit rule choose reasonable switch 200 ... Sn_1); When needs even frequency division is the 3rd switch S
eventhis even number feedback network of controlling is opened, then second switch (S1_2, S2_2, the S3_2 based in the closed N group of even frequency division circuit rule choose reasonable switch 200 ... Sn_2).
In an example of the present invention, as shown in figure 26, by the closed and disconnected correspondingly of four switch e, f, g, h in control chart, just can complete the selection of frequency division value 2,3,4.When switch h and e closure, other switches disconnect, and are frequency-halving circuits, have completed the function of two divided-frequency; When switch f is closed, other switches disconnect, and are three frequency division circuit, have completed the function of three frequency division; When switch g and e closure, other switches disconnect, and are divide by four circuits, have completed the function of four frequency divisions.
According to the divider circuit of the embodiment of the present invention, can by the regularity of circuit topological structure, construct as required the fraction frequency device of any positive integer frequency division value, and circuit structure is simple, small scale, convenient memory.
In addition, each functional unit in each embodiment of the present invention can be integrated in a processing module, can be also that the independent physics of unit exists, and also can be integrated in a module two or more unit.Above-mentioned integrated module both can adopt the form of hardware to realize, and also can adopt the form of software function module to realize.If described integrated module usings that the form of software function module realizes and during as production marketing independently or use, also can be stored in a computer read/write memory medium.
The above-mentioned storage medium of mentioning can be read-only memory, disk or CD etc.
In the description of this specification, the description of reference term " embodiment ", " some embodiment ", " example ", " concrete example " or " some examples " etc. means to be contained at least one embodiment of the present invention or example in conjunction with specific features, structure, material or the feature of this embodiment or example description.In this manual, the schematic statement of above-mentioned term is not necessarily referred to identical embodiment or example.And the specific features of description, structure, material or feature can be with suitable mode combinations in any one or more embodiment or example.
Although illustrated and described embodiments of the invention, for the ordinary skill in the art, be appreciated that without departing from the principles and spirit of the present invention and can carry out multiple variation, modification, replacement and modification to these embodiment, scope of the present invention is by claims and be equal to and limit.
Claims (6)
1. a divider circuit, is characterized in that, comprising:
N trigger, each trigger in a described N trigger comprises input, output and clock signal input terminal, and the clock signal input terminal of described each trigger is all connected, the described output of i trigger is connected with the described input of i+1 trigger, wherein, 1≤i≤N, N is more than or equal to 1 positive integer;
N organizes switch, and every group of switch in described N group switch comprises the first switch and second switch, and described the first switch in i group switch and one end of second switch are all connected with the output of described i trigger; And
Controller, the output of described controller is connected with the input of first trigger in a described N trigger, the first input end of described controller is connected with the other end that described N organizes the second switch in switch, the second input of described controller is connected with the other end of the first switch of even number set switch in described N group switch, the 3rd input of described controller is connected with the other end of the first switch of odd number group switch in described N group switch, described controller for selecting to control turn-on and turn-off to control all or part of the starting working in a described N trigger according to the frequency division parameter of input to the second switch of described N group switch under first mode, and according to the frequency division parameter of input, the first switch in described N group switch is selected to control turn-on and turn-off to control all or part of the starting working in a described N trigger under the second pattern.
2. divider circuit as claimed in claim 1, is characterized in that, described first mode is even frequency division pattern, and described the second pattern is frequency division by odd integers pattern.
3. divider circuit as claimed in claim 2, is characterized in that, described controller comprises:
Inverter, the input of described inverter is connected with the other end of second switch in described N group switch respectively;
The 3rd switch, described the 3rd one end of switch and the output of described inverter are connected, and described the 3rd other end of switch and the input of described first trigger are connected, and by described the 3rd switch, select to enter described even frequency division pattern.
4. divider circuit as claimed in claim 3, is characterized in that, described controller also comprises:
NAND gate, the first input end of described NAND gate is connected with the other end of the first switch of even number set switch in described N group switch respectively, and the other end that the second input of described NAND gate is organized the first switch of odd number group switch in switch with described N is respectively connected;
The 4th switch, described the 4th one end of switch and the output of described NAND gate are connected, and described the 4th other end of switch and the input of described first trigger are connected, and by described the 4th switch, select to enter described frequency division by odd integers pattern.
5. divider circuit as claimed in claim 1, is characterized in that, also comprises:
Clock signal unit, described clock signal unit is connected with the clock signal input terminal of described each trigger respectively, for to described each trigger input clock pulse control signal.
6. the divider circuit as described in claim 1-5 any one, is characterized in that, described trigger is d type flip flop.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210305614.1A CN103633995A (en) | 2012-08-24 | 2012-08-24 | Frequency divider circuit |
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| CN106559073A (en) * | 2016-11-25 | 2017-04-05 | 上海华力微电子有限公司 | A kind of low-power consumption output frequency divider for being applied to PLL |
| CN108964454A (en) * | 2017-05-17 | 2018-12-07 | 中芯国际集成电路制造(上海)有限公司 | DC-DC conversion circuitry and forming method thereof |
| CN117081581A (en) * | 2023-08-18 | 2023-11-17 | 上海奎芯集成电路设计有限公司 | Synchronous nine-frequency-division circuit and nine-frequency-division signal generation method |
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| CN106559073A (en) * | 2016-11-25 | 2017-04-05 | 上海华力微电子有限公司 | A kind of low-power consumption output frequency divider for being applied to PLL |
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| CN117081581A (en) * | 2023-08-18 | 2023-11-17 | 上海奎芯集成电路设计有限公司 | Synchronous nine-frequency-division circuit and nine-frequency-division signal generation method |
| CN117081581B (en) * | 2023-08-18 | 2024-03-22 | 上海奎芯集成电路设计有限公司 | Synchronous nine-frequency-division circuit and nine-frequency-division signal generation method |
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