CN109088622B - Circuit and method for fine-granularity delay output control - Google Patents
Circuit and method for fine-granularity delay output control Download PDFInfo
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- CN109088622B CN109088622B CN201810868335.3A CN201810868335A CN109088622B CN 109088622 B CN109088622 B CN 109088622B CN 201810868335 A CN201810868335 A CN 201810868335A CN 109088622 B CN109088622 B CN 109088622B
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- 238000000034 method Methods 0.000 title claims description 11
- 238000002347 injection Methods 0.000 claims abstract description 50
- 239000007924 injection Substances 0.000 claims abstract description 50
- 230000001360 synchronised effect Effects 0.000 claims abstract description 7
- 238000002955 isolation Methods 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 230000005540 biological transmission Effects 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 230000003111 delayed effect Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 6
- 239000000243 solution Substances 0.000 description 4
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/131—Digitally controlled
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00058—Variable delay controlled by a digital setting
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Nonlinear Science (AREA)
- Pulse Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention provides a circuit for controlling fine granularity delay output, which is characterized by comprising a REGISTER group REGISTER, a delay injection unit chain formed by cascading equal delay injection units TDO_CELL, an analog interpolation circuit INTERPLATE and a LATCH LATCH; the REGISTER group REGISTER is used for receiving a digital circuit control signal C_IN and a system synchronous clock clk, converting an input single-ended signal into a differential signal and sending the differential signal to a delay injection unit chain formed by cascading equal delay injection units TDO_CELL; the delay injection unit chain is used for finally outputting a delay signal I0/IB0, and meanwhile, the finally output delay signal I0/IB0 is subjected to one-stage delay injection unit to form a delay signal I1/IB1; the analog interpolation circuit INTERPLATE is configured to receive the delay signal I0/IB0 and the delay signal I1/IB1, divide the analog signals with N fine granularity phases according to the delay signals I0/IB0 and the delay signals I1/IB1, and select one signal from the N analog signals to output under the control of the P signal.
Description
Technical Field
The invention relates to the field of high-precision output time event signal control, in particular to a circuit and a method for fine-granularity delay output control.
Background
And circuits (DIE) which are arranged on the same silicon chip are arranged in the process consistency range, and the same units have consistent running environment temperature and power supply voltage, so that after the units with better output isolation characteristics are cascaded, the delay injection unit chain with equal difference delay can be obtained by controlling the layout and the wiring length. By choosing at which stage the signal change is injected, the corresponding delayed signal change can be seen at the final output stage. By selecting the injection point, the output delay can be controlled at the granularity of Δt.
On the basis, the method is further, N subdivision phases are obtained by carrying out resistance voltage division output on the last two adjacent taps, N subdivision phase signals are selected, and finer time phase output than that of a single-stage tap can be obtained, and the step is called analog interpolation.
Disclosure of Invention
The invention discloses a circuit and a method for controlling fine granularity delay output, which realize coarse granularity output delay control by delta t granularity control by selecting injection points of delay injection unit chains with equal difference delay on the same silicon wafer, and divide delta t into N fine granularity phases approximately by an N-phase analog difference technology on the basis of the output to select and output.
The invention solves the problems by adopting the following technical scheme: the circuit for controlling the fine-granularity delay output is characterized by comprising a REGISTER group REGISTER, a delay injection unit chain formed by cascading equal delay injection units TDO_CELL, an analog interpolation circuit INTERPLATE and a LATCH LATCH; the REGISTER group REGISTER is used for receiving a digital circuit control signal C_IN and a system synchronous clock clk, converting an input single-ended signal into a differential signal and sending the differential signal to a delay injection unit chain formed by cascading equal delay injection units TDO_CELL; the delay injection unit chain is used for finally outputting a delay signal I0/IB0, and meanwhile, the finally output delay signal I0/IB0 is subjected to one-stage delay injection unit to form a delay signal I1/IB1; the analog interpolation circuit INTERPLATE is configured to receive the delay signal I0/IB0 and the delay signal I1/IB1, divide the analog signals of the N fine granularity phases according to the I0/IB0 and the I1/IB1, and control the P signal to select one signal from the N analog signals for outputting;
the signal which is controlled by the P signal and is output by selecting one signal from the N analog signals can be output into a LATCH LATCH to be latched through the LATCH indication LATCH_EN control in a holding stage, and a front-stage circuit can act to achieve other purposes in the latching stage.
Further, the pre-stage circuit may act to achieve other objectives such as parameter learning and training in conjunction with the timing of the feedback signal FB.
Furthermore, the delay injection unit TDO_CELL adopts a symmetrical analog differential circuit, the input end adopts transmission gate combination and other delay forward or reverse gating, and the output end adopts an inverting amplifier for isolation.
Furthermore, the analog interpolation circuit INTERPLATE adopts a symmetrical analog differential circuit, wherein two positive arms and two negative arms of two groups of input taps are respectively divided by series resistors, and the divided voltages enter a selector after being matched by resistors, are controlled and selected by P signals, and are sent to an inverting amplifier for isolation. The analog interpolation circuit INTERPLATE includes an inverting analog interpolation circuit and a following analog interpolation circuit, which are distinguished in that the last stage of the inverting analog interpolation circuit employs an inverting amplifier, and the following analog interpolation circuit employs a follower, which have opposite levels, but can achieve the purpose of marking an output event with an edge.
Further, the delay signal I/IB is typically set to a fixed value: i=0, ib=1; inputs C and CB of the delay injection unit tdo_cell between two inputs of the analog interpolation circuit INTERPLATE are typically set to fixed values: c=0, cb=1.
The invention provides a fine granularity delay output control method which is characterized by comprising the following steps of:
A. the digital circuit control signal C_IN and the system synchronous clock clk are input into a REGISTER group REGISTER;
B. the REGISTER group REGISTER converts an input single-ended signal into a differential signal and sends the differential signal to a delay injection unit chain formed by cascading equal delay injection units TDO_CELL;
C. the delay injection unit chain finally outputs a delay signal I0/IB0 to the analog interpolation circuit INTERPLATE, and simultaneously, the delay signal I1/IB1 of the first-stage delay injection unit is sent to the analog interpolation circuit INTERPLATE;
D. the analog interpolation circuit INTERPLATE divides the analog signals of the N fine granularity phases according to the I0/IB0 and the I1/IB1, and selects one signal from the N analog signals to output under the control of the P signal.
Further, in the step D, the output signal may be output to the LATCH through the LATCH indication latch_en control in the hold stage, and the pre-stage circuit may be operated to achieve other purposes in the LATCH stage.
Further, the pre-stage circuit may act to achieve other objectives such as parameter learning and training in conjunction with the timing of the feedback signal FB.
Compared with the prior art, the invention has the following advantages:
(1) Providing a fine granularity delay output control, wherein the granularity can reach ps and 10ps levels;
(2) Can be realized with lower cost and can be replicated in large quantity in the CMOS process;
(3) The invention can be used for real-time learning and calibration according to specific application by combining external control.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a circuit block diagram of fine granularity delay output control.
Fig. 2 is a schematic circuit diagram of the delay injection unit tdo_cell.
FIG. 3 is a schematic diagram of an inverse analog interpolation circuit.
Fig. 4 is a schematic diagram of a follow-up analog interpolation circuit.
Fig. 5 is a schematic diagram of delay injection unit delay control.
Fig. 6 simulates a timing diagram of interpolation unit delay control.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1.
As shown in fig. 1 to 5, the circuit for fine-granularity delay output control in the embodiment of the present invention includes a REGISTER set REGISTER, a delay injection unit chain composed of equal delay injection units tdo_cell cascade, an analog interpolation circuit INTERPLATE, and a LATCH.
The REGISTER set REGISTER is used for receiving a digital circuit control signal C_IN and a system synchronous clock clk, converting an input single-ended signal into a differential signal, and sending the differential signal to a delay injection unit chain formed by cascading equal delay injection units TDO_CELL.
The delay injection unit chain is used for finally outputting a delay signal I0/IB0, and meanwhile, the finally output delay signal I0/IB0 is subjected to one-stage delay injection unit to form a delay signal I1/IB1.
The analog interpolation circuit INTERPLATE is configured to receive the delay signal I0/IB0 and the delay signal I1/IB1, divide the analog signals with N fine granularity phases according to the delay signals I0/IB0 and the delay signals I1/IB1, and select one signal from the N analog signals to output under the control of the P signal.
The signal which is controlled by the P signal and is output by selecting one signal from the N analog signals can be output into a LATCH LATCH to be latched through the LATCH indication LATCH_EN control in a holding stage, and a front-stage circuit can act to achieve other purposes in the latching stage.
The pre-stage circuit may act to achieve other purposes, such as parameter learning and training in conjunction with feedback signal FB timing.
The delay injection unit TDO_CELL adopts a symmetrical analog differential circuit, the input end adopts transmission gate combination and other delay forward or reverse gating, and the output end adopts an inverting amplifier for isolation.
The analog interpolation circuit INTERPLATE adopts a symmetrical analog differential circuit, two positive arms and two negative arms of two groups of input taps are divided by series resistors respectively, the divided voltages enter a selector after being matched by resistors, and the selection is controlled by a P signal and sent to an inverting amplifier for isolation. The analog interpolation circuit INTERPLATE is divided into an inverting analog interpolation circuit and a following analog interpolation circuit, wherein the difference is that the last stage of the inverting analog interpolation circuit adopts an inverting amplifier, and the following analog interpolation circuit adopts a follower, and the two stages are opposite in level, but the purpose of marking an output event by using an edge can be achieved.
The delay signal I/IB is typically set to a fixed value: i=0, ib=1; inputs C and CB of the delay injection unit tdo_cell between two inputs of the analog interpolation circuit INTERPLATE are typically set to fixed values: c=0, cb=1.
The embodiment provides a method for controlling fine granularity delay output, which is characterized by comprising the following steps:
A. the digital circuit control signal C_IN and the system synchronous clock clk are input into a REGISTER group REGISTER;
B. the REGISTER group REGISTER converts an input single-ended signal into a differential signal and sends the differential signal to a delay injection unit chain formed by cascading equal delay injection units TDO_CELL;
C. the delay injection unit chain finally outputs a delay signal I0/IB0 to the analog interpolation circuit INTERPLATE, and simultaneously, the delay signal I1/IB1 of the first-stage delay injection unit is sent to the analog interpolation circuit INTERPLATE;
D. the analog interpolation circuit INTERPLATE divides the analog signals of the N fine granularity phases according to the I0/IB0 and the I1/IB1, and selects one signal from the N analog signals to output under the control of the P signal.
In the step D, the output signal may be output to the LATCH by the LATCH instruction latch_en control in the hold stage, and the pre-stage circuit may be operated to achieve other purposes in the LATCH stage.
The pre-stage circuit may act to achieve other purposes, such as parameter learning and training in conjunction with feedback signal FB timing.
It should be noted that the above detailed description of the technical solution of the present invention by means of the preferred embodiments is illustrative and not restrictive. Modifications and substitutions of some technical features of the embodiments described in the embodiments may be made by those skilled in the art on the basis of the present description, and the modifications and substitutions do not depart from the spirit of the embodiments.
Claims (3)
1. The circuit is characterized by comprising a REGISTER group REGISTER, a delay injection unit chain formed by cascading equal delay injection units TDO_CELL, an analog interpolation circuit INTERPLATE and a LATCH LATCH;
the REGISTER group REGISTER is used for receiving a digital circuit control signal C_IN and a system synchronous clock clk, converting an input single-ended signal into a differential signal and sending the differential signal to a delay injection unit chain formed by cascading equal delay injection units TDO_CELL; the delay injection unit TDO_CELL adopts a symmetrical analog differential circuit, the input end adopts transmission gate combination and other delay forward or reverse gating, and the output end adopts an inverting amplifier for isolation; delay injection chains with equal difference delay are arranged on the same silicon wafer;
the delay injection unit chain is used for finally outputting a delay signal I0/IB0, and meanwhile, the finally output delay signal I0/IB0 is subjected to one-stage delay injection unit to form a delay signal I1/IB1;
the analog interpolation circuit INTERPLATE is configured to receive the delay signal I0/IB0 and the delay signal I1/IB1, divide the analog signals of the N fine granularity phases according to the I0/IB0 and the I1/IB1, and control the P signal to select one signal from the N analog signals for outputting; the analog interpolation circuit is used for dividing deltat into N fine granularity phases;
the P signal controls the signal which is output by selecting one path of signal from the N analog signals, the signal is output into a LATCH LATCH to be latched through LATCH indication LATCH_EN control in a holding stage, and a front-stage circuit performs parameter learning and training by combining feedback signal FB timing in the latching stage; the circuit for fine-granularity delay output control is realized in a CMOS chip in an analog IC design mode.
2. A circuit for fine grain delay output control as recited in claim 1, wherein: the analog interpolation circuit INTERPLATE adopts a symmetrical analog differential circuit, two positive arms and two negative arms of two groups of input taps are divided by series resistors respectively, the divided voltages enter a selector after being matched by resistors, and the selection is controlled by a P signal and sent to an inverting amplifier for isolation.
3. A method of fine grain delayed output control, the method comprising the steps of:
A. the digital circuit control signal C_IN and the system synchronous clock clk are input into a REGISTER group REGISTER;
B. the REGISTER group REGISTER converts an input single-ended signal into a differential signal and sends the differential signal to a delay injection unit chain formed by cascading equal delay injection units TDO_CELL; delay injection chains with equal difference delay are arranged on the same silicon wafer;
C. the delay injection unit chain finally outputs a delay signal I0/IB0 to the analog interpolation circuit INTERPLATE, and simultaneously, the delay signal I1/IB1 of the first-stage delay injection unit is sent to the analog interpolation circuit INTERPLATE; the delay injection unit TDO_CELL adopts a symmetrical analog differential circuit, the input end adopts transmission gate combination and other delay forward or reverse gating, and the output end adopts an inverting amplifier for isolation;
D. the analog interpolation circuit INTERPLATE divides the analog signals of N fine granularity phases according to I0/IB0 and I1/IB1, and the P signal controls the N analog signals to select one path of signal for output; the analog interpolation circuit is used for dividing deltat into N fine granularity phases;
in the step D, the output signal is output into a LATCH for latching through LATCH indication latch_EN control in a holding stage, and in the latching stage, a front-stage circuit performs parameter learning and training in combination with feedback signal FB timing; the circuit of fine-grained delay output control is implemented in a CMOS chip in an analog IC design.
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| CN201810868335.3A CN109088622B (en) | 2018-08-02 | 2018-08-02 | Circuit and method for fine-granularity delay output control |
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| CN109088622B true CN109088622B (en) | 2023-10-31 |
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| CN111812619B (en) * | 2020-06-23 | 2023-03-21 | 深圳市精嘉微电子有限公司 | Device and method for measuring edge arrival time of picosecond-level resolution electric signal |
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| CN104113342A (en) * | 2013-11-28 | 2014-10-22 | 西安电子科技大学 | High-speed data synchronous circuit used for high-speed digital-to-analog converter |
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- 2018-08-02 CN CN201810868335.3A patent/CN109088622B/en active Active
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|---|---|---|---|---|
| CN1679230A (en) * | 2002-08-21 | 2005-10-05 | 英特尔公司 | Receivers for controlled frequency signals |
| CN1625054A (en) * | 2003-12-04 | 2005-06-08 | 国际商业机器公司 | Dual edge programmable delay unit and method for providing programm of the unit |
| CN101233689A (en) * | 2005-08-03 | 2008-07-30 | Nxp股份有限公司 | Delay-locked loop |
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