CN117081581A - Synchronous nine-frequency-division circuit and nine-frequency-division signal generation method - Google Patents
Synchronous nine-frequency-division circuit and nine-frequency-division signal generation method Download PDFInfo
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Abstract
The invention provides a synchronous nine-frequency-division circuit and a nine-frequency-division signal generation method, which are characterized in that firstly, nine-bit cyclic state conversion of P4P3P2P1 is realized by using four triggers and combining four expressions of F1＝(P1！)&(P4！)，F2＝(P1&(P2！))+((P1！)&P2)，F3＝((P1！)&P3)+((P2！)&P3)+(P1&P2&(P3！)) and F4＝P1&P2&P3 and then using 1 trigger to displace P3 signals and simple logic operation to realize a nine-frequency-division circuit with 50% duty ratio, the synchronous nine-frequency-division circuit with 50% duty ratio can be realized under the condition that only five triggers are used, compared with other circuits with the same frequency-division ratio, the structure of the trigger is relatively simple, and the chip area and cost can be effectively saved in an integrated circuit.
Description
Technical Field
The invention relates to the technical field of signal processing, in particular to a synchronous nine-frequency-division circuit and a nine-frequency-division signal generation method.
Background
In high-speed circuits, there is a strict index requirement on the signal quality of the clock, and clocks with duty cycles other than 50% can affect the operating state of the module. Therefore, whether it is an odd or even divider, it is necessary to ensure that the duty cycle of the output signal is 50%. The existing frequency divider basically adopts N or more than N D flip-flops with setting or resetting to realize N frequency division, or needs to design special flip-flops to realize the frequency division. For example, patent US5438600a discloses an arbitrary integer divider, but the circuit scale is large, the cost is high, and the number of required flip-flops is larger than the division ratio; patent CN201210305614.1 also discloses an arbitrary integer divider circuit, but multiple switches are added, and a singlechip is required for control, so that implementation is complex. Therefore, the circuit of the frequency divider has large scale and high cost, and the number of required triggers is usually larger than or equal to the frequency dividing ratio, which is not beneficial to saving the chip area.
Disclosure of Invention
The invention provides a synchronous nine-frequency-division circuit and a nine-frequency-division signal generation method, which are used for solving the defects that the circuit scale is large, the cost is high, the number of required triggers is usually larger than or equal to the frequency division ratio, and the chip area is not beneficial to saving.
The invention provides a synchronous nine-frequency dividing circuit, which comprises:
a first output signal conversion circuit formed by connecting a signal operation circuit for performing an operation (P1 |) & (P4|) and a D flip-flop in series, for generating a first output signal;
a second output signal conversion circuit formed by connecting a signal operation circuit for executing operation (P1 & (P2 ≡)) + ((P1 ≡) P2) and a D trigger in series, for generating a second output signal;
a third output signal conversion circuit formed by connecting a signal operation circuit for executing operation ((P1|) and P3) +((P2|) and P3) + (P1 and P2& (P3|)) in series with a D trigger, for generating a third output signal;
a fourth output signal conversion circuit formed by connecting a signal operation circuit for executing operations P1, P2 and P3 and a D trigger in series, for generating a fourth output signal;
the nine-frequency-division signal output circuit comprises a D trigger and is used for delaying the third output signal by 1/2 clock period based on the reverse reference clock, generating a third delay signal, and carrying out logic operation on the third output signal and the third delay signal to obtain a nine-frequency-division signal;
Wherein, P1 is a first output signal output by the first output signal conversion circuit at a moment, P2 is a second output signal output by the second output signal conversion circuit at a moment, P3 is a third output signal output by the third output signal conversion circuit at a moment, and P4 is a fourth output signal output by the fourth output signal conversion circuit at a moment; under the action of a reference clock, the combined states of the fourth output signal, the third output signal, the second output signal and the first output signal are periodically changed according to the sequence of 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111 and 1000.
According to the synchronous divide-by-nine circuit provided by the invention, the signal operation circuit for executing operation (P1 |)/(P4|) comprises a first NOR gate; the input end of the first NOR gate is respectively connected with the in-phase output end of the D trigger in the first output signal conversion circuit and the in-phase output end of the D trigger in the fourth output signal conversion circuit; the output end of the first NOR gate is connected with the D end of the D trigger in the first output signal conversion circuit, and the clock edge of the D trigger in the first output signal conversion circuit is connected with the reference clock.
The invention provides a synchronous nine-frequency dividing circuit, which is used for executing the signal operation circuit of the operation (P1 & (P2 ≡)) + ((P1 ≡) P2) and comprises a first NAND gate, a second NAND gate and a third NAND gate; the input end of the first NAND gate is respectively connected with the inverting output end of the D trigger in the first output signal conversion circuit and the non-inverting output end of the D trigger in the second output signal conversion circuit; the input end of the second NAND gate is respectively connected with the in-phase output end of the D trigger in the first output signal conversion circuit and the anti-phase output end of the D trigger in the second output signal conversion circuit; the input end of the third NAND gate is connected with the output ends of the first NAND gate and the second NAND gate respectively; the output end of the third NAND gate is connected with the D end of the D trigger in the second output signal conversion circuit, and the clock edge of the D trigger in the second output signal conversion circuit is connected with the reference clock.
The signal operation circuit for executing operations ((P1 |) and P3) +((P2|) and P3) + (P1 and P2) & (P3|) comprises a second NAND gate, a fourth NAND gate, a fifth NAND gate, a sixth NAND gate and a seventh NAND gate; the input end of the second NOR gate is respectively connected with the D trigger in the first output signal conversion circuit and the inverting output end of the D trigger in the second output signal conversion circuit; the input end of the fourth NAND gate is respectively connected with the in-phase output end of the D trigger in the first output signal conversion circuit and the in-phase output end of the D trigger in the second output signal conversion circuit; the input end of the fifth NAND gate is respectively connected with the inverting output end of the D trigger in the third output signal conversion circuit and the output end of the second NAND gate; the input end of the sixth NAND gate is respectively connected with the in-phase output end of the D trigger in the third output signal conversion circuit and the output end of the fourth NAND gate; the input end of the seventh NAND gate is respectively connected with the output ends of the fifth NAND gate and the sixth NAND gate; the output end of the seventh NAND gate is connected with the D end of the D trigger in the third output signal conversion circuit, and the clock edge of the D trigger in the third output signal conversion circuit is connected with the reference clock.
According to the synchronous divide-by-nine circuit provided by the invention, the signal operation circuit for executing operations P1, P2 and P3 comprises a third NOR gate; the input end of the third NAND gate is respectively connected with the inverting output end of the D trigger in the third output signal conversion circuit and the output end of the fourth NAND gate; the output end of the third NOR gate is connected with the D end of the D trigger in the fourth output signal conversion circuit, and the clock edge of the D trigger in the fourth output signal conversion circuit is connected with the reference clock.
The invention also provides a nine-frequency-division signal generation method based on any one of the synchronous nine-frequency-division circuits, which comprises the following steps:
the first output signal conversion circuit, the second output signal conversion circuit, the third output signal conversion circuit, the fourth output signal conversion circuit, the first output signal, the third output signal, the fourth output signal are generated based on the first output signal conversion circuit formed by connecting in series the signal operation circuit for performing the operation (P1 |) & (P4 |) & and the one D flip-flop, the second output signal conversion circuit formed by connecting in series the signal operation circuit for performing the operation (P1) & (P2) & and the one D flip-flop, the signal operation circuit for performing the operation ((P1) & P3) +((P2) & P3) + (P1 & P2) & P3) and the third output signal conversion circuit formed by connecting in series the signal operation circuit for performing the operation (P1 & P2& P3) and the one D flip-flop, respectively;
Based on a nine-frequency-division signal output circuit comprising a D trigger, delaying the third output signal by 1/2 clock period by utilizing a reverse reference clock, generating a third delay signal, and carrying out logic operation on the third output signal and the third delay signal to obtain a nine-frequency-division signal;
wherein, P1 is a first output signal output by the first output signal conversion circuit at a moment, P2 is a second output signal output by the second output signal conversion circuit at a moment, P3 is a third output signal output by the third output signal conversion circuit at a moment, and P4 is a fourth output signal output by the fourth output signal conversion circuit at a moment; under the action of a reference clock, the combined states of the fourth output signal, the third output signal, the second output signal and the first output signal are periodically changed according to the sequence of 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111 and 1000.
According to the nine-divided signal generating method provided by the invention, a first output signal is generated based on a first output signal conversion circuit formed by connecting a signal operation circuit for executing operation (P1 |) & (P4|) and a D trigger in series, and the method concretely comprises the following steps:
Based on a first NOR gate, performing NOR operation on a first output signal and a fourth output signal which are output at the last moment by an in-phase output end of a D trigger in the first output signal conversion circuit and a D trigger in the fourth output signal conversion circuit to obtain a first trigger signal at the current moment;
and generating a first output signal at the current moment by using a D trigger in the first output signal conversion circuit based on the first trigger signal at the current moment.
According to the method for generating nine-frequency-division signals provided by the invention, a second output signal conversion circuit formed by connecting a signal operation circuit for executing operations (P1 & (P2 ≡)) + ((P1 ≡) P2) and a D trigger in series is generated, and the method specifically comprises the following steps:
based on a first NAND gate, performing NAND operation on a reversed first output signal output by an inverted output end of a D trigger in the first output signal conversion circuit at the last moment and a second output signal output by an in-phase output end of the D trigger in the second output signal conversion circuit at the last moment to obtain a first NAND gate output signal;
based on a second NAND gate, performing NAND operation on a first output signal output by an in-phase output end of a D trigger in the first output signal conversion circuit at the last moment and a second output signal output by an opposite-phase output end of the D trigger in the second output signal conversion circuit at the last moment to obtain a second NAND gate output signal;
Based on a third NAND gate, performing NAND operation on the first NAND gate output signal and the second NAND gate output signal to obtain a second trigger signal at the current moment;
and generating a second output signal at the current moment by using a D trigger in the second output signal conversion circuit based on the second trigger signal at the current moment.
According to the method for generating a nine-divided signal provided by the present invention, a third output signal is generated based on a third output signal conversion circuit formed by connecting a signal operation circuit for performing operations ((p1|) and p3) +((p2|) and p3) + (p1 and p2) & (p3|)) in series with a D flip-flop, specifically comprising:
based on a second NOR gate, performing NOR operation on a reverse first output signal and a reverse second output signal which are output at the last moment by a D trigger in the first output signal conversion circuit and an inverting output end of the D trigger in the second output signal conversion circuit to obtain a second NOR gate output signal;
based on a fourth NAND gate, performing NAND operation on a first output signal and a second output signal which are output at the last moment by an in-phase output end of a D trigger in the first output signal conversion circuit and a D trigger in the second output signal conversion circuit to obtain a fourth NAND gate output signal;
Based on a fifth NAND gate, performing NAND operation on an inverted third output signal output by an inverted output end of a D trigger in the third output signal conversion circuit at the last moment and the second NOR gate output signal to obtain a fifth NAND gate output signal;
based on a sixth NAND gate, performing NAND operation on a third output signal output by an in-phase output end of a D trigger in the third output signal conversion circuit at the last moment and the fourth NAND gate output signal to obtain a sixth NAND gate output signal;
performing NAND operation on the fifth NAND gate output signal and the sixth NAND gate output signal based on a seventh NAND gate to obtain a third trigger signal at the current moment;
and generating a third output signal at the current moment by using a D trigger in the third output signal conversion circuit based on the third trigger signal at the current moment.
According to the method for generating nine-frequency-division signals provided by the invention, a fourth output signal conversion circuit formed by connecting a signal operation circuit for executing operations P1, P2 and P3 and a D trigger in series is used for generating a fourth output signal, and the method specifically comprises the following steps:
based on a third NOR gate, performing NOR operation on an inverted third output signal output by an inverted output end of a D trigger in the third output signal conversion circuit at the last moment and the fourth NAND gate output signal to obtain a fourth trigger signal at the current moment;
And generating a fourth output signal at the current moment by using a D trigger in the fourth output signal conversion circuit based on the fourth trigger signal at the current moment.
According to the synchronous nine-frequency-division circuit and the nine-frequency-division signal generation method, firstly, through the operation of four expressions of F1 = (P1 |) & (P4 |), F2 = (P1 |) & (P2 |)) + ((P1 |) & P2), F3 = ((P1 |) & P3) +((P1 & P2 |) & (P3 |)) and F4 = P1& P2& P3, nine-bit cyclic state conversion of the combined state of P4, P3, P2 and P1 is achieved through the combination of four triggers, then the P3 signal is shifted through the use of 1 trigger, and the nine-frequency-division circuit with 50% duty ratio is achieved through the combination of P3 for simple logic operation under the condition that only five rising edge triggered D triggers are used, compared with other circuit triggers with the same duty ratio, 4-5 chip triggers can be saved, the circuit can be relatively simple in structure, and the cost can be saved.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a synchronous divide-by-nine circuit provided by the invention;
FIG. 2 is a schematic waveform diagram of signals provided by the present invention;
FIG. 3 is a state machine diagram of the combined states of the output signals provided by the present invention;
fig. 4 is a schematic flow chart of a method for generating a divide-by-nine signal according to the present invention;
reference numerals:
111: a signal operation circuit for performing an operation (P1 |)/(P4|); 110: a first output signal conversion circuit; 121: a signal operation circuit for performing an operation (P1 & (P2 ≡)) + ((P1 ≡) P2); 120: a second output signal conversion circuit; 131: a signal operation circuit for executing an operation ((p1|) and p3) +((p2|) and p3) + (p1 and p2| (p3|)); 130: a third output signal conversion circuit; 141: a signal operation circuit for performing operations P1& P2& P3; 140: a fourth output signal conversion circuit; 112. 122, 132, 142, 151: a D trigger; 150: and a divide by nine signal output circuit.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Fig. 1 is a schematic flow chart of a synchronous divide-by-nine circuit according to the present invention, as shown in fig. 1, the circuit includes:
a first output signal conversion circuit 110 formed by connecting a signal operation circuit 111 for performing an operation (P1 |) & (P4 |) and a D flip-flop 112 in series, for generating a first output signal P1;
a second output signal conversion circuit 120 formed by connecting a signal operation circuit 121 for performing an operation (P1 & (P2 ≡)) + ((P1 ≡) P2) and a D flip-flop 122 in series, for generating a second output signal P2;
a third output signal conversion circuit 130 formed by connecting a signal operation circuit 131 for performing an operation ((p1|) and p3) +((p2|) and p3) + (p1 & p2) & (p3|)) in series with a D flip-flop 132, for generating a third output signal P3;
a fourth output signal conversion circuit 140 formed by connecting a signal operation circuit 141 for performing operations P1& P2& P3 and a D flip-flop 142 in series, for generating a fourth output signal P4;
the divide by nine signal output circuit 150 including a D flip-flop 151 is configured to delay the third output signal P3 by 1/2 clock cycle based on the inverted reference clock, generate a third delayed signal P3X, and perform a logic operation on the third output signal P3 and the third delayed signal P3X to obtain a divide by nine signal.
Specifically, the signal operation circuit 111 is configured to perform an operation f1= (p1|) & (p4|), where p1|! For the inverted first output signal outputted from the D flip-flop 112 at the previous time in the first output signal conversion circuit 110, P4 ≡! Is the inverted fourth output signal output at the time on the D flip-flop 142 in the fourth output signal conversion circuit 140. After the signal operation circuit 111 performs the above operation and outputs the first trigger signal F1, the first trigger signal F1 enters the D flip-flop 112 in the first output signal conversion circuit 110, so as to obtain the first output signal that is output by the D flip-flop 112 at the current time. In FIG. 1, the Q terminal of the D flip-flop 112 is an in-phase output terminal for outputting the first output signal P1, and the QB terminal is an inverted output terminal for outputting the inverted first output signal P1-! . The D flip-flop 122, the D flip-flop 132, and the D flip-flop 142 are similar, and will not be described in detail.
The signal operation circuit 121 is configured to perform an operation f2= (p1++ (p2+|)) + ((p1+|)) and P2), wherein P1 is a first output signal outputted by the D flip-flop 112 in the first output signal conversion circuit 110 at the previous time, P2 is a second output signal outputted by the D flip-flop 122 in the second output signal conversion circuit 120 at the previous time, and P2+|! Is the inverted second output signal output at the time on the D flip-flop 122 in the second output signal conversion circuit 120. After the signal operation circuit 121 performs the above operation and outputs the second trigger signal F2, the second trigger signal F2 enters the D flip-flop 122 in the second output signal conversion circuit 120, so as to obtain the second output signal that is output by the D flip-flop 122 at the current time.
The signal operation circuit 131 is configured to perform an operation f3= ((p1|) and p3) +((p2|) and p3) + (p1 and p2++ (p3|)), wherein p3 is the third output signal outputted from the D flip-flop 132 in the third output signal conversion circuit 130 at the previous time, and p3|! Is the inverted third output signal output at the last time of the D flip-flop 132 in the third output signal conversion circuit 130. After the signal operation circuit 131 performs the above operation and outputs the third trigger signal F3, the third trigger signal F3 enters the D flip-flop 132 in the third output signal conversion circuit 130, so as to obtain the third output signal output by the D flip-flop 132 at the current time.
The signal operation circuit 141 is configured to perform operations f4=p1 & P2& P3. After the signal operation circuit 141 performs the above operation and outputs the fourth trigger signal F4, the fourth trigger signal F4 enters the D flip-flop 142 in the fourth output signal conversion circuit 140, so as to obtain the fourth output signal output by the D flip-flop 142 at the current time.
Note that, since the above-described logic operation has various changeable forms, the connection method in fig. 1 is merely an example, and the connection method may be determined according to the logic operation formulas specifically executed by the signal operation circuit 111, the signal operation circuit 121, the signal operation circuit 131, and the signal operation circuit 141.
Under the action of the reference clock, waveforms of the fourth output signal P4 output by the D flip-flop 142, the third output signal P3 output by the D flip-flop 132, the second output signal P2 output by the D flip-flop 122, and the first output signal P1 output by the D flip-flop 112 are as shown in fig. 2, it can be seen that one signal period of the combined state P4P3P2P1 of the four output signals is a clock period of nine reference clocks, and the P4P3P2P1 is cyclically changed in the order of 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, and 1000, but it should be noted that the first state after the P4P3P2P1 enters the above cycle may be any of the above 9 states. As shown in fig. 3, the state machine of P4P3P2P1 may be configured such that after P4, P3, P2 and P1 enter the signal operation circuit 111, the signal operation circuit 121, the signal operation circuit 131 and the signal operation circuit 141 in any initial state, the combined states of the D flip-flop 142 in the fourth output signal conversion circuit 140, the D flip-flop 132 in the third output signal conversion circuit 130, the D flip-flop 122 in the second output signal conversion circuit 120 and the D flip-flop 112 in the first output signal conversion circuit 110 are counted into the timing sequence of 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111 and 1000 in the next clock cycle, and are periodically changed in the timing sequence in the subsequent clock cycle. Taking the waveform diagram shown in fig. 2 as an example, after P4, P3, P2, and P1 are input to the corresponding signal operation circuits in the initial state of 1010, P4, P3, P2, and P1 and the combined state transition are taken into the above-described timing at the next clock cycle as 0010.
Subsequently, the divide by nine signal generating circuit 150 processes the third output signal P3 output by the D flip-flop 132 in the third output signal converting circuit 130, specifically may invert the reference clock based on the inverter to obtain an inverted reference clock, and then delay the third output signal P3 by 1/2 clock cycle based on the inverted reference clock by using the D flip-flop 151 (the inverted reference clock is connected to the clock edge of the D flip-flop 151, and the third output signal P3 is connected to the D terminal of the D flip-flop 151), generate the third delayed signal P3X, and perform an or operation on the third output signal P3 and the third delayed signal P3X to obtain the divide by nine signal. The waveforms of the third delay signal P3X and the divide-by-nine signal are shown in fig. 2. Here, the third delayed signal P3X may be inverted based on an inverter, and then the inverted third delayed signal and the inverted third output signal may be input into one nand gate, to implement the or operation of the third output signal P3 and the third delayed signal P3X.
In some embodiments, considering that basic logic gates such as nand gates and nor gates are generally adopted in the logic operation circuit, the logic operation performed by the signal operation circuit 111 may be converted into f1= (p1+p4) +.! The method comprises the steps of carrying out a first treatment on the surface of the The signal arithmetic circuit 121 may convert the logical operation performed by the signal arithmetic circuit into f2= ((P1 & (P2 ≡)) ≡ -! The method comprises the steps of carrying out a first treatment on the surface of the For the signal operation circuit 131, the logical operation performed by it may be converted into f3= (((P1 & P2) | P3) | and (((P1 |+p 2 |) | P3 |)) | -! The method comprises the steps of carrying out a first treatment on the surface of the For the signal operation circuit 141, the logical operation it performs may be converted into f4= ((P1 & P2) + (P3 |)) +, the following! . Subsequently, the signal operation circuit 111, the signal operation circuit 121, the signal operation circuit 131, and the signal operation circuit 141 are constructed on the basis of this.
Specifically, in some embodiments, the signal operation circuit 111 includes a first nor gate. Wherein the input terminal of the first NOR gate is connected to the non-inverting output terminal of the D flip-flop 112 in the first output signal converting circuit 110 and the D flip-flop 142 in the fourth output signal converting circuit 140, respectively, to perform (P1+P4) ≡! . The output end of the first nor gate is connected to the D end of the D flip-flop 112 in the first output signal conversion circuit 110, the clock edge of the D flip-flop 112 in the first output signal conversion circuit 110 is connected to the reference clock, and the D flip-flop 112 in the first output signal conversion circuit 110 is triggered by the rising edge.
In some embodiments, the signal operation circuit 121 includes a first nand gate, a second nand gate, and a third nand gate; wherein the input end of the first NAND gate is connected to the inverting output end of the D flip-flop 112 in the first output signal converting circuit 110 and the non-inverting output end of the D flip-flop 122 in the second output signal converting circuit 120 respectively to execute ((P1-! The method comprises the steps of carrying out a first treatment on the surface of the The input terminal of the second NAND gate is connected to the non-inverting output terminal of the D flip-flop 112 in the first output signal converting circuit 110 and the inverting output terminal of the D flip-flop 122 in the second output signal converting circuit 120, respectively, to perform (P1 ≡ (P2 ≡)) -! The method comprises the steps of carrying out a first treatment on the surface of the The input end of the third NAND gate is connected with the output ends of the first NAND gate and the second NAND gate respectively to execute ((P1 & (P2-! . The output end of the third nand gate is connected to the D end of the D flip-flop 122 in the second output signal conversion circuit 120, the clock edge of the D flip-flop 122 in the second output signal conversion circuit 120 is connected to the reference clock, and the D flip-flop 122 in the second output signal conversion circuit 120 is triggered by the rising edge.
In some embodiments, the signal operation circuit 131 includes a second nor gate, a fourth nand gate, a fifth nand gate, a sixth nand gate, and a seventh nand gate; wherein the input terminal of the second NOR gate is connected to the inverting output terminal of the D flip-flop 112 in the first output signal converting circuit 110 and the D flip-flop 122 in the second output signal converting circuit 120, respectively, to perform (P1! The method comprises the steps of carrying out a first treatment on the surface of the The input terminals of the fourth NAND gate are respectively connected to the non-inverting output terminals of the D flip-flop 112 in the first output signal conversion circuit 110 and the D flip-flop 122 in the second output signal conversion circuit 120 to perform (P1 & P2) -! The method comprises the steps of carrying out a first treatment on the surface of the The input terminal of the fifth NAND gate is connected to the inverting output terminal of the D flip-flop 132 in the third output signal converting circuit 130 and the output terminal of the second NOR gate, respectively, to execute ((P1! The method comprises the steps of carrying out a first treatment on the surface of the The input terminal of the sixth NAND gate is connected to the non-inverting output terminal of the D flip-flop 132 in the third output signal conversion circuit 130 and the output terminal of the fourth NAND gate, respectively, to perform ((P1 & P2) |P 3) |! The method comprises the steps of carrying out a first treatment on the surface of the The input end of the seventh NAND gate is respectively connected with the output ends of the fifth NAND gate and the sixth NAND gate, to execute (((P1 & P2) & P3) & (((P1 & P2 & P3.)) & ]! . The output end of the seventh nand gate is connected to the D end of the D flip-flop 132 in the third output signal conversion circuit 130, the clock edge of the D flip-flop 132 in the third output signal conversion circuit 130 is connected to the reference clock, and the D flip-flop 132 in the third output signal conversion circuit 130 is triggered by the rising edge.
In some embodiments, the signal operation circuit 141 includes a third nor gate; wherein the input terminal of the third nor gate is connected to the inverting output terminal of the D flip-flop 132 in the third output signal conversion circuit 130 and the output terminal of the fourth nor gate, respectively, to perform ((P1 & P2) + (P3 +)) ]! . It can be seen that the signal operation circuit 141 and the signal operation circuit 131 may share a fourth nand gate. The output end of the third nor gate is connected to the D end of the D flip-flop 142 in the fourth output signal conversion circuit 140, the clock edge of the D flip-flop 142 in the fourth output signal conversion circuit 140 is connected to the reference clock, and the D flip-flop 142 in the fourth output signal conversion circuit 140 is triggered by the rising edge.
In summary, in the synchronous nine-frequency dividing circuit provided by the embodiment of the invention, first, through the operation of four expressions of f1= (p1|) & (p4|), f2= (p1 & (p2|)) + ((p1|) and P2), f3= ((p1|) & p3) +((p2|) & p3) + (p1 & p2& (p3|)) and f4=p1 & p2& P3, then, four flip-flops are combined, nine-bit cyclic state conversion of the P4P3P2P1 combined state is realized, then, the P3 signal is shifted by using 1 flip-flop, and a nine-frequency divider with 50% duty ratio output is realized by combining P3 to perform simple logic operation, so that compared with other circuits with the same ratio, the synchronous nine-frequency dividing circuit can save 4-5 flip-flops, and the required circuit can save the cost by relatively simple chip structure and relatively has a simple chip structure.
The method for generating a divide-by-nine signal provided by the present invention will be described below, and the method for generating a divide-by-nine signal described below and the synchronous divide-by-nine circuit described above may be referred to correspondingly to each other.
Based on any of the above embodiments, fig. 4 is a schematic flow chart of a method for generating a divide by nine signal according to the present invention, as shown in fig. 4, where the method is based on the synchronous divide by seven circuit provided in the above embodiment, and the method includes:
step 410, generating a first output signal, a second output signal, a third output signal, and a fourth output signal based on a first output signal conversion circuit in which a signal operation circuit for performing the operation (P1 |) & (P4 |) & and a D flip-flop are connected in series, a second output signal conversion circuit in which a signal operation circuit for performing the operation (P1) & P2) & lt+ & gt (P1 |) & P3) + (P2) & P3) + (P1 & P2) & P3|) and a D flip-flop are connected in series, a signal operation circuit for performing the operation (P1 & P2& P3) and a fourth output signal conversion circuit in which a D flip-flop is connected in series, respectively;
step 420, based on a divide by nine signal output circuit including a D flip-flop, delaying the third output signal by 1/2 clock cycle with the inverted reference clock, generating a third delayed signal, and performing logic operation on the third output signal and the third delayed signal to obtain a divide by nine signal;
Wherein, P1 is a first output signal output by the first output signal conversion circuit at a moment, P2 is a second output signal output by the second output signal conversion circuit at a moment, P3 is a third output signal output by the third output signal conversion circuit at a moment, and P4 is a fourth output signal output by the fourth output signal conversion circuit at a moment; under the action of a reference clock, the combined states of the fourth output signal, the third output signal, the second output signal and the first output signal are periodically changed according to the sequence of 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111 and 1000.
According to any one of the above embodiments, the generating of the first output signal based on the first output signal conversion circuit formed by connecting the signal operation circuit for performing the operation (P1 |)/(P4|) and one D flip-flop in series specifically includes:
based on a first NOR gate, performing NOR operation on a first output signal and a fourth output signal which are output at the last moment by an in-phase output end of a D trigger in the first output signal conversion circuit and a D trigger in the fourth output signal conversion circuit to obtain a first trigger signal at the current moment;
And generating a first output signal at the current moment by using a D trigger in the first output signal conversion circuit based on the first trigger signal at the current moment.
According to any of the above embodiments, the generation of the second output signal based on the second output signal conversion circuit formed by connecting in series the signal operation circuit for performing the operation (P1 & (P2 ≡)) + ((P1 ≡) P2) and one D flip-flop specifically includes:
based on a first NAND gate, performing NAND operation on a reversed first output signal output by an inverted output end of a D trigger in the first output signal conversion circuit at the last moment and a second output signal output by an in-phase output end of the D trigger in the second output signal conversion circuit at the last moment to obtain a first NAND gate output signal;
based on a second NAND gate, performing NAND operation on a first output signal output by an in-phase output end of a D trigger in the first output signal conversion circuit at the last moment and a second output signal output by an opposite-phase output end of the D trigger in the second output signal conversion circuit at the last moment to obtain a second NAND gate output signal;
based on a third NAND gate, performing NAND operation on the first NAND gate output signal and the second NAND gate output signal to obtain a second trigger signal at the current moment;
And generating a second output signal at the current moment by using a D trigger in the second output signal conversion circuit based on the second trigger signal at the current moment.
According to any of the above embodiments, the generation of the third output signal based on the third output signal conversion circuit formed by connecting in series the signal operation circuit for performing the operation ((p1|) and p3) +((p2|) and p3) + (p1 and p2|) and the one D flip-flop specifically includes:
based on a second NOR gate, performing NOR operation on a reverse first output signal and a reverse second output signal which are output at the last moment by a D trigger in the first output signal conversion circuit and an inverting output end of the D trigger in the second output signal conversion circuit to obtain a second NOR gate output signal;
based on a fourth NAND gate, performing NAND operation on a first output signal and a second output signal which are output at the last moment by an in-phase output end of a D trigger in the first output signal conversion circuit and a D trigger in the second output signal conversion circuit to obtain a fourth NAND gate output signal;
based on a fifth NAND gate, performing NAND operation on an inverted third output signal output by an inverted output end of a D trigger in the third output signal conversion circuit at the last moment and the second NOR gate output signal to obtain a fifth NAND gate output signal;
Based on a sixth NAND gate, performing NAND operation on a third output signal output by an in-phase output end of a D trigger in the third output signal conversion circuit at the last moment and the fourth NAND gate output signal to obtain a sixth NAND gate output signal;
performing NAND operation on the fifth NAND gate output signal and the sixth NAND gate output signal based on a seventh NAND gate to obtain a third trigger signal at the current moment;
and generating a third output signal at the current moment by using a D trigger in the third output signal conversion circuit based on the third trigger signal at the current moment.
According to any one of the above embodiments, the generating of the fourth output signal based on the fourth output signal conversion circuit formed by connecting the signal operation circuit for executing the operations P1& P2& P3 and one D flip-flop in series specifically includes:
based on a third NOR gate, performing NOR operation on an inverted third output signal output by an inverted output end of a D trigger in the third output signal conversion circuit at the last moment and the fourth NAND gate output signal to obtain a fourth trigger signal at the current moment;
and generating a fourth output signal at the current moment by using a D trigger in the fourth output signal conversion circuit based on the fourth trigger signal at the current moment.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A synchronous divide-by-nine circuit, comprising:
a first output signal conversion circuit formed by connecting a signal operation circuit for performing an operation (P1 |) & (P4|) and a D flip-flop in series, for generating a first output signal;
a second output signal conversion circuit formed by connecting a signal operation circuit for executing operation (P1 & (P2 ≡)) + ((P1 ≡) P2) and a D trigger in series, for generating a second output signal;
a third output signal conversion circuit formed by connecting a signal operation circuit for executing operation ((P1|) and P3) +((P2|) and P3) + (P1 and P2& (P3|)) in series with a D trigger, for generating a third output signal;
a fourth output signal conversion circuit formed by connecting a signal operation circuit for executing operations P1, P2 and P3 and a D trigger in series, for generating a fourth output signal;
the nine-frequency-division signal output circuit comprises a D trigger and is used for delaying the third output signal by 1/2 clock period based on the reverse reference clock, generating a third delay signal, and carrying out logic operation on the third output signal and the third delay signal to obtain a nine-frequency-division signal;
wherein, P1 is a first output signal output by the first output signal conversion circuit at a moment, P2 is a second output signal output by the second output signal conversion circuit at a moment, P3 is a third output signal output by the third output signal conversion circuit at a moment, and P4 is a fourth output signal output by the fourth output signal conversion circuit at a moment; under the action of a reference clock, the combined states of the fourth output signal, the third output signal, the second output signal and the first output signal are periodically changed according to the sequence of 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111 and 1000.
2. The synchronous divide-by-nine circuit according to claim 1, wherein the signal operation circuit for performing an operation (P1 |)/(P4|) includes a first nor gate; the input end of the first NOR gate is respectively connected with the in-phase output end of the D trigger in the first output signal conversion circuit and the in-phase output end of the D trigger in the fourth output signal conversion circuit; the output end of the first NOR gate is connected with the D end of the D trigger in the first output signal conversion circuit, and the clock edge of the D trigger in the first output signal conversion circuit is connected with the reference clock.
3. The synchronous divide-by-nine circuit according to claim 1, wherein the signal operation circuit for performing an operation (P1 & (P2 ≡)) + ((P1 ≡) P2) includes a first nand gate, a second nand gate, and a third nand gate; the input end of the first NAND gate is respectively connected with the inverting output end of the D trigger in the first output signal conversion circuit and the non-inverting output end of the D trigger in the second output signal conversion circuit; the input end of the second NAND gate is respectively connected with the in-phase output end of the D trigger in the first output signal conversion circuit and the anti-phase output end of the D trigger in the second output signal conversion circuit; the input end of the third NAND gate is connected with the output ends of the first NAND gate and the second NAND gate respectively; the output end of the third NAND gate is connected with the D end of the D trigger in the second output signal conversion circuit, and the clock edge of the D trigger in the second output signal conversion circuit is connected with the reference clock.
4. The synchronous divide-by-nine circuit of claim 1, wherein the signal operation circuit for performing operations ((p1|) and p3) +((p2|) and p3) + (p1 & p2|) and (p3|)) comprises a second nor gate, a fourth nand gate, a fifth nand gate, a sixth nand gate, and a seventh nand gate; the input end of the second NOR gate is respectively connected with the D trigger in the first output signal conversion circuit and the inverting output end of the D trigger in the second output signal conversion circuit; the input end of the fourth NAND gate is respectively connected with the in-phase output end of the D trigger in the first output signal conversion circuit and the in-phase output end of the D trigger in the second output signal conversion circuit; the input end of the fifth NAND gate is respectively connected with the inverting output end of the D trigger in the third output signal conversion circuit and the output end of the second NAND gate; the input end of the sixth NAND gate is respectively connected with the in-phase output end of the D trigger in the third output signal conversion circuit and the output end of the fourth NAND gate; the input end of the seventh NAND gate is respectively connected with the output ends of the fifth NAND gate and the sixth NAND gate; the output end of the seventh NAND gate is connected with the D end of the D trigger in the third output signal conversion circuit, and the clock edge of the D trigger in the third output signal conversion circuit is connected with the reference clock.
5. The synchronous divide-by-nine circuit of claim 4 wherein the signal operation circuit for performing operations P1& P2& P3 comprises a third nor gate; the input end of the third NAND gate is respectively connected with the inverting output end of the D trigger in the third output signal conversion circuit and the output end of the fourth NAND gate; the output end of the third NOR gate is connected with the D end of the D trigger in the fourth output signal conversion circuit, and the clock edge of the D trigger in the fourth output signal conversion circuit is connected with the reference clock.
6. A divide-by-nine signal generating method based on the synchronous divide-by-nine circuit according to any one of claims 1 to 5, comprising:
the first output signal conversion circuit, the second output signal conversion circuit, the third output signal conversion circuit, the fourth output signal conversion circuit, the first output signal, the third output signal, the fourth output signal are generated based on the first output signal conversion circuit formed by connecting in series the signal operation circuit for performing the operation (P1 |) & (P4 |) & and the one D flip-flop, the second output signal conversion circuit formed by connecting in series the signal operation circuit for performing the operation (P1) & (P2) & and the one D flip-flop, the signal operation circuit for performing the operation ((P1) & P3) +((P2) & P3) + (P1 & P2) & P3) and the third output signal conversion circuit formed by connecting in series the signal operation circuit for performing the operation (P1 & P2& P3) and the one D flip-flop, respectively;
Based on a nine-frequency-division signal output circuit comprising a D trigger, delaying the third output signal by 1/2 clock period by utilizing a reverse reference clock, generating a third delay signal, and carrying out logic operation on the third output signal and the third delay signal to obtain a nine-frequency-division signal;
wherein, P1 is a first output signal output by the first output signal conversion circuit at a moment, P2 is a second output signal output by the second output signal conversion circuit at a moment, P3 is a third output signal output by the third output signal conversion circuit at a moment, and P4 is a fourth output signal output by the fourth output signal conversion circuit at a moment; under the action of a reference clock, the combined states of the fourth output signal, the third output signal, the second output signal and the first output signal are periodically changed according to the sequence of 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111 and 1000.
7. The nine-divided signal generating method according to claim 6, wherein the generating of the first output signal based on a first output signal converting circuit formed by a signal operating circuit for performing an operation (P1 |)/(P4|) and a D flip-flop connected in series, specifically comprises:
Based on a first NOR gate, performing NOR operation on a first output signal and a fourth output signal which are output at the last moment by an in-phase output end of a D trigger in the first output signal conversion circuit and a D trigger in the fourth output signal conversion circuit to obtain a first trigger signal at the current moment;
and generating a first output signal at the current moment by using a D trigger in the first output signal conversion circuit based on the first trigger signal at the current moment.
8. The method of generating a divide-by-nine signal according to claim 6, wherein generating the second output signal based on a second output signal conversion circuit formed by connecting a signal operation circuit for performing an operation (P1 & (P2 ≡)) + ((P1 ≡) P2) in series with one D flip-flop, specifically comprises:
based on a first NAND gate, performing NAND operation on a reversed first output signal output by an inverted output end of a D trigger in the first output signal conversion circuit at the last moment and a second output signal output by an in-phase output end of the D trigger in the second output signal conversion circuit at the last moment to obtain a first NAND gate output signal;
based on a second NAND gate, performing NAND operation on a first output signal output by an in-phase output end of a D trigger in the first output signal conversion circuit at the last moment and a second output signal output by an opposite-phase output end of the D trigger in the second output signal conversion circuit at the last moment to obtain a second NAND gate output signal;
Based on a third NAND gate, performing NAND operation on the first NAND gate output signal and the second NAND gate output signal to obtain a second trigger signal at the current moment;
and generating a second output signal at the current moment by using a D trigger in the second output signal conversion circuit based on the second trigger signal at the current moment.
9. The method of generating a divide-by-nine signal according to claim 6, wherein the generating of the third output signal based on a third output signal conversion circuit formed by connecting a signal operation circuit for performing operations ((p1|) and p3) +((p2|) and p3) + (p1 and p2|) and a D flip-flop in series, specifically comprises:
based on a second NOR gate, performing NOR operation on a reverse first output signal and a reverse second output signal which are output at the last moment by a D trigger in the first output signal conversion circuit and an inverting output end of the D trigger in the second output signal conversion circuit to obtain a second NOR gate output signal;
based on a fourth NAND gate, performing NAND operation on a first output signal and a second output signal which are output at the last moment by an in-phase output end of a D trigger in the first output signal conversion circuit and a D trigger in the second output signal conversion circuit to obtain a fourth NAND gate output signal;
Based on a fifth NAND gate, performing NAND operation on an inverted third output signal output by an inverted output end of a D trigger in the third output signal conversion circuit at the last moment and the second NOR gate output signal to obtain a fifth NAND gate output signal;
based on a sixth NAND gate, performing NAND operation on a third output signal output by an in-phase output end of a D trigger in the third output signal conversion circuit at the last moment and the fourth NAND gate output signal to obtain a sixth NAND gate output signal;
performing NAND operation on the fifth NAND gate output signal and the sixth NAND gate output signal based on a seventh NAND gate to obtain a third trigger signal at the current moment;
and generating a third output signal at the current moment by using a D trigger in the third output signal conversion circuit based on the third trigger signal at the current moment.
10. The method of generating a divide-by-nine signal according to claim 9, wherein the generating a fourth output signal based on a fourth output signal conversion circuit formed by connecting a signal operation circuit for performing operations P1& P2& P3 and a D flip-flop in series, specifically comprises:
based on a third NOR gate, performing NOR operation on an inverted third output signal output by an inverted output end of a D trigger in the third output signal conversion circuit at the last moment and the fourth NAND gate output signal to obtain a fourth trigger signal at the current moment;
And generating a fourth output signal at the current moment by using a D trigger in the fourth output signal conversion circuit based on the fourth trigger signal at the current moment.
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