CN2872451Y

CN2872451Y - Dynamic switching circuit of clock

Info

Publication number: CN2872451Y
Application number: CN 200520046182
Authority: CN
Inventors: 朱志明; 吴子熙; 赖志强; 李长征
Original assignee: ZHIDUO MICRO ELECTRON (SHANGHAI) CO Ltd
Current assignee: ZHIDUO MICRO ELECTRON (SHANGHAI) CO Ltd
Priority date: 2005-11-01
Filing date: 2005-11-01
Publication date: 2007-02-21
Anticipated expiration: 2015-11-01

Abstract

The utility model relates to a new clock dynamic switching circuit. The principle of the circuit lies in that: in clock switching time, an output clock keeps low in certain period, avoiding the generation of narrow pulse and guaranteeing the stability of the circuit. The circuit is mainly composed of three registers and two latches in connection. Use a synchronous circuit to synchronize selective signals, generate inhibit signals by the register deferred method and generate clk_out by selecting proper signals. The utility model mainly solves the technical problem about a narrow negative impulse generated in clk_out, when switch_0 jumping between clk_1 and clk_0 in the existing clock dynamic switching circuit usage. And the utility model is applicable to the switch between any two clocks with different frequencies and different phase positions.

Description

The dynamic commutation circuit of novel clock

Technical field

The utility model relates to circuit design, and especially the circuit that switches at clock in the low power dissipation design of SOC (System on a Chip) chip is realized.

Background technology

It is common dynamically switching between 2 clocks in the integrated circuit, normally in order to reduce chip power-consumption.This needs the dynamic commutation circuit of clock to realize.The function that this circuit will be realized (as shown in Figure 1), when switch_0 was high, clk_out showed as clk_0; When switch_0 when low, clk_out shows as clk_1.

Classic method one: directly use the implementation method of No. 2 selector switchs (Fig. 2) the simplest, have potential problem.

One of potential problem: as shown in Figure 3, saltus step is 1 soon after the rising edge of switch_0 at clk_1, can form a very narrow positive pulse at clk_out.Such clk_out may cause integrated circuit to be made mistakes.

Two of potential problem: as shown in Figure 4,, may form a very narrow negative pulse at clk_out when switch_0 saltus step between clk_1 clk_0.Such clk_out may cause integrated circuit to be made mistakes.The reason that occurs is, when selecting signal to switch, positive pulse that might the 2 kinds of clocks in front and back is leaned on very closely.

Classic method two: use latch to improve circuit (Fig. 5), eliminated one of potential problem (Fig. 6).Two of potential problem still might take place.

Summary of the invention

The purpose of this utility model is to provide a kind of novel clock dynamic commutation circuit, when mainly solving the dynamic commutation circuit of existing clock and using, when switch_0 saltus step between clk_1 and clk_0, may form the technical matters of a very narrow negative pulse at clk_out, it is applicable to the switching between any two different frequency out of phase clocks.

The technical scheme that its technical matters that solves the utility model adopts is:

The composition and the annexation of circuit elements device are in the dynamic commutation circuit of a kind of this novel clock:

1, the switch_0 signal input part be connected respectively to first register D end and first with input end;

2, the clk_0 signal input part be connected respectively to first register, pair register synchronizing circuit, first latch clk end and second with input end; What wherein, insert first latch is the reverse signal of clk_0 signal;

3, the clk_1 signal input part be connected respectively to second register, second latch clk end and the 3rd with the input end of door; What wherein, insert second latch is the reverse signal of clk_1 signal;

4, the Q of this first register end is connected respectively to the D end of second register, pair register synchronizing circuit and the input end of rejection gate; Another input end of this rejection gate then with the Q of second register 12 end, its output terminal then is connected to the D end of second latch;

5, first is connected with the Q end of another input end and the pair register synchronizing circuit of door, and the D that its output terminal then is connected to first latch holds;

6, second is connected with the Q end of another input end and first latch of door, and its output terminal is connected to one or an input end;

7, the 3rd is connected with the Q end of another input end and second latch of door, its output terminal be connected to or another input end;

8, should or gate output terminal be the output terminal of the dynamic commutation circuit of this clock, and with the output of treated clock signal.

The beneficial effects of the utility model are: avoided the problem that may occur in the dynamic handoff procedure of clock fully, and circuit scale is less, is applicable to the switching between any two different frequency out of phase clocks.

Description of drawings

Fig. 1 is the circuit waveform figure that dynamically switches between 2 clocks.

Fig. 2 is existing with the dynamic commutation circuit figure of the clock of No. 2 selector switchs.

The circuit waveform figure of potential problems one when Fig. 3 is the use of Fig. 2 circuit.

The circuit waveform figure of potential problems two when Fig. 4 is the use of Fig. 2 circuit.

Fig. 5 is the existing dynamic commutation circuit figure of clock with latch.

The circuit waveform figure of potential problems when Fig. 6 is the use of Fig. 5 circuit.

Fig. 7 is the dynamic commutation circuit figure of the utility model clock.

Fig. 8 is the oscillogram of Fig. 7 circuit user mode.

Embodiment

See also Fig. 7, it is the dynamic commutation circuit figure of the utility model clock.As shown in the figure: it is on the basis of Fig. 5 circuit, and elder generation to selecting signal Synchronization, by the method for register delay, produces inhibit signal with synchronizing circuit again.By selecting appropriate signals to produce clk_out.Restriction: the time between twice clock switches must be greater than 5 clock period and 5 quick clock period length overalls at a slow speed.

The principle of this circuit is: it is at the clock switching instant, and output clock a period of time remains low, thereby has avoided the generation of burst pulse, guarantees the stability of circuit.Only need a spot of register and latch, support 2 input clocks of asynchronous input and optional frequency ratio.

As Fig. 7, the composition and the annexation of circuit elements device are in the dynamic commutation circuit of this novel clock:

1, the switch_0 signal input part be connected respectively to first register 11 D end and first with 21 input end;

2, the clk_0 signal input part be connected respectively to first register 11, pair register synchronizing circuit 13, first latch 31 clk end and second with 22 input end; What wherein, insert first latch 31 is the reverse signal of clk_0 signal;

3, the clk_1 signal input part be connected respectively to second register 12, second latch 32 clk end and the 3rd with the input end of door 23; What wherein, insert second latch 32 is the reverse signal of clk_1 signal;

4, the Q of this first register 11 end is connected respectively to the D end of second register 12, pair register synchronizing circuit 13 and the input end of rejection gate 4; Another input end of this rejection gate 4 then with the Q of second register 12 end, its output terminal then is connected to the D end of second latch 32;

5, first is connected with the Q end of pair register synchronizing circuit 13 with door another input end of 21, and the D that its output terminal then is connected to first latch 31 holds;

6, second is connected with the Q end of first latch 31 with door another input end of 22, and its output terminal is connected to one or 5 input end;

7, the 3rd is connected with the Q end of second latch 32 with door another input end of 23, and its output terminal is connected to or another input end of 5;

8, should or door 5 output terminals are output terminals of the dynamic commutation circuit of this clock, and with the output of treated clock signal.

See also Fig. 8, use the dynamic commutation circuit of clock of the present utility model to avoid the problem that may occur in the dynamic handoff procedure of clock fully, particularly avoid when switch_0 between clk_1 clk_0 during saltus step, may form the problem of a very narrow negative pulse at clk_out, and circuit scale is less.

Claims

1, the dynamic commutation circuit of a kind of novel clock is characterized in that the formation of components and parts in this circuit and annexation are:

1. the switch_0 signal input part is connected respectively to the D end and first and the input end of (21) of first register (11);

2. the clk_0 signal input part is connected respectively to the clk end and second and the input end of (22) of first register (11), pair register synchronizing circuit (13), first latch (31); What wherein, insert first latch (31) is the reverse signal of clk_0 signal;

3. the clk_1 signal input part be connected respectively to second register (12), second latch (32) clk end and the 3rd with the input end of (23); What wherein, insert second latch (32) is the reverse signal of clk_1 signal;

4. the Q of this first register (11) end is connected respectively to the D end of second register (12), pair register synchronizing circuit (13) and the input end of rejection gate (4); Another input end of this rejection gate (4) then with the Q of second register (12) end, its output terminal then is connected to the D end of second latch (32);

5. first is connected with the Q end of another input end and the pair register synchronizing circuit (13) of door (21), and the D that its output terminal then is connected to first latch (31) holds;

6. second is connected with the Q end of another input end and first latch (31) of door (22), and its output terminal is connected to one or (5) input end;

7. the 3rd is connected with the Q end of another input end and second latch (32) of door (23), and its output terminal is connected to or another input end of (5);

8. should or the door (a 5) output terminal be the output terminal of the dynamic commutation circuit of this clock.