CN203135818U - A multiphase non-overlapping clock circuit - Google Patents
A multiphase non-overlapping clock circuit Download PDFInfo
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- CN203135818U CN203135818U CN 201320040075 CN201320040075U CN203135818U CN 203135818 U CN203135818 U CN 203135818U CN 201320040075 CN201320040075 CN 201320040075 CN 201320040075 U CN201320040075 U CN 201320040075U CN 203135818 U CN203135818 U CN 203135818U
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Abstract
The utility model discloses a multiphase non-overlapping clock circuit comprising a delaying module, a periodic pulse generating module, multiple inverters, and multiple RS triggers. The input end of the delaying module and one input end of the periodic pulse generating module are connected and are used as the input port of a main clock. The output end of the delaying module is connected with the other input end of the periodic pulse generating module. The output end of the periodic pulse generating module is connected with the setting ends of the RS triggers. The input ends of the inverters are used as the input ports of a multiphase clock. The output ends of the inverters are connected with the other input end of a corresponding RS trigger, respectively. The output ends of the RS triggers are used as the output ports of the multiphase non-overlapping clock. The multiphase non-overlapping clock circuit has characteristics of simple structure, little occupied area of a chip, high reliability, and a capability of processing a multiphase clock synchronous with the main clock.
Description
Technical field
The utility model relates to a kind of multi-phase clock treatment circuit, particularly a kind of heterogeneous non-overlapping clock circuit.
Background technology
The integrated circuit (IC) design technology is constantly progressive, and people require the integrated circuit operation result more and more accurate, thereby require control circuit more and more accurate.In circuit, same node can be set up signal path by many switches and other a plurality of signal sources, these signal sources may be the different nodes in the circuit, it also may be different power supplys, control circuit must produce certain switching signal and control node and be connected in order with other signal source, usually, the switching signal that control circuit produces can make node and other signal source timesharing connect basically, but because these switching signals are got by same master clock frequency division mostly, thereby all synchronous with master clock, so, rising edge between the different switching signals, trailing edge will occur overlapping, a switch does not also disconnect or does not disconnect fully, and another switch is just closed, and at this moment two signal sources have just coupled together by these switches, cause signal source error to occur, even cause power supply short circuit.In the collector design, too these phenomenons may appear not only in hardware circuit design.So, the circuit computing result just may be inaccurate, even may burn out power supply.
Summary of the invention
In order to solve above-mentioned technical problem of the prior art, the utility model provides a kind of simple in structure, chip occupying area is little, reliability is high a kind of heterogeneous non-overlapping clock circuit, described circuit can be to handling with the synchronous multi-phase clock of master clock, each phase clock rising edge is postponed and trailing edge is not postponed, perhaps each phase clock trailing edge is postponed and rising edge does not promote, thereby guarantee that each phase clock rising edge and trailing edge are not overlapping, obtain heterogeneous non-overlapping clock.For reaching this purpose the utility model by the following technical solutions: described a kind of heterogeneous non-overlapping clock circuit comprises Postponement module, the recurrent pulse generation module, a plurality of reversers and a plurality of rest-set flip-flop, wherein: the input of described Postponement module is connected with one of them input of recurrent pulse generation module, and the output of Postponement module is connected to another input of recurrent pulse generation module; The output of recurrent pulse generation module is connected to the set end of each rest-set flip-flop, the input of each reverser is respectively as the input port of multi-phase clock, the output of each reverser is connected to the reset terminal of each rest-set flip-flop respectively, the output of each rest-set flip-flop is respectively as the output port of heterogeneous non-overlapping clock, each reverser structure is identical, is the signals reverse device of not gate, NAND gate, NOR gate or rest-set flip-flop formation.
When described recurrent pulse generation module be two inputs with or door, rest-set flip-flop is the basic rest-set flip-flop that two NOR gate are formed.
When described recurrent pulse generation module is two input XOR gate, rest-set flip-flop is the basic rest-set flip-flop that two NAND gate are formed.
Described Postponement module can be connecting of the connecting of transmission gate and transmission gate, even level reverser and even level reverser or connecting of even level reverser and transmission gate.
Adopt technique scheme, the utility model only needs a plurality of reversers, same or door or XOR gate, and rest-set flip-flop just can be with the multi-phase clock rising edge synchronous with master clock, and trailing edge effectively separates.
The utility model is simple in structure, cost is lower, and the unfailing performance height, is fit to marketing and uses.
Description of drawings:
Fig. 1 is the non-overlapping clock circuit structure principle chart of three-phase of the present utility model;
Fig. 2 is the structure principle chart of the utility model embodiment one;
Fig. 3 is the structure principle chart of the utility model embodiment two;
Fig. 4 for master clock CLK among the utility model embodiment one and two and import heterogeneous overlapping clock the waveform schematic diagram;
Fig. 5 is the heterogeneous non-overlapping clock signal waveform schematic diagram of Ao, Bo, Co among the utility model embodiment one, CLKA, CLKB, CLKC in CLKA', CLKB', the CLKC' difference corresponding diagram 4;
Fig. 6 is the heterogeneous non-overlapping clock signal waveform schematic diagram of Ao, Bo, Co among the utility model embodiment two, CLKA, CLKB, CLKC in CLKA'', CLKB'', the CLKC'' difference corresponding diagram 4;
Fig. 7 be the rest-set flip-flop formed of two NOR gate of the utility model circuit structure with and corresponding symbol;
Fig. 8 be the rest-set flip-flop formed of two NAND gate of the utility model circuit structure with and corresponding symbol;
Specific embodiment:
Below in conjunction with specific embodiments and the drawings the utility model is further expalined explanation, as shown in Figure 2, embodiment one is the non-overlapping clock circuit of a kind of three-phase, heterogeneous non-overlapping clock circuit and three facies principles are similar, it comprises Postponement module 1, recurrent pulse generation module 2, a plurality of reversers 3 and a plurality of rest-set flip-flop 4, described recurrent pulse generation module 2 is the same or doors of two inputs, trigger 4 is the basic rest-set flip-flop that two NOR gate are formed, each reverser 3 structure is identical, and the input of described Postponement module 1 is connected with recurrent pulse generation module 2 one of them input, and the output of Postponement module 1 is connected to another input of recurrent pulse generation module 2; The output of recurrent pulse generation module 2 is connected to the set end of each rest-set flip-flop 4, the input of each reverser 3 is respectively as the input port of multi-phase clock, the output of each reverser 3 is connected to the reset terminal of each rest-set flip-flop 4 respectively, and the output of each rest-set flip-flop 4 is respectively as the output port of heterogeneous non-overlapping clock.The operation principle of this embodiment is as follows: each phase signals of multi-phase clock is respectively from the input port A of heterogeneous non-overlapping clock circuit, B, the C input, multi-phase clock CLKA, CLKB, the waveform of CLKC and master clock CLK as shown in Figure 4, CLKA, all occurred overlapping between CLKB and CLKC three's rising edge and the trailing edge, master clock CLK is from the master clock input port CK input of heterogeneous non-overlapping clock circuit, the master clock signal that the Postponement module 1 of leading up to obtains postponing is exported to together or door, directly receive together or another input of door on another road, same or two identical parts of input signal of door knob are set to high level, different parts is set to low level, output one-period undersuing, master clock CLK is the low level time of cycle undersuing by the time that Postponement module 1 postpones, the cycle undersuing is received the set end S of rest-set flip-flop 4, CLKA, CLKB, CLKC is respectively by being connected to the reset terminal R of each rest-set flip-flop behind the reverser 3, CLKA, CLKB and CLKC are by passing through together or the retardation time of door less than master clock CLK the time of delay of reverser 3, each rest-set flip-flop 4 respectively the signals reverse that is input to reset terminal R and will on fall along postponing about low level time of negative pulse trailing edge and do not postpone the back and export from output Q, so at heterogeneous non-overlapping output terminal of clock Ao, Bo, Co obtains rising edge, the heterogeneous non-overlapping clock signal that trailing edge is not overlapping, CLKA' as shown in Figure 5, CLKB', CLKC'.Here the heterogeneous non-overlapping clock that produces drives the switch of high level closure, or passes through the switch of reverser rear drive low level closure, can guarantee that another switch is just closed, avoids signal errors and power supply short circuit phenomenon after the switch disconnection.
Embodiment two as shown in Figure 3, it comprises Postponement module 1, recurrent pulse generation module 2, a plurality of reversers 3 and a plurality of rest-set flip-flop 4, described recurrent pulse generation module 2 is two input XOR gate, and each trigger 4 is the basic rest-set flip-flop that two NAND gate are formed, and each reverser 3 structure is identical, the input of described Postponement module 1 is connected with recurrent pulse generation module 2 one of them input, and the output of Postponement module 1 is connected to another input of recurrent pulse generation module 2; The output of recurrent pulse generation module 2 is connected to the set end of each rest-set flip-flop 4, the input of each reverser 3 is respectively as the input port of multi-phase clock, the output of each reverser 3 is connected to the reset terminal of each rest-set flip-flop 4 respectively, and the output of each rest-set flip-flop 4 is respectively as the output port of heterogeneous non-overlapping clock.The operation principle of this embodiment is as follows: each phase signals of multi-phase clock is respectively from the input port A of heterogeneous non-overlapping clock circuit, B, the C input, multi-phase clock CLKA, CLKB, the waveform of CLKC and master clock CLK as shown in Figure 4, CLKA, all occurred overlapping between CLKB and CLKC three's rising edge and the trailing edge, master clock CLK is from the master clock input port CK input of heterogeneous non-overlapping clock circuit, the master clock that the Postponement module 1 of leading up to obtains postponing is exported to XOR gate, an input of XOR gate is received on another road, XOR gate is set to low level to two identical parts of input signal, different parts is set to high level, output one-period positive pulse signal, master clock CLK is the high level time of cycle positive pulse signal by the time that Postponement module 1 postpones, the cycle positive pulse signal is received the set end S of rest-set flip-flop, CLKA, CLKB, CLKC is respectively from input port A, B, the C input is by being connected to the reset terminal R of rest-set flip-flop behind the reverser, CLKA, CLKB, CLKC must be less than the postponement of master clock CLK by XOR gate by the postponement of reverser, rest-set flip-flop respectively the signals reverse that is input to reset terminal R and with trailing edge postpone an about pulse high level time and on fall along do not postpone the back export from output Q', so at output terminals A o, Bo, Co obtains rising edge, the heterogeneous non-overlapping clock signal that trailing edge is not overlapping, CLKA'' as shown in Figure 6, CLKB'', CLKC''.The heterogeneous non-overlapping clock that produces drives the switch of low level closure, or passes through the switch of reverser rear drive high level closure, can guarantee that another switch is just closed, avoids signal errors and power supply short circuit phenomenon after the switch disconnection.
The number of the not overlapping circuit of multi-phase clock comprises among the above embodiment reverser, rest-set flip-flop and input clock only is exemplary, description according to the front, those skilled in the art can recognize now, the utility model can be applied to two-phase and the above not overlapping multi-phase clock signal of rising edge, trailing edge that needs.In fact, this circuit structure can be made independent chip and use, and also can utilize discrete component to build out application.So above embodiment only is better embodiment of the present utility model, but be not the whole of the utility model overlay content, all in the utility model spirit scope with the interior equivalents of being done, all will be in the utility model protection range.
Claims (6)
1. heterogeneous non-overlapping clock circuit, it is characterized in that: it comprises Postponement module (1), recurrent pulse generation module (2), a plurality of reversers (3) and a plurality of rest-set flip-flop (4), each reverser (3) structure is identical, wherein:
The input of described Postponement module (1) is connected with one of them input of recurrent pulse generation module (2), and the output of Postponement module (1) is connected to another input of recurrent pulse generation module (2);
The output of recurrent pulse generation module (2) is connected to the set end of each rest-set flip-flop (4), the input of each reverser (3) is respectively as the input port of multi-phase clock, the output of each reverser (3) is connected to the reset terminal of each rest-set flip-flop (4) respectively, and the output of each rest-set flip-flop (4) is respectively as the output port of heterogeneous non-overlapping clock.
2. described recurrent pulse generation module (2) is the same or doors of two inputs, and trigger (4) is the basic rest-set flip-flop that two NOR gate are formed.
3. heterogeneous non-overlapping clock circuit according to claim 1 is characterized in that: described recurrent pulse generation module (2) is two input XOR gate, and trigger (4) is the basic rest-set flip-flop that two NAND gate are formed.
4. according to claim 2 or 3 described heterogeneous non-overlapping clock circuits, it is characterized in that: described Postponement module (1) is connected for transmission gate and transmission gate.
5. according to claim 2 or 3 described heterogeneous non-overlapping clock circuits, it is characterized in that: described Postponement module (1) is connected for even level reverser and even level reverser.
6. according to claim 2 or 3 described heterogeneous non-overlapping clock circuits, it is characterized in that: described Postponement module (1) is connected for even level reverser and transmission gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320040075 CN203135818U (en) | 2013-01-25 | 2013-01-25 | A multiphase non-overlapping clock circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201320040075 CN203135818U (en) | 2013-01-25 | 2013-01-25 | A multiphase non-overlapping clock circuit |
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| CN203135818U true CN203135818U (en) | 2013-08-14 |
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| CN 201320040075 Withdrawn - After Issue CN203135818U (en) | 2013-01-25 | 2013-01-25 | A multiphase non-overlapping clock circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103166605A (en) * | 2013-01-25 | 2013-06-19 | 湘潭芯力特电子科技有限公司 | Multiphase non-overlapping clock circuit |
-
2013
- 2013-01-25 CN CN 201320040075 patent/CN203135818U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103166605A (en) * | 2013-01-25 | 2013-06-19 | 湘潭芯力特电子科技有限公司 | Multiphase non-overlapping clock circuit |
| CN103166605B (en) * | 2013-01-25 | 2016-04-06 | 江苏芯力特电子科技有限公司 | A kind of heterogeneous non-overlapping clock circuit |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20130814 Effective date of abandoning: 20160406 |
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| C25 | Abandonment of patent right or utility model to avoid double patenting |