CN103208980B - A kind of window voltage comparison means - Google Patents
A kind of window voltage comparison means Download PDFInfo
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Abstract
A kind of window voltage comparison means, comprising: sequence circuit, voltage comparator circuit and logic processing circuit; The clock signal clk frequency division of input is obtained second clock signal and the 3rd clock signal by sequence circuit, and exports second clock signal and the 3rd clock signal to voltage comparator circuit; Voltage comparator circuit comprises selector and comparator, selector according to the control of second clock signal and the 3rd clock signal, bottoming threshold voltage or upper limit threshold voltage; The lower threshold voltage that selector exports by described comparator or upper limit threshold voltage and voltage to be detected compare, and export comparative result to logic processing circuit; Logic processing circuit, according to the triggering of the clock signal clk of input, carries out logical process to the comparative result that voltage comparator circuit exports, and output processing result.The window voltage comparison means that the present invention relates to, has and takies the advantage that circuit area is little, consistency good, quiescent current is little.
Description
Technical field
The present invention relates to voltage compare checkout gear, particularly relate to a kind of window voltage comparison means.
Background technology
Whether in integrated circuit design, relate in particular in automatic gain control circuit, often can need to drop in a certain voltage range the voltage swing of signal to judge, this will use voltage compare testing circuit.
Conventional voltage compare testing circuit is window voltage comparator, as shown in Figure 1, it comprises the first comparator Comp1, the second comparator Comp2 and XOR gate XOR, and voltage vin to be detected inputs the positive input terminal of the first comparator Comp1 and the second comparator Comp2 respectively; The negative input end input lower threshold voltage vth1 of the first comparator Comp1, the negative input end input upper limit threshold voltage vth2 of the second comparator Comp2, power end and the ground end of the first comparator Comp1, the second comparator Comp2 meet vcc and gnd respectively, the output of the first comparator Comp1 is connected to the first input end of XOR gate, the output of the second comparator Comp2 is connected to second input of XOR gate XOR, and the output of XOR gate XOR exports comparative result.This window voltage comparator must use two comparators capping threshold voltage and lower threshold voltage respectively, compares output, to reach the object judging voltage range.
Inventor finds, the window voltage comparator using two comparators to form carries out detection to voltage swing and there is following shortcoming:
1. comparator area occupied is larger;
2. the quiescent current of comparator self is large, thus causes quiescent dissipation larger;
3. the consistency of performance of two comparators is poor.
Summary of the invention
The technical problem of the present invention existing for the window voltage comparison means that solves existing two comparators and form, provides that a kind of area occupied is less, quiescent current is less, the good window voltage comparison means of consistency.
For solving the problems of the technologies described above, the invention provides following technical scheme: sequence circuit, voltage comparator circuit and logic processing circuit; The clock signal clk frequency division of input is obtained second clock signal and the 3rd clock signal by described sequence circuit, and exports second clock signal and the 3rd clock signal to voltage comparator circuit; Described voltage comparator circuit comprises selector and comparator, described selector, according to the control of second clock signal and the 3rd clock signal, and bottoming threshold voltage vth1 or upper limit threshold voltage vth2; Described comparator, the lower threshold voltage vth1 export selector or upper limit threshold voltage vth2 and voltage vin to be detected compares, and exports comparative result to logic processing circuit; Described logic processing circuit, according to the triggering of the clock signal clk of input, carries out logical process to the comparative result that voltage comparator circuit exports, and output processing result.
The window voltage comparison means that the present invention relates to, judged in voltage range by sequence circuit, voltage comparator circuit and logic processing circuit, described voltage comparator circuit only uses a comparator, need to use two comparators in existing window voltage comparator, and circuit area shared by comparator is larger, although other circuit parts of the window voltage comparison means that the present invention relates to have use relevant components and parts, much smaller than the circuit area shared by comparator.Can be there is inconsistent situation when comparing voltage in two comparators, and this situation would not appear in a comparator, in addition, the quiescent current of comparator itself is large, cause quiescent dissipation large, and in the embodiment of the present invention, only use a comparator, therefore quiescent current is less.Therefore, the window voltage comparison means that the present invention relates to has and takies the advantage that circuit area is little, consistency good, quiescent current is little.
Accompanying drawing explanation
Fig. 1 is the window voltage comparison means figure of prior art.
Fig. 2 is the block diagram of the window voltage comparison means of the embodiment of the present invention.
Fig. 3 is the figure of the sequence circuit of window voltage comparison means in the embodiment of the present invention.
Fig. 4 is voltage comparator circuit and the logic processing circuit figure of window voltage comparison means in the embodiment of the present invention.
Fig. 5 is voltage comparator circuit and the logic processing circuit figure of the embodiment of the present invention one window voltage comparison means.
Fig. 6 is voltage comparator circuit and the logic processing circuit figure of the embodiment of the present invention two window voltage comparison means.
Fig. 7 is voltage comparator circuit and the logic processing circuit figure of the embodiment of the present invention three window voltage comparison means.
Embodiment
In order to make technical problem solved by the invention, technical scheme and beneficial effect clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
As shown in Figure 2, be the block diagram of the window voltage comparison means of the embodiment of the present invention, it comprises:
Sequence circuit 1, voltage comparator circuit 2 and logic processing circuit 3; The clock signal clk frequency division of input is obtained second clock signal and the 3rd clock signal by described sequence circuit 1, and exports second clock signal and the 3rd clock signal to voltage comparator circuit 2; Lower threshold voltage vth1 or upper limit threshold voltage vth2 and voltage vin to be detected compares according to second clock signal and the 3rd clock signal by described voltage comparator circuit 2, and exports comparative result to logic processing circuit 3; Described logic processing circuit 3, according to the triggering of the clock signal clk of input, carries out logical process to the comparative result that voltage comparator circuit 2 exports, and output processing result.
Fig. 3 and Fig. 4 is the schematic diagram of the embodiment of the present invention, and this window voltage comparison means comprises sequence circuit, voltage comparator circuit and logic processing circuit.
Described sequence circuit comprises: the first inverter inv1, the first d type flip flop dffr1, the second inverter inv2 and the 3rd inverter inv3; The input receive clock signal clk of the first inverter inv1, the output of the first inverter inv1 exports the input end of clock of the first clock signal clk1 to the first d type flip flop dffr1, the forward output of the first d type flip flop dffr1 is connected with the input of the second inverter inv2, second inverter inv2 exports second clock signal clk2, the input of the 3rd inverter inv3 is connected with the output of the second inverter inv2, exports the 3rd clock signal clk3 according to the second clock signal clk2 that the second inverter inv2 exports.In concrete enforcement, described clock signal clk is square-like clock signal, and to duty ratio no requirement (NR).Described first d type flip flop dffr1 plays two divided-frequency effect, and second clock signal clk2 and the 3rd clock signal clk3 is differential clock signal.
Described voltage comparator circuit comprises comparator Comp and selector, described selector, according to the control of second clock signal clk2 and the 3rd clock signal clk3, and bottoming threshold voltage vth1 or upper limit threshold voltage vth2; Described comparator Comp, the lower threshold voltage vth1 export selector or upper limit threshold voltage vth2 and voltage vin to be detected compares, and exports comparative result to logic processing circuit.
In the present embodiment, voltage comparator circuit only uses a comparator, need to use two comparators in existing window voltage comparator, and circuit area shared by comparator is larger, although other circuit parts in the embodiment of the present invention have use relevant components and parts, much smaller than the circuit area shared by comparator.Can be there is inconsistent situation when comparing voltage in two comparators, and this situation would not appear in a comparator, in addition, the quiescent current of comparator itself is large, cause quiescent dissipation large, and in the embodiment of the present invention, only use a comparator, therefore quiescent current is less.
As shown in Figure 4, described selector comprises the first switch S 1 and second switch S2; First switch S 1 disconnects according to the control of second clock signal clk2 or closes, and the input of the first switch S 1 connects lower threshold voltage vth1, and the output of the first switch S 1 is connected with the negative input end of comparator Comp; Second switch S2 disconnects according to the control of the 3rd clock signal clk3 or closes, and the input of second switch S2 connects upper limit threshold voltage vth2, and the output of second switch S2 is connected with the negative input end of comparator Comp.Voltage vin to be detected is from the input of comparator Comp positive input terminal, and the power end of comparator Comp and ground end meet power supply vcc and ground gnd respectively, and the output of comparator Comp is connected with logic processing circuit.
In concrete enforcement, described first switch and second switch can be CMOS tube, enhancement mode PMOS or enhancement mode NMOS tube.
As shown in Figure 5, be the voltage comparator circuit of window voltage comparison means and the logic processing circuit schematic diagram of the embodiment of the present invention one.First switch of described voltage comparator circuit and second switch are CMOS tube, i.e. the first CMOS tube T1 and the second CMOS tube T2, the input of the first CMOS tube T1 connects lower threshold voltage vth1, the positive control end input second clock signal clk2 of the first cmos transmission gate T1, the negative control end of the first CMOS tube T1 connects the 3rd clock signal clk3, the input of the second CMOS tube T2 connects upper limit threshold voltage vth2, the negative control end of the second CMOS tube T2 connects second clock signal clk2, the positive control end of the second CMOS tube T2 connects the 3rd clock signal clk3, first CMOS tube T1 is connected with the negative input end of comparator Comp with the output of the second CMOS tube T2, voltage vin to be detected connects comparator Comp positive input terminal, the power end of comparator Comp and ground end meet power supply vcc and ground gnd respectively, the output of comparator Comp exports logic processing circuit to as the output of voltage comparator circuit.
As shown in Figure 6, be the voltage comparator circuit of window voltage comparison means and the logic processing circuit schematic diagram of the embodiment of the present invention two.First switch of described voltage comparator circuit and second switch are enhancement mode PMOS, i.e. the first enhancement mode PMOS PMOS1 and the second enhancement mode PMOS PMOS2, the grid of the first enhancement mode PMOS PMOS1 connects second clock signal clk2, the source electrode of the first enhancement mode PMOS PMOS1 connects upper limit threshold voltage vth2, the grid of the second enhancement mode PMOS PMOS2 connects the source electrode connection lower threshold voltage vth1 of the 3rd clock signal clk3 second enhancement mode PMOS PMOS2, first enhancement mode PMOS PMOS1 is connected with the negative input end of comparator Comp with the drain electrode of the second enhancement mode PMOS PMOS2, substrate all meets power supply VCC, voltage vin to be detected connects comparator Comp positive input terminal, power end and the ground end of comparator Comp meet vcc and gnd respectively, the output of comparator Comp exports logic processing circuit to as the output of voltage comparator circuit.
As shown in Figure 7, be the voltage comparator circuit of window voltage comparison means and the logic processing circuit schematic diagram of the embodiment of the present invention three.First switch of described voltage comparator circuit and second switch are enhancement mode NMOS tube, i.e. the first enhancement mode NMOS tube NMOS1 and the second enhancement mode NMOS tube NMOS2, the grid of the first enhancement mode NMOS tube NMOS1 connects the 3rd clock signal clk3, the drain electrode of the first enhancement mode NMOS tube NMOS1 connects upper limit threshold voltage vth2, the grid of the second enhancement mode NMOS tube NMOS2 connects second clock signal clk2, the drain electrode of the second enhancement mode NMOS tube NMOS connects lower threshold voltage vth1, first enhancement mode NMOS tube NMOS1 is connected with the negative input end of comparator Comp with the source electrode of the second enhancement mode NMOS tube NMOS2, the equal ground connection gnd of substrate, voltage vin to be detected connects comparator Comp positive input terminal, power end and the ground end of comparator Comp meet vcc and gnd respectively, the output of comparator Comp exports logic processing circuit to as the output of voltage comparator circuit.
Described logic processing circuit comprises the second d type flip flop dffr2,3d flip-flop dffr3, XOR gate XOR, the D end of the second d type flip flop dffr2 connects the output of described voltage comparator circuit, namely the output of comparator Comp is connect, the reset termination reset signal rst of the second d type flip flop dffr2 and 3d flip-flop dffr3, input end of clock all meets clock signal clk, the forward output of the second d type flip flop dffr2
Connect the D end of 3d flip-flop dffr3 and the first input end of XOR gate XOR, the forward output of 3d flip-flop dffr3 connects second input of XOR gate XOR.
Export to carry out latch to the output of XOR gate XOR, the second d type flip flop dffr2 and 3d flip-flop dffr3 is avoided to occur logical process mistake when triggering due to level saltus step, described logic processing circuit can comprise four d flip-flop dffr4 and time delay module, described time delay module can comprise the 4th inverter inv4 and the 5th inverter inv5, the D end of described four d flip-flop dffr4 is connected with the output of XOR gate XOR, the reset terminal CLR of four d flip-flop dffr4 meets reset signal rst, the forward output of four d flip-flop dffr4 is the output of logic processing circuit, the input of the 4th inverter inv4 of described time delay module connects clock signal clk, the output of the 4th inverter inv4 is connected with the input of the 5th inverter inv5, the input end of clock of the output termination four d flip-flop dffr4 of the 5th inverter inv5.
Described time delay module utilizes the 4th inverter inv4 and the 5th time delay of inverter inv5 to input clock signal clk to make the edging trigger moment of four d flip-flop dffr4 lag behind the trigger instants of the second d type flip flop dffr2 and 3d flip-flop dffr3, ensures that the level of XOR gate XOR output is obtained by the level after the second d type flip flop dffr2 and 3d flip-flop dffr3 triggers.This also means in time delay module can insert even number of inverters in the middle of the 4th inverter inv4 and the 5th inverter inv5, and to obtain more multiple-time delay surplus, its connected mode is constant.
In the present embodiment, described second d type flip flop dffr2,3d flip-flop dffr3 and four d flip-flop dffr4 are the d type flip flop of band set end, and its SET end is set to the level contrary with reset level, does not namely carry out set to it.In the embodiment of the present invention, the second d type flip flop dffr2,3d flip-flop dffr3 and four d flip-flop dffr4 also can use the d type flip flop not with set end to replace completely simultaneously.
According to Fig. 2, Fig. 3 and Fig. 4, the operation principle of the window voltage comparison means that the embodiment of the present invention provides is described below.
During beginning, initial reset signal rst resets to all d type flip flops, and the SET termination fixed level of d type flip flop, does not carry out set, and now XOR gate XOR exports as low level; The clock signal clk of input obtains differential clock signal through the second inverter inv2 and the 3rd inverter inv3 again after two divided-frequency after the first inverter inv1 and the first d type flip flop dffr1, i.e. second clock signal clk2 and the 3rd clock signal clk3, it is used for the conducting of control first switch S 1 and second switch S2 and disconnection.When second clock signal clk2 is high level, 3rd clock signal clk3 is low level, first switch S 1 conducting, second switch S2 disconnects, voltage vin to be detected compares output with lower threshold voltage vth1, because second clock signal clk2 is the two divided-frequency of clock signal clk, namely be between high period at second clock signal clk2, clock signal clk edging trigger second d type flip flop dffr2 shifts the forward output at the second d type flip flop dffr2 the comparative result of voltage vin to be detected and lower threshold voltage vth1; When second clock signal clk2 is low level, 3rd clock signal clk3 is high level, first switch S 1 disconnects, second switch S2 conducting, voltage vin to be detected compares output with upper limit threshold voltage vth2, and be between low period, also have clock signal clk edge-triggered D flip-flop at second clock signal clk2, the comparative result of voltage vin to be detected and upper limit threshold voltage vth2 is transferred in the second d type flip flop dffr2, the forward output level of original second d type flip flop dffr2 is transferred to the forward output of 3d flip-flop dffr3 simultaneously; By the mode of shift register, two comparative results are stored in the second d type flip flop dffr2 and 3d flip-flop dffr3 successively like this, second d type flip flop dffr2 and the output of 3d flip-flop dffr3 are connected first input end and second input of XOR gate XOR respectively, XOR gate XOR exports comparative result, can realize the comparison to window voltage.
In concrete enforcement, can by exporting to carry out latch to the output of XOR gate XOR, the second d type flip flop dffr2 and 3d flip-flop dffr3 is avoided to occur logical process mistake when triggering due to level saltus step, described logic processing circuit also comprises four d flip-flop dffr4, 4th inverter inv4 and the 5th inverter inv5, four d flip-flop dffr4 carries out latch to the output of XOR gate XOR and exports, 4th inverter inv4 and the 5th inverter inv5 makes the edging trigger moment of four d flip-flop dffr4 lag behind the trigger instants of the second d type flip flop dffr2 and 3d flip-flop dffr3 to the time delay of clock signal clk, ensure that the level of XOR gate XOR output is obtained by the level after the second d type flip flop dffr2 and 3d flip-flop dffr3 triggers, logical process mistake is there is when triggering due to level saltus step to avoid the second d type flip flop dffr2 and 3d flip-flop dffr3.Because threshold voltage upper limit threshold voltage vth2 is greater than lower threshold voltage vth1, when voltage vin to be detected is less than lower threshold voltage vth1 or be greater than upper limit threshold voltage vth2, output is 0, when voltage vin to be detected is between lower threshold voltage vth1 and upper limit threshold voltage vth2, output is 1.So just can indicate voltage vin to be measured legibly and whether drop on threshold voltage interval.
A kind of window voltage comparison means that the present invention relates to, realize window voltage by adopting a comparator to compare, owing to only having a comparator, thus compare comprise two comparators at present window voltage comparator its have and take the advantage that circuit area is little, consistency good, quiescent current is little.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. a window voltage comparison means, is characterized in that, comprising: sequence circuit, voltage comparator circuit and logic processing circuit;
The clock signal clk frequency division of input is obtained second clock signal and the 3rd clock signal by described sequence circuit, and exports second clock signal and the 3rd clock signal to voltage comparator circuit;
Described voltage comparator circuit comprises selector and comparator, described selector, according to the control of second clock signal and the 3rd clock signal, and bottoming threshold voltage vth1 or upper limit threshold voltage vth2; Described comparator, the lower threshold voltage vth1 export selector or upper limit threshold voltage vth2 and voltage vin to be detected compares, and exports comparative result to logic processing circuit;
Described logic processing circuit, according to the triggering of the clock signal clk of input, carries out logical process to the comparative result that voltage comparator circuit exports, and output processing result;
Described logic processing circuit comprises the second d type flip flop, 3d flip-flop, XOR gate,
The D end of the second d type flip flop connects the output of described voltage comparator circuit,
The reset termination reset signal rst of the second d type flip flop and 3d flip-flop, input end of clock all connects clock signal clk, the forward output of the second d type flip flop connects the D end of 3d flip-flop and the first input end of XOR gate, the forward output of 3d flip-flop connects the second input of XOR gate, the output Output rusults of XOR gate.
2. window voltage comparison means according to claim 1, is characterized in that, described sequence circuit comprises: the first inverter, the first d type flip flop, the second inverter and the 3rd inverter;
The input receive clock signal of the first inverter, the output of the first inverter exports the input end of clock of the first clock signal to the first d type flip flop, the forward output of the first d type flip flop is connected with the input of the second inverter, second inverter exports second clock signal, the input of the 3rd inverter is connected with the output of the second inverter, exports the 3rd clock signal according to the second clock signal that the second inverter exports.
3. window voltage comparison means according to claim 1, is characterized in that, described clock signal clk is square-like clock signal.
4. window voltage comparison means according to claim 1, is characterized in that: described selector comprises the first switch and second switch;
First switch disconnects according to the control of second clock signal or closes, and the input of the first switch connects lower threshold voltage, and the output of the first switch is connected with the negative input end of comparator;
Second switch disconnects according to the control of the 3rd clock signal or closes, and the input of second switch connects upper limit threshold voltage, and the output of second switch is connected with the negative input end of comparator.
5. window voltage comparison means according to claim 4, is characterized in that, described first switch and second switch are CMOS tube, enhancement mode PMOS or enhancement mode NMOS tube.
6. window voltage comparison means according to claim 1, is characterized in that, described logic processing circuit comprises four d flip-flop and time delay module further,
The D end of described four d flip-flop is connected with the output of XOR gate, the reset termination reset signal rst of four d flip-flop, and the forward output of four d flip-flop is the output of logic processing circuit,
Time delay module input connects clock signal clk, and the output of time delay module connects the input end of clock of four d flip-flop.
7. window voltage comparison means according to claim 6, is characterized in that, described time delay module comprises the 4th inverter and the 5th inverter further,
The input of described 4th inverter connects clock signal clk, and the output of the 4th inverter is connected with the input of the 5th inverter, the input end of clock of the output termination four d flip-flop of the 5th inverter.
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| CN104237606B (en) * | 2014-09-09 | 2017-09-29 | 四川迪佳通电子有限公司 | A kind of infrared receiving terminal detection circuit and equipment |
| US10153757B2 (en) * | 2015-03-06 | 2018-12-11 | Microchip Technology Incorporated | Three input comparator |
| CN105162441B (en) * | 2015-09-25 | 2017-11-17 | 中国电子科技集团公司第二十四研究所 | A kind of high-speed low-power-consumption dynamic comparer |
| CN108880211A (en) * | 2018-08-31 | 2018-11-23 | 上海艾为电子技术股份有限公司 | A kind of sawtooth generator, DC-DC converter and electronic equipment |
| CN111400074A (en) * | 2019-01-02 | 2020-07-10 | 珠海格力电器股份有限公司 | Watchdog simulating device and control method thereof |
| CN115334300B (en) * | 2022-08-09 | 2023-10-13 | 慷智集成电路(上海)有限公司 | Line fault detection module and vehicle-mounted video transmission chip |
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| CN101231890A (en) * | 2007-01-24 | 2008-07-30 | 松下电器产业株式会社 | Analog voltage latch |
| CN101814919A (en) * | 2009-02-24 | 2010-08-25 | 恩益禧电子股份有限公司 | Analog-digital converter |
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| DE10156026B4 (en) * | 2001-11-15 | 2007-02-22 | Advanced Micro Devices, Inc., Sunnyvale | Comparator circuit and method for determining a time interval |
| US7157945B2 (en) * | 2004-12-06 | 2007-01-02 | Texas Instruments Incorporated | Window comparator and method of providing a window comparator function |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101231890A (en) * | 2007-01-24 | 2008-07-30 | 松下电器产业株式会社 | Analog voltage latch |
| CN101814919A (en) * | 2009-02-24 | 2010-08-25 | 恩益禧电子股份有限公司 | Analog-digital converter |
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Address after: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee after: BYD Semiconductor Co.,Ltd. Address before: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee before: SHENZHEN BYD MICROELECTRONICS Co.,Ltd. Address after: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee after: BYD Semiconductor Co.,Ltd. Address before: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee before: BYD Semiconductor Co.,Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151209 |
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| CF01 | Termination of patent right due to non-payment of annual fee |