CN209267548U - A kind of quick low-power consumption single ended interfaces - Google Patents
A kind of quick low-power consumption single ended interfaces Download PDFInfo
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- CN209267548U CN209267548U CN201821589723.XU CN201821589723U CN209267548U CN 209267548 U CN209267548 U CN 209267548U CN 201821589723 U CN201821589723 U CN 201821589723U CN 209267548 U CN209267548 U CN 209267548U
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- push
- collision detection
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- detection module
- pull configuration
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Abstract
The utility model discloses a kind of quick low-power consumption single ended interfaces, including push-pull configuration and collision detection module, push-pull configuration includes PMOS tube and NMOS tube, and collision detection circuit module includes two comparators, is also possible to the phase inverter or Schmitt trigger of different threshold values.The utility model uses push-pull configuration output end, does not all have DC channel power consumption in logic high and low level, low in energy consumption；Working frequency is high, at least high an order of magnitude of signal frequency.Collision detection module is had additional simultaneously, more host contention bus is avoided, can not determine that bus state problem, bus state detection circuit structure are simpler.
Description
Technical field
The utility model relates to a kind of single ended interfaces more particularly to a kind of quick low-power consumption single ended interfaces.
Background technique
Traditional single ended interfaces (I2C) include two signal lines, a clock cable, a data signal wire.Such as figure
Shown in 1, the internal circuit of data-signal uses open drain structure, the plug-in pull-up resistor of signal wire.Why open is used
The additional pull-up resistor of drain structure is in order to realize more host shared buses, and convenient for checking bus state.
The high level of data path is realized by pull-up resistor, causes rising edge will not quickly, interface frequency will be by
Limitation, can not be too fast.The pull-down circuit (open drain) of low level close to the inner portion is realized, but when drop-down, pull-up resistor is leaking electricity,
Electric current is consumed, the slow failing edge time is also dragged.Here it needs to solve there are three problem, one is to shorten rising time；Another
It is pull-up access conducting when avoiding failing edge；Finally also have the problem that bus state detects.
Utility model content
Goal of the invention: in view of the above problems, the utility model proposes a kind of quick low-power consumption single ended interfaces, conflict is increased
Detection module and push-pull configuration.
Technical solution: to realize above-mentioned purpose of design, the technical scheme adopted by the utility model is a kind of quickly low function
Single ended interfaces are consumed, including push-pull configuration and collision detection module, data-signal are exported through push-pull configuration, while using collision detection
Module check bus state.
Further, the push-pull configuration includes PMOS tube and NMOS tube, and the source electrode of PMOS tube connects input voltage VDD,
The drain electrode of the drain electrode connection NMOS tube of PMOS tube, tie point is output signal VOUT, the source electrode ground voltage GND of NMOS tube；
Collision detection module exports enable signal OE, and the input signal VIN for exporting enable signal OE and push-pull configuration connects after NAND gate
It is connected to the control electrode of PMOS tube；Enable signal OE is exported through NOT gate, is connected after nor gate with the input signal VIN of push-pull configuration afterwards
It is connected to the control electrode of NMOS tube.
Further, the collision detection module includes two voltage comparators, and the cathode of first voltage comparator inputs
End connection threshold value Vt1, the output signal VOUT of electrode input end connection host, an input of output end the first XOR gate of connection
End；The negative input of second voltage comparator connects threshold value Vt2, the output signal VOUT of electrode input end connection host, output
One input terminal of the second XOR gate of end connection；Another input of another input terminal and the second XOR gate of the first XOR gate
The common connection input signal VIN in end, the output of two XOR gates is by exporting enable signal OE after one or logic gate.
Further, the threshold value of first voltage comparator is Vt1, the threshold value of second voltage comparator is Vt2, Vt1<Vt2。
Further, the different phase inverter of threshold value also can be used in the voltage comparator of the collision detection module or this is close
Special trigger substitution.
The utility model has the advantages that having the advantage that compared with prior art: push-pull configuration output end is used, in logic high and low
Level does not all have DC channel power consumption, low in energy consumption；Working frequency is high, at least high an order of magnitude of signal frequency.There is collision detection
Module avoids more host contention bus, can not determine that bus state problem, bus state detection circuit structure are simpler.
Detailed description of the invention
Fig. 1 is the schematic diagram of single ended interfaces in the prior art；
Fig. 2 is the schematic diagram of quick low-power consumption single ended interfaces described in the utility model；
Fig. 3 is the schematic diagram of collision detection module.
Specific embodiment
The technical solution of the utility model is further described with reference to the accompanying drawings and examples.
As shown in Fig. 2, quick low-power consumption single ended interfaces described in the utility model, increase MP1 on original circuit base,
Push-pull configuration is formed, while increasing a collision detection module.
With push-pull configuration, all there is no DC channel power consumption in logic high and low level, low in energy consumption and working frequency is high.
There is collision detection module, avoid more host contention bus, can not determine bus state problem, bus state detection circuit structure is more
Simply.
Quick low-power consumption single ended interfaces of the present invention include push-pull configuration, collision detection module and some basic logics
Door, push-pull configuration includes PMOS tube MP1 and NMOS tube MN1.The source electrode of PMOS tube connects input voltage VDD, the drain electrode of PMOS tube
The drain electrode of NMOS tube is connected, tie point is output signal VOUT, the source electrode ground voltage GND of NMOS tube.
As shown in figure 3, collision detection circuit module includes two comparators and some logic gates, it is also possible to different threshold values
Phase inverter or Schmitt trigger.The threshold value of first voltage comparator is Vt1, the threshold value of second voltage comparator is Vt2,
Make Vt1<Vt2.The negative input input connection threshold value V of first voltage comparatort1, electrode input end input connection host
VOUT, output end connect an input terminal of the first XOR gate.The negative input input connection threshold value of second voltage comparator
Vt2, the VOUT of electrode input end input connection host, an input terminal of output end the second XOR gate of connection.First XOR gate
Another input terminal of another input terminal and the second XOR gate connects input signal VIN jointly, and the output of two XOR gates is logical
Become output enable signal OE after crossing one or logic gate.
As shown in Fig. 2, the input signal VIN of output enable signal OE and push-pull configuration is connected to PMOS tube after NAND gate
Control electrode.It exports enable signal OE and is connected to NMOS tube MN1 after nor gate through the input signal VIN of NOT gate and push-pull configuration
Control electrode.
VIN is the input of push-pull configuration, is equal to VOUT in logic, that is, VIN=1, MP1 are connected, MN1 shutdown, VOUT
=1.Similarly VIN=0, MP1 shutdown, MN1 conducting, VOUT=0.When exporting VOUT high-impedance state, MP1, MN1 is turned off.
When collision detection circuit module works normally, VOL<Vt1, VOH>Vt2.When bus clashes, two hosts are all
The pull-up MP1 of output state, a host is opened, and the drop-down MN1 of another host is opened, and VOUT is V at this timeCD, VCD=VDD*
RMN1/(RMP1+RMN1), adjustment circuit makes Vt1<VCD<Vt2.When entering conflict situation, VOUT is kept are as follows: Vt1<VCD<Vt2, slave is defeated
High-impedance state out, abandons the control to bus, and host regains bus.
Quick low-power consumption single ended interfaces described in the utility model, in normal condition, the not upper pull-down circuit of bus is simultaneously
Conducting, when exporting low level, collision detection module detects VOUT while being lower than Vt1And Vt2.Two Schmitt trigger are defeated
It is all low level out.When exporting high level, collision detection module detects VOUT simultaneously above Vt1And Vt2.Two Schmitt
Trigger output is all high level.
Under abnormality, bus has upper pull-down circuit to simultaneously turn on, bus voltage Vt1<VCD<Vt2.Two detection circuits one
A output high level, an output low level, conflict situation are set up.
The utility model uses push-pull configuration output end, does not all have DC channel power consumption in logic high and low level,
It is low in energy consumption；Working frequency is high, at least high an order of magnitude of signal frequency.Collision detection module is had additional simultaneously, avoids more hosts
Contention bus can not determine that bus state problem, bus state detection circuit structure are simpler.
Claims (3)
1. a kind of quick low-power consumption single ended interfaces, which is characterized in that including push-pull configuration and collision detection module, data-signal warp
Push-pull configuration output, while using collision detection module check bus state；
The push-pull configuration includes PMOS tube and NMOS tube, and the source electrode of PMOS tube connects input voltage VDD, and the drain electrode of PMOS tube connects
The drain electrode of NMOS tube is connect, tie point is output signal VOUT, the source electrode ground voltage GND of NMOS tube；
Collision detection module exports enable signal OE, exports the input signal VIN of enable signal OE and push-pull configuration through NAND gate
It is connected to the control electrode of PMOS tube afterwards；Enable signal OE is exported through NOT gate, afterwards with the input signal VIN of push-pull configuration through nor gate
It is connected to the control electrode of NMOS tube afterwards；
The collision detection module includes two voltage comparators, and the negative input of first voltage comparator connects threshold value Vt1,
Electrode input end connects the output signal VOUT of host, and output end connects an input terminal of the first XOR gate；
The negative input of second voltage comparator connects threshold value Vt2, electrode input end connects the output signal VOUT of host, defeated
Outlet connects an input terminal of the second XOR gate；
Another input terminal of first XOR gate and another input terminal of the second XOR gate connect input signal VIN jointly, and two
The output of a XOR gate is by exporting enable signal OE after one or logic gate.
2. quick low-power consumption single ended interfaces according to claim 1, which is characterized in that the threshold value of first voltage comparator is
Vt1, the threshold value of second voltage comparator is Vt2, Vt1<Vt2。
3. quick low-power consumption single ended interfaces according to claim 1, which is characterized in that the voltage of the collision detection module
Comparator can be threshold value different phase inverter or Schmitt trigger.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821589723.XU CN209267548U (en) | 2018-09-28 | 2018-09-28 | A kind of quick low-power consumption single ended interfaces |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821589723.XU CN209267548U (en) | 2018-09-28 | 2018-09-28 | A kind of quick low-power consumption single ended interfaces |
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| Publication Number | Publication Date |
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| CN209267548U true CN209267548U (en) | 2019-08-16 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109104182A (en) * | 2018-09-28 | 2018-12-28 | 南京观海微电子有限公司 | A kind of quick low-power consumption single ended interfaces |
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2018
- 2018-09-28 CN CN201821589723.XU patent/CN209267548U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109104182A (en) * | 2018-09-28 | 2018-12-28 | 南京观海微电子有限公司 | A kind of quick low-power consumption single ended interfaces |
| WO2020063145A1 (en) * | 2018-09-28 | 2020-04-02 | 南京观海微电子有限公司 | Fast single-ended interface with low power consumption |
| CN109104182B (en) * | 2018-09-28 | 2024-01-05 | 南京观海微电子有限公司 | Quick low-power consumption single-ended interface |
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