CN109684762B - Chip and setting circuit of pin thereof - Google Patents
Chip and setting circuit of pin thereof Download PDFInfo
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- CN109684762B CN109684762B CN201811652719.8A CN201811652719A CN109684762B CN 109684762 B CN109684762 B CN 109684762B CN 201811652719 A CN201811652719 A CN 201811652719A CN 109684762 B CN109684762 B CN 109684762B
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- phase inverter
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- nand gate
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
Abstract
The invention discloses a chip and a setting circuit of pins of the chip, wherein the setting circuit comprises a switching tube, a first NAND gate module, a first phase inverter, a second phase inverter and a circuit output end; the drain electrode of the switch tube is respectively and electrically connected with the input pin of the chip and the input end of the first phase inverter, the grid electrode of the switch tube is electrically connected with the output end of the first NAND gate module, and the source electrode of the switch tube is grounded; the output end of the first phase inverter is electrically connected with the input end of the second phase inverter; the first input end of the first NAND gate module is electrically connected with the power-on reset end of the chip, and the second input end of the first NAND gate module is electrically connected with the output end of the second phase inverter and the circuit output end respectively. The invention realizes the function which can be realized only by huge layout area with less analog devices and smaller layout area, saves the layout area under the condition of ensuring the function of setting the default value of chip pins to be 0, and has the advantages of high integration level, low cost and the like, and the static power consumption is basically zero.
Description
Technical Field
The invention relates to the technical field of circuit design, in particular to a chip and a setting circuit of pins of the chip.
Background
With the development of integrated circuit technology, electrically Erasable Programmable Read Only Memory (EEPROM) has been widely used. An I2C (Inter-Integrated Circuit) protocol is used between the EEPROM chip as the slave and the host to exchange data. Since the I2C protocol allows multiple slaves to be mounted on the bus, each slave is required to have its own independent slave identification address for identification by the master. Usually, an EEPROM chip has a 3-bit identification address, so that at most 8 chips can be mounted on a bus at the same time, and the 3-bit identification address pin needs to set a default value (i.e., a default value of a chip pin) to ensure that the identification address is 000 when the pin does not receive an external signal, i.e., the static power consumption of the chip pin is 0, thereby achieving the purpose of reducing the power consumption.
Currently, as shown IN fig. 1, the identification address of the chip PIN is 000 by using a large number of resistors (R1-Rn) at the chip input PIN (PIN _ IN) to be grounded IN series; as shown IN fig. 2, the identification address of the chip PIN is made 000 by using a large number of MOS (metal-oxide-semiconductor) transistors (M1-Mn) connected IN series to ground at the chip input PIN (PIN _ IN). In order to achieve the purpose of static power consumption of a chip pin which is almost 0, the two modes both need to adopt a plurality of devices, so that a large amount of layout area is occupied, the integration level of the chip is greatly reduced, and the cost is high.
Disclosure of Invention
The invention aims to solve the technical problems that in the prior art, a default value of a chip pin is 0 by using a large number of resistors or a mode that MOS (metal oxide semiconductor) tubes are grounded in series, so that the defects of low integration level, high cost and the like exist, and the chip and the pin setting circuit thereof are provided.
The invention solves the technical problems through the following technical scheme:
the invention provides a setting circuit of a chip pin, which comprises a switching tube, a first NAND gate module, a first phase inverter, a second phase inverter and a circuit output end, wherein the switching tube is connected with the first NAND gate module;
the drain electrode of the switch tube is respectively and electrically connected with the input pin of the chip and the input end of the first phase inverter, the grid electrode of the switch tube is electrically connected with the output end of the first NAND gate module, and the source electrode of the switch tube is grounded;
the output end of the first phase inverter is electrically connected with the input end of the second phase inverter;
and a first input end of the first NAND gate module is electrically connected with an electrifying reset end of the chip, and a second input end of the first NAND gate module is respectively electrically connected with an output end of the second phase inverter and an output end of the circuit.
Preferably, the setting circuit further comprises a second nand gate module, a third inverter and a fourth inverter;
the input end of the third phase inverter is electrically connected with the pulse signal end of the chip, and the output end of the third phase inverter is electrically connected with the third input end of the second NAND gate module;
a fourth input end of the second NAND gate module is electrically connected with an upper power reset end of the chip, and an output end of the second NAND gate module is electrically connected with an input end of the fourth phase inverter;
an output end of the fourth inverter is electrically connected to the first input end of the first nand gate module.
Preferably, when the input pin of the chip is at a high level, the output end of the circuit outputs a high level;
and when the input pin of the chip is in a suspended state or the input pin of the chip inputs a low level, the output end of the circuit outputs the low level.
Preferably, the switching tube is an MOS tube.
Preferably, the switch tube is an NMOS (N-type metal-oxide-semiconductor) tube.
The invention also provides a chip which comprises the chip pin setting circuit.
The positive progress effects of the invention are as follows:
according to the invention, the traditional circuit design of connecting a large number of resistors or MOS (metal oxide semiconductor) tubes in series is replaced, the function which can be realized only by a huge layout area is realized by matching a small number of analog devices with time sequence control and a small layout area, the layout area is saved under the condition of ensuring the function of setting the default value of a chip pin to be 0, and the purposes of higher integration level and lower cost are realized; in the aspect of power consumption, the instantaneous power consumption is basically zero in the whole working process, so that the aim of 0 static power consumption is fulfilled, and the power consumption is effectively reduced.
Drawings
Fig. 1 is a first structural diagram of a conventional chip pin setting circuit.
Fig. 2 is a schematic diagram of a second structure of a conventional chip pin setting circuit.
Fig. 3 is a schematic structural diagram of a chip pin arrangement circuit according to embodiment 1 of the present invention.
Fig. 4 is a schematic structural diagram of a circuit for setting chip pins according to embodiment 2 of the present invention.
Fig. 5 is a schematic diagram of timing signals in a circuit for setting chip pins according to embodiment 2 of the present invention.
Detailed Description
The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.
Example 1
As shown in fig. 3, the setting circuit of the chip pin of the present embodiment includes a switch tube M, a first nand gate module I1, a first inverter I2, a second inverter I3, and a circuit output end OUT. Wherein, the switching tube M is an MOS tube.
The drain electrode of the switching tube M is respectively and electrically connected with an input PIN PIN _ IN of the chip and the input end of the first phase inverter I2, the grid electrode of the switching tube M is electrically connected with the output end of the first NAND gate module I1, and the source electrode of the switching tube M is grounded;
the output end of the first inverter I2 is electrically connected with the input end of the second inverter I3;
the first input end of the first nand gate module I1 is electrically connected to the power-on reset port of the chip, and the second input end of the first nand gate module I1 is electrically connected to the output end of the second inverter I3 and the circuit output end OUT, respectively.
The circuit of the present embodiment can realize: when the input PIN PIN _ IN of the chip is IN a high level, the output end OUT of the circuit outputs a high level; when the input PIN _ IN of the chip is IN a floating state or the input PIN _ IN of the chip inputs a low level, the output terminal OUT of the circuit outputs a low level.
The circuit provided by the embodiment replaces the traditional circuit design of connecting a large number of resistors or MOS (metal oxide semiconductor) tubes in series, realizes the function which can be realized only by a huge layout area in the past by matching a small number of analog devices with time sequence control and a small layout area, saves the layout area under the condition of ensuring the function of setting the default value of a chip pin to be 0, and realizes the purposes of higher integration level and lower cost; in the aspect of power consumption, the instantaneous power consumption is basically zero in the whole working process, so that the aim of 0 static power consumption is fulfilled, and the power consumption is effectively reduced.
Example 2
As shown in fig. 4, the circuit for setting chip pins of this embodiment is a further improvement of embodiment 1, specifically:
the switch tube M is an NMOS tube.
The setting circuit further comprises a second NAND gate module I4, a third inverter I5 and a fourth inverter I6.
The input end of the third phase inverter I5 is electrically connected with a pulse SIGNAL end SIGNAL of the chip, and the output end of the third phase inverter I5 is electrically connected with the third input end of the second NAND gate module I4;
the pulse SIGNAL of the pulse SIGNAL terminal SIGNAL may be a detection SIGNAL generated at a START stage (START stage) IN the I2C protocol, or may be another self-made pulse SIGNAL as long as it is before the system detects the input state of the input PIN _ IN of the chip.
A fourth input end of the second nand-gate module I4 is electrically connected with an upper power reset port of the chip, and an output end of the second nand-gate module I4 is electrically connected with an input end of a fourth inverter I6;
the output end of the fourth inverter I6 is electrically connected to the first input end of the first nand gate module I1.
The first nand gate module I1, the first inverter I2, the second inverter I3, the second nand gate module I4, the third inverter I5, and the fourth inverter I6 may all be CMOS (complementary metal oxide semiconductor) devices.
The operation principle of the setting circuit of the present embodiment is explained in detail below:
as shown in fig. 5, the timing SIGNAL of the power-on reset port of the chip, the system detection timing SIGNAL corresponding to the START stage of the I2C protocol of the pulse SIGNAL terminal SIGNAL, and the timing SIGNAL corresponding to the switch M are respectively shown.
Considering that when the parasitic capacitance of the input PIN _ IN of the chip is relatively large, the discharging time of the parasitic capacitance by using the reset signal of the power-on reset port alone may be insufficient, IN this embodiment, the reset signal of the power-on reset port of the chip IN the power-on stage is used to open the switch tube M (corresponding to the stage a IN fig. 5), and then the system IN the START stage of the I2C protocol is used to detect the signal switch tube M (corresponding to the stage b IN fig. 5), that is, the input PIN _ IN of the chip IN the floating state (suspended state) is better pulled down by sequentially using two signals to open the switch tube M.
The first nand gate module I1, the first inverter I2 and the second inverter I3 form a latch structure with the same-direction output, so that a level signal of an input PIN _ IN of the chip is equal to a level signal of an output terminal OUT of the circuit, and the setting circuit can only latch a state of PIN _ IN = 0.
Through the width-length ratio of rational design switch tube M, circuit output OUT can not be pulled down GND (low level) when guaranteeing the level signal of the input PIN PIN _ IN of chip for VDD (high level), and can pull down GND completely to circuit output OUT when the input PIN PIN _ IN of chip is IN the floating state, promptly:
when PIN _ IN = VDD, OUT = VDD after the switch tube M is turned on and off;
when PIN _ IN = floating, OUT = GND after the switch tube M is turned on and off;
when PIN _ IN = GND, OUT = GND after the switching tube M is turned on and off.
Therefore, the setting circuit of the embodiment has no direct current path under the condition that the input PIN _ IN of the chip is IN the three input states, so that the aim of zero static power consumption is fulfilled.
The circuit provided by the embodiment replaces the traditional circuit design of serially grounding a large number of resistors or MOS (metal oxide semiconductor) tubes, realizes the function which can be realized only by a huge layout area in the past by matching a small number of analog devices with time sequence control and a small layout area, saves the layout area under the condition of ensuring the function of setting the default value of a chip pin to be 0, and realizes the purposes of higher integration level and lower cost; in the aspect of power consumption, the instantaneous power consumption is basically zero in the whole working process, so that the aim of 0 static power consumption is fulfilled, and the power consumption is effectively reduced.
Example 3
The chip of the present embodiment includes the setting circuit of the chip pin in embodiment 1 or embodiment 2.
The chip in the embodiment comprises a setting circuit of the chip pin, so that the function of setting the default value of the pin of the chip to 0 is ensured, and the chip has the advantages of improving the integration level of the chip, reducing the cost and the like.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that these are by way of example only, and that the scope of the invention is defined by the appended claims. Various changes or modifications to these embodiments can be made by those skilled in the art without departing from the principle and spirit of this invention, and these changes and modifications all fall into the scope of this invention.
Claims (5)
1. A setting circuit of a chip pin is characterized by comprising a switch tube, a first NAND gate module, a first phase inverter, a second phase inverter and a circuit output end;
the drain electrode of the switch tube is respectively and electrically connected with the input pin of the chip and the input end of the first phase inverter, the grid electrode of the switch tube is electrically connected with the output end of the first NAND gate module, and the source electrode of the switch tube is grounded;
the output end of the first phase inverter is electrically connected with the input end of the second phase inverter;
a first input end of the first NAND gate module is electrically connected with an upper power reset end of the chip, and a second input end of the first NAND gate module is electrically connected with an output end of the second phase inverter and an output end of the circuit respectively;
when the input of an input pin of the chip is at a high level, the output end of the circuit outputs the high level;
and when the input pin of the chip is in a suspended state or the input pin of the chip inputs a low level, the output end of the circuit outputs the low level.
2. The chip pin setting circuit according to claim 1, further comprising a second nand gate module, a third inverter and a fourth inverter;
the input end of the third phase inverter is electrically connected with the pulse signal end of the chip, and the output end of the third phase inverter is electrically connected with the third input end of the second NAND gate module;
a fourth input end of the second NAND gate module is electrically connected with an upper power reset end of the chip, and an output end of the second NAND gate module is electrically connected with an input end of the fourth phase inverter;
an output end of the fourth inverter is electrically connected with the first input end of the first nand gate module.
3. The chip pin setting circuit according to claim 1, wherein the switching tube is a MOS tube.
4. The chip pin setting circuit according to claim 1, wherein the switch tube is an NMOS tube.
5. A chip comprising the setting circuit of the chip pin according to any one of claims 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811652719.8A CN109684762B (en) | 2018-12-28 | 2018-12-28 | Chip and setting circuit of pin thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811652719.8A CN109684762B (en) | 2018-12-28 | 2018-12-28 | Chip and setting circuit of pin thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109684762A CN109684762A (en) | 2019-04-26 |
| CN109684762B true CN109684762B (en) | 2023-03-24 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201811652719.8A Active CN109684762B (en) | 2018-12-28 | 2018-12-28 | Chip and setting circuit of pin thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112218513B (en) * | 2020-10-13 | 2023-08-22 | Oppo广东移动通信有限公司 | Chip, antenna module and terminal |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN2785260Y (en) * | 2005-03-22 | 2006-05-31 | 苏州市华芯微电子有限公司 | Low power-consuming, high reliability remote controller chip keystroke input port circuit |
| KR101743115B1 (en) * | 2010-11-02 | 2017-06-02 | 삼성전자 주식회사 | Voltage detection device and Semiconductor device having the same |
| CN103023484A (en) * | 2012-12-03 | 2013-04-03 | 无锡海威半导体科技有限公司 | Ultra-low power consumption key scanning state selection circuit |
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