CN110166040B - IO multiplexing circuit, integrated circuit and control method - Google Patents
IO multiplexing circuit, integrated circuit and control method Download PDFInfo
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- CN110166040B CN110166040B CN201910274614.1A CN201910274614A CN110166040B CN 110166040 B CN110166040 B CN 110166040B CN 201910274614 A CN201910274614 A CN 201910274614A CN 110166040 B CN110166040 B CN 110166040B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
Abstract
The invention discloses an IO multiplexing circuit, an integrated circuit and a control method, wherein the IO multiplexing circuit comprises a first NAND gate, a second NAND gate, a NOT gate, a push-pull circuit, a first switch tube and a second switch tube, wherein the third input end of the first NAND gate is connected with the output end of the second NAND gate, the first input end of the second NAND gate is connected with the second input end of the first NAND gate, and the output end of the second NAND gate is respectively connected with the third input end of the first NAND gate and the input end of the NOT gate. The IO multiplexing circuit in the embodiment of the invention can respectively realize the functions of push-pull output, open-drain output, high-impedance state output, pull-up input, pull-down input and the like by receiving the open-drain-push-pull selection signal, the input-output selection signal, the pull-up control signal and the pull-down control signal, can realize the functions of a plurality of circuits by only one circuit, and saves the hardware cost. The invention is widely applied to the technical field of electronic circuits.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to an IO multiplexing circuit, an integrated circuit and a control method.
Background
IO is an English abbreviation for Output and Output (Input/Output). The IO circuit is an important component of an electronic circuit, particularly an integrated circuit, in which an internal core of the integrated circuit is connected with a peripheral circuit to perform functions of level matching, impedance transformation, power amplification, protection and the like. In practical applications, peripheral circuits connected to the integrated circuit have different properties, for example, some peripheral circuits belong to a load, some peripheral circuits belong to a power amplifier circuit, and the like, and different peripheral circuits are respectively suitable for IO modes such as push-pull output, open-drain output, pull-up input, pull-down input, and the like. However, the functions of the existing IO circuits, especially the circuits inside the integrated circuit, are determined by the hardware structures of the existing IO circuits, and if the integrated circuit is to realize a plurality of different IO modes, such as push-pull output, open-drain output, pull-up input, pull-down input, and the like, a plurality of different groups of IO circuits are required to be arranged, so that the hardware cost is increased. Especially, in the integrated circuit design and production process, the IO circuit needs to occupy a larger layout area, and if a plurality of groups of IO circuits are designed, the design difficulty and the manufacturing cost are greatly increased.
Disclosure of Invention
In order to solve the above technical problem, an object of the present invention is to provide an IO multiplexing circuit, an integrated circuit, and a control method.
In one aspect, an embodiment of the present invention includes an IO multiplexing circuit, including a first nand gate, a second nand gate, a not gate, a push-pull circuit, a first switch tube, and a second switch tube;
the first NAND gate is provided with a first input end, a second input end and a third input end; the third input end of the first NAND gate is connected with the output end of the second NAND gate;
the second NAND gate is provided with a first input end and a second input end; the first input end of the second NAND gate is connected with the second input end of the first NAND gate, and the output end of the second NAND gate is respectively connected with the third input end of the first NAND gate and the input end of the NOT gate;
the push-pull circuit is provided with a first input end and a second input end; the first input end of the push-pull circuit is connected with the output end of the first NAND gate; a second input end of the push-pull circuit is connected with an output end of the NOT gate;
the output end of the push-pull circuit is respectively connected with the second end of the first switch tube and the first end of the second switch tube; the first end of the first switch tube is connected to a first power supply, and the second end of the second switch tube is grounded.
Further, the push-pull circuit comprises a third switching tube and a fourth switching tube;
the control end of the third switching tube is used as the first input end of the push-pull circuit, the first end of the third switching tube is connected to the first power supply, and the second end of the third switching tube is used as the output end of the push-pull circuit;
the control end of the fourth switching tube is used as a second input end of the push-pull circuit; and a first end of the fourth switching tube is connected with a second end of the third switching tube, and a second end of the fourth switching tube is grounded.
Further, the IO multiplexing circuit further includes a fifth switching tube and a sixth switching tube; the control end and the first end of the fifth switch tube are both connected to a first power supply, the second end of the fifth switch tube is connected with the first end of the sixth switch tube, and the control end and the second end of the sixth switch tube are both grounded.
Further, the IO multiplexing circuit further includes a first level shift module and a second level shift module; the first level conversion module is connected in series between the output end of the first nand gate and the first input end of the push-pull circuit, and the second level conversion module is connected in series between the output end of the not gate and the second input end of the push-pull circuit.
Further, the IO multiplexing circuit further includes a third level shift module and a fourth level shift module; the output end of the third level conversion module is connected with the control end of the first switch tube, and the output end of the fourth level conversion module is connected with the control end of the second switch tube.
Further, the IO multiplexing circuit further includes a fifth level shift module and an inverting module; the input end of the fifth level conversion module is connected with the output end of the push-pull circuit, and the output end of the fifth level conversion module is connected with the input end of the phase inversion module.
Further, the fifth level shift module includes a seventh switching tube, an eighth switching tube, a ninth switching tube, a tenth switching tube, an eleventh switching tube and a twelfth switching tube;
a first end of the seventh switching tube is connected to a second power supply, a second end of the seventh switching tube is respectively connected with a first end of the eighth switching tube and a control end of the ninth switching tube, and the control end of the seventh switching tube is connected with a second end of the ninth switching tube;
the control end of the eighth switching tube is respectively connected with the second end of the eleventh switching tube and the first end of the twelfth switching tube; the second end of the eighth switching tube is grounded;
a first end of the ninth switching tube is connected to a second power supply, a second end of the ninth switching tube is connected to a first end of the tenth switching tube, and a second end of the ninth switching tube is used as an output end of the fifth level shift module;
a control end of the tenth switching tube is connected with a control end of the eleventh switching tube and a control end of the twelfth switching tube respectively, and the control end of the tenth switching tube is used as an input end of the fifth level conversion module;
a first end of the eleventh switch tube is connected to a first power supply;
and the second end of the twelfth switching tube is grounded.
Further, the inverting module comprises a thirteenth switching tube and a fourteenth switching tube;
a first end of the thirteenth switching tube is connected to a second power supply, a control end of the thirteenth switching tube is connected with a control end of the fourteenth switching tube, and a second end of the thirteenth switching tube is connected with a first end of the fourteenth switching tube;
a second end of the fourteenth switching tube is grounded;
the control end of the thirteenth switching tube is used as the input end of the inverting module, and the second end of the thirteenth switching tube is used as the output end of the inverting module.
On the other hand, the embodiment of the present invention further includes an integrated circuit integrated with the IO multiplexing circuit in the embodiment of the present invention.
On the other hand, the embodiment of the invention also comprises a control method, which comprises at least one of the following steps:
setting the second input end of the first NAND gate, the first input end of the second NAND gate and the first input end of the first NAND gate to be low level;
setting the second input end of the first NAND gate and the first input end of the second NAND gate to be low level, and setting the first input end of the first NAND gate to be high level;
setting the second input end of the first NAND gate and the first input end of the second NAND gate to be high level;
setting the second input end of the first NAND gate, the first input end of the second NAND gate, the control end of the first switch tube and the control end of the second switch tube to be high level;
setting the second input end of the first NAND gate and the first input end of the second NAND gate to be at high level, and setting the control end of the first switch tube and the control end of the second switch tube to be at low level.
The invention has the beneficial effects that: the IO multiplexing circuit in the embodiment of the invention can respectively realize the functions of push-pull output, open-drain output, high-impedance state output, pull-up input, pull-down input and the like by receiving the open-drain-push-pull selection signal, the input-output selection signal, the pull-up control signal and the pull-down control signal, can realize the functions of a plurality of circuits by only one circuit, and saves the hardware cost. Further, aiming at the condition that the IO multiplexing circuit is integrated in the integrated circuit, the IO multiplexing circuit in the embodiment of the invention provides an electrostatic protection function, and can protect the inner core of the integrated circuit from being damaged by the static electricity of the peripheral circuit; by arranging the plurality of level conversion modules, the integrated circuit can still be matched for use under the condition that the integrated circuit core and the peripheral circuit use different working voltages, and the use flexibility of the integrated circuit is improved.
Drawings
Fig. 1 is a basic circuit configuration diagram of an IO multiplexing circuit according to an embodiment of the present invention;
fig. 2 is a circuit structure diagram of the IO multiplexing circuit after the electrostatic protection circuit is provided in the embodiment of the present invention;
fig. 3 is a circuit structure diagram of the IO multiplexing circuit after a level shift module is provided in the embodiment of the present invention;
FIG. 4 is a circuit diagram of a fifth level shifter module according to an embodiment of the present invention;
FIG. 5 is a circuit diagram of an inverting module in an embodiment of the invention;
fig. 6 is a circuit diagram of a first level shift module, a second level shift module, a third level shift module or a fourth level shift module according to an embodiment of the present invention.
Detailed Description
Example 1
In this embodiment, the indicative descriptions of the "first input terminal", "second input terminal", "first terminal", and "second terminal" all correspond to the arabic numerals labeled on the pins of the corresponding devices in the drawings. For example, the port labeled "1" in the first nand gate is the first input end of the first nand gate, and the port labeled "2" in the first switch tube is the second end of the first switch tube.
In this embodiment, referring to fig. 1, an IO multiplexing circuit includes a first NAND gate NAND1, a second NAND gate NAND2, an NOT gate NOT, a push-pull circuit, a first switch tube P1, and a second switch tube N2;
the first NAND gate NAND1 is provided with a first input end, a second input end and a third input end; the third input end of the first NAND gate NAND1 is connected with the output end of the second NAND gate NAND 2;
the second NAND gate NAND2 is provided with a first input end and a second input end; a first input end of the second NAND gate NAND2 is connected with a second input end of the first NAND gate NAND1, and an output end of the second NAND gate NAND2 is respectively connected with a third input end of the first NAND gate NAND1 and an input end of the NOT gate NOT;
the push-pull circuit is provided with a first input end and a second input end; the first input end of the push-pull circuit is connected with the output end of the first NAND gate NAND 1; a second input end of the push-pull circuit is connected with an output end of the NOT;
the output end of the push-pull circuit is respectively connected with the second end of the first switch tube P1 and the first end of the second switch tube N2; a first end of the first switch tube P1 is connected to a first power supply VO, and a second end of the second switch tube N2 is grounded.
The first NAND gate NAND1 used in this embodiment is a three-input device, the first NAND gate NAND1 has three input terminals, and the level output by the output terminal of the first NAND gate NAND1 is the NAND operation result of the level of the three input terminals. The second NAND gate NAND2 used in this embodiment is a two-input device, the second NAND gate NAND2 has two input terminals, and the level output by the output terminal of the second NAND gate NAND2 is the NAND operation result of the level of the two input terminals.
In this embodiment, the first input terminal of the first NAND gate NAND1 is configured to receive an open drain-push pull selection signal ODEN, the second input terminal of the first NAND gate NAND1 and the first input terminal of the second NAND gate NAND2 are configured to receive an input-output selection signal IOEN, the control terminal of the first switch tube P1 is configured to receive a pull-up control signal PUEN, and the control terminal of the second switch tube N2 is configured to receive a pull-down control signal PDEN.
The second input end of the second NAND gate NAND2 is used for receiving the output signal of the data bus. After the output signal of the data bus is input through the second input terminal of the second NAND gate NAND2, as shown in fig. 1, the output of the first NAND gate NAND1 and the output of the NOT gate NOT form a pair of complementary signals, and the pair of complementary signals enter the push-pull circuit through the first input terminal and the second input terminal of the push-pull circuit, and finally are output from the output terminal of the push-pull circuit to the multiplexing pin, which is connected to the peripheral circuit, and at this time, the multiplexing pin is an output terminal with respect to the IO multiplexing circuit as a whole shown in fig. 1.
As shown in fig. 1, when a signal sent by a peripheral circuit needs to be received, the multiplexing pin is an input end with respect to the whole IO multiplexing circuit shown in fig. 1, the signal sent by the peripheral circuit received by the multiplexing pin is an input signal with respect to a data bus, and the input signal is led out to the data bus after reaching the output end of the push-pull circuit.
Further as a preferred embodiment, referring to fig. 1, the push-pull circuit includes a third switching tube P3 and a fourth switching tube N4;
the control end of the third switching tube P3 is used as the first input end of the push-pull circuit, the first end of the third switching tube P3 is connected to the first power supply VO, and the second end of the third switching tube P3 is used as the output end of the push-pull circuit;
the control end of the fourth switching tube N4 is used as the second input end of the push-pull circuit; the first end of the fourth switching tube N4 is connected to the second end of the third switching tube P3, and the second end of the fourth switching tube N4 is grounded.
In this embodiment, the first switching tube P1 and the third switching tube P3 are both PMOS tubes, and the second switching tube N2 and the fourth switching tube N4 are both NMOS tubes. The first end of the first switch tube P1/the third switch tube P3 refers to a source electrode of the first switch tube P1/the third switch tube P3, the second end of the first switch tube P1/the third switch tube P3 refers to a drain electrode of the first switch tube P1/the third switch tube P3, and the control end of the first switch tube P1/the third switch tube P3 refers to a grid electrode of the first switch tube P1/the third switch tube P3. The first end of the second switch tube N2/the fourth switch tube N4 is a drain electrode of the second switch tube N2/the fourth switch tube N4, the second end of the second switch tube N2/the fourth switch tube N4 is a source electrode of the second switch tube N2/the fourth switch tube N4, and the control end of the second switch tube N2/the fourth switch tube N4 is a grid electrode of the second switch tube N2/the fourth switch tube N4. Since the PMOS transistor and the NMOS transistor have a certain symmetry in the manufacturing process, that is, the source and the drain of the same PMOS transistor and NMOS transistor are similar to each other with respect to the electrical characteristics of the gate, in this embodiment, the first end of each switching transistor may also be referred to as the drain of the switching transistor, and the second end of each switching transistor may also be referred to as the source of the switching transistor.
In this embodiment, the first power supply VO is a power supply terminal VO dedicated to supply power to the IO multiplexing circuit shown in fig. 1, and the ground in the "ground" is a common connection terminal VSS.
In this embodiment, the operation principle of the IO multiplexing circuit shown in fig. 1 is as follows:
(1) When the input-output selection signal IOEN received by the second input terminal of the first NAND gate NAND1 and the first input terminal of the second NAND gate NAND2 is at low level 0, and the receive open-drain-push-pull selection signal ODEN received by the first input terminal of the first NAND gate NAND1 is at low level 0, it can be known from the relevant truth table that after the output signal of the data bus is input through the second input terminal of the second NAND gate NAND2, the output of the first NAND gate NAND1 and the output of the NOT gate form a pair of complementary signals, and the pair of complementary signals respectively enter the push-pull circuit through the first input terminal and the second input terminal of the push-pull circuit and are finally output from the output terminal of the push-pull circuit to the multiplexing pin, that is, at this time, the IO multiplexing circuit shown in fig. 1 can be used as a push-pull output;
(2) When the input-output selection signal IOEN received by the second input end of the first NAND gate NAND1 and the first input end of the second NAND gate NAND2 is at low level 0 and the receive open-drain-push-pull selection signal ODEN received by the first input end of the first NAND gate NAND1 is at high level 1, it can be known from the relevant truth table that the third switch tube P3 in the push-pull circuit is in an off state and the drain of the fourth switch tube N4 is open-drain output, that is, the IO multiplexing circuit shown in fig. 1 can be used as open-drain output; in an open-drain output state, a pull-up resistor needs to be arranged at the multiplexing pin shown in fig. 1, so that the IO multiplexing circuit shown in fig. 1 can realize high-level output, and the pull-up resistor can be used as a part of the IO multiplexing circuit shown in fig. 1 or a part of a peripheral circuit; one end of the pull-up resistor is connected to the multiplexing pin, and the other end of the pull-up resistor is connected to the first power supply VO; in the open-drain output state, the IO multiplexing circuit shown in fig. 1 has a strong current absorption capability, and is suitable for being used as a current mode driver;
(3) When the input-output selection signal IOEN received by the second input terminal of the first NAND gate NAND1 and the first input terminal of the second NAND gate NAND2 is at the high level 1, according to the associated truth table and the properties of the NMOS transistor, the fourth switch transistor N4 in the push-pull circuit is in the on state, so that the IO multiplexing circuit shown in fig. 1 can be used as the high impedance state output at this time; meanwhile, the IO multiplexing circuit shown in fig. 1 may also be used as an input of a receiving peripheral circuit;
(4) When the input-output selection signal IOEN received by the second input end of the first NAND gate NAND1 and the first input end of the second NAND gate NAND2 is at a high level 1, the pull-up control signal PUEN received by the control end of the first switch tube P1 is at a low level 0, and the pull-down control signal PDEN received by the control end of the second switch tube N2 is at a high level 1, the first switch tube P1 and the second switch tube N2 are both in an off state, and the first switch tube P1 and the second switch tube N2 do not act on the signal received by the multiplexing pin from the peripheral circuit;
(5) When the input-output selection signal IOEN received by the second input end of the first NAND gate NAND1 and the first input end of the second NAND gate NAND2 is at a high level 1, the pull-up control signal PUEN received by the control end of the first switch tube P1 is at a high level 1, and the pull-down control signal PDEN received by the control end of the second switch tube N2 is at a high level 1, the first switch tube P1 is in a conducting state, the second switch tube N2 is in an off state, the first switch tube P1 plays a pull-up role on a signal received by a multiplexing pin from a peripheral circuit, and at this time, the IO multiplexing circuit shown in fig. 1 can be used as a pull-up input;
(6) When the input-output selection signal IOEN received by the second input end of the first NAND gate NAND1 and the first input end of the second NAND gate NAND2 is at a high level 1, the pull-up control signal PUEN received by the control end of the first switch tube P1 is at a low level 0, and the pull-down control signal PDEN received by the control end of the second switch tube N2 is at a low level 0, the first switch tube P1 is in a cut-off state, the second switch tube N2 is in a conducting state, the second switch tube N2 performs a pull-down function on a signal received by the multiplexing pin from the peripheral circuit, and at this time, the IO multiplexing circuit shown in fig. 1 can be used as a pull-down input.
Further as a preferred embodiment, referring to fig. 2, in this embodiment, the IO multiplexing circuit further includes a fifth switching tube P5 and a sixth switching tube N6; the control end and the first end of the fifth switch tube P5 are both connected to a first power supply VO, the second end of the fifth switch tube P5 is connected with the first end of the sixth switch tube N6, and the control end and the second end of the sixth switch tube N6 are both grounded.
In this embodiment, the fifth switching tube P5 is a PMOS tube, and the sixth switching tube N6 is an NMOS tube. The first end of the fifth switching tube P5 is a source electrode of the fifth switching tube P5, the second end of the fifth switching tube P5 is a drain electrode of the fifth switching tube P5, and the control end of the fifth switching tube P5 is a gate electrode of the fifth switching tube P5. The first end of the sixth switching tube N6 is a drain of the fifth switching tube P5, the second end of the sixth switching tube N6 is a source of the sixth switching tube N6, and the control end of the sixth switching tube N6 is a gate of the sixth switching tube N6. Since the PMOS transistor and the NMOS transistor have a certain symmetry in the manufacturing process, that is, the source and the drain of the same PMOS transistor and NMOS transistor are similar to each other with respect to the electrical characteristics of the gate, in this embodiment, the first end of each switching transistor may also be referred to as the drain of the switching transistor, and the second end of each switching transistor may also be referred to as the source of the switching transistor.
By arranging the fifth switching tube P5 and the sixth switching tube N6 according to the manner of fig. 2, electrostatic discharge (ESD) can be performed on the voltage at the multiplexing pin, so as to prevent external Static electricity from directly entering the data bus through the multiplexing pin to cause damage.
Further as a preferred implementation, referring to fig. 3, in this embodiment, the IO multiplexing circuit further includes a first level shift module and a second level shift module; the first level shift module is connected in series between the output end of the first NAND gate NAND1 and the first input end of the push-pull circuit, and the second level shift module is connected in series between the output end of the NOT gate NOT and the second input end of the push-pull circuit.
In this embodiment, the first level shift module is connected in series between the output end of the first NAND gate NAND1 and the first input end of the push-pull circuit, which means that the input end of the first level shift module is connected to the output end of the first NAND gate NAND1, and the output end of the first level shift module is connected to the first input end of the push-pull circuit. The second level shift module is connected in series between the output end of the NOT gate NOT and the second input end of the push-pull circuit, which means that the input end of the second level shift module is connected with the output end of the NOT gate NOT, and the output end of the second level shift module is connected with the second input end of the push-pull circuit.
In this embodiment, the input-output select signal IOEN and the open-drain-push-pull select signal ODEN received by the first NAND gate NAND1 and the second NAND gate NAND2 are from the control bus, and the output signals are from the data bus, so that the operating voltages of the first NAND gate NAND1, the second NAND gate NAND2 and the NOT gate are matched with the control bus and the data bus. For the push-pull circuit, an independent first power supply VO may be used for supplying power, that is, the power supply manner of the push-pull circuit is independent from the power supply manner of the control bus and the data bus, which may cause the "high level" corresponding to the push-pull circuit to be mismatched with the "high level" output by the first NAND gate NAND1 and the NOT gate NOT, for example, 5V with respect to the "high level" of the push-pull circuit and 1.1V with respect to the "high level" of the first NAND gate NAND 1. In this embodiment, the first level shift module and the second level shift module are configured to perform level shift, for example, when the input end level of the first level shift module is 1.1V, the output end level of the first level shift module is 5V, so as to keep consistency of digital logic.
Further as a preferred implementation manner, referring to fig. 3, in this embodiment, the IO multiplexing circuit further includes a third level shift module and a fourth level shift module; the output end of the third level conversion module is connected with the control end of the first switch tube P1, and the output end of the fourth level conversion module is connected with the control end of the second switch tube N2.
In this embodiment, the pull-up control signal PUEN received by the first switch tube P1 and the pull-down control signal PDEN received by the second switch tube N2 come from the control bus, and the first power supply VO and the second power supply VO can be used for supplying power to the first switch tube P1 and the second switch tube N2, so that the "high level" corresponding to the control bus is not matched with the "high level" corresponding to the first switch tube P1 and the second switch tube N2. Through the arrangement of the third level conversion module and the fourth level conversion module, the high level corresponding to the control bus can be converted into the high level corresponding to the first switch tube P1 and the second switch tube N2, so that the consistency of digital logic is maintained.
Further as a preferred implementation manner, referring to fig. 3, in this embodiment, the IO multiplexing circuit further includes a fifth level shift module and an inverting module; the input end of the fifth level conversion module is connected with the output end of the push-pull circuit, and the output end of the fifth level conversion module is connected with the input end of the phase inversion module.
Referring to fig. 1, the peripheral circuits received through the multiplexing pin are brought out to the data bus, and the operating voltage of the peripheral circuits is generally different from the operating voltage of the data bus, which causes the "high level" corresponding to the data bus not to match the "high level" corresponding to the peripheral circuits. Referring to fig. 3, by providing the fifth level shift module, the "high level" of the peripheral circuit may be shifted to the "high level" corresponding to the data bus, thereby maintaining the consistency of the digital logic.
Since the fifth level shift module generally generates an inversion effect on the input signal when implementing the level shift function, the inversion module is configured to invert the output of the fifth level shift module, so that the final input signal is consistent with the digital logic of the signal received in the multiplexing pin.
Further as a preferred embodiment, referring to fig. 4, the fifth level shift module includes a seventh switching tube P7, an eighth switching tube N8, a ninth switching tube P9, a tenth switching tube N10, an eleventh switching tube P11 and a twelfth switching tube N12;
a first end of the seventh switching tube P7 is connected to a second power supply TVDD, a second end of the seventh switching tube P7 is connected to the first end of the eighth switching tube N8 and the control end of the ninth switching tube P9, respectively, and the control end of the seventh switching tube P7 is connected to the second end of the ninth switching tube P9;
the control end of the eighth switching tube N8 is connected to the second end of the eleventh switching tube P11 and the first end of the twelfth switching tube N12 respectively; a second end of the eighth switching tube N8 is grounded;
a first end of the ninth switching tube P9 is connected to a second power supply TVDD, a second end of the ninth switching tube P9 is connected to a first end of the tenth switching tube N10, and a second end of the ninth switching tube P9 is used as an output end of the fifth level shift module;
a control end of the tenth switching tube N10 is connected to a control end of the eleventh switching tube P11 and a control end of the twelfth switching tube N12, respectively, and the control end of the tenth switching tube N10 is used as an input end of the fifth level shift module;
a first end of the eleventh switching tube P11 is connected to the first power supply VO;
a second end of the twelfth switching tube N12 is grounded.
In this embodiment, the seventh switch tube P7, the ninth switch tube P9 and the eleventh switch tube P11 are all PMOS tubes, and the eighth switch tube N8, the tenth switch tube N10 and the twelfth switch tube N12 are all NMOS tubes. The first end of the seventh switch tube P7/the ninth switch tube P9/the eleventh switch tube P11 is a source of the seventh switch tube P7/the ninth switch tube P9/the eleventh switch tube P11, the second end of the seventh switch tube P7/the ninth switch tube P9/the eleventh switch tube P11 is a drain of the seventh switch tube P7/the ninth switch tube P9/the eleventh switch tube P11, and the control end of the seventh switch tube P7/the ninth switch tube P9/the eleventh switch tube P11 is a gate of the seventh switch tube P7/the ninth switch tube P9/the eleventh switch tube P11. The first end of the eighth switch tube N8/the tenth switch tube N10/the twelfth switch tube N12 is a drain of the eighth switch tube N8/the tenth switch tube N10/the twelfth switch tube N12, the second end of the eighth switch tube N8/the tenth switch tube N10/the twelfth switch tube N12 is a source of the eighth switch tube N8/the tenth switch tube N10/the twelfth switch tube N12, and the control end of the eighth switch tube N8/the tenth switch tube N10/the twelfth switch tube N12 is a gate of the eighth switch tube N8/the tenth switch tube N10/the twelfth switch tube N12. Since the PMOS transistor and the NMOS transistor have a certain symmetry in the manufacturing process, that is, the source and the drain of the same PMOS transistor and NMOS transistor are similar to each other with respect to the electrical characteristics of the gate, in this embodiment, the first end of each switching transistor may also be referred to as the drain of the switching transistor, and the second end of each switching transistor may also be referred to as the source of the switching transistor.
In this embodiment, the second power supply TVDD refers to a power supply terminal TVDD used by a data bus and a control bus connected to the IO multiplexing circuit. When the data bus and the control bus are integrated in the chip core, the TVDD is the power supply used by the chip core.
The working principle of the fifth level shift module shown in fig. 4 is as follows: the eleventh switching transistor P11 and the twelfth switching transistor N12 form an inverter structure, which is powered by the first power supply VO and thus can match the level transmitted to the input terminal IN by the peripheral circuit. When the signal inputted by the peripheral circuit is at a low level (where the low level is relative to the first power supply VO), the gate of the tenth switching tube N10 is at a low level, the gate of the eighth switching tube N8 is at a high level, the tenth switching tube N10 is turned off, the eighth switching tube N8 is turned on, so that the gate of the ninth switching tube P9 is pulled to a low level, the ninth switching tube P9 is turned on, the gate of the seventh switching tube P7 is at a high level, the seventh switching tube P7 is turned off, and the signal outputted from the output terminal OUT of the fifth level conversion module (i.e., the drain of the ninth switching tube P9) is at a high level (where the high level is relative to the second power supply TVDD, i.e., where the high level is the voltage of the second power supply TVDD without considering voltage drop); when the signal inputted from the peripheral circuit is at a high level (where the high level is relative to the first power supply VO, that is, the high level is the voltage of the first power supply VO without considering the voltage drop), the gate of the tenth switching tube N10 is at a high level, the gate of the eighth switching tube N8 is at a low level, the tenth switching tube N10 is turned on, the eighth switching tube N8 is turned off, so that the gate of the ninth switching tube P9 is pulled to a high level, the ninth switching tube P9 is turned off, the gate of the seventh switching tube P7 is at a low level, the seventh switching tube P7 is turned on, and the signal outputted from the output terminal OUT (i.e., the drain of the ninth switching tube P9) of the fifth level conversion module is at a low level (where the low level is relative to the second power supply TVDD). Therefore, the fifth level conversion module can realize the conversion of the value of the level corresponding to the digital logic, and under the condition that the ground part of each circuit is uniformly connected to VSS, the "low level" received or output by the fifth level conversion module is the voltage of VSS, the "high level" received by the fifth level conversion module is the voltage of the first power supply VO end, and the "high level" output by the fifth level conversion module is the voltage of the second power supply TVDD end. Meanwhile, since the eleventh switching tube P11 and the twelfth switching tube N12 provided IN the fifth level shifter module have an inverting function, the levels of the input terminal IN and the output terminal OUT of the fifth level shifter module are inverted, and thus an inverting module is further provided IN the circuit shown IN fig. 3 to counteract the inverting function of the fifth level shifter module itself.
Further as a preferred embodiment, referring to fig. 5, the inverting module includes a thirteenth switching tube P13 and a fourteenth switching tube N14;
a first end of the thirteenth switching tube P13 is connected to a second power supply TVDD, a control end of the thirteenth switching tube P13 is connected to a control end of the fourteenth switching tube N14, and a second end of the thirteenth switching tube P13 is connected to a first end of the fourteenth switching tube N14;
a second end of the fourteenth switching tube N14 is grounded;
a control end of the thirteenth switching tube P13 is used as an input end of the inverter module, and a second end of the thirteenth switching tube P13 is used as an output end of the inverter module.
In this embodiment, the circuit structures of the first level conversion module, the second level conversion module, the third level conversion module, the fourth level conversion module and the fifth level conversion module are completely the same, but since the input ends of the first level conversion module, the second level conversion module, the third level conversion module and the fourth level conversion module receive the level adapted to the data bus and the control bus, and the output ends output the level adapted to the IO multiplexing circuit components such as the first switching tube P1 and the second switching tube N2, the first level conversion module, the second level conversion module, the third level conversion module and the fourth level conversion module use the circuit shown in fig. 6, that is, the seventh switching tube P7 and the ninth switching tube P9 are connected to the first power supply VO matched with the IO multiplexing circuit components, and the eleventh switching tube P11 is connected to the second power supply TVDD matched with the data bus and the control bus.
Under the condition that the grounding parts of all circuits are uniformly connected with VSS, the received or output low levels of the first level conversion module, the second level conversion module, the third level conversion module and the fourth level conversion module are all VSS voltage, the received high level is voltage of a TVDD end of the second power supply, and the output high level is voltage of a VO end of the first power supply, so that level conversion is realized.
Example 2
This embodiment includes an integrated circuit that includes a data bus and a control bus. The control bus may output various combinations of levels as control signals under control of programming instructions. The integrated circuit further integrates the IO multiplexing circuit described in embodiment 1, in the IO multiplexing circuit, a first input end of a first nand gate, a second input end of the first nand gate, a first input end of a second nand gate, an input end of a third level conversion module, and an input end of a fourth level conversion module are respectively connected to different ports in the control bus, and a second input end of the second nand gate and an output end of the inversion module are respectively connected to the data bus.
Example 3
This embodiment includes a control method for controlling the IO multiplexing circuit described in embodiment 1, where the method includes at least one of the following steps:
s1, when a push-pull mode request is detected, setting a second input end of a first NAND gate, a first input end of a second NAND gate and a first input end of the first NAND gate to be low level;
s2, when a leakage output mode request is detected, setting the second input end of the first NAND gate and the first input end of the second NAND gate to be low level, and setting the first input end of the first NAND gate to be high level;
s3, when a high-impedance state output mode request is detected, setting the second input end of the first NAND gate and the first input end of the second NAND gate to be high levels;
s4, when a pull-up input mode request is detected, setting the second input end of the first NAND gate, the first input end of the second NAND gate, the control end of the first switch tube and the control end of the second switch tube to be high level;
and S5, when a pull-down input mode request is detected, setting the second input end of the first NAND gate and the first input end of the second NAND gate to be high level, and setting the control end of the first switch tube and the control end of the second switch tube to be low level.
As can be seen from the description in embodiment 1, when step S1 is performed, the IO multiplexing circuit can be used as a push-pull output; when step S2 is executed, the IO multiplexing circuit enters an open-drain output state; when step S3 is executed, the IO multiplexing circuit may be used as a high impedance state output, and may also be used as an input for receiving a peripheral circuit; when step S4 is executed, the IO multiplexing circuit may be used as a pull-up input; when step S5 is performed, the IO multiplexing circuit may be used as a pull-down input.
After the first input end of the first nand gate, the second input end of the first nand gate, the first input end of the second nand gate, the input end of the third level conversion module and the input end of the fourth level conversion module in the IO multiplexing circuit shown in fig. 1 to 3 are respectively connected to the control bus, the IO multiplexing circuit can respectively realize functions of push-pull output, open-drain output, high-impedance output, pull-up input, pull-down input and the like by outputting different control levels.
While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
It should be noted that, unless otherwise specified, when a feature is referred to as being "fixed" or "connected" to another feature, it may be directly fixed or connected to the other feature or indirectly fixed or connected to the other feature. Furthermore, the descriptions of upper, lower, left, right, etc. used in the present disclosure are only relative to the mutual positional relationship of the constituent parts of the present disclosure in the drawings. As used in this disclosure, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any combination of one or more of the associated listed items.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one type of element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. The use of any and all examples, or exemplary language ("e.g.," such as "or the like") provided herein, is intended merely to better illuminate embodiments of the invention and does not pose a limitation on the scope of the invention unless otherwise claimed.
The above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiment, and any modifications, equivalent substitutions, improvements, etc. within the spirit and principle of the present invention should be included in the protection scope of the present invention as long as the technical effects of the present invention are achieved by the same means. The technical solution and/or the embodiments thereof may be variously modified and varied within the scope of the present invention.
Claims (10)
1. An IO multiplexing circuit is characterized by comprising a first NAND gate, a second NAND gate, a NOT gate, a push-pull circuit, a first switching tube and a second switching tube;
the first NAND gate is provided with a first input end, a second input end and a third input end; the third input end of the first NAND gate is connected with the output end of the second NAND gate; the first input end of the first NAND gate is used for receiving an open drain-push pull selection signal;
the second NAND gate is provided with a first input end and a second input end; the first input end of the second NAND gate is connected with the second input end of the first NAND gate, and the output end of the second NAND gate is respectively connected with the third input end of the first NAND gate and the input end of the NOT gate; a second input end of the first NAND gate and a first input end of the second NAND gate are used for receiving input-output selection signals;
the push-pull circuit is provided with a first input end and a second input end; the first input end of the push-pull circuit is connected with the output end of the first NAND gate; the second input end of the push-pull circuit is connected with the output end of the NOT gate;
the output end of the push-pull circuit is respectively connected with the second end of the first switch tube and the first end of the second switch tube; the first end of the first switch tube is connected to a first power supply, and the second end of the second switch tube is grounded.
2. The IO multiplexing circuit of claim 1, wherein the push-pull circuit comprises a third switch tube and a fourth switch tube;
the control end of the third switching tube is used as the first input end of the push-pull circuit, the first end of the third switching tube is connected to the first power supply, and the second end of the third switching tube is used as the output end of the push-pull circuit;
the control end of the fourth switching tube is used as the second input end of the push-pull circuit; and the first end of the fourth switching tube is connected with the second end of the third switching tube, and the second end of the fourth switching tube is grounded.
3. The IO multiplexing circuit of claim 1, further comprising a fifth switching tube and a sixth switching tube; the control end and the first end of the fifth switch tube are both connected to a first power supply, the second end of the fifth switch tube is connected with the first end of the sixth switch tube, and the control end and the second end of the sixth switch tube are both grounded.
4. An IO multiplexing circuit according to claim 1, further comprising a first level shift module and a second level shift module; the first level conversion module is connected in series between the output end of the first nand gate and the first input end of the push-pull circuit, and the second level conversion module is connected in series between the output end of the not gate and the second input end of the push-pull circuit.
5. The IO multiplexing circuit according to claim 1, further comprising a third level shift module and a fourth level shift module; the output end of the third level conversion module is connected with the control end of the first switch tube, and the output end of the fourth level conversion module is connected with the control end of the second switch tube.
6. The IO multiplexing circuit according to claim 1, further comprising a fifth level shift module and an inversion module; the input end of the fifth level conversion module is connected with the output end of the push-pull circuit, and the output end of the fifth level conversion module is connected with the input end of the inverting module.
7. The IO multiplexing circuit of claim 6, wherein the fifth level shift module includes a seventh switch tube, an eighth switch tube, a ninth switch tube, a tenth switch tube, an eleventh switch tube and a twelfth switch tube;
a first end of the seventh switching tube is connected to a second power supply, a second end of the seventh switching tube is respectively connected with a first end of the eighth switching tube and a control end of the ninth switching tube, and the control end of the seventh switching tube is connected with a second end of the ninth switching tube;
the control end of the eighth switching tube is respectively connected with the second end of the eleventh switching tube and the first end of the twelfth switching tube; the second end of the eighth switching tube is grounded;
a first end of the ninth switching tube is connected to a second power supply, a second end of the ninth switching tube is connected to a first end of the tenth switching tube, and a second end of the ninth switching tube is used as an output end of the fifth level conversion module;
a control end of the tenth switching tube is connected with a control end of the eleventh switching tube and a control end of the twelfth switching tube respectively, and the control end of the tenth switching tube is used as an input end of the fifth level conversion module;
a first end of the eleventh switch tube is connected to a first power supply;
and the second end of the twelfth switching tube is grounded.
8. The IO multiplexing circuit of claim 6, wherein the inverting module comprises a thirteenth switching tube and a fourteenth switching tube;
a first end of the thirteenth switching tube is connected to a second power supply, a control end of the thirteenth switching tube is connected with a control end of the fourteenth switching tube, and a second end of the thirteenth switching tube is connected with a first end of the fourteenth switching tube;
a second end of the fourteenth switching tube is grounded;
the control end of the thirteenth switching tube is used as the input end of the inverting module, and the second end of the thirteenth switching tube is used as the output end of the inverting module.
9. An integrated circuit, characterized in that an IO multiplexing circuit according to any one of claims 1 to 8 is integrated.
10. A control method for controlling an IO multiplexing circuit according to any one of claims 1 to 8, comprising at least one of the following steps:
setting the second input end of the first NAND gate, the first input end of the second NAND gate and the first input end of the first NAND gate to be low level;
setting the second input end of the first NAND gate and the first input end of the second NAND gate to be low level, and setting the first input end of the first NAND gate to be high level;
setting the second input end of the first NAND gate and the first input end of the second NAND gate to be high level;
setting the second input end of the first NAND gate, the first input end of the second NAND gate, the control end of the first switch tube and the control end of the second switch tube to be high level;
setting the second input end of the first NAND gate and the first input end of the second NAND gate to be high level, and setting the control end of the first switch tube and the control end of the second switch tube to be low level.
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| US6215344B1 (en) * | 1998-01-19 | 2001-04-10 | Kabushiki Kaisha Toshiba | Data transmission circuit |
| CN105471425A (en) * | 2015-12-08 | 2016-04-06 | 无锡芯响电子科技有限公司 | Circuit capable of realizing multiplexing of exclusive-OR gate or XNOR gate |
| CN205265661U (en) * | 2015-12-08 | 2016-05-25 | 无锡芯响电子科技有限公司 | Can realize that anticoincidence gate is perhaps with multiplexing circuit of disjunction gate |
| US9979396B1 (en) * | 2017-02-23 | 2018-05-22 | Stmicroelectronics (Grenoble 2) Sas | Bidirectional analog multiplexer |
| CN207638640U (en) * | 2017-12-13 | 2018-07-20 | 中天鸿骏半导体（上海）有限公司 | A kind of imput output circuit of compatible recommending output mode and open-drain output |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100480596B1 (en) * | 2002-04-03 | 2005-04-06 | 삼성전자주식회사 | Output driver circuit for controlling up-slew rate and down-slew rate, up-driving strength and down-driving strength, each independently |
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| US6215344B1 (en) * | 1998-01-19 | 2001-04-10 | Kabushiki Kaisha Toshiba | Data transmission circuit |
| CN105471425A (en) * | 2015-12-08 | 2016-04-06 | 无锡芯响电子科技有限公司 | Circuit capable of realizing multiplexing of exclusive-OR gate or XNOR gate |
| CN205265661U (en) * | 2015-12-08 | 2016-05-25 | 无锡芯响电子科技有限公司 | Can realize that anticoincidence gate is perhaps with multiplexing circuit of disjunction gate |
| US9979396B1 (en) * | 2017-02-23 | 2018-05-22 | Stmicroelectronics (Grenoble 2) Sas | Bidirectional analog multiplexer |
| CN207638640U (en) * | 2017-12-13 | 2018-07-20 | 中天鸿骏半导体（上海）有限公司 | A kind of imput output circuit of compatible recommending output mode and open-drain output |
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