CN105471425A - Circuit capable of realizing multiplexing of exclusive-OR gate or XNOR gate - Google Patents
Circuit capable of realizing multiplexing of exclusive-OR gate or XNOR gate Download PDFInfo
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Abstract
The invention discloses a circuit capable of realizing multiplexing of an exclusive-OR gate or an XNOR gate, belonging to the technical field of integrated circuits. The circuit comprises a compound logic gate circuit and an either-or gating circuit which are cascaded; the compound logic gate circuit comprises a NOR gate unit, an AND-OR-NOT gate unit and a first phase inverter, an input end of the NOR gate unit and the input end of the AND-OR-NOT gate unit are respectively connected with two paths of input signals, an output end of the NOR gate unit is connected with a control end of the AND-OR-NOT gate unit, the output end of the AND-OR-NOT gate unit is connected with the input end of the first phase inverter and outputs an exclusive-OR operation result, and the output end of the first phase inverter outputs an XNOR operation result; and the either-or gating circuit performs gating on an exclusive-OR gate unit composed of the NOR gate unit and the AND-OR-NOT gate unit, or an XNOR gate unit composed of the NOR gate unit, the AND-OR-NOT gate unit and the first phase inverter. The circuit provided by the invention realizes simple multiplexing of the exclusive-OR gate or XNOR gate circuit, reduces the number of transistors of the whole circuit system, and consequently reduces the layout area and circuit power consumption.
Description
Technical field
The invention discloses a kind of realize XOR gate or with or the multiplexing circuit of door, belong to the technical field of integrated circuit.
Background technology
In the encrypting and decrypting computing of integrated circuit fields, XOR gate and with or door be a large amount of logic gates used, make them on circuit layout, occupy the area of quite a few thus.Application number be 200510075399.0 invention devise a kind of AES decipher circuit optimization method and multiplexing Sbox module, by make decipher circuit share a Sbox module to reduce circuit scale and to reduce circuit power consumption and area; Existing encryption and decryption computing circuit adopts independent XOR gate or same or door mostly, rarely has and realizes XOR gate or same or that door is multiplexing circuit.Urgently design a kind of reusable logic gates, composition XOR gate and transistor that is same or door can be reused, to reduce the quantity of whole Circuits System transistor, thus reach the object reducing chip area and circuit power consumption.
Summary of the invention
Technical problem to be solved by this invention is the deficiency for above-mentioned background technology, provide a kind of realize XOR gate or with or the multiplexing circuit of door, achieve XOR gate or simply multiplexing with OR circuit, decrease the number of transistors of whole Circuits System, thus reduce chip area and circuit power consumption, solve XOR gate in encryption and decryption computing circuit/with the multiplexing technical problem of OR circuit.
The present invention adopts following technical scheme for achieving the above object:
A kind of realize XOR gate or with or the multiplexing circuit of door, comprise compound logic gate circuit and the alternative gating circuit of cascade, described compound logic gate circuit comprises: NOR gate unit and AND OR NOT gate unit and the first inverter, the input of described NOR gate unit and the input of AND OR NOT gate unit connect two-way input signal respectively, NOR gate unit exports termination AND OR NOT gate unit controls end, AND OR NOT gate unit output connects the first inverter input and exports XOR result, first inverter output exports same or operation result, the XOR gate unit that alternative gating circuit gating is made up of NOR gate unit and AND OR NOT gate unit or the same or gate cell be made up of NOR gate unit and AND OR NOT gate unit and the first inverter,
Wherein,
Described NOR gate unit comprises: the first PMOS, the second PMOS, the first NMOS tube, the second NMOS tube, described AND OR NOT gate unit comprises: the 3rd PMOS, the 4th PMOS, the 5th PMOS, the 3rd NMOS tube, the 4th NMOS tube, the 5th NMOS tube
The grid of described first PMOS connects first via input signal, and source electrode connects power supply, and drain electrode connects the second PMOS source electrode,
The grid of described second PMOS connects the second road input signal, and drain electrode and the first NMOS tube drain and the second NMOS tube drains and connects the rear output as NOR gate unit,
The grid of described first NMOS tube connects first via input signal, source ground,
The grid of described second NMOS tube connects the second road input signal, source ground,
The grid of described 3rd PMOS connects first via input signal, source electrode drains with the 4th PMOS source electrode and the 5th PMOS and is connected, drain electrode and the 4th PMOS drain and the 3rd NMOS tube drains and the 5th NMOS tube drains and connect the rear output as AND OR NOT gate unit
Described 4th PMOS grid connects the second road input signal,
The grid of described 5th PMOS and the 5th NMOS tube grid also connect the rear control end as AND OR NOT gate unit, and source electrode connects power supply,
The grid of described 3rd NMOS tube connects first via input signal, and source electrode connects the 4th NMOS tube drain electrode,
The grid of described 4th NMOS tube connects the second road input signal, source ground,
The source ground of described 5th NMOS tube.
As described realize XOR gate or with or the further prioritization scheme of the multiplexing circuit of door, described alternative gating circuit, comprising: the second inverter, the 3rd inverter, the first transmission gate, the second transmission gate, wherein:
The input termination control signal of described 3rd inverter, output is connected with a control end of the first transmission gate and a control end of the second transmission gate;
The input termination AND OR NOT gate unit output of described first transmission gate, another controls another control end of termination second transmission gate, exports termination second inverter input;
Input termination first inverter output of described second transmission gate, exports termination second inverter input;
Described second inverter exports XOR result or same or operation result.
Further, described realize XOR gate or with or the multiplexing circuit of door in, described first inverter, the second inverter, the 3rd reverser are CMOS inverter, and described first transmission gate, the second transmission gate are cmos transmission gate.
Further, described realize XOR gate or with or the multiplexing circuit of door in, described CMOS inverter, comprise: a PMOS and a NMOS tube, PMOS source electrode connects power supply, NMOS tube source ground, PMOS grid and NMOS tube grid also connect the rear input as inverter, and PMOS drain electrode drains with NMOS tube and connects the rear output as inverter.
Further, described reusable XOR gate/with in OR circuit, described cmos transmission gate, comprise: a PMOS and a NMOS tube, PMOS drain electrode drains with NMOS tube and connects the rear input as cmos transmission gate, PMOS source electrode and NMOS tube source electrode also connect the rear output as cmos transmission gate, and PMOS grid and NMOS tube grid are respectively as a control end of cmos transmission gate.
The present invention adopts technique scheme, has following beneficial effect:
(1) what the present invention designed realizes XOR gate or same or that door is multiplexing circuit, comprise compound logic gate circuit and the alternative gating circuit of cascade, XOR gate or simply multiplexing with OR circuit is achieved by alternative gating circuit, XOR is realized when alternative gating circuit control signal is low level, same or logic is realized when alternative gating circuit control signal is high level, decrease the number of transistors of whole Circuits System, thus reduce chip area and circuit power consumption;
(2) compound logic gate circuit comprises: the XOR gate of NOR gate unit and AOI unit composition and the first inverter, compound logic gate circuit not only exported XOR but also export with or, alternative gating circuit then selects XOR or same or output according to the logic level of control signal S, the XOR unit only comprising 10 pipes decreases the quantity of pipe relative to 12 traditional pipe XOR unit, and reduces circuit power consumption.
Accompanying drawing explanation
Fig. 1 can realize XOR gate or same or that door is multiplexing circuit.
Fig. 2 be can realize XOR gate or with or the block diagram of the multiplexing circuit of door.
Number in the figure illustrate: P1 to P10 be the first PMOS to the tenth PMOS, N1 to N10 is that the first NMOS tube is to the tenth NMOS tube.
Embodiment
Be described in detail below in conjunction with the technical scheme of accompanying drawing to invention.
The invention provides a kind of logic gates connected based on two-stage circuit as shown in Figure 1 and Figure 2, achieve XOR gate and reusable that is same or door.First order circuit be an XOR gate/with or the compound logic gate circuit of door, comprise: the NOR gate unit be made up of the first PMOS P1, the second PMOS P2, the first NMOS tube N1, the second NMOS tube N2, the AND OR NOT gate unit be made up of the 3rd PMOS P3, the 4th PMOS P4, the 5th PMOS P5, the 3rd NMOS tube N3, the 4th NMOS tube N4, the 5th NMOS tube N5, and, the first inverter INV1 of the 6th PMOS P6, the 6th NMOS tube N6 composition; Second level circuit is an alternative gating circuit, comprise: the first transmission gate TG1 of the 8th PMOS P8, the 8th NMOS tube N8 composition, second transmission gate TG2 of the 7th PMOS P7, the 7th NMOS tube N7 composition, 3rd inverter INV3 of the second inverter INV2 of the 9th PMOS P9, the 9th NMOS tube N9 composition, the tenth PMOS P10, the tenth NMOS tube N10 composition.
In first order circuit, the first PMOS P1 and the second PMOS P2 connects, and the first NMOS tube N1 and the second NMOS tube N2 is in parallel, and they together form a NOR gate unit.The source class of the first PMOS P1 connects power vd D, and grid connects input signal A, the source class short circuit of drain electrode and the second PMOS P2.The grid of the second PMOS P2 connects input signal B, drain electrode and the drain electrode of the first NMOS tube N1 and the drain electrode short circuit of the second NMOS tube N2.The grid of the first NMOS tube N1 connects input signal A, and the grid of the second NMOS tube N2 connects input signal B, and the source electrode of the first NMOS tube N1 and the source class of the second NMOS tube N2 are connected power supply ground VSS jointly.3rd PMOS P3 and the 4th PMOS P4 is in parallel, and the then with five PMOS P5 series connection, the 3rd NMOS tube N3 and the 4th NMOS tube N4 connects, and the then with five NMOS tube N5 is in parallel, and they together form an AND OR NOT gate unit.The source class of the 5th PMOS P5 connects power vd D, and drain electrode and the source electrode of the 3rd PMOS P3 and the source class short circuit of the 4th PMOS P4, the grid of grid and the 5th NMOS tube N5 is connected to the drain electrode of the second PMOS P2 jointly.The grid of the 3rd PMOS P3 connects input signal A, and the grid of the 4th PMOS P4 connects input signal B, and the grid of the 3rd NMOS tube N3 connects input signal A, and the grid of the 4th NMOS tube N4 connects input signal B.The source class of the 3rd NMOS tube N3 and the drain electrode short circuit of the 4th NMOS tube N4, source electrode and the source class of the 5th NMOS tube N5 of the 4th NMOS tube N4 are connected power supply ground VSS jointly.The source electrode of the drain electrode of the 3rd NMOS tube N3 and the drain electrode of the 5th NMOS tube N5 and the 3rd PMOS P3 and the drain electrode of the 4th PMOS P4 are shorted together, and draw an output signal Y at the corresponding levels.6th PMOS P6 and the 6th NMOS tube N6 connects, and forms the first inverter INV1.Y, through the first inverter INV1, draws another output signal YN at the corresponding levels.
In the circuit of the second level, 8th PMOS P8 and the 8th NMOS tube N8 is in parallel, the i.e. source class of the 8th PMOS P8 and the source class short circuit of the 8th NMOS tube N8, the drain electrode of the 8th PMOS P8 and the drain electrode short circuit of the 8th NMOS tube N8, they constitute the first transmission gate unit TG1.7th PMOS P7 and the 7th NMOS tube N7 is in parallel, i.e. the source class of the 7th PMOS P7 and the source class short circuit of the 7th NMOS tube N7, the drain electrode of the 7th PMOS P7 and the drain electrode short circuit of the 7th NMOS tube N7, they constitute the second transmission gate unit TG2.9th PMOS P9 and the 9th NMOS tube N9 connects, and forms the second inverter INV2.Tenth PMOS P10 and the tenth NMOS tube N10 connects, and forms the 3rd inverter INV3.Annexation is: the input of the first transmission gate unit TG1 is connected to the output Y of first order circuit, the input of the second transmission gate unit TG2 is connected to the output YN of first order circuit, the output of the first transmission gate unit TG1 after the output short circuit of the second transmission gate unit TG2 together be connected to the input of the second inverter INV2.The input control end S of circuit is connected to together with after the grid short circuit of the input of the 3rd inverter INV3 and the grid of the 7th PMOS P7 and the 8th NMOS tube N8.Second inverter INV2 outputs signal Z.
Analyze the logic function of first order circuit below.
When input signal A and input signal B is 0, first PMOS P1 and the equal conducting of the second PMOS P2, the first NMOS tube N1 and the second NMOS tube N2 all ends, and the drain electrode of the second PMOS P2 exports as high level, make the 5th PMOS P5 cut-off, the 5th NMOS tube N5 conducting.So it is low level, i.e. Y=0, so YN=1 that the drain electrode of the 5th NMOS tube N5 just exports.
When input signal A and input signal B is 1, first PMOS P1 and the second PMOS P2 all ends, first NMOS tube N1 and the equal conducting of the second NMOS tube N2, the drain electrode of the first NMOS tube N1 and the drain electrode of the second NMOS tube N2 export as low level, make the 5th PMOS P5 conducting, the 5th NMOS tube N5 cut-off.And the 3rd NMOS tube N3 and the equal conducting of the 4th NMOS tube N4, so it is low level that the drain electrode of the 3rd NMOS tube N3 just exports, i.e. Y=0, so YN=1.
When input signal A is 0, when input signal B is 1, second NMOS tube N2 conducting, the drain electrode of the second NMOS tube N2 exports as low level, makes the 5th PMOS P5 conducting, 5th NMOS tube N5 cut-off, and the 3rd PMOS P3 now also conducting, like this, it is high level that the drain electrode of the 3rd PMOS P3 just exports, i.e. Y=1, so YN=0.
When input signal A is 1, when input signal B is 0, first NMOS tube N1 conducting, the drain electrode of the first NMOS tube N1 exports as low level, makes the 5th PMOS P5 conducting, 5th NMOS tube N5 cut-off, and the 4th PMOS P4 now also conducting, like this, it is high level that the drain electrode of the 4th PMOS P4 just exports, i.e. Y=1, so YN=0.
In sum, be exactly when input signal A is identical with the logic level of input signal B, export Y=0, YN=1; And when input signal A is not identical with the logic level of input signal B, export Y=1, YN=0.Therefore, first order circuit realiration XOR and with or the function of logic, namely Y is the XOR of A and B, YN be the same of A and B or.
Analyze the logic function of second level circuit below again.
When control end signal S is 0, the second transmission gate unit TG2 conducting, the first transmission gate unit TG1 closes, and the output YN of front stage circuits, through the second transmission gate unit TG2, the second inverter INV2, arrives the output Z of circuit.Now Z=! YN=Y, namely exports the XOR that Z is input A and B, achieves the multiplexing of XOR gate unit.
When control end signal S is 1, the first transmission gate unit TG1 conducting, the second transmission gate unit TG2 closes, the output Y approach first transmission gate unit TG1 of front stage circuits, the second inverter INV2, arrives the output Z of circuit.Now Z=! Y, namely export Z be input A and B same or, achieve with or gate cell multiplexing.
In sum, when control signal S is 0, the XOR of A and B is selected to export; When control signal S is 1, the same or logic of A and B is selected to export.So whole circuit just achieves XOR gate and multiplexing function that is same or door.
In sum, the present invention has following beneficial effect:
(1) what the present invention designed realizes XOR gate or same or that door is multiplexing circuit, comprise compound logic gate circuit and the alternative gating circuit of cascade, the simply multiplexing of XOR gate/with OR circuit is achieved by alternative gating circuit, XOR is realized when alternative gating circuit control signal is low level, same or logic is realized when alternative gating circuit control signal is high level, decrease the number of transistors of whole Circuits System, thus reduce chip area and circuit power consumption;
(2) compound logic gate circuit comprises: the XOR gate of NOR gate unit and AOI unit composition and the first inverter, compound logic gate circuit not only exported XOR but also export with or, alternative gating circuit then selects XOR or same or output according to the logic level of control signal S, the XOR unit only comprising 10 pipes decreases the quantity of pipe relative to 12 traditional pipe XOR unit, and reduces circuit power consumption.
Claims (5)
1. one kind can realize XOR gate or same or that door is multiplexing circuit, it is characterized in that, comprise compound logic gate circuit and the alternative gating circuit of cascade, described compound logic gate circuit comprises: NOR gate unit and AND OR NOT gate unit and the first inverter, the input of described NOR gate unit and the input of AND OR NOT gate unit connect two-way input signal respectively, NOR gate unit exports termination AND OR NOT gate unit controls end, AND OR NOT gate unit output connects the first inverter input and exports XOR result, first inverter output exports same or operation result, the XOR gate unit that alternative gating circuit gating is made up of NOR gate unit and AND OR NOT gate unit or the same or gate cell be made up of NOR gate unit and AND OR NOT gate unit and the first inverter,
Wherein,
Described NOR gate unit comprises: the first PMOS, the second PMOS, the first NMOS tube, the second NMOS tube, described AND OR NOT gate unit comprises: the 3rd PMOS, the 4th PMOS, the 5th PMOS, the 3rd NMOS tube, the 4th NMOS tube, the 5th NMOS tube
The grid of described first PMOS connects first via input signal, and source electrode connects power supply, and drain electrode connects the second PMOS source electrode,
The grid of described second PMOS connects the second road input signal, and drain electrode and the first NMOS tube drain and the second NMOS tube drains and connects the rear output as NOR gate unit,
The grid of described first NMOS tube connects first via input signal, source ground,
The grid of described second NMOS tube connects the second road input signal, source ground,
The grid of described 3rd PMOS connects first via input signal, source electrode drains with the 4th PMOS source electrode and the 5th PMOS and is connected, drain electrode and the 4th PMOS drain and the 3rd NMOS tube drains and the 5th NMOS tube drains and connect the rear output as AND OR NOT gate unit
Described 4th PMOS grid connects the second road input signal,
The grid of described 5th PMOS and the 5th NMOS tube grid also connect the rear control end as AND OR NOT gate unit, and source electrode connects power supply,
The grid of described 3rd NMOS tube connects first via input signal, and source electrode connects the 4th NMOS tube drain electrode,
The grid of described 4th NMOS tube connects the second road input signal, source ground,
The source ground of described 5th NMOS tube.
2. according to claim 1 realize XOR gate or with or the multiplexing circuit of door, it is characterized in that, described alternative gating circuit, comprising: the second inverter, the 3rd inverter, the first transmission gate, the second transmission gate, wherein:
The input termination control signal of described 3rd inverter, output is connected with a control end of the first transmission gate and a control end of the second transmission gate;
The input termination AND OR NOT gate unit output of described first transmission gate, another controls another control end of termination second transmission gate, exports termination second inverter input;
Input termination first inverter output of described second transmission gate, exports termination second inverter input;
Described second inverter exports XOR result or same or operation result.
3. according to claim 2 realize XOR gate or with or the multiplexing circuit of door, it is characterized in that, described first inverter, the second inverter, the 3rd reverser are CMOS inverter, and described first transmission gate, the second transmission gate are cmos transmission gate.
4. according to claim 3 realize XOR gate or with or the multiplexing circuit of door, it is characterized in that, described CMOS inverter, comprise: a PMOS and a NMOS tube, PMOS source electrode connects power supply, NMOS tube source ground, PMOS grid and NMOS tube grid also connect the rear input as inverter, and PMOS drain electrode drains with NMOS tube and connects the rear output as inverter.
5. reusable XOR gate according to claim 3/same to OR circuit, it is characterized in that, described cmos transmission gate, comprise: a PMOS and a NMOS tube, PMOS drain electrode drains with NMOS tube and connects the rear input as cmos transmission gate, PMOS source electrode and NMOS tube source electrode also connect the rear output as cmos transmission gate, and PMOS grid and NMOS tube grid are respectively as a control end of cmos transmission gate.
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| CN201510892656.3A CN105471425B (en) | 2015-12-08 | 2015-12-08 | A kind of achievable XOR gate or the circuit with OR gate multiplexing |
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| CN107301834A (en) * | 2017-08-25 | 2017-10-27 | 京东方科技集团股份有限公司 | A kind of logic unit circuit and pixel-driving circuit |
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| CN109412580A (en) * | 2017-08-17 | 2019-03-01 | 深圳指芯智能科技有限公司 | Selection circuit |
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| WO2019019434A1 (en) * | 2017-07-24 | 2019-01-31 | 武汉华星光电技术有限公司 | Multiplexer control circuit |
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| US11886292B2 (en) | 2021-01-14 | 2024-01-30 | Changxin Memory Technologies, Inc. | Memory system |
| US11935616B2 (en) | 2021-01-14 | 2024-03-19 | Changxin Memory Technologies, Inc. | Comparison system |
| US11990201B2 (en) | 2021-01-14 | 2024-05-21 | Changxin Memory Technologies, Inc. | Storage system |
| CN113572471A (en) * | 2021-07-12 | 2021-10-29 | 沈阳工业大学 | 4-transistor bidirectional exclusive-nor CMOS integrated circuit and using and connecting method thereof |
| CN113572471B (en) * | 2021-07-12 | 2023-10-13 | 沈阳工业大学 | 4-transistor bidirectional exclusive nor gate CMOS integrated circuit and using and connecting method |
| CN116054816A (en) * | 2023-03-29 | 2023-05-02 | 山东云海国创云计算装备产业创新中心有限公司 | Encryption logic unit circuit, encryption chip, server and image encryption method |
| CN116054816B (en) * | 2023-03-29 | 2023-07-14 | 山东云海国创云计算装备产业创新中心有限公司 | Encryption logic unit circuit, encryption chip, server and image encryption method |
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