CN116054816A - Encryption logic unit circuit, encryption chip, server and image encryption method - Google Patents
Encryption logic unit circuit, encryption chip, server and image encryption method Download PDFInfo
- Publication number
- CN116054816A CN116054816A CN202310315587.4A CN202310315587A CN116054816A CN 116054816 A CN116054816 A CN 116054816A CN 202310315587 A CN202310315587 A CN 202310315587A CN 116054816 A CN116054816 A CN 116054816A
- Authority
- CN
- China
- Prior art keywords
- memristor
- encryption
- logic unit
- circuit
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0009—RRAM elements whose operation depends upon chemical change
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/14—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using a plurality of keys or algorithms
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/44—Secrecy systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
Abstract
The invention relates to the field of chip design. The invention provides an encryption logic unit circuit, an encryption chip, a server and an image encryption method, wherein the encryption logic unit circuit comprises: the exclusive-OR gate unit comprises an AND gate consisting of a first memristor and a second memristor, an OR gate consisting of a third memristor and a fourth memristor, an exclusive-OR gate consisting of a fifth memristor and a first NMOS, and an NOT gate consisting of a sixth memristor and a second NMOS; and the source electrode of the PMOS in the CMOS inverter is connected to the drain electrode of the first NMOS of the exclusive-or gate unit, and the source electrode of the NMOS in the CMOS inverter is connected to the drain electrode of the second NMOS of the exclusive-or gate unit. On the basis of memristor proportional logic gates, the invention designs an exclusive OR gate and an exclusive OR gate or two improved MRL gates, and combines CMOS to form an encryption logic unit, thereby opening up a new path for image encryption.
Description
Technical Field
The present invention relates to the field of chip design, and more particularly, to an encryption logic unit circuit, an encryption chip, a server, and an image encryption method.
Background
Memristor-based and or gates have been implemented, which are typically composed of two memristors in series. The input end of the AND gate is connected to the positive electrode terminals of the two memristors, and the output end is a common node of the memristors. The output voltage of the AND gate is determined by the voltage divider of the two memristive devices. The input end of the OR gate is connected to the negative terminals of the two memristors, and the output end is a common node of the memristors. The output voltage of an or gate is determined by the voltage divider of two memristive devices. In the prior art regarding memristor proportional logic, no non-logic is proposed how to construct boolean logic.
Disclosure of Invention
In view of this, an objective of the embodiments of the present invention is to provide an encryption Logic unit circuit, an encryption chip, a server and an encryption method, in which an inverter formed by an NMOS (N Metal Oxide Semiconductor, N-type metal oxide semiconductor) and a Memristor can replace CMOS (Complementary Metal Oxide Semiconductor ) to effectively reduce the area of a transistor.
Based on the above object, an aspect of an embodiment of the present invention provides an encryption logic unit circuit, including: the exclusive-OR gate unit comprises an AND gate consisting of a first memristor and a second memristor, an OR gate consisting of a third memristor and a fourth memristor, an exclusive-OR gate consisting of a fifth memristor and a first NMOS, and an NOT gate consisting of a sixth memristor and a second NMOS; and a CMOS inverter, a source of PMOS in the CMOS inverter being connected to a drain of the first NMOS of the nor-gate unit, and a source of NMOS in the CMOS inverter being connected to a drain of the second NMOS of the nor-gate unit.
In some embodiments, the exclusive-or gate unit includes: a first input signal is connected to a negative terminal of the first memristor and a positive terminal of the third memristor, and a second input signal is connected to a negative terminal of the second memristor and a positive terminal of the fourth memristor.
In some embodiments, the exclusive-or gate unit includes: the gates of the first NMOS are connected to positive terminals of the first memristor and the second memristor, the drain of the first NMOS is connected to the positive terminal of the fifth memristor, and the negative terminals of the fifth memristor are connected to the negative terminals of the third memristor and the fourth memristor.
In some embodiments, the exclusive-or gate unit includes: the gate of the second NMOS is connected to the drain of the first NMOS, and the drain of the second NMOS is connected to the negative terminal of the sixth memristor.
In some embodiments, the CMOS inverter is configured to: and receiving an encryption mode selection signal and selecting an encryption mode in the encryption logic unit based on the encryption mode selection signal.
In some embodiments, the CMOS inverter is configured to: selecting the same or mode in the encryption logic unit to encrypt the input signal in response to the encryption mode selection signal being high level; and selecting an exclusive-or mode in the encryption logic unit to encrypt the input signal in response to the encryption mode selection signal being low.
In some embodiments, the CMOS inverter is configured to: and performing an exclusive OR operation on the first input signal and the second input signal.
In some embodiments, the encryption logic unit circuit is configured to: and constructing a pixel array according to the arrangement of the pixel points of the original image in the input signal to encrypt the image.
In some embodiments, the encryption logic unit circuit is configured to: and respectively converting black and white pixel points of the original image into high and low levels to form a voltage signal matrix, and randomly generating a corresponding key matrix.
In some embodiments, the encryption logic unit circuit is configured to: and determining an encryption mode according to the height of the encryption mode selection signal, and operating the voltage signal matrix and the key matrix according to the determined encryption mode.
In some embodiments, the encryption logic unit circuit is configured to: and performing exclusive or exclusive nor operation on the corresponding elements of the voltage signal matrix and the key matrix to obtain an encrypted ciphertext matrix.
In some embodiments, the encryption logic unit circuit further comprises: and the read-write circuit unit is configured to store and read images according to the read-write circuit unit formed by the memristor, the input voltage source and the switch.
In some embodiments, the read-write circuit unit includes: the positive terminal of the memristor is connected to the control voltage, the negative terminal of the memristor is connected to the single-pole double-throw switch, and two terminals on the other side of the single-pole double-throw switch are respectively connected with the writing voltage and the reading voltage.
In some embodiments, the read-write circuit unit is configured to: writing an image in response to the single pole double throw switch communicating with the write voltage; and reading an image in response to the single pole double throw switch communicating with the read voltage.
In some embodiments, the read-write circuit unit is configured to: in response to the write voltage being high, the memristor resistance changing from a high resistance state to a low resistance state to write a first logic value; and writing a second logic value from a low resistance state to a high resistance state in response to the write voltage being a low level.
In some embodiments, the read-write circuit unit is configured to: and reading the current value of the circuit, and determining the resistance corresponding to the memristor according to the magnitude of the current value.
In some embodiments, the read-write circuit unit is configured to: responding to the current value of the circuit being larger than a current threshold value, wherein the resistance value of the memristor is a low resistance state, and a first logic value is read; and responsive to the current value of the circuit not being greater than the current threshold, reading a second logic value for the high resistance state by the memristor resistance value.
In another aspect of the embodiments of the present invention, there is provided an image encryption method for encrypting an image using the encryption logic unit circuit as described above, determining whether or not an encryption mode selection signal is high level in response to receiving an input signal and the encryption mode selection signal; selecting the same or mode in the encryption logic unit to encrypt the input signal in response to the encryption mode selection signal being high level; and selecting an exclusive-or mode in the encryption logic unit to encrypt the input signal in response to the encryption mode selection signal being low.
In yet another aspect of the embodiment of the present invention, there is also provided an encryption chip including the encryption logic unit circuit as described above.
In yet another aspect of the embodiment of the present invention, there is also provided a server including the encryption logic unit circuit as described above.
The invention has the following beneficial technical effects: the invention designs an exclusive-or and same-or two-type improved MRL gate based on the proportional logic gate of the memristor, and forms an encryption logic unit based on the exclusive-or and same-or two-type improved MRL gate combined with the CMOS, thereby designing a pixel array to complete the design of an image encryption circuit, and the invention is widely used in the Boolean encryption technology, and completes the reading and writing of image data according to the memristor characteristics and the reasonable design storage and reading operation of the threshold voltage range of the memristor.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are necessary for the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention and that other embodiments may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an embodiment of a NOT gate provided by the present invention;
FIG. 2 shows the present invention
A schematic diagram of an embodiment of a door;
FIG. 3 is a schematic diagram of an embodiment of an XOR and XOR gate unit provided by the present invention;
FIG. 4 is a schematic diagram of an embodiment of an encryption logic unit circuit according to the present invention;
FIG. 5 is a schematic diagram of an image encryption circuit according to the present invention;
FIG. 6 is a schematic diagram of an image encryption and decryption process provided by the invention;
FIG. 7 is a schematic diagram of an embodiment of a read/write circuit unit according to the present invention;
FIG. 8 is a schematic diagram of an embodiment of an encryption chip provided by the present invention;
fig. 9 is a schematic diagram of an embodiment of a server provided by the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
It should be noted that, in the embodiments of the present invention, all the expressions "first" and "second" are used to distinguish two entities with the same name but different entities or different parameters, and it is noted that the "first" and "second" are only used for convenience of expression, and should not be construed as limiting the embodiments of the present invention, and the following embodiments are not described one by one.
The memristor and the CMOS transistor can be well compatible, namely, the memristor can be manufactured on a metal layer of a CMOS process, and various combined logic circuits can be realized after the basic gate circuit design is completed. Exclusive or gate units are widely used in combination logic circuits, and are also widely used in boolean encryption techniques, which are based on the use of a combination logic to protect the original circuit by inserting a number of key gates of basic gate units into the original design. Boolean encryption can effectively hide a secret key, and even if a secret key door is determined, a real secret key cannot be obtained; the original circuit can be protected without designing an excessively complex algorithm; the operation is simple, and the cost is low.
According to the invention, an inverter formed by an NMOS and a memristor can replace a CMOS, so that the area of a transistor is effectively reduced, meanwhile, on the basis of a proportional logic gate of the memristor, an exclusive-OR gate and an exclusive-OR gate or two improved MRL gates are designed, and an encryption logic unit is formed by combining the CMOS on the basis of the exclusive-OR gate and the exclusive-OR gate or the two improved MRL gates, so that an m multiplied by n pixel array is designed to complete the design of an image encryption circuit, and the method is widely used in a Boolean encryption technology; and reasonably designing storage and reading operations according to memristor characteristics and the range of threshold voltage of the memristor, and finishing reading and writing of image data.
And constructing an exclusive-or gate unit based on the memristor proportional logic gate, and constructing an encryption logic unit according to the exclusive-or gate unit. And receiving an input signal and an encryption mode selection signal, and judging whether the encryption mode selection signal is in a high level or not. And selecting the same or mode in the encryption logic unit to encrypt the input signal in response to the encryption mode selection signal being high. And selecting an exclusive or mode in the encryption logic unit to encrypt the input signal in response to the encryption mode selection signal being at a low level. Both high and low levels in embodiments of the present invention are well understood in the art.
In some implementations, the memristor-based proportional logic gate-building exclusive-or gate unit includes: and forming an NOT gate according to the NMOS and the memristor, and constructing an exclusive OR gate unit according to the NOT gate and the memristor proportional logic gate.
In some implementations, the configuring the not gate from the NMOS and the memristor includes: and connecting the drain electrode of the NMOS to the negative electrode terminal of the memristor, and connecting an external direct-current high voltage to the positive electrode terminal of the memristor.
Because the area occupation ratio of the CMOS device is larger, the proportional logic of the memristor formed by the CMOS transistors increases the circuit area, and the NOT gate circuit formed by the NMOS transistors is only provided on the premise of reducing the chip area, but the pull resistor R is required to be additionally arranged for realizing the reverse function of the NMOS transistors, compared with the memristor, the area occupied by the resistor is larger, so that the invention uses the inverter formed by one NMOS and one memristor M to replace the CMOS, thereby effectively reducing the area of the transistors. Fig. 1 is a schematic diagram of an embodiment of a not gate provided in the present invention.
External DC high voltage V cc Connected to the positive terminal of the memristor, where V in Is set as an input signal, V out Is considered as an output signal. When V is in When=1 (input signal is high voltage), the transistor is turned on, the memristor is forward biased, and the memristor has a value R M =R on . At this time, the NMOS saturated on-resistance R T The output is approximately 0 as follows:
when V is in When the transistor is turned off, R is T The output is approximately ≡infinity as follows:
therefore, the inverting function can be completed by using the NMOS tube and the memristor, and compared with a NOT circuit formed by CMOS, the inverting function effectively reduces the circuit area.
In addition, if the signal V in1 Instead of external DC bias voltage V cc Logic can be obtained as input signal
. FIG. 2 shows the +.>
A schematic diagram of an embodiment of the door, as shown in FIG. 2, when V in1 =1 and V in2 When=1, the memristor M and the transistor T respectively exhibit low memristance R on And low resistance R T Approximately 0, leading to V out =0, realizing logic ∈>
=0. When V is in1 When=0, i.e. transistor T is not biased, no matter the input signal V in2 Whether=1 or V in2 =0, the transistors will be off, which also results in V out =0, i.e. logic->
=0. Only when V in1 =1 and V in2 Logic is implemented only when =0
=1。
In some implementations, the constructing an nor-exclusive-or gate unit from the nor gate and the memristor proportional logic gate includes: the method comprises the steps of implementing a logical AND by using a first memristor and a second memristor, implementing a logical OR by using a third memristor and a fourth memristor, implementing an exclusive OR by using a fifth memristor and a first NMOS, and forming an NOT by using a sixth memristor and a second NMOS.
In some implementations, the constructing an nor-exclusive-or gate unit from the nor gate and the memristor proportional logic gate includes: connecting a first voltage signal to a negative terminal of the first memristor and a positive terminal of the third memristor, and connecting a second voltage signal to a negative terminal of the second memristor and a positive terminal of the fourth memristor; connecting the gate of the first NMOS to positive terminals of the first memristor and the second memristor, the drain of the first NMOS to the fifth memristor positive terminal, and the negative terminal of the fifth memristor to the negative terminals of the third memristor and the fourth memristor; and connecting the gate of the second NMOS to the drain of the first NMOS and the drain of the second NMOS to the negative terminal of the sixth memristor.
In the digital logic circuit, besides basic logic gates (AND), OR, AND NOT), NAND, NOR, XOR, AND XNOR are also taken as basic logic circuit modules, AND the existing logic circuit module (1T-4M-1R) consists of 1 CMOS transistor, 4 memristors, AND 1 resistor, AND can realize XOR AND AND outputs at the same time. The circuit structure can reduce the use of transistors, improve the operation speed and reduce the power consumption. However, this structure must use resistors, which are not significant for small scale integrated circuits, but a large number of resistors occupy a large amount of valuable chip area for the chip. The invention provides an improved logic module (2T-6M) composed of 2 NMOS tubes and 6 memristors, and an exclusive OR gate or two improved MRL gates are designed on the basis of proportional logic gates of the memristors, so that AND, OR, XOR and XNOR can be realized simultaneously.
FIG. 3 is a schematic diagram of an embodiment of an XOR and XOR gate unit according to the present invention, wherein the first memristor M1 and the second memristor M2 implement logic V as shown in FIG. 3 and =V in1 ·V in2 The method comprises the steps of carrying out a first treatment on the surface of the The third memristor M3 and the fourth memristor M4 implement the logic V or =V in1 +V in2 The circuit consisting of the fifth memristor M5 and the first NMOS T1 is implementedNow V or ·V and The logic of (2) can obtain the XOR logic output, and the circuit formed by the sixth memristor M6 and the second NMOS T2 realizes the not gate operation, so as to obtain the NOR logic output.
The principle of this circuit can be expressed by the following equation:
the above is a basic logic circuit on the basis of which some more complex logic designs can be designed. Particularly, in the process of constructing a combinational logic circuit based on the memristor proportional logic, a large number of components can be saved.
In the field of data transmission security, in order to prevent image data from being intercepted and stolen and destroyed by others in the process of transmission, encryption of the data transmission by using a key encryption algorithm is a common security means, and the encryption algorithm can encrypt the image by using a boolean encryption technology. An encryption system mainly comprises a plaintext, a secret key and a ciphertext, and the secret key plays an important role in encrypting the plaintext and decrypting the ciphertext. The encryption key and the decryption key are different and referred to as a dual key system, and the same is referred to as a single key system.
In a first aspect of the present invention, an embodiment of an encryption logic unit circuit is provided, including: the exclusive-OR gate unit comprises an AND gate consisting of a first memristor and a second memristor, an OR gate consisting of a third memristor and a fourth memristor, an exclusive-OR gate consisting of a fifth memristor and a first NMOS, and an NOT gate consisting of a sixth memristor and a second NMOS; and a CMOS inverter, a source of PMOS in the CMOS inverter being connected to a drain of the first NMOS of the nor-gate unit, and a source of NMOS in the CMOS inverter being connected to a drain of the second NMOS of the nor-gate unit.
In some embodiments, the exclusive-or gate unit includes: a first input signal is connected to a negative terminal of the first memristor and a positive terminal of the third memristor, and a second input signal is connected to a negative terminal of the second memristor and a positive terminal of the fourth memristor.
In some embodiments, the exclusive-or gate unit includes: the gates of the first NMOS are connected to positive terminals of the first memristor and the second memristor, the drain of the first NMOS is connected to the positive terminal of the fifth memristor, and the negative terminals of the fifth memristor are connected to the negative terminals of the third memristor and the fourth memristor.
In some embodiments, the exclusive-or gate unit includes: the gate of the second NMOS is connected to the drain of the first NMOS, and the drain of the second NMOS is connected to the negative terminal of the sixth memristor.
In some embodiments, the CMOS inverter is configured to: and receiving an encryption mode selection signal and selecting an encryption mode in the encryption logic unit based on the encryption mode selection signal.
In some embodiments, the CMOS inverter is configured to: selecting the same or mode in the encryption logic unit to encrypt the input signal in response to the encryption mode selection signal being high level; and selecting an exclusive-or mode in the encryption logic unit to encrypt the input signal in response to the encryption mode selection signal being low.
In some embodiments, the CMOS inverter is configured to: and performing an exclusive OR operation on the first input signal and the second input signal.
In some embodiments, the encryption logic unit circuit is configured to: and constructing a pixel array according to the arrangement of the pixel points of the original image in the input signal to encrypt the image.
In some embodiments, the encryption logic unit circuit is configured to: and respectively converting black and white pixel points of the original image into high and low levels to form a voltage signal matrix, and randomly generating a corresponding key matrix.
In some embodiments, the encryption logic unit circuit is configured to: and determining an encryption mode according to the height of the encryption mode selection signal, and operating the voltage signal matrix and the key matrix according to the determined encryption mode.
In some embodiments, the encryption logic unit circuit is configured to: and performing exclusive or exclusive nor operation on the corresponding elements of the voltage signal matrix and the key matrix to obtain an encrypted ciphertext matrix.
In some embodiments, the encryption logic unit circuit further comprises: and the read-write circuit unit is configured to store and read images according to the read-write circuit unit formed by the memristor, the input voltage source and the switch.
In some embodiments, the read-write circuit unit includes: the positive terminal of the memristor is connected to the control voltage, the negative terminal of the memristor is connected to the single-pole double-throw switch, and two terminals on the other side of the single-pole double-throw switch are respectively connected with the writing voltage and the reading voltage.
In some embodiments, the read-write circuit unit is configured to: writing an image in response to the single pole double throw switch communicating with the write voltage; and reading an image in response to the single pole double throw switch communicating with the read voltage.
In some embodiments, the read-write circuit unit is configured to: in response to the write voltage being high, the memristor resistance changing from a high resistance state to a low resistance state to write a first logic value; and writing a second logic value from a low resistance state to a high resistance state in response to the write voltage being a low level.
In some embodiments, the read-write circuit unit is configured to: and reading the current value of the circuit, and determining the resistance corresponding to the memristor according to the magnitude of the current value.
In some embodiments, the read-write circuit unit is configured to: responding to the current value of the circuit being larger than a current threshold value, wherein the resistance value of the memristor is a low resistance state, and a first logic value is read; and responsive to the current value of the circuit not being greater than the current threshold, reading a second logic value for the high resistance state by the memristor resistance value.
In some embodiments, said constructing an encryption logic unit from said exclusive nor gate unit comprises: an encryption logic unit is formed based on the exclusive-or gate unit and the CMOS inverter.
In some embodiments, the forming the encryption logic unit based on the nor-nor gate unit and the CMOS inverter includes: the source of the PMOS in the CMOS inverter is connected to the drain of the first NMOS of the nor-gate unit and the source of the NMOS in the CMOS inverter is connected to the drain of the second NMOS of the nor-gate unit.
In some embodiments, the selecting the same or a same way in the encryption logic unit to encrypt the input signal comprises: the original image input signal and the key input signal are exclusive nor-ored.
In some embodiments, the selecting the exclusive-or manner in the encryption logic unit to encrypt the input signal includes: an exclusive or operation is performed on the original image input signal and the key input signal.
The embodiment of the present invention is illustrated by a single key, FIG. 4 is a schematic diagram of an embodiment of the encryption logic unit circuit provided by the present invention, as shown in FIG. 4, V cc For external direct current high voltage, the encryption logic unit has 3 input units, V in Is the input signal of the original image, V key For key input signal, V choose Selection for encryption modeA signal. V (V) out And V choose The CMOS inverter is arranged between the two, the upper half part of the CMOS inverter is PMOS (P Metal Oxide Semiconductor, P-type metal oxide semiconductor) and the lower half part of the CMOS inverter is NMOS. When V is choose When the level is high, XNOR is selected as encryption mode, when V choose The encryption mode of XOR is selected when it is low. V (V) out The signal is output for ciphertext. If the same key is input again to the ciphertext, the decryption process may be performed. The specific encryption and decryption logic expression is as follows:
encryption process:
（i）V choose at the time of the low level of the voltage,
（ii）V choose at the time of the high level of the voltage,
decryption:
1. the encryption process (i) is decrypted and,
(
2. the encryption process (ii) is decrypted and,
(
in some embodiments, the method further comprises: and constructing a pixel array according to the encryption logic unit to complete encryption of the image.
In some embodiments, the constructing the pixel array according to the encryption logic unit to complete the encryption of the image includes: respectively converting black and white pixel points of an original image into high and low levels to form a voltage signal matrix, and randomly generating a corresponding key matrix; and determining an encryption mode according to the encryption mode selection signal, and operating the voltage signal matrix and the key matrix according to the determined encryption mode.
In some embodiments, the computing the voltage signal matrix and the key matrix according to the determined encryption scheme includes: and performing exclusive or exclusive nor operation on the corresponding elements of the voltage signal matrix and the key matrix to obtain an encrypted ciphertext matrix.
Fig. 5 is a schematic diagram of an image encryption circuit provided by the present invention. An m×n pixel array is designed according to the encryption logic unit circuit to complete the design of the image encryption circuit, as shown in fig. 5.
Firstly, converting original images of black and white pixel points into high and low levels respectively to realize a voltage signal matrix A of m rows and n columns, then randomly generating a corresponding key matrix B, and then controlling V choose The encryption mode is selected, the encryption process of the matrix A can be completed by performing XOR or XNOR operation on the corresponding elements of the matrix A and the matrix B, and then the original matrix A can be obtained by performing decryption process on the ciphertext matrix by using the key matrix B again.
Fig. 6 is a schematic diagram of an image encryption and decryption process provided by the present invention, and as shown in fig. 6, the encryption and decryption process is an exclusive or process.
In some embodiments, the method further comprises: and forming a read-write circuit unit according to the memristor, the input voltage source and the switch, and storing and reading the image through the read-write circuit unit.
In some embodiments, the forming a read-write circuit unit from the memristor, the input voltage source, and the switch includes: the positive terminal of the memristor is connected to the control voltage, the negative terminal of the memristor is connected to the single-pole double-throw switch, and two terminals on the other side of the single-pole double-throw switch are respectively connected with the writing voltage and the reading voltage.
In some embodiments, the storing and reading the image by the read-write circuit unit includes: and communicating the single-pole double-throw switch with the writing voltage to write the image, and communicating the single-pole double-throw switch with the reading voltage to read the image.
In some embodiments, said communicating the single pole double throw switch with the write voltage to write an image comprises: in response to the write voltage being high, the memristor resistance changing from a high resistance state to a low resistance state to write a first logic value; and writing a second logic value from a low resistance state to a high resistance state in response to the write voltage being a low level.
In some embodiments, said placing the single pole double throw switch in communication with the read voltage reads an image comprising: and reading the current value of the circuit, and determining the resistance corresponding to the memristor according to the magnitude of the current value.
Memristors contain different threshold voltages, with voltages of different polarities corresponding to the different threshold voltages. When the applied voltage exceeds the positive threshold voltage, the memristance will transition from HRS (High Resistance State ) to LRS (Low Resistances State, low resistance state). Similarly, when the applied voltage exceeds a negative threshold voltage, it will change the memristance from LRS to HRS. Otherwise, the state of the memristor will remain unchanged, so that the memristance can be obtained correctly.
The read-write circuit unit in the embodiment of the invention is composed of a memristor M, two input voltage sources and a switch, and FIG. 7 is a schematic diagram of the embodiment of the read-write circuit unit provided by the invention, as shown in FIG. 7, V write To write voltage V read To read the voltage, V control For controlling the voltage. M has two resistance jump voltage thresholds, called V set (positive threshold voltage) and V rset (negative threshold voltage), typically memristor Vset>0，Vrset<0。
Write operation:
the switch is arranged at the S1 end, V write A cathode connected with M, V control And accessing the positive electrode of M. When input V write At high level (5V), the voltage difference V between the two ports write -V control >V set The memristor resistance is changed from the high resistance state (R off ) Becomes a low resistance state (R) on ) A logical "1" is written. When input V write At low level (0V), the voltage difference V between the two ports write -V control <V rset The memristor resistance is changed from the low resistance state (R on ) Becomes a high resistance state (R) off ) A logical "0" is written.
Reading operation:
the switch is arranged at the S2 end, and in order to ensure that the written resistance value can be accurately read, the voltage V=V applied at the two ends of the memristor is needed read -V control And in the threshold range of the memristor, the resistance value of the device can be ensured not to be changed. When the resistance value of the stored memristor is logic "1" (low resistance state R on ) When the circuit current I=V/R can be obtained through reading on . When the resistance value of the stored memristor is logic "0" (low resistance state R off ) When the circuit current I=V/R can be obtained through reading off . According to the strategy, the magnitude of the resistance value can be judged according to the magnitude of the reading current, so that the read-write circuit unit in the embodiment of the invention realizes the storage and the reading of images.
In view of the above object, a second aspect of the embodiments of the present invention proposes an image encryption method for encrypting an image using an encryption logic unit circuit as described above, determining whether or not an encryption mode selection signal is high level in response to receiving an input signal and the encryption mode selection signal; selecting the same or mode in the encryption logic unit to encrypt the input signal in response to the encryption mode selection signal being high level; and selecting an exclusive-or mode in the encryption logic unit to encrypt the input signal in response to the encryption mode selection signal being low.
In some implementations, the memristor-based proportional logic gate-building exclusive-or gate unit includes: and forming an NOT gate according to the NMOS and the memristor, and constructing an exclusive OR gate unit according to the NOT gate and the memristor proportional logic gate.
In some implementations, the configuring the not gate from the NMOS and the memristor includes: and connecting the drain electrode of the NMOS to the negative electrode terminal of the memristor, and connecting an external direct-current high voltage to the positive electrode terminal of the memristor.
In some implementations, the constructing an nor-exclusive-or gate unit from the nor gate and the memristor proportional logic gate includes: the method comprises the steps of implementing a logical AND by using a first memristor and a second memristor, implementing a logical OR by using a third memristor and a fourth memristor, implementing an exclusive OR by using a fifth memristor and a first NMOS, and forming an NOT by using a sixth memristor and a second NMOS.
In some implementations, the constructing an nor-exclusive-or gate unit from the nor gate and the memristor proportional logic gate includes: connecting a first voltage signal to a negative terminal of the first memristor and a positive terminal of the third memristor, and connecting a second voltage signal to a negative terminal of the second memristor and a positive terminal of the fourth memristor; connecting the gate of the first NMOS to positive terminals of the first memristor and the second memristor, the drain of the first NMOS to the fifth memristor positive terminal, and the negative terminal of the fifth memristor to the negative terminals of the third memristor and the fourth memristor; and connecting the gate of the second NMOS to the drain of the first NMOS and the drain of the second NMOS to the negative terminal of the sixth memristor.
In some embodiments, said constructing an encryption logic unit from said exclusive nor gate unit comprises: an encryption logic unit is formed based on the exclusive-or gate unit and the CMOS inverter.
In some embodiments, the forming the encryption logic unit based on the nor-nor gate unit and the CMOS inverter includes: the source of the PMOS in the CMOS inverter is connected to the drain of the first NMOS of the nor-gate unit and the source of the NMOS in the CMOS inverter is connected to the drain of the second NMOS of the nor-gate unit.
In some embodiments, the selecting the same or a same way in the encryption logic unit to encrypt the input signal comprises: the original image input signal and the key input signal are exclusive nor-ored.
In some embodiments, the selecting the exclusive-or manner in the encryption logic unit to encrypt the input signal includes: an exclusive or operation is performed on the original image input signal and the key input signal.
In some embodiments, the method further comprises: and constructing a pixel array according to the encryption logic unit to complete encryption of the image.
In some embodiments, the constructing the pixel array according to the encryption logic unit to complete the encryption of the image includes: respectively converting black and white pixel points of an original image into high and low levels to form a voltage signal matrix, and randomly generating a corresponding key matrix; and determining an encryption mode according to the encryption mode selection signal, and operating the voltage signal matrix and the key matrix according to the determined encryption mode.
In some embodiments, the computing the voltage signal matrix and the key matrix according to the determined encryption scheme includes: and performing exclusive or exclusive nor operation on the corresponding elements of the voltage signal matrix and the key matrix to obtain an encrypted ciphertext matrix.
In some embodiments, the method further comprises: and forming a read-write circuit unit according to the memristor, the input voltage source and the switch, and storing and reading the image through the read-write circuit unit.
In some embodiments, the forming a read-write circuit unit from the memristor, the input voltage source, and the switch includes: the positive terminal of the memristor is connected to the control voltage, the negative terminal of the memristor is connected to the single-pole double-throw switch, and two terminals on the other side of the single-pole double-throw switch are respectively connected with the writing voltage and the reading voltage.
In some embodiments, the storing and reading the image by the read-write circuit unit includes: and communicating the single-pole double-throw switch with the writing voltage to write the image, and communicating the single-pole double-throw switch with the reading voltage to read the image.
In some embodiments, said communicating the single pole double throw switch with the write voltage to write an image comprises: in response to the write voltage being high, the memristor resistance changing from a high resistance state to a low resistance state to write a first logic value; and writing a second logic value from a low resistance state to a high resistance state in response to the write voltage being a low level.
In some embodiments, said placing the single pole double throw switch in communication with the read voltage reads an image comprising: and reading the current value of the circuit, and determining the resistance corresponding to the memristor according to the magnitude of the current value.
Based on the above object, a third aspect of the embodiments of the present invention proposes an encryption chip. Fig. 8 is a schematic diagram of an embodiment of an encryption chip provided in the present invention, and as shown in fig. 8, the encryption chip 200 includes the encryption logic unit circuit 201 described above.
Based on the above object, a fourth aspect of the embodiments of the present invention proposes a server. Fig. 9 is a schematic diagram of an embodiment of a server according to the present invention, and as shown in fig. 9, the server 300 includes the encryption logic unit circuit 301 described above.
It should be understood by those skilled in the art that the above description of the encryption logic unit circuit is applicable to the encryption chip and the server in the present embodiment, and is not repeated herein for the sake of brevity.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The foregoing embodiment of the present invention has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, and the program may be stored in a computer readable storage medium, where the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will appreciate that: the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the invention, including the claims, is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the idea of an embodiment of the invention, and many other variations of the different aspects of the embodiments of the invention as described above exist, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present invention.
Claims (20)
1. An encryption logic unit circuit, comprising:
the exclusive-OR gate unit comprises an AND gate consisting of a first memristor and a second memristor, an OR gate consisting of a third memristor and a fourth memristor, an exclusive-OR gate consisting of a fifth memristor and a first NMOS, and an NOT gate consisting of a sixth memristor and a second NMOS; and
a CMOS inverter, the source of the PMOS in the CMOS inverter being connected to the drain of the first NMOS of the exclusive-or gate unit and the source of the NMOS in the CMOS inverter being connected to the drain of the second NMOS of the exclusive-or gate unit.
2. The encryption logic unit circuit of claim 1, wherein the nor-nor gate unit comprises:
a first input signal is connected to a negative terminal of the first memristor and a positive terminal of the third memristor, and a second input signal is connected to a negative terminal of the second memristor and a positive terminal of the fourth memristor.
3. The encryption logic unit circuit of claim 2, wherein the nor-nor gate unit comprises:
the gates of the first NMOS are connected to positive terminals of the first memristor and the second memristor, the drain of the first NMOS is connected to the positive terminal of the fifth memristor, and the negative terminals of the fifth memristor are connected to the negative terminals of the third memristor and the fourth memristor.
4. The encryption logic unit circuit of claim 3, wherein the nor-nor gate unit comprises:
the gate of the second NMOS is connected to the drain of the first NMOS, and the drain of the second NMOS is connected to the negative terminal of the sixth memristor.
5. The cryptographic logic unit circuit of claim 4, wherein the CMOS inverter is configured to:
and receiving an encryption mode selection signal and selecting an encryption mode in the encryption logic unit based on the encryption mode selection signal.
6. The cryptographic logic unit circuit of claim 5, wherein the CMOS inverter is configured to:
selecting the same or mode in the encryption logic unit to encrypt the input signal in response to the encryption mode selection signal being high level; and
and selecting an exclusive or mode in the encryption logic unit to encrypt the input signal in response to the encryption mode selection signal being at a low level.
7. The cryptographic logic unit circuit of claim 6, wherein the CMOS inverter is configured to:
and performing an exclusive OR operation on the first input signal and the second input signal.
8. The encryption logic unit circuit of claim 7, wherein the encryption logic unit circuit is configured to:
and constructing a pixel array according to the arrangement of the pixel points of the original image in the input signal to encrypt the image.
9. The encryption logic unit circuit of claim 8, wherein the encryption logic unit circuit is configured to:
and respectively converting black and white pixel points of the original image into high and low levels to form a voltage signal matrix, and randomly generating a corresponding key matrix.
10. The encryption logic unit circuit of claim 9, wherein the encryption logic unit circuit is configured to:
and determining an encryption mode according to the height of the encryption mode selection signal, and operating the voltage signal matrix and the key matrix according to the determined encryption mode.
11. The encryption logic unit circuit of claim 10, wherein the encryption logic unit circuit is configured to:
and performing exclusive or exclusive nor operation on the corresponding elements of the voltage signal matrix and the key matrix to obtain an encrypted ciphertext matrix.
12. The encryption logic unit circuit of claim 1, wherein the encryption logic unit circuit further comprises:
and the read-write circuit unit is configured to store and read images according to the read-write circuit unit formed by the memristor, the input voltage source and the switch.
13. The encryption logic unit circuit according to claim 12, wherein the read-write circuit unit includes:
the positive terminal of the memristor is connected to the control voltage, the negative terminal of the memristor is connected to the single-pole double-throw switch, and two terminals on the other side of the single-pole double-throw switch are respectively connected with the writing voltage and the reading voltage.
14. The encryption logic unit circuit of claim 13, wherein the read-write circuit unit is configured to:
writing an image in response to the single pole double throw switch communicating with the write voltage; and
and reading the image in response to the single pole double throw switch communicating with the read voltage.
15. The encryption logic unit circuit of claim 14, wherein the read-write circuit unit is configured to:
responding to the writing voltage to be high level, and writing a first logic value when the resistance value of the memristor is changed from a high resistance state to a low resistance state; and
and in response to the write voltage being a low level, writing a second logic value from a low resistance state to a high resistance state.
16. The encryption logic unit circuit of claim 15, wherein the read-write circuit unit is configured to:
and reading the current value of the circuit, and determining the resistance corresponding to the memristor according to the magnitude of the current value.
17. The encryption logic unit circuit of claim 16, wherein the read-write circuit unit is configured to:
responding to the current value of the circuit being larger than a current threshold value, wherein the resistance value of the memristor is a low resistance state, and a first logic value is read; and
and in response to the current value of the circuit not being greater than the current threshold, reading a second logic value for the high resistance state by the memristor resistance value.
18. An image encryption method, characterized in that an image is encrypted using the encryption logic unit circuit according to any one of claims 1 to 17,
in response to receiving an input signal and an encryption mode selection signal, determining whether the encryption mode selection signal is high level;
selecting the same or mode in the encryption logic unit to encrypt the input signal in response to the encryption mode selection signal being high level; and
and selecting an exclusive or mode in the encryption logic unit to encrypt the input signal in response to the encryption mode selection signal being at a low level.
19. An encryption chip comprising the encryption logic unit circuit of any one of claims 1-17.
20. A server comprising the encryption logic unit circuit of any one of claims 1-17.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310315587.4A CN116054816B (en) | 2023-03-29 | 2023-03-29 | Encryption logic unit circuit, encryption chip, server and image encryption method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310315587.4A CN116054816B (en) | 2023-03-29 | 2023-03-29 | Encryption logic unit circuit, encryption chip, server and image encryption method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116054816A true CN116054816A (en) | 2023-05-02 |
| CN116054816B CN116054816B (en) | 2023-07-14 |
Family
ID=86129778
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310315587.4A Active CN116054816B (en) | 2023-03-29 | 2023-03-29 | Encryption logic unit circuit, encryption chip, server and image encryption method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116054816B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117595859A (en) * | 2024-01-19 | 2024-02-23 | 山东云海国创云计算装备产业创新中心有限公司 | Memristor-based logic circuit, output method and electronic equipment |
| CN117595859B (en) * | 2024-01-19 | 2024-05-14 | 山东云海国创云计算装备产业创新中心有限公司 | Memristor-based logic circuit, output method and electronic equipment |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150146869A1 (en) * | 2013-11-28 | 2015-05-28 | Fujitsu Limited | Electronic circuit, electronic apparatus, and authentication system |
| CN105471425A (en) * | 2015-12-08 | 2016-04-06 | 无锡芯响电子科技有限公司 | Circuit capable of realizing multiplexing of exclusive-OR gate or XNOR gate |
| US9548741B1 (en) * | 2015-07-14 | 2017-01-17 | Technion Research And Development Foundation Ltd. | Memristive akers logic array |
| US20180159536A1 (en) * | 2016-12-05 | 2018-06-07 | Board Of Regents, The University Of Texas System | Memristor logic design using driver circuitry |
| CN108449080A (en) * | 2018-04-20 | 2018-08-24 | 西南大学 | The full power-up road constituted based on CMOS inverter and memristor |
| CN111555751A (en) * | 2020-06-02 | 2020-08-18 | 杭州电子科技大学 | Three-value exclusive-or and exclusive-or logic gate circuit based on memristor |
| CN113131928A (en) * | 2019-12-31 | 2021-07-16 | 华为技术有限公司 | Memristor-based exclusive-OR gate device and operation method thereof |
| CN113314176A (en) * | 2021-06-04 | 2021-08-27 | 哈尔滨工程大学 | memristor-CMOS (complementary Metal oxide semiconductor transistor) logic module and factorization carry look-ahead adder |
| CN113872586A (en) * | 2020-06-30 | 2021-12-31 | 华为技术有限公司 | Logic gate device, operation method thereof, search task execution chip and search task execution method |
| CN114496030A (en) * | 2020-10-23 | 2022-05-13 | 超聚变数字技术有限公司 | Memristor array and logic operation method thereof |
-
2023
- 2023-03-29 CN CN202310315587.4A patent/CN116054816B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150146869A1 (en) * | 2013-11-28 | 2015-05-28 | Fujitsu Limited | Electronic circuit, electronic apparatus, and authentication system |
| US9548741B1 (en) * | 2015-07-14 | 2017-01-17 | Technion Research And Development Foundation Ltd. | Memristive akers logic array |
| CN105471425A (en) * | 2015-12-08 | 2016-04-06 | 无锡芯响电子科技有限公司 | Circuit capable of realizing multiplexing of exclusive-OR gate or XNOR gate |
| US20180159536A1 (en) * | 2016-12-05 | 2018-06-07 | Board Of Regents, The University Of Texas System | Memristor logic design using driver circuitry |
| CN108449080A (en) * | 2018-04-20 | 2018-08-24 | 西南大学 | The full power-up road constituted based on CMOS inverter and memristor |
| CN113131928A (en) * | 2019-12-31 | 2021-07-16 | 华为技术有限公司 | Memristor-based exclusive-OR gate device and operation method thereof |
| CN111555751A (en) * | 2020-06-02 | 2020-08-18 | 杭州电子科技大学 | Three-value exclusive-or and exclusive-or logic gate circuit based on memristor |
| CN113872586A (en) * | 2020-06-30 | 2021-12-31 | 华为技术有限公司 | Logic gate device, operation method thereof, search task execution chip and search task execution method |
| CN114496030A (en) * | 2020-10-23 | 2022-05-13 | 超聚变数字技术有限公司 | Memristor array and logic operation method thereof |
| CN113314176A (en) * | 2021-06-04 | 2021-08-27 | 哈尔滨工程大学 | memristor-CMOS (complementary Metal oxide semiconductor transistor) logic module and factorization carry look-ahead adder |
Non-Patent Citations (1)
| Title |
|---|
| 杨辉;段书凯;董哲康;王丽丹;胡小方;尚柳汀;: "基于忆阻器-CMOS的通用逻辑电路及其应用", 中国科学:信息科学, no. 02 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117595859A (en) * | 2024-01-19 | 2024-02-23 | 山东云海国创云计算装备产业创新中心有限公司 | Memristor-based logic circuit, output method and electronic equipment |
| CN117595859B (en) * | 2024-01-19 | 2024-05-14 | 山东云海国创云计算装备产业创新中心有限公司 | Memristor-based logic circuit, output method and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116054816B (en) | 2023-07-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5875642B2 (en) | A logistic mapping circuit that implements a general-purpose logic array with a highly variable circuit topology and various logic gates with constant output. | |
| CN108694335B (en) | SRAM-based physical unclonable function and method for generating PUF response | |
| Joshi et al. | Everything you wanted to know about PUFs | |
| EP2643750B1 (en) | Physical unclonable function | |
| EP2897322B1 (en) | Semiconductor integrated circuit, authentication system, and authentication method | |
| US8854866B2 (en) | Identification circuit and method for generating an identification bit | |
| Shifman et al. | An SRAM-based PUF with a capacitive digital preselection for a 1E-9 key error probability | |
| US10797891B2 (en) | Physically unclonable function resistant to side-channel attack and method therefor | |
| CN102271038A (en) | method for generating a bit vector | |
| US11012246B2 (en) | SRAM-based authentication circuit | |
| CN107368755A (en) | Circuit and its security architecture design method, device, equipment and storage medium | |
| Gao et al. | Efficient erasable PUFs from programmable logic and memristors | |
| Alasad et al. | Resilient AES against side-channel attack using all-spin logic | |
| CN116054816B (en) | Encryption logic unit circuit, encryption chip, server and image encryption method | |
| CN116170161B (en) | Physical unclonable function circuit based on ferroelectric transistor array and application thereof | |
| US7876893B2 (en) | Logic circuit and method for calculating an encrypted result operand | |
| CN110298181A (en) | Data encryption storage method, data decryption method and encrypted memory chip | |
| CN117614621A (en) | Controllable random reconfigurable encryption circuit and control method thereof | |
| US11023209B2 (en) | On-chip hardware random number generator | |
| CN116170160B (en) | Physical unclonable function circuit and application thereof | |
| US11894061B2 (en) | Non-volatile memory programming circuit and a method of programming non-volatile memory devices | |
| CN112165384B (en) | Data encryption method and decryption method, and data encryption device and decryption device | |
| CN117150578A (en) | Implementation method of reconfigurable physical unclonable function | |
| Reis | Circuits and Architectures for Data-Centric Computing | |
| CN116167104A (en) | Scrambling device, scrambling method and chip of ternary content addressable memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |