CN111555751A - Three-value exclusive-or and exclusive-or logic gate circuit based on memristor - Google Patents

Abstract

The invention discloses a three-value exclusive-OR and exclusive-OR logic gate circuit based on a memristor. The three-value NAND gate circuit comprises a three-value OR gate TOR, a three-value AND gate TAND, a three-value NOT gate TI and a three-value NAND gate TNAND, and is realized by utilizing the switching characteristic and the memory characteristic of a memristor, wherein a first input end IN1 and a second input end IN2 are respectively the common input ends of the three-value OR gate TOR and the three-value NAND gate TNAND, the output of the three-value OR gate TOR and the output of the three-value NAND gate are two inputs of the three-value AND gate TAND, the output of the three-value AND gate TI is the input of the three-value NOT gate TI, the output of the three-value AND gate TAND is TXOR finally obtained, and the output of the three-value NOT gate TI is the same or. The invention has clear and simple structure and is easy to realize. The gate circuit model can be applied to application research in multiple fields such as multi-valued digital logic operation and the like, and has important significance.

Description

Three-valued XOR and XOR logic gates based on memristor

technical field

The invention belongs to the technical field of circuit design, and relates to a three-valued digital logic gate circuit, in particular to a physically realizable three-valued XOR and XOR logic gate circuit based on a memristor.

Background technique

In 1971, Professor Cai Shaotang, a Chinese scientist, first proposed the concept of memristor. In 2008, the research team of Hewlett Packard Lab successfully made a nano-memristor device, which confirmed Professor Cai Shaotang's inference; and further research found that the non-volatile memristor Microscopic and nanoscale dimensions contribute to the continuation of Moore's Law, enabling memristors to compute and store simultaneously.

The unique properties of memristors make them promising applications in analog circuit design, non-volatile memory, neural networks, digital logic, etc. As transistors reach physical limits, the tiny size of memristors' switching behavior is generalized as An alternative to transistor-based memory.

Traditional number systems are built on binary numbers, in which only logical 0s and 1s are considered; recently, the concept of multi-valued logic has become a common research topic. In 1840, Thomas Fowler of the United Kingdom built an early computer with a balanced ternary design using wood; in 1958, Nikolay Brusentsov built the first digital electronic ternary computer Setun at Moscow State University in the Soviet Union. Binary computers have more advantages in future development.

The main advantage of ternary numbers is that they can carry more information than binary numbers in the same number of bits, which reduces interconnect and chip area complexity. With the progress of component manufacturing process technology, it provides the possibility for the realization of ternary logic circuit. In the 1980s, the first implementations of ternary logic gates were introduced based on CMOS using enhancement and depletion transistors. Ternary logic circuits are not only faster and more reliable than binary logic circuits, they also reduce area and interconnect complexity, and require less device power.

The memristor is a good candidate for implementing a ternary system, as it can handle more than two states without using additional hardware, which can be further divided into different quantization levels to multilevel elements. Practical memristors are compatible with standard CMOS technologies, and these memristors are relatively small in size in the 2–10 nm range, and the use of memristors to implement ternary logic operations opens up new opportunities to enhance novel functionalities.

SUMMARY OF THE INVENTION

In view of the deficiencies of the prior art, the present invention proposes a ternary XOR and XOR logic gate circuit based on a memristor.

The technical scheme adopted by the present invention to solve the technical problem is as follows:

The three-valued XOR and XOR logic gate circuits based on memristors specifically include a three-valued OR gate, a three-valued AND gate, a three-valued NOT gate, and a three-valued NAND gate.

The ternary OR gate circuit consists of two memristors. The anode of the first memristor M1 is used as the first input terminal, and the anode of the second memristor M2 is used as the second input terminal. The negative electrode of the first memristor M1 is connected to the negative electrode of the second memristor M2 and serves as an output terminal. For a three-valued OR gate, the output is the maximum of the two inputs.

The ternary AND gate circuit consists of two memristors. The negative electrode of the third memristor M3 is used as the first input end, and the negative electrode of the fourth memristor M4 is used as the second input end. The positive electrode of the third memristor M3 is connected to the positive electrode of the fourth memristor M4 and serves as an output terminal. For a three-valued AND gate, the output is the minimum of the two inputs.

The ternary NOT gate circuit consists of two memristors and two NMOS transistors. The negative electrode of the fifth memristor M5 is connected to the power supply V _CC , and the positive electrode of the fifth memristor M5 is connected to the drain ( D1 ) of the first NMOS transistor N1 and serves as an output terminal. The input end of the ternary NOT gate is connected to the gate (G1) of the first NMOS transistor N1 and the gate (G2) of the second NMOS transistor N2. The source (S1) of the first NMOS transistor N1 is connected to the drain (D2) of the second NMOS transistor and the negative electrode of the sixth memristor M6, the positive electrode of the sixth memristor M6 is grounded, and the source of the second NMOS transistor N2 Pole (S2) is grounded. The threshold turn-on voltage of the first NMOS transistor N1 is 0.5V, and the threshold turn-on voltage of the second NMOS transistor N2 is 1.5V. For a ternary NOT gate, the negation of 0 is 2, the negation of 1 is 1, and the negation of 2 is 0.

The three-valued NAND gate is composed of a three-valued AND gate and a three-valued NOT gate. Connect a three-valued NOT gate after the output of a three-valued AND gate, and the output that can be obtained is logical AND.

Beneficial effects of the present invention: the present invention has a clear and simple structure and is easy to implement. The gate circuit model can be used for application research in many fields such as multi-valued digital logic operations, and is of great significance.

Description of drawings

FIG. 1 is a block diagram of a three-value XOR and XOR logic gate circuit based on a memristor of the present invention.

2 is a circuit diagram of a memristor-based ternary XOR and XOR logic gates of the present invention.

Detailed ways

The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

The three-valued XOR and XOR logic gate circuit model based on memristor designed by the present invention, its circuit block diagram is shown in Figure 1, which consists of a three-valued AND gate, a three-valued OR gate, a three-valued NOT gate and a three-valued NOT gate. It is composed of a three-valued NAND gate and is realized by using the switching characteristics and memory characteristics of the memristor.

The logic state in the ternary XOR and XOR logic gate circuits is a voltage value, where the voltage V _CC is defined as 2V, corresponding to logic 2, the voltage V _CC /2, 1V, corresponding to logic 1, GND is 0V, corresponding to logic 0 . For the three-valued XOR and XOR gates, the corresponding logical expressions are:

The truth table is shown in the following table:

IN₁ IN₂ TXOR TXNOR 0 0 0 2 0 1 1 1 0 2 2 0 1 0 1 1 1 1 1 1 1 2 1 1 2 0 2 0 2 1 1 1 2 2 0 2

The circuit block diagram shown in Figure 1 can be constructed according to the logic expressions corresponding to the ternary XOR and the EXOR gate, wherein the first input terminal IN1 and the second input terminal IN2 are the ternary OR gate TOR and the ternary NAND gate, respectively The common input terminal of TNAND, the output of the three-valued OR gate TOR and the output of the three-valued NAND gate are the two inputs of the three-valued AND gate TAND, the output of the three-valued AND gate is the input of the three-valued NOT gate TI, and finally three values are obtained. The output of the value AND gate TAND is the exclusive OR TXOR, and the output of the three-valued NOT gate TI is the same OR TXNOR.

The detailed circuit of the three-valued XOR gate and the exclusive-OR gate is shown in FIG. 2 . Specifically, the first memristor M1 and the second memristor M2 constitute a three-valued OR gate TOR. The three-valued NAND gate TNAND is composed of a three-valued AND gate and a three-valued NOT gate, wherein, the AND gate in the three-valued NAND gate is composed of a third memristor M3 and a fourth memristor M4, and the three-valued NAND gate The NOT gate is composed of a fifth memristor M5, a sixth memristor M6, a first NMOS transistor N1, and a second NMOS transistor N2. The seventh memristor M7 and the eighth memristor M8 constitute a three-valued AND gate TAND. A ternary NOT gate composed of the ninth memristor M9, the tenth memristor M10, the third NMOS transistor N3, and the fourth NMOS transistor N4.

The specific circuit structure is as follows: the first input terminal IN1 is connected to the positive pole of the first memristor M1 and the negative pole of the third memristor, the second input terminal IN2 is connected to the positive pole of the second memristor M2 and the negative pole of the fourth memristor M4 . The negative electrode of the first memristor M1 and the negative electrode of the second memristor M2 are connected to the negative electrode of the seventh memristor M7. The anode of the third memristor M3, the anode of the fourth memristor M4, the gate (G1) of the first NMOS transistor N1, and the gate (G2) of the second NMOS transistor N2 are connected to each other. The negative electrode of the fifth memristor M5 is connected to the power supply V _CC , and the positive electrode of the fifth memristor M5 is connected to the drain ( D1 ) of the first NMOS transistor N1 and the negative electrode of the eighth memristor M8 . The source (S1) of the first NMOS transistor N1 is connected to the negative electrode of the sixth memristor M6 and the drain (D2) of the second NMOS transistor N2. The anode of the sixth memristor M6 is connected to the source (S2) of the second NMOS transistor N2. The source (S2) of the second NMOS transistor N2, the anode of the sixth memristor M6 and the ground terminal are connected. The positive electrode of the seventh memristor M7 is connected to the positive electrode of the eighth memristor M8, and the corresponding output is a three-value exclusive OR TXOR. The gate (G3) of the third NMOS transistor N3 and the gate (G4) of the fourth NMOS transistor N4 are connected to the anode of the eighth memristor M8. The negative electrode of the ninth memristor M9 is connected to the power supply V _CC , and the positive electrode of the ninth memristor M9 is connected to the drain ( D3 ) of the third NMOS transistor N3 . The source ( S3 ) of the third NMOS transistor N3 is connected to the negative electrode of the tenth memristor M10 and the drain ( D4 ) of the fourth NMOS transistor N4 . The anode of the tenth memristor M10 is connected to the source (S4) of the fourth NMOS transistor N4 and the ground terminal. Among them, the drain voltage of the third NMOS transistor N3 is the output triple-valued OR TXNOR.

Those of ordinary skill in the art should realize that the above embodiments are only used to verify the present invention, not as a limitation of the present invention. As long as they are within the scope of the present invention, the changes and deformations of the above embodiments will fall within the scope of the present invention. within the protection scope of the present invention.

Claims (3)

1. Memristor-based ternary XOR and XOR logic gate circuits, including a ternary OR gate TOR, a ternary AND gate TAND, a ternary NOT gate TI, and a ternary NAND gate TNAND. The switching characteristics and memory characteristics of the resistor are realized, which are characterized by: The first input terminal IN1 and the second input terminal IN2 are the common input terminals of the three-valued OR gate TOR and the three-valued NAND gate TNAND, respectively. The output of the three-valued OR gate TOR and the output of the three-valued NAND gate are the three-valued AND gate. Two inputs of TAND, the output of the three-valued AND gate is the input of the three-valued NOT gate TI, and finally the output of the three-valued AND gate TAND is XOR TXOR, and the output of the three-valued NOT gate TI is the same OR TXNOR. 2. the ternary XOR and XOR logic gate circuit based on memristor according to claim 1, is characterized in that: concrete structure is: The three-valued OR gate TOR is composed of a first memristor M1 and a second memristor M2; The three-valued AND gate TAND is composed of the seventh memristor M7 and the eighth memristor M8; The three-valued NOT gate TI is composed of a ninth memristor M9, a tenth memristor M10, a third NMOS transistor N3, and a fourth NMOS transistor N4; The three-valued NAND gate TNAND is composed of a three-valued AND gate and a three-valued NOT gate, wherein the AND gate in the three-valued NAND gate is composed of a third memristor M3 and a fourth memristor M4, and the three-valued AND gate is composed of a third memristor M3 and a fourth memristor M4. The NOT gate in the NAND gate is composed of the fifth memristor M5, the sixth memristor M6, the first NMOS transistor N1, and the second NMOS transistor N2; The specific connection relationship is as follows: The first input terminal IN1 is connected to the positive pole of the first memristor M1 and the negative pole of the third memristor M3, and the second input terminal IN2 is connected to the positive pole of the second memristor M2 and the negative pole of the fourth memristor M4; The negative electrode of the first memristor M1 and the negative electrode of the second memristor M2 are connected to the negative electrode of the seventh memristor M7; the positive electrode of the third memristor M3, the positive electrode of the fourth memristor M4, and the grid of the first NMOS transistor N1 is connected to the gate of the second NMOS transistor N2; The positive electrode of the fifth memristor M5 is connected to the drain of the first NMOS transistor N1 and the negative electrode of the eighth memristor M8; the source of the first NMOS transistor N1 is connected to the negative electrode of the sixth memristor M6 and the negative electrode of the second NMOS transistor N2. The drain is connected; the anode of the sixth memristor M6 is connected to the source of the second NMOS transistor N2; the source of the second NMOS transistor N2, the anode of the sixth memristor M6 are connected to the ground; The positive electrode of the seventh memristor M7 is connected to the positive electrode of the eighth memristor M8, and the corresponding output is a three-value exclusive OR TXOR; The gate of the third NMOS transistor N3 and the gate of the fourth NMOS transistor N4 are connected to the positive electrode of the eighth memristor M8; the negative electrode of the ninth memristor M9 is connected to the power supply V _CC , and the positive electrode of the ninth memristor M9 is connected to The drain of the third NMOS transistor N3 is connected; the source of the third NMOS transistor N3 is connected to the negative electrode of the tenth memristor M10 and the drain of the fourth NMOS transistor N4; the positive electrode of the tenth memristor M10 is connected to the fourth NMOS The source of the transistor N4 is connected to the ground; the drain voltage of the third NMOS transistor N3 is the output ternary or TXNOR. 3. The memristor-based ternary XOR and XOR logic gate circuit according to claim 1, wherein the logic state in the ternary XOR and XOR logic gate circuit is a voltage value, wherein, the definition Voltage V _CC is 2V, corresponding to logic 2, voltage V _CC /2, is 1V, corresponding to logic 1, GND is 0V, corresponding to logic 0.

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