CN111555751A - Three-value exclusive-or and exclusive-or logic gate circuit based on memristor - Google Patents
Three-value exclusive-or and exclusive-or logic gate circuit based on memristor Download PDFInfo
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- H—ELECTRICITY
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
- H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors
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Abstract
The invention discloses a three-value exclusive-OR and exclusive-OR logic gate circuit based on a memristor. The three-value NAND gate circuit comprises a three-value OR gate TOR, a three-value AND gate TAND, a three-value NOT gate TI and a three-value NAND gate TNAND, and is realized by utilizing the switching characteristic and the memory characteristic of a memristor, wherein a first input end IN1 and a second input end IN2 are respectively the common input ends of the three-value OR gate TOR and the three-value NAND gate TNAND, the output of the three-value OR gate TOR and the output of the three-value NAND gate are two inputs of the three-value AND gate TAND, the output of the three-value AND gate TI is the input of the three-value NOT gate TI, the output of the three-value AND gate TAND is TXOR finally obtained, and the output of the three-value NOT gate TI is the same or. The invention has clear and simple structure and is easy to realize. The gate circuit model can be applied to application research in multiple fields such as multi-valued digital logic operation and the like, and has important significance.
Description
Technical Field
The invention belongs to the technical field of circuit design, relates to a three-value digital logic gate circuit, and particularly relates to a physically-realized three-value exclusive-OR and exclusive-OR logic gate circuit based on a memristor.
Background
In 1971, the concept of a memristor was first proposed by the Huanscientist Chua Chuan Tang professor, and in 2008, a Hewlett packard laboratory research team successfully made a nano memristive device, which confirmed the inference of the Chua Chuan Tang professor; and further research finds that the nonvolatile and nanoscale dimensions of the memristor contribute to continuation of moore's law, enabling the memristor to be computed and stored simultaneously.
The unique characteristics of memristors make them have good application prospects in analog circuit design, non-volatile storage, neural networks, digital logic, and the like, as transistors reach physical limits, the tiny size of the memristor's switching behavior is generalized as a replacement device for transistor-based memories.
Traditional digital systems are built on binary numbers, where only logical 0 and 1 are considered; recently, the concept of multivalued logic has become a common subject of research. In 1840, Thomas Fowler, UK, built an early computer using wood in a balanced ternary design; in 1958, the first digital electronic ternary computer Setun was built by Nikolay Brusensov at the national university of Susan Mosco, which is more advantageous than the binary computer in future developments.
The main advantage of a ternary number is that it can carry a larger amount of information than a binary number can at the same number of bits, which reduces the complexity of the interconnect and chip area. With the progress of the component manufacturing technology, the possibility is provided for the realization of the ternary logic circuit. In the 80's of the 20 th century, the first three-valued logic gate implementation was introduced based on CMOS using enhancement and depletion transistors. Ternary logic circuits are faster and more reliable than binary logic circuits, and also reduce area and interconnect complexity and require less device power consumption.
A memristor is a good candidate for implementing a ternary system because it can handle more than two states without using additional hardware, and can be further divided into different quantization levels to multi-level elements. Practical memristors are compatible with standard CMOS technology, the size of the memristors is relatively small within the range of 2-10nm, and new opportunities are opened up for enhancing novel functions by using the memristors to realize ternary logic operation.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a three-value exclusive-OR and exclusive-OR logic gate circuit based on a memristor.
The technical scheme adopted by the invention for solving the technical problem is as follows:
the memristor-based three-value exclusive-OR and exclusive-OR logic gate circuit specifically comprises a three-value OR gate, a three-value AND gate, a three-value NOT gate and a three-value NAND gate.
The three-value OR gate circuit is composed of two memristors. The positive electrode of the first memristor M1 serves as a first input end, and the positive electrode of the second memristor M2 serves as a second input end. The cathode of the first memristor M1 is connected with the cathode of the second memristor M2 and serves as an output end. For a three-valued or gate, the output is the maximum of the two inputs.
The three-value AND circuit is composed of two memristors. The cathode of the third memristor M3 is used as a first input end, and the cathode of the fourth memristor M4 is used as a second input end. The anode of the third memristor M3 is connected with the anode of the fourth memristor M4 and is used as an output end. For a three-valued AND gate, the output is the minimum of two inputs.
The three-value NOT gate circuit is composed of two memristors and two NMOS tubes. Wherein the negative pole of the fifth memristor M5 and the power supply VCCAnd the anode of the fifth memristor M5 is connected with the drain (D1) of the first NMOS transistor N1 and serves as an output end. The input ends of the three-valued NOT gate are connected with the gate (G1) of the first NMOS transistor N1 and the gate (G2) of the second NMOS transistor N2. The source (S1) of the first NMOS transistor N1 is connected with the drain (D2) of the second NMOS transistor and the negative electrode of the sixth memristor M6, the positive electrode of the sixth memristor M6 is grounded, and the source (S2) of the second NMOS transistor N2 is grounded. The threshold turn-on voltage of the first NMOS transistor N1 is 0.5V, and the threshold turn-on voltage of the second NMOS transistor N2 is 1.5V. For a three-valued NOT gate, the NOT of 0 is 2, the NOT of 1 is 1, and the NOT of 2 is 0.
The three-value NAND gate consists of a three-value AND gate and a three-value NOT gate, and the three-value NOT gate is connected behind the output end of the three-value AND gate, namely the obtained output is a logical NAND.
The invention has the beneficial effects that: the invention has clear and simple structure and is easy to realize. The gate circuit model can be applied to application research in multiple fields such as multi-valued digital logic operation and the like, and has important significance.
Drawings
FIG. 1 is a block diagram of a memristor-based three-valued XOR and XNOR logic gate circuit of the present invention.
FIG. 2 is a diagram of a memristor-based three-valued XOR and XNOR logic gate circuit of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
The circuit block diagram of the three-value exclusive-OR and exclusive-OR logic gate circuit model based on the memristor is shown in fig. 1 and comprises a three-value AND gate, a three-value OR gate, a three-value NOT gate and a three-value NAND gate, and the three-value exclusive-OR and exclusive-OR logic gate circuit model is realized by utilizing the switching characteristic and the memory characteristic of the memristor.
The logic states in a three-valued XOR and XNOR logic gate circuit are voltage values, wherein a voltage V is definedCCIs 2V, corresponding to logic 2, voltage VCCAnd/2, 1V corresponds to logic 1, GND is 0V, and corresponds to logic 0. For a three-valued exclusive or and exclusive or gate, the corresponding logic expressions are respectively:
the truth table is shown in the following table:
| IN1 | IN2 | TXOR | TXNOR |
| 0 | 0 | 0 | 2 |
| 0 | 1 | 1 | 1 |
| 0 | 2 | 2 | 0 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 1 | 1 |
| 1 | 2 | 1 | 1 |
| 2 | 0 | 2 | 0 |
| 2 | 1 | 1 | 1 |
| 2 | 2 | 0 | 2 |
the circuit block diagram shown IN fig. 1 may be constructed according to a logic expression corresponding to a three-valued exclusive-or and exclusive-nor gate, where the first input terminal IN1 and the second input terminal IN2 are common input terminals of a three-valued or gate TOR and a three-valued nand gate TNAND, outputs of the three-valued or gate TOR and the three-valued nand gate are two inputs of a three-valued and gate TAND, outputs of the three-valued and gate TI are inputs of a three-valued not gate TI, and finally, an output of the three-valued and gate TAND is an exclusive-or TXOR, and an output of the three-valued not gate TI is an exclusive-nor.
The detailed circuit for the three-valued exclusive-or gate and the exclusive-or gate is shown in fig. 2, and specifically, the first memristor M1 and the second memristor M2 form a three-valued or gate TOR. The three-value NAND gate TNAND comprises a three-value AND gate and a three-value NOT gate, wherein the AND gate in the three-value NAND gate comprises a third memristor M3 and a fourth memristor M4, and the NOT gate in the three-value NAND gate comprises a fifth memristor M5, a sixth memristor M6, a first NMOS transistor N1 and a second NMOS transistor N2. The seventh memristor M7 and the eighth memristor M8 form a three-valued and gate TAND. And the three-value NOT gate is composed of a ninth memristor M9, a tenth memristor M10, a third NMOS transistor N3 and a fourth NMOS transistor N4.
The specific circuit structure is as follows: the first input end IN1 is connected with the positive electrode of the first memristor M1 and the negative electrode of the third memristor, and the second input end IN2 is connected with the positive electrode of the second memristor M2 and the negative electrode of the fourth memristor M4. The negative electrode of the first memristor M1, the negative electrode of the second memristor M2 and the negative electrode of the seventh memristor M7 are connected. The positive electrode of the third memristor M3, the positive electrode of the fourth memristor M4, the gate (G1) of the first NMOS transistor N1 and the gate (G2) of the second NMOS transistor N2 are connected. Negative pole and power supply V of fifth memristor M5CCAnd the positive electrode of the fifth memristor M5 is connected with the drain electrode (D1) of the first NMOS transistor N1 and the negative electrode of the eighth memristor M8. The source (S1) of the first NMOS transistor N1 is connected with the cathode of the sixth memristor M6 and the drain (D2) of the second NMOS transistor N2. The positive electrode of the sixth memristor M6 is connected to the source (S2) of the second NMOS transistor N2. First, theThe sources (S2) of the two NMOS tubes N2 and the positive electrode of the sixth memristor M6 are connected with the ground terminal. The positive electrode of the seventh memristor M7 is connected with the positive electrode of the eighth memristor M8, and the corresponding output of the seventh memristor M7 is a three-valued exclusive OR TXOR. The gate (G3) of the third NMOS transistor N3 and the gate (G4) of the fourth NMOS transistor N4 are connected to the positive electrode of the eighth memristor M8. Ninth memristor M9 cathode and power supply VCCThe positive electrode of the ninth memristor M9 is connected to the drain (D3) of the third NMOS transistor N3. The source (S3) of the third NMOS transistor N3 is connected to the cathode of the tenth memristor M10 and the drain (D4) of the fourth NMOS transistor N4. The positive electrode of the tenth memristor M10 is connected to the source (S4) and the ground terminal of the fourth NMOS transistor N4. The drain voltage of the third NMOS transistor N3 is the same or TXNOR output.
It should be appreciated by those skilled in the art that the above embodiments are only used for verifying the present invention, and are not to be construed as limiting the present invention, and that the changes and modifications of the above embodiments are within the scope of the present invention.
Claims (3)
1. The three-value exclusive-OR and exclusive-OR logic gate circuit based on the memristor comprises a three-value OR gate TOR, a three-value AND gate TAND, a three-value NOT gate TI and a three-value NAND gate TNAND, and is realized by utilizing the switching characteristic and the memory characteristic of the memristor, and is characterized in that:
the first input terminal IN1 and the second input terminal IN2 are respectively common input terminals of a three-value or gate TOR and a three-value nand gate TNAND, outputs of the three-value or gate TOR and the three-value nand gate are two inputs of a three-value and gate TAND, outputs of the three-value and gate are inputs of a three-value not gate TI, and finally, an output of the three-value and gate TAND is an exclusive or TXOR, and an output of the three-value not gate TI is an exclusive or TXNOR.
2. The memristor-based three-valued exclusive-OR and exclusive-OR logic gate circuit of claim 1, wherein: the concrete structure is as follows:
the three-value OR gate TOR consists of a first memristor M1 and a second memristor M2;
the three-value AND gate TAND is composed of a seventh memristor M7 and an eighth memristor M8;
the three-value NOT gate TI is composed of a ninth memristor M9, a tenth memristor M10, a third NMOS tube N3 and a fourth NMOS tube N4;
the three-value NAND gate TNAND comprises a three-value AND gate and a three-value NOT gate, wherein the AND gate in the three-value NAND gate comprises a third memristor M3 and a fourth memristor M4, and the NOT gate in the three-value NAND gate comprises a fifth memristor M5, a sixth memristor M6, a first NMOS tube N1 and a second NMOS tube N2;
the specific connection relationship is as follows:
the first input end IN1 is connected with the anode of a first memristor M1 and the cathode of a third memristor M3, and the second input end IN2 is connected with the anode of a second memristor M2 and the cathode of a fourth memristor M4;
the negative electrode of the first memristor M1 and the negative electrode of the second memristor M2 are connected with the negative electrode of the seventh memristor M7; the positive electrode of the third memristor M3, the positive electrode of the fourth memristor M4, the gate of the first NMOS transistor N1 and the gate of the second NMOS transistor N2 are connected;
the positive electrode of the fifth memristor M5 is connected with the drain electrode of the first NMOS transistor N1 and the negative electrode of the eighth memristor M8; the source electrode of the first NMOS tube N1 is connected with the negative electrode of the sixth memristor M6 and the drain electrode of the second NMOS tube N2; the anode of the sixth memristor M6 is connected with the source electrode of the second NMOS transistor N2; the source electrode of the second NMOS tube N2 and the positive electrode of the sixth memristor M6 are connected with the ground terminal;
the positive electrode of the seventh memristor M7 is connected with the positive electrode of the eighth memristor M8, and the corresponding output of the seventh memristor M7 is a three-value exclusive OR TXOR;
the grid electrode of the third NMOS tube N3 and the grid electrode of the fourth NMOS tube N4 are connected with the positive electrode of the eighth memristor M8; ninth memristor M9 cathode and power supply VCCThe positive electrode of the ninth memristor M9 is connected with the drain electrode of the third NMOS transistor N3; the source electrode of the third NMOS transistor N3 is connected with the negative electrode of the tenth memristor M10 and the drain electrode of the fourth NMOS transistor N4; the positive electrode of the tenth memristor M10 is connected with the source electrode and the grounding end of the fourth NMOS transistor N4; the drain voltage of the third NMOS transistor N3 is the output tri-equal or TXNOR.
3. The memristor-based three-valued exclusive OR and XNOR logic gate circuit of claim 1The road, its characterized in that: the logic states in a three-valued XOR and XNOR logic gate circuit are voltage values, wherein a voltage V is definedCCIs 2V, corresponding to logic 2, voltage VCCAnd/2, 1V corresponds to logic 1, GND is 0V, and corresponds to logic 0.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112910457A (en) * | 2021-01-21 | 2021-06-04 | 西南大学 | Memristor-based data selector and IC topological structure thereof |
| CN113098492A (en) * | 2021-03-26 | 2021-07-09 | 杭州电子科技大学 | Digital same or and exclusive OR gate implementation method based on ternary memristor cross array |
| CN114741050A (en) * | 2022-04-11 | 2022-07-12 | 安徽工程大学 | Full-addition circuit, high carry circuit and adder based on memristor and CMOS transistor |
| CN116054816A (en) * | 2023-03-29 | 2023-05-02 | 山东云海国创云计算装备产业创新中心有限公司 | Encryption logic unit circuit, encryption chip, server and image encryption method |
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| CN113098492B (en) * | 2021-03-26 | 2022-07-26 | 杭州电子科技大学 | Digital same or and exclusive OR gate implementation method based on ternary memristor cross array |
| CN114741050A (en) * | 2022-04-11 | 2022-07-12 | 安徽工程大学 | Full-addition circuit, high carry circuit and adder based on memristor and CMOS transistor |
| CN116054816A (en) * | 2023-03-29 | 2023-05-02 | 山东云海国创云计算装备产业创新中心有限公司 | Encryption logic unit circuit, encryption chip, server and image encryption method |
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Application publication date: 20200818 |