CN112751570A - Three-variable odd-even detection circuit based on memristor - Google Patents
Three-variable odd-even detection circuit based on memristor Download PDFInfo
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
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Abstract
The invention relates to a memristor-based three-variable parity detection circuit which comprises two-input OR gates, six two-input AND gates and three phase inverters, wherein the two-input OR gates are connected with the six two-input AND gates; the inverter is based on a CMOS device, and the AND gate and the OR gate are both based on a memristor; the OR gate comprises a first OR gate and a second OR gate; the AND gates comprise a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate and a sixth AND gate; the inverters include a first inverter, a second inverter, and a third inverter. The input and output signals follow the following logical relationship: when the level input by the input signal a, b and c ends simultaneously corresponds to even number of 1's in the logic, the output signal out end outputs high level corresponding to logic 1; when the input signals a, b and c have odd numbers of 1 in the corresponding logic, the output signal out outputs low level corresponding to 0. The invention has reasonable structure and easy implementation. The circuit can be applied to the field of digital circuits.
Description
Technical Field
The invention belongs to the technical field of circuit design, and relates to a memristor-based three-variable parity detection circuit.
Background
The memristor is a novel nanoscale device. In 2008, the wheatstone williams research group announced the first practical memristor implementation that immediately elicited academic and industrial interest. The memristor is actually a two-terminal device and is mainly characterized by non-volatility and nanoscale characteristic size, so that the memristor can perform calculation and storage simultaneously. The unique property of the memristor makes the memristor have good application prospect in logic circuits.
In a conventional digital device, the data transfer amount is large, and the data is composed of binary digits consisting of 0 and 1. In the data transmission process, errors in the transmission of binary information such as 0 to 1 or 1 to 0 may occur due to noise, interference, and the like. To check for such errors, a parity method is often employed. That is, a check bit is added after the original binary information code group, so that the number of 1 code elements in the whole code group after the check bit code elements are added is an odd number or an even number. If the number is odd, the method is called odd check; if the number is even, the parity is called even parity.
The parity detection circuit is a basic circuit for realizing parity check and is also an important circuit structure commonly seen in digital circuits. Conventional integrated circuit technology has matured very well and CMOS technology has nearly reached physical size limits. Compared with the traditional circuit, the memristor attracts numerous scientific researchers to research the circuit based on the memristor because of the advantages of being compatible with a CMOS circuit, high in operation speed, low in power consumption, small in layout area and the like. Circuits such as adders, multipliers, encoders, decoders, and numerical comparators based on memristors have been widely studied and designed, but few circuits related to parity detection functions based on memristors have been studied. The invention designs a three-variable odd-even detection circuit based on a memristor.
Disclosure of Invention
Aiming at the technical problems of low operation speed, high power consumption, large layout area and the like of an odd-even detection circuit of the conventional circuit, the invention designs a memristor-based three-variable odd-even detection circuit.
The embodiments adopted by the invention are as follows:
the invention comprises two-input OR gates, six two-input AND gates and three phase inverters, wherein the phase inverters are based on CMOS devices, and the AND gates and the OR gates are based on memristors; the OR gate comprises a first OR gate and a second OR gate; the AND gates comprise a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate and a sixth AND gate; the inverters include a first inverter, a second inverter, and a third inverter.
The AND gate and the OR gate comprise a first input end, a second input end and an output end.
The first input end of the first AND gate is connected with an input signal a, the second input end of the first AND gate is connected with an input signal b, and the output end of the first AND gate is connected with the input end of the first inverter; the first input end of the second AND gate is connected with the input signal a, the second input end of the second AND gate is connected with the output end of the first inverter, and the output end of the second AND gate is connected with the first input end of the first OR gate; the first input end of the third AND gate is connected with the output end of the first inverter, the second input end of the third AND gate is connected with the b end of the input signal, and the output end of the third AND gate is connected with the second input end of the first OR gate; the output end of the first OR gate is connected with the input end of the second inverter; the first input end of the fourth AND gate is connected with the output end of the second inverter, the second input end of the fourth AND gate is connected with the c end of the input signal, and the output end of the fourth AND gate is connected with the input end of the third inverter; the first input end of the fifth AND gate is connected with the output end of the second inverter, the second input end of the fifth AND gate is connected with the output end of the third inverter, and the output end of the fifth AND gate is connected with the first input end of the second OR gate; the first input end of the sixth AND gate is connected with the output end of the third inverter, the second input end of the sixth AND gate is connected with the c end of the input signal, and the output end of the sixth AND gate is connected with the second input end of the second OR gate; the output terminal of the second or gate serves as an output signal out terminal.
The three input signal a, b, c terminals and the output signal out terminal of the circuit follow the following logical relationship:
when the input signals a, b and c are respectively input with low level, low level and low level, the output signal out terminal outputs high level corresponding to logic "0", "0" and "0", and the output signal a, b and c terminal outputs logic "1";
when the input signals a, b and c are respectively input with low level, low level and high level, the output signal out terminal outputs low level corresponding to logic "0", "0" and "1" and corresponds to logic "0";
when the input signals a, b and c are respectively input with low level, high level and low level, the output signal out terminal outputs low level corresponding to logic "0", "1" and "0";
when the input signals a, b and c are respectively input with low level, high level and high level, the output signal out terminal outputs high level corresponding to logic '0', '1' and '1';
when the input signals a, b and c are respectively input with high level, low level and low level, the output signal out terminal outputs low level corresponding to logic "1", "0" and "0";
when the input signals a, b and c are respectively input with high level, low level and high level, the output signal out terminal outputs high level corresponding to logic '1', '0' and '1';
when the input signals a, b and c are respectively input with high level, high level and low level, the output signal out terminal outputs high level corresponding to logic '1', '1' and '0';
when the input signals a, b, and c are inputted with high level, and high level, respectively, the output signal out outputs low level corresponding to logic "1", and corresponds to logic "0".
The logical relationship has the following characteristics:
when the level input by the input signal a, b and c ends simultaneously corresponds to even number of 1's in the logic, the output signal out end outputs high level corresponding to logic 1;
when the input signals a, b and c have odd numbers of 1 in the corresponding logic, the output signal out outputs low level corresponding to 0.
The circuit structure can construct an arbitrary bit number parity detection circuit based on the memristor in a cascading mode.
The invention designs a novel three-variable odd-even detection circuit based on the memristor, and the three-variable odd-even detection circuit is reasonable in structure and convenient to implement. The circuit can be applied to the field of digital circuits for application research and has important significance for future circuit research based on memristors.
Drawings
FIG. 1 is a memristor AND gate circuit structure;
FIG. 2 is a memristor AND gate symbol;
FIG. 3 is a memristor or gate structure;
FIG. 4 is a memristor or gate symbol;
FIG. 5 is a CMOS inverter symbol;
FIG. 6 is a circuit diagram of a memristor-based three-variable parity detection circuit of the present disclosure;
FIG. 7 is a graph of simulation results for a memristor-based tri-variable parity-detection circuit of the present disclosure.
In the figure, 1, a first input end of an AND gate, 2, a second input end of the AND gate, 3, an output end of the AND gate, 4, a first input end of an OR gate, 5, a second input end of the OR gate, 6, an output end of the OR gate, 7, an input signal a end, 8, an input signal b end, 9, an input signal c end and 10, and an output signal out end.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
The invention designs a memristor-based three-variable parity detection circuit, which is shown in a circuit diagram of fig. 6 and comprises two-input OR gates, six two-input AND gates and three inverters, wherein the logical relation of the AND gates and the logical relation of the OR gates are realized through the switching characteristic and the memory characteristic of a memristor.
The logic state in a memristor-based tri-variable parity-detection circuit is represented by the magnitude of a voltage value, where a high-level voltage is defined as 1V, corresponding to a logic "1", and a low-level voltage is defined as 0V, corresponding to a logic "0".
According to the working principle of the memristor, in the circuit, the AND gate is connected with the anodes of the two memristors, the cathodes of the two memristors are respectively used as a first input end and a second input end of the AND gate, the connected anodes are used as output ends, and the output signal is positive voltage. The OR gate is connected by the negative poles of the two memristors, the positive poles of the two memristors are respectively used as a first input end and a second input end of the OR gate, the connected negative poles are used as output ends, and the output signal is negative voltage. The structure of the AND gate circuit is shown in FIG. 1, and the structure of the OR gate circuit is shown in FIG. 3. The AND gate symbol is shown in FIG. 2, and the OR gate symbol is shown in FIG. 4.
The CMOS inverter circuit symbol is shown in fig. 5.
The circuit diagram of the memristor-based three-variable parity detection circuit is shown in fig. 6, wherein a first input end of a first and gate is connected with an input signal a, a second input end of the first and gate is connected with an input signal b, and an output end of the first and gate is connected with an input end of a first inverter; the first input end of the second AND gate is connected with the input signal a, the second input end of the second AND gate is connected with the output end of the first inverter, and the output end of the second AND gate is connected with the first input end of the first OR gate; the first input end of the third AND gate is connected with the output end of the first phase inverter, the second input end of the third AND gate is connected with the b end of the input signal, and the output end of the third AND gate is connected with the second input end of the first OR gate; the output end of the first OR gate is connected with the input end of the second inverter; the first input end of the fourth AND gate is connected with the output end of the second inverter, the second input end of the fourth AND gate is connected with the c end of the input signal, and the output end of the fourth AND gate is connected with the input end of the third inverter; the first input end of the fifth AND gate is connected with the output end of the second inverter, the second input end of the fifth AND gate is connected with the output end of the third inverter, and the output end of the fifth AND gate is connected with the first input end of the second OR gate; the first input end of the sixth AND gate is connected with the output end of the third inverter, the second input end of the sixth AND gate is connected with the c end of the input signal, and the output end of the sixth AND gate is connected with the second input end of the second OR gate; the output of the second or-gate serves as the output signal out.
According to the working principle of the parity detection circuit, the three input signal a, b and c ends and the output signal out end of the memristor-based three-variable parity detection circuit follow the following logic relationship:
when the input signals a, b and c are respectively input with low level, low level and low level, the output signal out terminal outputs high level corresponding to logic "0", "0" and "0", and the output signal a, b and c terminal outputs logic "1";
when the input signals a, b and c are respectively input with low level, low level and high level, the output signal out terminal outputs low level corresponding to logic "0", "0" and "1" and corresponds to logic "0";
when the input signals a, b and c are respectively input with low level, high level and low level, the output signal out terminal outputs low level corresponding to logic "0", "1" and "0";
when the input signals a, b and c are respectively input with low level, high level and high level, the output signal out terminal outputs high level corresponding to logic '0', '1' and '1';
when the input signals a, b and c are respectively input with high level, low level and low level, the output signal out terminal outputs low level corresponding to logic "1", "0" and "0";
when the input signals a, b and c are respectively input with high level, low level and high level, the output signal out terminal outputs high level corresponding to logic '1', '0' and '1';
when the input signals a, b and c are respectively input with high level, high level and low level, the output signal out terminal outputs high level corresponding to logic '1', '1' and '0';
when the input signals a, b, and c are inputted with high level, and high level, respectively, the output signal out outputs low level corresponding to logic "1", and corresponds to logic "0".
The logical relationship has the following characteristics:
when the level input by the input signal a, b and c ends simultaneously corresponds to even number of 1's in the logic, the output signal out end outputs high level corresponding to logic 1;
when the input signals a, b and c have odd numbers of 1 in the corresponding logic, the output signal out outputs low level corresponding to 0.
When the input signals a, b and c have odd numbers of 1 in the corresponding logic, the output signal out outputs low level corresponding to 0.
A truth table corresponding to the input-output logic relationship of the memristor-based three-variable parity detection circuit is shown in the following table:
| input signal a | Input signal b | Input signal c | Output signal out |
| 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 0 |
The circuit structure of the memristor-based three-variable parity detection circuit can complete the parity detection function, the circuit is subjected to simulation verification, and the simulation result is shown in FIG. 7. The simulation result is in accordance with expectation, and the logic state is accurate and stable. The circuit structure feasibility of the memristor-based three-variable parity detection circuit is proved.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and variations and modifications of the above embodiment are within the scope of the present invention.
Claims (6)
1. A three-variable parity detection circuit based on a memristor is characterized by comprising two-input OR gates, six two-input AND gates and three inverters; the inverter is based on a CMOS device, and the AND gate and the OR gate are both based on a memristor; the OR gate comprises a first OR gate and a second OR gate; the AND gates comprise a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate and a sixth AND gate; the inverters include a first inverter, a second inverter, and a third inverter.
2. The memristor-based tri-variable parity detection circuit according to claim 1, wherein the AND gate and the OR gate comprise a first input terminal, a second input terminal and an output terminal.
3. The memristor-based three-variable parity detection circuit according to claim 1, wherein a first input end of the first AND gate is connected with an input signal a, a second input end of the first AND gate is connected with an input signal b, and an output end of the first AND gate is connected with an input end of the first inverter; the first input end of the second AND gate is connected with the input signal a, the second input end of the second AND gate is connected with the output end of the first inverter, and the output end of the second AND gate is connected with the first input end of the first OR gate; the first input end of the third AND gate is connected with the output end of the first inverter, the second input end of the third AND gate is connected with the b end of the input signal, and the output end of the third AND gate is connected with the second input end of the first OR gate; the output end of the first OR gate is connected with the input end of the second inverter; the first input end of the fourth AND gate is connected with the output end of the second inverter, the second input end of the fourth AND gate is connected with the c end of the input signal, and the output end of the fourth AND gate is connected with the input end of the third inverter; the first input end of the fifth AND gate is connected with the output end of the second inverter, the second input end of the fifth AND gate is connected with the output end of the third inverter, and the output end of the fifth AND gate is connected with the first input end of the second OR gate; the first input end of the sixth AND gate is connected with the output end of the third inverter, the second input end of the sixth AND gate is connected with the c end of the input signal, and the output end of the sixth AND gate is connected with the second input end of the second OR gate; the output terminal of the second or gate serves as an output signal out terminal.
4. A memristor-based tri-variable parity detection circuit according to claims 1 and 3, wherein the three input signal a, b, c terminals and the output signal out terminal of the circuit follow the following logical relationship:
when the input signals a, b and c are respectively input with low level, low level and low level, the output signal out terminal outputs high level corresponding to logic "0", "0" and "0", and the output signal a, b and c terminal outputs logic "1";
when the input signals a, b and c are respectively input with low level, low level and high level, the output signal out terminal outputs low level corresponding to logic "0", "0" and "1" and corresponds to logic "0";
when the input signals a, b and c are respectively input with low level, high level and low level, the output signal out terminal outputs low level corresponding to logic "0", "1" and "0";
when the input signals a, b and c are respectively input with low level, high level and high level, the output signal out terminal outputs high level corresponding to logic '0', '1' and '1';
when the input signals a, b and c are respectively input with high level, low level and low level, the output signal out terminal outputs low level corresponding to logic "1", "0" and "0";
when the input signals a, b and c are respectively input with high level, low level and high level, the output signal out terminal outputs high level corresponding to logic '1', '0' and '1';
when inputting signals a and b; b. when the end c inputs high level, high level and low level respectively, the end c corresponds to logic '1', '1' and '0', and the end out of the output signal outputs high level and corresponds to logic '1';
when the input signals a, b, and c are inputted with high level, and high level, respectively, the output signal out outputs low level corresponding to logic "1", and corresponds to logic "0".
5. The memristor-based tri-variable parity detection circuit according to claim 4, wherein the logical relationship is characterized by:
when the level input by the input signal a, b and c ends simultaneously corresponds to even number of 1's in the logic, the output signal out end outputs high level corresponding to logic 1;
when the input signals a, b and c have odd numbers of 1 in the corresponding logic, the output signal out outputs low level corresponding to 0.
6. The memristor-based three-variable parity detection circuit according to claim 3, wherein the circuit structure is capable of constructing the memristor-based arbitrary-bit-number parity detection circuit in a cascade manner.
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