CN110768660A - Memristor-based reversible logic circuit and operation method - Google Patents

Memristor-based reversible logic circuit and operation method Download PDF

Info

Publication number
CN110768660A
CN110768660A CN201910999035.3A CN201910999035A CN110768660A CN 110768660 A CN110768660 A CN 110768660A CN 201910999035 A CN201910999035 A CN 201910999035A CN 110768660 A CN110768660 A CN 110768660A
Authority
CN
China
Prior art keywords
memristor
resistance state
applying
upper electrode
voltage pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910999035.3A
Other languages
Chinese (zh)
Inventor
李祎
王卓睿
缪向水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huazhong University of Science and Technology
Original Assignee
Huazhong University of Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huazhong University of Science and Technology filed Critical Huazhong University of Science and Technology
Priority to CN201910999035.3A priority Critical patent/CN110768660A/en
Publication of CN110768660A publication Critical patent/CN110768660A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

The invention discloses a reversible logic circuit based on memristors and an operation method thereof, wherein the reversible logic circuit comprises n memristors M1～MnWord line WL and bit line BL1～BLnA control line CL and a fixed value resistor; memristor MiAnd the bit line BLiAnd the lower electrodes of all the memristors are connected with the word line WL, one end of the constant value resistor is connected with the word line WL, and the other end of the constant value resistor is connected with the control line CL. By applying an input signal to the memristor, a logic calculation result is stored in the memristor in a resistance state form of the memristor in real time to realize a series of basic reversible logic gates, and various complex reversible networks are constructed in an energy cascade mode. Unnecessary erasing operation is not needed, the loss of computing energy is not caused, the reversible network with the combination of computing and storage can further reduce the power consumption of the computing network in terms of algorithm, and the reversible network has great application value in the aspect of novel computing architecture in the future and reduces computing loss.

Description

Memristor-based reversible logic circuit and operation method
Technical Field
The invention belongs to the field of microelectronic devices, and particularly relates to a reversible logic circuit based on a memristor and an operation method.
Background
Reversible logic, also known as quantum logic gates, is widely studied in quantum computing and quantum information technology. In addition, the reversible logic also occupies an important position in the fields of nanotechnology, information security, low-power-consumption network design and the like. The huge application value of the reversible logic is attracting the wide attention of the academic and industrial fields and is an indispensable component in the fields of future computer science and quantum computing. Nowadays, the comprehensive theory of reversible logic is gradually mature, the design of a reversible logic network is more and more perfect, and the application of the reversible logic is more and more extensive.
The common purpose of both reversible logic calculation and memristor state logic calculation is to break through the limitation of the prior moore's law and further improve the calculation efficiency, but no researcher carries out related research at present by combining the reversible logic calculation and the memristor state logic calculation.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a reversible logic circuit based on a memristor and an operation method, and aims to reduce the calculation power consumption, simplify the circuit, reduce garbage bits and realize a series of basic reversible logic gates to be cascaded in parallel to construct various complex reversible networks.
To achieve the above object, according to an aspect of the present invention, there is provided a memristor-based reversible logic circuit, including n memristors M1～MnWord line WL and bit line BL1～BLnControl line CL and constant value resistor 100, memristor MiUpper electrode and bit line BLiAnd the lower electrodes of all the memristors are connected with a word line WL, one end of the fixed-value resistor 100 is connected with the word line WL, and the other end of the fixed-value resistor is connected with a control line CL.
Wherein, i is 1, 2, …, n is positive integer.
Preferably, during work, when a forward voltage pulse larger than a first threshold value is applied to two ends of the positive electrode and the negative electrode of the memristor, the memristor is changed to a low-resistance state; when a negative voltage pulse exceeding a second threshold value is applied to the two ends of the positive electrode and the negative electrode of the memristor, the memristor is changed to a high-resistance state;
when the memristor is changed to a low resistance state, the low resistance state of the memristor is recorded as a logic value '1'; when the memristor is changed to a high-resistance state, the high-resistance state of the memristor is recorded as a logic value '0'.
According to another aspect of the present invention, there is provided an operation method for implementing a binary NAND by a reversible logic circuit, where n is 3, comprising the steps of:
respectively writing input information x and input information y into memristor M1And memristor M2Is stored in the memristor M in the form of a resistance state1And memristor M2In, will remember the resistance M3The resistance state of (a) is initialized to a high resistance state;
on recall and hinder ware M1And M2Applying a voltage pulse V to the upper electrodeLIn memory of resistor M3Applying a voltage pulse V to the upper electrodeHThe control line CL applies the ground signal GND,
realizing binary NAND operation, and logic calculating result by memory resistor M3Is stored in the memristor M in real time in the form of the final resistance state3Performing the following steps;
wherein, VHFirst threshold > VLFirst threshold value > (V)H-VL) (ii) a When memory resistor M1And memristor M2Memristor M when at least one is in low resistance state3The voltage across is (V)H-VL) Less than a first threshold, memristor M3The resistance state change does not occur; when memory resistor M1And memristor M2When all are in high-resistance state, the memristor M3Voltage at both ends is VHMemristor M3A resistance state change occurs.
According to another aspect of the present invention, there is provided an operation method for implementing a binary AND in a reversible logic circuit, where n is 3, comprising the steps of:
respectively writing input information x and input information y into memristor M1And memristor M2In the form of resistance state, the resistance state is stored in the memristor M1And memristor M2In, will remember the resistance M3The resistance state of (a) is initialized to a high resistance state;
on recall and hinder ware M1And M2Upper electrode applying connection ofGround signal GND at memristor M3Applying a voltage pulse V to the upper electrodeHThe control line CL is connected to the voltage pulse VLRealizing binary AND operation, AND logic calculation result by memory resistor M3Is stored in the memristor M in real time in the form of the final resistance state3Performing the following steps;
wherein, VHFirst threshold > VLFirst threshold value > (V)H-VL) (ii) a When memory resistor M1And memristor M2Memristor M when at least one is in low resistance state3Voltage at both ends is VHMemristor M3A change in resistance state occurs; when memory resistor M1And memristor M2When all are in high-resistance state, the memristor M3The voltage across is (V)H-VL) Less than a first threshold, memristor M3No resistance state change occurs.
According to another aspect of the present invention, there is provided an operation method for implementing one-bit NOT in a reversible logic circuit, where n is 2, including the steps of:
writing and storing input information x in memristor M1In, will remember the resistance M2The resistance state of (a) is initialized to a high resistance state;
on recall and hinder ware M1Applying a voltage pulse V to the upper electrodeLIn memory of resistor M2Applying a voltage pulse V to the upper electrodeHThe control line CL applies a grounding signal GND to realize one-bit NOT operation, and the logic calculation result is memorized by the memristor M2Is stored in the memristor M in real time in the form of the final resistance state2Performing the following steps;
wherein, VHFirst threshold > VLFirst threshold value > (V)H-VL) (ii) a When memory resistor M1At low resistance state, the memristor M2The voltage across is (V)H-VL) Less than a first threshold, memristor M2The resistance state change does not occur; when memory resistor M1When in the high-resistance state, the memristor M2Voltage at both ends is VHMemristor M2A resistance state change occurs.
According to another aspect of the present invention, there is provided a method for operating a reversible logic circuit to implement a one-bit Data Transfer, where n is 2, comprising the steps of:
writing and storing input information x in memristor M1In, will remember the resistance M2The resistance state of (a) is initialized to a high resistance state;
on recall and hinder ware M1Applying a ground signal GND, a voltage pulse V to the upper electrodeLIn memory of resistor M2Applying a voltage pulse V to the upper electrodeHControl line CL applies voltage pulse VLRealizing one-bit Data Transfer operation, and logic calculation result with memristor M2Is stored in the memristor M in real time in the form of the final resistance state2Performing the following steps;
wherein, VHFirst threshold > VLFirst threshold value > (V)H-VL) (ii) a When memory resistor M1At low resistance state, the memristor M2Voltage at both ends is VHMemristor M2A change in resistance state occurs; when memory resistor M1When in the high-resistance state, the memristor M2The voltage across is (V)H-VL) Less than a first threshold, memristor M2No resistance state change occurs.
According to another aspect of the present invention, there is provided an operation method for implementing a two-bit CNOT in a reversible logic circuit, where n is 4, comprising the steps of:
respectively writing and storing input information x and input information y in the memristor M1And memristor M2In the form of resistance state, the resistance state is stored in the memristor M1And memristor M2In, will remember the resistance M3And memristor M4The resistance state of (a) is initialized to a high resistance state;
on recall and hinder ware M1And M2Applying a voltage pulse V to the upper electrodeLIn memory of resistor M3Applying a voltage pulse V to the upper electrodeHThe control line CL applies a ground signal GND;
on recall and hinder ware M1Applying a low voltage pulse V to the upper electrodeLIn memory of resistor M4Applying a high voltage pulse V to the upper electrodeHMeanwhile, the control line CL is ensured to apply a grounding signal GND;
on recall and hinder ware M4Applying a low voltage pulse V to the upper electrodeLIn memory of resistor M3Applying a high voltage pulse V to the upper electrodeHMeanwhile, the control line CL is ensured to apply a grounding signal GND to realize two-bit CNOT operation, and a logic calculation result is stored by a memristor M1As a first output to recall the resistor M3As a second output;
wherein, VHFirst threshold > VLFirst threshold value > (V)H-VL) When memory resistor M1～M4The voltage across is (V)H-VL) Less than the first threshold, the resistance state does not change when the memristor M is recalled1～M4Voltage at both ends is VHThe resistance state changes.
According to another aspect of the present invention, there is provided an operation method for implementing a two-bit SSG in a reversible logic circuit, where n is 4, including the steps of:
respectively writing and storing input information x and input information y in the memristor M1And memristor M2In the form of resistance state, memory resistor M1And memristor M2In, will remember the resistance M3And memristor M4The resistance state of (a) is initialized to a high resistance state;
on recall and hinder ware M1Applying a ground voltage signal GND to the upper electrode of the memory resistor M4Applying a high voltage pulse V to the upper electrodeHApplying a low voltage pulse V to the control line CLL；
On recall and hinder ware M2Applying a ground voltage signal GND to the upper electrode of the memory resistor M3Applying a high voltage pulse V to the upper electrodeHWhile applying a low voltage pulse V to the control line CLL(ii) a Realize two-bit SSG operation, logic calculation result with memory resistor M3As a first output to recall the resistor M4As a second output;
wherein, VHFirst threshold > VLFirst threshold value > (V)H-VL) When memory resistor M1～M4The voltage across is (V)H-VL) When the resistance is smaller than the first threshold value, the resistance state does not change, and when the memristor M is used1～M4Voltage at both ends is VHThe resistance state changes.
According to another aspect of the present invention, there is provided an operation method for implementing CCNOT in a reversible logic circuit, where n is 6, including the following steps:
respectively writing and storing the input information x, the input information x and the input information t in the memristor M1Memristor M2And memristor M3In, will remember the resistance M4～M6The resistance state of (a) is initialized to a high resistance state;
on recall and hinder ware M1And M2Applying a ground signal GND to the upper electrode of the memristor M5Applying a high voltage pulse V to the upper electrodeHWhile a low voltage pulse V is connected to the control line CLL；
On recall and hinder ware M3And M5Applying a low voltage pulse V to the upper electrodeLIn memory of resistor M4Applying a high voltage pulse V to the upper electrodeHThe control line CL applies a ground signal GND;
on recall and hinder ware M5Applying a low voltage pulse V to the upper electrodeLIn memory of resistor M6Applying a high voltage pulse V to the upper electrodeHThe control line CL applies a ground signal GND;
on recall and hinder ware M3Applying a low voltage pulse V to the upper electrodeLIn memory of resistor M6Applying a high voltage pulse V to the upper electrodeHThe control line CL applies a ground signal GND;
on recall and hinder ware M6Applying a low voltage pulse V to the upper electrodeLIn memory of resistor M4Applying a high voltage pulse V to the upper electrodeHThe control line CL applies a ground signal GND; realize CCNOT operation, logic calculation result with memory resistor M1As a first output to recall the resistor M2As a second output to recall the resistor M4As a third output;
wherein, VHFirst threshold > VLFirst threshold value > (V)H-VL) When memory resistor M1～M6The voltage across is (V)H-VL) Less than the first threshold, the resistance state does not change when the memristor M is recalled1～M6Voltage at both ends is VHThe resistance state changes.
According to another aspect of the present invention, there is provided a method of operation of a reversible logic circuit implementing a multi-bit n-CNOT, comprising the steps of:
will input information x1～xnAnd the input information t are respectively written into and stored in the memristor M1～MnAnd Mn+1In, will remember the resistance Mn+2～Mn+4The resistance state of (a) is initialized to a high resistance state;
on recall and hinder ware M1～MnIs grounded at the memristor Mn+3Applying a high voltage pulse V to the upper electrodeHThe control line CL is connected to a low-voltage pulse VL；
On recall and hinder ware Mn+1And Mn+3Applying a low voltage pulse V to the upper electrodeLIn memory of resistor Mn+2Applying a high voltage pulse V to the upper electrodeHThe control line CL applies a ground signal GND;
on recall and hinder ware Mn+3Applying a low voltage pulse V to the upper electrodeLIn memory of resistor Mn+4Applying a high voltage pulse V to the upper electrodeHThe control line CL applies a ground signal GND;
on recall and hinder ware Mn+1Applying a low voltage pulse V to the upper electrodeLIn memory of resistor Mn+4Applying a high voltage pulse V to the upper electrodeHThe control line CL applies a ground signal GND;
on recall and hinder ware Mn+4Applying a low voltage pulse V to the upper electrodeLIn memory of resistor Mn+2Applying a high voltage pulse V to the upper electrodeHThe control line CL applies a ground signal GND; realizing multi-bit n-CNOT operation, and logic calculation result by memory resistor M1～MnThe final resistance state of the first n-bit output is used as a memristor Mn+2As the n +1 th bit outputs z ═ x1·x2·…·xn)⊕t；
Wherein, VHFirst threshold > VLFirst threshold value > (V)H-VL) When memory resistor M1～Mn+4The voltage across is (V)H-VL) Less than the first threshold, the resistance state does not change when the memristor M is recalled1～Mn+4Voltage at both ends is VHThe resistance state changes.
Through the technical scheme, compared with the prior art, the invention has the following beneficial effects:
1. the input and output information of the reversible logic circuit based on the memristor is directly stored in the memristor unit in the form of a resistance state, redundant erasing and writing operations are not needed, and the loss of computing energy is not caused;
2. the reversible logic circuit based on the memristor is convenient to cascade, in a large-scale memristor array, the reversible logic circuit can be easily cascaded no matter in series or in parallel with the reversible logic gate, and the input unit and the output unit are reasonably distributed, so that the cascading problem of the traditional CMOS reversible network can be greatly simplified, and the complexity of the reversible network is reduced;
3. the general reversible logic gate is successfully constructed based on the memristor array, on the basis, all reversible logic gates in the traditional sense can be realized, and input information can be used as output information at the same time, so that a large amount of circuit resources can be saved, the circuit is greatly simplified, simultaneously, junk bit information is reduced, and particularly for an n-bit control NOT gate, the realization can be realized only by n +4 memristor units and 6 steps of sequential logic operation.
Drawings
FIG. 1 is a schematic diagram of a memristor-based reversible logic circuit provided by an embodiment of the present disclosure;
FIG. 2(a) is a schematic diagram of a binary NAND logic operation of the reversible logic circuit according to an embodiment of the present invention;
fig. 2(b) is a schematic diagram of AND logic operation of the reversible logic circuit provided in the embodiment of the present invention;
fig. 3(a) is a schematic diagram of a one-bit reversible logic gate NOT logic operation of the reversible logic circuit according to an embodiment of the present invention;
fig. 3(b) is a NOT logic truth table of a one-bit reversible logic gate of the reversible logic circuit according to the embodiment of the present invention;
fig. 3(c) is a schematic circuit symbol diagram of a one-bit reversible logic gate NOT of the reversible logic circuit provided in the embodiment of the present invention;
fig. 4(a) is a schematic diagram of a one-bit reversible logic gate Data Transfer logic operation of the reversible logic circuit according to the embodiment of the present invention;
fig. 4(b) is a Data Transfer logic truth table of a one-bit reversible logic gate of the reversible logic circuit according to the embodiment of the present invention;
fig. 4(c) is a schematic circuit diagram of a one-bit reversible logic gate Data Transfer of the reversible logic circuit according to the embodiment of the present invention;
fig. 5(a) is a schematic diagram of a two-bit reversible logic gate CNOT logic operation of the reversible logic circuit according to an embodiment of the present invention;
fig. 5(b) is a two-bit reversible logic gate CNOT logic truth table of the reversible logic circuit according to the embodiment of the present invention;
fig. 5(c) is a schematic circuit diagram of a two-bit reversible logic gate CNOT of the reversible logic circuit according to an embodiment of the present invention;
FIG. 6(a) is a schematic diagram of an SSG logic operation of a reversible logic circuit according to an embodiment of the present invention;
FIG. 6(b) is a two-bit reversible logic gate SSG logic truth table for the reversible logic circuit according to an embodiment of the present invention;
FIG. 6(c) is a schematic circuit diagram of a two-bit reversible logic gate SSG of the reversible logic circuit according to an embodiment of the present invention;
fig. 7(a) is a schematic diagram of a universal reversible logic gate CCNOT logic operation of the reversible logic circuit provided in the embodiment of the present invention;
fig. 7(b) is a common reversible logic gate CCNOT logic truth table of the reversible logic circuit provided by the embodiment of the present invention;
fig. 7(c) is a schematic circuit symbol diagram of a general-purpose reversible logic gate CCNOT of the reversible logic circuit provided by the embodiment of the present invention;
fig. 8 is a schematic diagram of an n-bit reversible logic gate n-CNOT logic operation of the reversible logic circuit according to an embodiment of the present invention;
throughout the drawings, the same reference numerals are used to designate the same elements or structures, wherein 100 is a constant resistance.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The reversible logic circuit based on the memristor, as shown in fig. 1, includes: bit line BL1～BLnFor inputting a bit line signal; a word line WL for inputting a word line signal; a control line CL for inputting a control signal; memristor M1～MnAnd a fixed resistor 100. Wherein the memristor MiUpper electrode and bit line BLiConnected (i is 1, 2 …, n, n is a positive integer), the bottom electrodes of all memristors are connected with a word line WL, one end of a constant resistance 100 is connected with the word line WL, the other end is connected with a control line CL, and the resistance value of the constant resistance is defined as Rs. Memristors have two resistance states: a High resistance state (H) and a Low resistance state (L), the High resistance state resistance value being defined as RHThe low resistance state resistance value is defined as RL，RH>>RLDefining the resistance value R of the constant value resistor 100sIs composed of
Figure BDA0002240685930000091
We define the high resistance state of the memristor as the logic signal "1" and the low resistance state as the logic signal "0".
In the subsequent logic operation process, the voltage pulse signals are adopted, and particularly comprise low-voltage pulse signals VLHigh voltage pulse signal VHAnd a ground voltage signal GND. Wherein the high voltage pulse signal VHThe memristor can be subjected to Set transition, the high resistance state H is changed into the low resistance state L, and the low voltage pulse signal V is obtainedLGround voltage signals GND and VH-VLThe memristive device cannot be subjected to resistance transition.
FIG. 2 shows a logic circuit AND an operation method for implementing conventional binary NAND AND AND logic operations based on the memristive-reversible logic circuit of FIG. 1, specifically including bit line BL1～BL3Word line WL, control line CL, memristor M1～M3And a fixed resistor 100. Wherein the memristor M1Is a logic input signal x, M2Is another logic input signal y, the memristor M3Is a high resistance state, and the result of the final logic operation is stored as a resistance state in the memristor M3 as a logic output signal.
The logic operation method for realizing the binary NAND comprises the following steps: on recall and hinder ware M1And M2Applying a low voltage pulse V to the upper electrodeLIn memory of resistor M3Applying a high voltage pulse V to the upper electrodeHWhile ensuring that the control line CL is grounded, as shown in fig. 2 (a).
The logical operation method for realizing the binary AND is as follows: on recall and hinder ware M1And M2Is grounded at the memristor M3Applying a high voltage pulse V to the upper electrodeHWhile a low voltage pulse V is connected to the control line CLLAs shown in fig. 2 (b).
FIG. 3(a) shows a logic truth table for a one-bit reversible logic gate NOT, including a one-bit input x and a one-bit output
Figure BDA0002240685930000101
FIG. 3(b) shows a logic circuit and an operation method for realizing a one-bit reversible logic gate NOT based on the memristive reversible logic circuit shown in FIG. 1, wherein M is1As a logic input signal x, a memristor M2The initial resistance state of the memory is a high resistance state, and the final logic operation result is stored in the memory resistor M in the form of the resistance state2And as a logic output signal.
The specific logical operation method is as follows: on recall and hinder ware M1Applying a low voltage pulse V to the upper electrodeLIn memory of resistor M2Applying a high voltage pulse V to the upper electrodeHWhile ensuring that the control line CL is grounded.
Fig. 3(c) shows a circuit symbol of the one-bit reversible logic gate NOT.
Fig. 4(a) shows a logic truth table of a one-bit reversible logic gate Data transfer, which includes a one-bit input x and a one-bit output x. FIG. 4(b) shows a logic circuit and an operation method for implementing a one-bit reversible logic gate Data transfer based on the memristive reversible logic circuit of FIG. 1, wherein M is1As a logic input signal x, a memristor M2The initial resistance state of the memory is a high resistance state, and the final logic operation result is stored in the memory resistor M in the form of the resistance state2And as a logic output signal.
The specific logical operation method is as follows: on recall and hinder ware M1Applying a ground voltage signal GND to the upper electrode of the memory resistor M2Applying a high voltage pulse V to the upper electrodeHWhile applying a low voltage pulse V to the control line CLL。
Fig. 4(c) shows a circuit symbol of one-bit reversible logic gate Data transfer.
Fig. 5(a) shows a logic truth table of a two-bit reversible logic gate CNOT, which includes two bits of input information x and y and two bits of output information x and z. FIG. 5(b) shows a logic circuit based on the memristive reversible logic circuit of FIG. 1 to realize a two-bit reversible logic gate CNOT gate, wherein a memristor M is connected to the two-bit reversible logic gate CNOT gate1Is defined as control bit input informationx, memristor M2The initial resistance state of (a) is defined as the second bit of input information y, since the input bit of information does not change during subsequent logic operations, the memristor M may be made to1Is defined as one of the bits outputting information, the memristor M3And M4The initial resistance states are all high resistance states, and the memristor M3Is defined as the second bit of output information z, the memristor M4And the logic calculation is participated as an auxiliary device.
The specific logical operation method is as follows:
(1) will remember the resistance M1And M2Initializing the resistance state of (1) to input information x and y, and (2) memristor M3And M4Is initialized to a high resistance state;
(2) on recall and hinder ware M1And M2Applying a low voltage pulse V to the upper electrodeLIn memory of resistor M3Applying a high voltage pulse V to the upper electrodeHMeanwhile, the control line CL is ensured to be grounded;
(3) on recall and hinder ware M1Applying a low voltage pulse V to the upper electrodeLIn memory of resistor M4Applying a high voltage pulse V to the upper electrodeHMeanwhile, the control line CL is ensured to be grounded;
(4) on recall and hinder ware M2Applying a low voltage pulse V to the upper electrodeLIn memory of resistor M4Applying a high voltage pulse V to the upper electrodeHMeanwhile, the control line CL is ensured to be grounded;
(5) on recall and hinder ware M4Applying a low voltage pulse V to the upper electrodeLIn memory of resistor M3Applying a high voltage pulse V to the upper electrodeHWhile ensuring that the control line CL is grounded. Will remember the resistance M1As the first bit of output information, will recall the resistor M3As the second bit output information.
Fig. 5(c) shows a circuit symbol of the two-bit reversible logic gate CNOT gate.
FIG. 6(a) shows a logic truth table of a two-bit reversible logic gate SSG, which includes two-bit input information x and y, and two-bit output information y andx. FIG. 6(b) shows a logic circuit implementing a two-bit reversible logic gate SSG based on the memristive reversible logic circuit of FIG. 1, wherein a memristor M is connected to the logic circuit1Is defined as the first bit of input information x, the memristor M2Is defined as the second bit of input information y, the memristor M3And M4The initial resistance states are all high resistance states, and the memristor M3Is defined as the first bit of output information y, the memristor M4Is defined as the second bit output information x.
The specific logical operation method is as follows:
(1) and (5) initializing. Will remember the resistance M1And M2Initializing the resistance state of (1) to input information x and y, and (2) memristor M3And M4The resistance state of (a) is initialized to a high resistance state;
(2) on recall and hinder ware M1Applying a ground voltage signal GND to the upper electrode of the memory resistor M4Applying a high voltage pulse V to the upper electrodeHWhile applying a low voltage pulse V to the control line CLL。
(3) On recall and hinder ware M2Applying a ground voltage signal GND to the upper electrode of the memory resistor M3Applying a high voltage pulse V to the upper electrodeHWhile applying a low voltage pulse V to the control line CLL。
Fig. 6(c) shows a circuit symbol of the two-bit reversible logic gate SSG.
Fig. 7(a) shows a logic truth table of the general-purpose reversible logic gate CCNOT, which includes three-bit input information x, y, and t and three-bit output information x, y, and z. Fig. 7(b) shows a circuit symbol of the general-purpose reversible logic gate CCNOT. FIG. 7(c) shows a logic circuit for implementing a universal reversible logic gate CCNOT based on the memristive reversible logic circuit of FIG. 1, wherein a memristor M is used1Is defined as a first bit of control bit input information x, a memristor M2Is defined as the second bit control bit input information y, the memristor M3Is defined as the third bit target bit input information t. Memristor M during subsequent logic operation1～M3Resistance state ofWill not change, so the memristor M can be used1Is defined as the first bit of output information x, the memristor M2Is defined as the second bit of output information y, the memristor M4～M6The initial resistance states are all high resistance states, and the memristor M4Is defined as the third bit of output information z, the memristor M5And M6And the logic calculation is participated as an auxiliary device.
The specific logical operation method is as follows:
(1) and (5) initializing. Will remember the resistance M1～M3Respectively initializing the resistance states of the memristors into input information x, y and t, and memorizing the memristor M4～M6Is initialized to a high resistance state;
(2) on recall and hinder ware M1And M2Is grounded at the memristor M5Applying a high voltage pulse V to the upper electrodeHWhile a low voltage pulse V is connected to the control line CLL；
(3) On recall and hinder ware M3And M5Applying a low voltage pulse V to the upper electrodeLIn memory of resistor M4Applying a high voltage pulse V to the upper electrodeHMeanwhile, the control line CL is ensured to be grounded;
(4) on recall and hinder ware M5Applying a low voltage pulse V to the upper electrodeLIn memory of resistor M6Applying a high voltage pulse V to the upper electrodeHMeanwhile, the control line CL is ensured to be grounded;
(5) on recall and hinder ware M3Applying a low voltage pulse V to the upper electrodeLIn memory of resistor M6Applying a high voltage pulse V to the upper electrodeHMeanwhile, the control line CL is ensured to be grounded;
(6) on recall and hinder ware M6Applying a low voltage pulse V to the upper electrodeLIn memory of resistor M4Applying a high voltage pulse V to the upper electrodeHWhile ensuring that the control line CL is grounded. Memristor M at this moment4The logic operation result stored in the memory is (x.y) ⊕ t1Is defined as the first bit of output information x, the memristor M2Final electricity ofThe resistance state is defined as the second bit output information y, which will recall the resistor M4As the third bit output information z.
FIG. 8 shows a logic circuit for realizing an n-bit general reversible logic gate n-CNOT based on the memristive reversible logic circuit in FIG. 1, wherein an input bit of the n-bit general reversible logic gate n-CNOT includes n pieces of control bit information x1～xnAnd a target bit information t, the output bit information including n bits of output information x1～xnAnd one-bit output information z, where z ═ x1·x2·…·xn) The ⊕ t.n bit universal reversible logic gate circuit comprises n +4 memristive devices M1～Mn+4And a fixed resistor 100. Wherein the memristor M1～MnThe resistance state information (x) stored in1～xn) Can be used as input information and output information at the same time, and the memristor Mn+1The initial resistance state of (1) is defined as target bit input information t, memristor Mn+2～Mn+4The initial resistance states are all high resistance states, and the memristor Mn+2Is defined as the output information z, the memristor Mn+3And Mn+4And the logic calculation is participated as an auxiliary device.
The specific logical operation method is as follows:
(1) and (5) initializing. Will remember the resistance M1～Mn+1Respectively initialized to the input information x1、x2、…、xnT, will recall and hinder ware Mn+2～Mn+4Is initialized to a high resistance state;
(2) on recall and hinder ware M1～MnIs grounded at the memristor Mn+3Applying a high voltage pulse V to the upper electrodeHWhile a low voltage pulse V is connected to the control line CLL；
(3) On recall and hinder ware Mn+1And Mn+3Applying a low voltage pulse V to the upper electrodeLIn memory of resistor Mn+2Applying a high voltage pulse V to the upper electrodeHMeanwhile, the control line CL is ensured to be grounded;
(4) on recall and hinder ware Mn+3Applying a low voltage pulse V to the upper electrodeLIn memory of resistor Mn+4Applying a high voltage pulse V to the upper electrodeHMeanwhile, the control line CL is ensured to be grounded;
(5) on recall and hinder ware Mn+1Applying a low voltage pulse V to the upper electrodeLIn memory of resistor Mn+4Applying a high voltage pulse V to the upper electrodeHMeanwhile, the control line CL is ensured to be grounded;
(6) on recall and hinder ware Mn+4Applying a low voltage pulse V to the upper electrodeLIn memory of resistor Mn+2Applying a high voltage pulse V to the upper electrodeHWhile ensuring that the control line CL is grounded. Memristor M at this momentn+2The result of the logical operation stored in (c) is (x)1·x2·…·xn) ⊕ t. will remember the resistor M1～MnThe resistance state information (x) stored in1～xn) As the first n bits of output information, the memristor Mn+2As the n +1 th bit output information z.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (10)

1. A reversible logic circuit based on memristors is characterized by comprising n memristors M1～MnWord line WL and bit line BL1～BLnA control line CL and a fixed value resistor; memristor MiAnd the bit line BLiThe lower electrodes of all the memristors are connected with the word line WL and pass through the memristor MiThe upper electrode and the lower electrode apply voltage pulses, and the size of the voltage pulses is controlled to realize different reversible logic operations; one end of the fixed resistor is connected with the word line WL, and the other end of the fixed resistor is connected with the control line CL;
wherein, i is 1, 2, …, n is a positive integer of 2 or more.
2. The reversible logic circuit according to claim 1, wherein in operation, the memristor is resistive to a low resistance state by applying a forward voltage pulse greater than a first threshold across positive and negative electrodes of the memristor; when negative voltage pulses exceeding a second threshold value are applied to the two ends of the positive electrode and the negative electrode of the memristor, the memristor is changed into a high-resistance state;
when the memristor is changed to a low resistance state, the low resistance state of the memristor is recorded as a logic value '1'; when the memristor is changed to a high-resistance state, the high-resistance state of the memristor is recorded as a logic value '0'.
3. An operation method for implementing binary NAND based on the reversible logic circuit of claim 2, wherein n is 3, comprising the steps of:
writing input signal x and input signal y into the memristor M, respectively1And the memristor M2Storing the memristor M1 and the memristor M2 in a form of a resistance state3The resistance state of (a) is initialized to a high resistance state;
at the memristor M1And M2Applying a voltage pulse V to the upper electrodeLIn memory of resistor M3Applying a voltage pulse V to the upper electrodeHThe control line CL applies a grounding signal GND to realize binary NAND operation, and the logic calculation result is obtained by the memristor M3Is stored in the memristor M in real time in the form of the final resistance state3Performing the following steps;
wherein, VHFirst threshold > VLFirst threshold value > (V)H-VL) When the memristor M1 and the memristor M2The memristor M is in a low resistance state3The voltage across is (V)H-VL) Less than a first threshold, insufficient to change the resistance state when said memristor M1And the memristor M2When the resistance states are all high, the memristor M3Voltage at both ends is VHSaid memristor M3A resistance state change occurs.
4. An operating method for implementing a binary AND based on the reversible logic circuit of claim 2, when n is 3, comprising the following steps:
writing input signal x and input signal y into the memristor M, respectively1And the memristor M2In the form of resistance state, the resistance state is stored in the memristor M1 and the memristor M2In (c), the memristor M3The resistance state of (a) is initialized to a high resistance state;
at the memristor M1And M2Applying a ground signal GND to the upper electrode of the memristor M3Applying a voltage pulse V to the upper electrodeHControl line CL applies voltage pulse VLRealizing binary AND operation, AND logically calculating the result by the memristor M3Is stored in the memristor M in real time in the form of the final resistance state3Performing the following steps;
wherein, VHFirst threshold > VLFirst threshold value > (V)H-VL) When the memristor M1 and the memristor M2The memristor M is in a low resistance state3Voltage at both ends is VHSaid memristor M3The resistance state change occurs when the memristor M1And the memristor M2When the resistance states are all high, the memristor M3The voltage across is (V)H-VL) Less than the first threshold, is insufficient to change the resistance state.
5. An operation method for implementing one-bit NOT based on the reversible logic circuit as claimed in claim 2, wherein n is 2, comprising the following steps:
writing and storing an input signal x in the memristor M1In (c), the memristor M2The resistance state of (a) is initialized to a high resistance state;
at the memristor M1Applying a voltage pulse V to the upper electrodeLAt the memristor M2Applying a voltage pulse V to the upper electrodeHThe control line CL applies a ground signal GND to realize a one-bit NOT operation and logically calculate the resultThe memristor M2Is stored in the memristor M in real time in the form of the final resistance state2Performing the following steps;
wherein, VHFirst threshold > VLFirst threshold value > (V)H-VL) When the memristor M1When the resistance state is low, the memristor M2The voltage across is (V)H-VL) Less than a first threshold, insufficient to change the resistance state when said memristor M1When the resistance state is high, the memristor M2Voltage at both ends is VHSaid memristor M3A resistance state change occurs.
6. An operation method for implementing one-bit Data Transfer based on the reversible logic circuit as claimed in claim 2, wherein n is 2, comprising the following steps:
writing and storing an input signal x in the memristor M1In (c), the memristor M2The resistance state of (a) is initialized to a high resistance state;
at the memristor M1Applying a ground signal GND, a voltage pulse V to the upper electrodeLAt the memristor M2Applying a voltage pulse V to the upper electrodeHControl line CL applies voltage pulse VL，
Realizing one-bit Data Transfer operation, and logically calculating the result by the memristor M2Is stored in the memristor M in real time in the form of the final resistance state2Performing the following steps;
wherein, VHFirst threshold > VLFirst threshold value > (V)H-VL) When the memristor M1When the resistance state is low, the memristor M2Voltage at both ends is VHSaid memristor M2The resistance state change occurs when the memristor M1When the resistance state is high, the memristor M2The voltage across is (V)H-VL) Less than the first threshold, is insufficient to change the resistance state.
7. An operation method for implementing a two-bit CNOT based on the reversible logic circuit as claimed in claim 2, wherein n is 4, comprising the following steps:
writing and storing an input signal x and an input signal y in the memristor M respectively1And the memristor M2In the form of a resistance state, is stored in the memristor M1And the memristor M2In (c), the memristor M3And memristor M4The resistance state of (a) is initialized to a high resistance state;
on recall and hinder ware M1And M2Applying a voltage pulse V to the upper electrodeLIn memory of resistor M3Applying a voltage pulse V to the upper electrodeHThe control line CL applies a ground signal GND;
on recall and hinder ware M1Applying a low voltage pulse V to the upper electrodeLIn memory of resistor M4Applying a high voltage pulse V to the upper electrodeHMeanwhile, the control line CL is ensured to apply a grounding signal GND;
on recall and hinder ware M2Applying a low voltage pulse V to the upper electrodeLIn memory of resistor M4Applying a high voltage pulse V to the upper electrodeHMeanwhile, the control line CL is ensured to apply a grounding signal GND;
on recall and hinder ware M4Applying a low voltage pulse V to the upper electrodeLIn memory of resistor M3Applying a high voltage pulse V to the upper electrodeHMeanwhile, the control line CL is ensured to apply a grounding signal GND to realize two-bit CNOT operation, and a logic calculation result is obtained by the memristor M1As a first output, with the memristor M3As a second output;
wherein, VHFirst threshold > VLFirst threshold value > (V)H-VL) Said memristor M1～M4The voltage across is (V)H-VL) Less than a first threshold, no change in resistance state, said memristor M1～M4Voltage at both ends is VHThe resistance state changes.
8. An operation method for realizing two-bit SSG based on the reversible logic circuit of claim 2, comprising the steps of:
writing and storing an input signal x and an input signal y in the memristor M respectively1And the memristor M2In the form of a resistance state, is stored in the memristor M1And the memristor M2In (c), the memristor M3And memristor M4The resistance state of (a) is initialized to a high resistance state;
on recall and hinder ware M1Applying a ground voltage signal GND to the upper electrode of the memory resistor M4Applying a high voltage pulse V to the upper electrodeHApplying a low voltage pulse V to the control line CLL；
On recall and hinder ware M2Applying a ground voltage signal GND to the upper electrode of the memory resistor M3Applying a high voltage pulse V to the upper electrodeHWhile applying a low voltage pulse V to the control line CLL；
Implementing a two-bit SSG operation, a logical computation result with the memristor M3As a first output, with the memristor M4As a second output;
wherein, VHFirst threshold > VLFirst threshold value > (V)H-VL) Said memristor M1～M4The voltage across is (V)H-VL) Less than a first threshold, no change in resistance state, said memristor M1～M4The voltage across is (V)H-VL) And if the resistance value is smaller than the first threshold value, the resistance state change does not occur.
9. An operation method for implementing CCNOT based on the reversible logic circuit as claimed in claim 2, wherein n is 6, comprising the following steps:
writing and storing an input signal x, an input signal x and an input signal t in the memristor M respectively1The memristor M2And the memristor M3In (c), the memristor M4～M6The resistance state of (a) is initialized to a high resistance state;
on recall and hinder ware M1And M2Applying a ground signal GND to the upper electrode of the memristor M5Applying a high voltage pulse V to the upper electrodeHWhile a low voltage pulse V is connected to the control line CLL；
On recall and hinder ware M3And M5Applying a low voltage pulse V to the upper electrodeLIn memory of resistor M4Applying a high voltage pulse V to the upper electrodeHThe control line CL applies a ground signal GND;
on recall and hinder ware M5Applying a low voltage pulse V to the upper electrodeLIn memory of resistor M6Applying a high voltage pulse V to the upper electrodeHThe control line CL applies a ground signal GND;
on recall and hinder ware M3Applying a low voltage pulse V to the upper electrodeLIn memory of resistor M6Applying a high voltage pulse V to the upper electrodeHThe control line CL applies a ground signal GND;
on recall and hinder ware M6Applying a low voltage pulse V to the upper electrodeLIn memory of resistor M4Applying a high voltage pulse V to the upper electrodeHThe control line CL applies a ground signal GND;
realizing CCNOT operation, and logically calculating a result by the memristor M1As a first output, with the memristor M2As a second output, with the memristor M4As a third output;
wherein, VHFirst threshold > VLFirst threshold value > (V)H-VL) Said memristor M1～M6The voltage across is (V)H-VL) Less than a first threshold, no change in resistance state, said memristor M1～M6Voltage at both ends is VHThe resistance state changes.
10. An operation method for realizing multi-bit n-CNOT based on the reversible logic circuit of claim 2, comprising the steps of:
respectively at the memristor M1～MnIs applied with the input signal x1～xnRealizing the input signal x1～xnAnd target bit information t are respectively written into and stored in the memristor M1～MnAnd Mn+1In (c), the memristor Mn+2～Mn+4Initializing the resistance state of (a) and the target information t to a high resistance state;
on recall and hinder ware M1～MnIs grounded at the memristor Mn+3Applying a high voltage pulse V to the upper electrodeHThe control line CL is connected to a low-voltage pulse VL；
On recall and hinder ware Mn+1And Mn+3Applying a low voltage pulse V to the upper electrodeLIn memory of resistor Mn+2Applying a high voltage pulse V to the upper electrodeHThe control line CL applies a ground signal GND;
on recall and hinder ware Mn+3Applying a low voltage pulse V to the upper electrodeLIn memory of resistor Mn+4Applying a high voltage pulse V to the upper electrodeHThe control line CL applies a ground signal GND;
on recall and hinder ware Mn+1Applying a low voltage pulse V to the upper electrodeLIn memory of resistor Mn+4Applying a high voltage pulse V to the upper electrodeHThe control line CL applies a ground signal GND;
on recall and hinder ware Mn+4Applying a low voltage pulse V to the upper electrodeLIn memory of resistor Mn+2Applying a high voltage pulse V to the upper electrodeHThe control line CL applies a ground signal GND;
implementing a multi-bit n-CNOT operation, a logical computation result with the memristor M1～MnAs the first n-bit output, with the memristor Mn+2As the n +1 th bit output
Figure FDA0002240685920000061
Figure FDA0002240685920000062
Wherein, VHFirst threshold > VLFirst threshold value > (V)H-VL) Said memristor M1～Mn+4The voltage across is (V)H-VL) Less than a first threshold, no change in resistance state, said memristor M1～Mn+4Voltage at both ends is VHThe resistance state changes.
CN201910999035.3A 2019-10-21 2019-10-21 Memristor-based reversible logic circuit and operation method Pending CN110768660A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910999035.3A CN110768660A (en) 2019-10-21 2019-10-21 Memristor-based reversible logic circuit and operation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910999035.3A CN110768660A (en) 2019-10-21 2019-10-21 Memristor-based reversible logic circuit and operation method

Publications (1)

Publication Number Publication Date
CN110768660A true CN110768660A (en) 2020-02-07

Family

ID=69332283

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910999035.3A Pending CN110768660A (en) 2019-10-21 2019-10-21 Memristor-based reversible logic circuit and operation method

Country Status (1)

Country Link
CN (1) CN110768660A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112865786A (en) * 2020-12-31 2021-05-28 杭州电子科技大学 Digital NOT gate implementation method based on ternary memristor

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150262075A1 (en) * 2012-06-22 2015-09-17 Alex Nugent Methods and systems for feature extraction of surface manifolds
CN105761750A (en) * 2016-02-04 2016-07-13 华中科技大学 Memristor-based multivalued logic device and operating method thereof
CN106297876A (en) * 2016-08-09 2017-01-04 北京大学 Operational approach based on memristor array
CN109388853A (en) * 2018-09-07 2019-02-26 北京大学 A kind of bipolar mixed high-efficient memristor logic circuit of list and its control method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150262075A1 (en) * 2012-06-22 2015-09-17 Alex Nugent Methods and systems for feature extraction of surface manifolds
CN105761750A (en) * 2016-02-04 2016-07-13 华中科技大学 Memristor-based multivalued logic device and operating method thereof
CN106297876A (en) * 2016-08-09 2017-01-04 北京大学 Operational approach based on memristor array
CN109388853A (en) * 2018-09-07 2019-02-26 北京大学 A kind of bipolar mixed high-efficient memristor logic circuit of list and its control method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MIAO-MIAO JIN等: ""Reconfigurable logic in nanosecond Cu/GeTe/TiN filamentary memristors for energy-efficient in-memory computing"", 《NANOTECHNOLOGY》 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112865786A (en) * 2020-12-31 2021-05-28 杭州电子科技大学 Digital NOT gate implementation method based on ternary memristor

Similar Documents

Publication Publication Date Title
CN110827898B (en) Voltage-resistance type reversible logic circuit based on memristor and operation method thereof
CN109994139B (en) Complete non-volatile logic implementation method based on unipolar memristor and application thereof
CN104124960B (en) A kind of non-volatile boolean calculation circuit and its operating method
WO2020173040A1 (en) Reversible logic circuit and operation method thereof
CN110362291B (en) Method for performing nonvolatile complex operation by using memristor
CN111061454B (en) Logic implementation method based on bipolar memristor
CN108182959B (en) Method for realizing logic calculation based on crossing array structure of resistive device
CN110569962B (en) Convolution calculation accelerator based on 1T1R memory array and operation method thereof
CN109388853B (en) Single-pole and double-pole mixed efficient memristor logic circuit and control method thereof
CN105356876A (en) Memristor-based logic gate circuit
Yuan et al. Efficient 16 Boolean logic and arithmetic based on bipolar oxide memristors
CN104318955B (en) Data reading circuit and data reading method of phase change memory based on diode gating
Ma et al. Efficient Parallel Multi‐Bit Logic‐in‐Memory Based on a Ultrafast Ferroelectric Tunnel Junction Memristor
CN117612587A (en) Memristor-based nonvolatile majority gate logic circuit and operation method thereof
CN113362872B (en) Memristor-based complete nonvolatile Boolean logic circuit and operation method
Luo et al. Nonvolatile Boolean logic in the one-transistor-one-memristor crossbar array for reconfigurable logic computing
CN110768660A (en) Memristor-based reversible logic circuit and operation method
US11189345B2 (en) Method for implementing logic calculation based on a crossbar array structure of resistive switching device
CN116107963A (en) Memristor-based in-memory logic circuit, in-memory logic computing system and application
CN113658625A (en) 1T1R array-based reconfigurable state logic operation circuit and method
CN113539327A (en) Device for realizing rapid logic calculation of phase change memory unit and data retrieval method
CN110572149B (en) Toffoli gate circuit and operation method thereof
CN117978154B (en) Memristor-based logic circuit and full adder
Song et al. Efficient Implementation of Complete Reconfigurable Boolean Logic Primitives Based on Memristors
Ping et al. A high reliable design of memristor-based multilevel memory

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20200207

WD01 Invention patent application deemed withdrawn after publication