CN112865786A - Digital NOT gate implementation method based on ternary memristor - Google Patents
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Abstract
The invention discloses a digital NOT gate implementation method based on a three-value memristor. The invention designs a novel ternary digital logic NOT gate circuit model based on a ternary memristor, which comprises an NTI circuit model, a PTI circuit model and four different STI circuit models. The circuit model can use one structure to realize different types of three-value NOT gates, and has clear and simple structure and easy realization. The NOT gate circuit model has important significance in the fields of multi-value digital logic circuits and the like.
Description
Technical Field
The invention belongs to the technical field of circuit design, and relates to a digital NOT gate implementation method based on a three-value memristor.
Background
Memristors are a new type of circuit element that is non-volatile. By the fourth circuit element, the memristor describes the relationship between the magnetic flux and the electric charge, filling the gap of the relationship between the four basic variables of the circuit. Due to the nanoscale nature of memristors, memristor-based digital logic circuits have less area and power consumption than traditional digital logic circuits using CMOS. The memristor can realize the processing and the storage of information in the same physical device, the unique characteristic is widely applied to a binary digital logic circuit, and a novel computer different from a traditional von Neumann architecture is expected to be realized.
The uk inventor, Thomas Fowler, first proposed an alternative method of computation based on a ternary logic system in 1840. Compared with the traditional binary logic, the ternary logic has the advantages of higher information carrying capacity of a single signal line, stronger circuit series-parallel operation capability, lower circuit complexity and the like. Since the establishment of the ternary logic, many advances have been made in related research, but until now, there is still no corresponding practical ternary device, which makes the ternary logic difficult to be effectively popularized in practical application. While memristors can handle more than two states without additional hardware, the advent of memristors and the introduction of multivalued memristors is a good solution to implement ternary logic.
Although the actual device of the memristor is physically realized in 2008, the actual memristor device is difficult to obtain for application research by researchers due to the severe technical conditions and high cost. Meanwhile, in the existing research, a digital logic circuit based on a three-value memristor is very limited and faces the problem of integration of storage and calculation. Therefore, the method has important significance in establishing a mathematical model, a simulation model, an effective circuit and other models of the three-value memristor and introducing the models into the digital logic circuit design.
Disclosure of Invention
Aiming at the defects existing in the existing research, the invention provides a digital NOT gate implementation method based on a three-value memristor.
The three-value NOT gate circuit is composed of two memristors, an auxiliary resistor and a direct-current power supply.
A Standard Forward-reverse three-valued NOT gate (FB-STI) circuit consists of two memristors RinAnd RoutA 25 omega auxiliary resistor R and a direct current power supply V. Wherein R isinMemristor is connected with auxiliary resistor R in parallelinBE terminal and RoutIs connected to the BE terminal of RinIs connected with the positive pole of a direct current power supply V, RoutThe TE end of the direct current power supply V is connected with the negative electrode of the direct current power supply V, and the negative electrode of the direct current power supply V is grounded.
A Standard Forward-Forward Standard Ternary Inverter (FF-STI) circuit is formed by two memoriesResistor RinAnd RoutA 25 omega auxiliary resistor R and a direct current power supply V. Wherein R isinMemristor is connected with auxiliary resistor R in parallelinBE terminal and RoutIs connected to the TE terminal of RinIs connected with the positive pole of a direct current power supply V, RoutThe BE terminal of the signal processing circuit is connected with the negative electrode of the direct current power supply V, and the negative electrode of the direct current power supply V is grounded.
A BF-STI (Back-Forward Standard Ternary Inverter) circuit consists of two memristors RinAnd RoutA 25 omega auxiliary resistor R and a direct current power supply V. Wherein R isinMemristor is connected with auxiliary resistor R in parallelinTE terminal and R ofoutIs connected to the TE terminal of RinIs connected to the positive pole of a DC power supply V, RoutThe BE terminal of the signal processing circuit is connected with the negative electrode of the direct current power supply V, and the negative electrode of the direct current power supply V is grounded.
A BB-STI (reverse-reverse Standard Ternary Inverter) circuit consists of two memristors RinAnd RoutA 25 omega auxiliary resistor R and a direct current power supply V. Wherein R isinMemristor is connected with auxiliary resistor R in parallelinTE terminal and R ofoutIs connected to the BE terminal of RinIs connected to the positive pole of a DC power supply V, RoutThe TE end of the direct current power supply V is connected with the negative electrode of the direct current power supply V, and the negative electrode of the direct current power supply V is grounded.
A Negative three-valued Not (NTI) circuit consists of two memristors RinAnd RoutA 100 omega auxiliary resistor and a DC power supply V. Wherein R isinMemristor is connected with auxiliary resistor R in parallelinBE terminal and RoutIs connected to the BE terminal of RinIs connected with the positive pole of a direct current power supply V, RoutThe TE end of the direct current power supply V is connected with the negative electrode of the direct current power supply V, and the negative electrode of the direct current power supply V is grounded.
A Positive three-valued not gate (PTI) circuit is composed of two memristors RinAnd RoutA 100 omega auxiliary resistor and a DC power supply V. Wherein R isinMemristors connected in parallel with auxiliary resistors, RinBE (a)Terminal and RoutIs connected to the BE terminal of RinIs connected with the positive pole of a direct current power supply V, RoutThe TE end of the direct current power supply V is connected with the negative electrode of the direct current power supply V, and the negative electrode of the direct current power supply V is grounded.
The invention has the beneficial effects that: the invention designs a novel ternary digital logic NOT gate circuit model based on a ternary memristor, which comprises an NTI circuit model, a PTI circuit model and four different STI circuit models. The circuit model can use one structure to realize different types of three-value NOT gates, and has clear and simple structure and easy realization. The NOT gate circuit model has important significance in the fields of multi-value digital logic circuits and the like.
Drawings
FIG. 1 is a forward-forward ternary NOT circuit of the present invention;
FIG. 2 is a reverse-forward ternary NOT circuit of the present invention;
FIG. 3 is a forward-reverse ternary NOT circuit of the present invention;
FIG. 4 is an inverted-inverted ternary NOT circuit of the present invention;
FIG. 5 is a positive-negative tri-value NOT gate circuit of the present invention;
fig. 6 is a forward-reverse positive three-valued nor circuit of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
The three-value memristor model adopted by the design is a pressure-controlled threshold type three-value memristor, and the mathematical model of the three-value memristor is described by the following formula:
in the formula, a, b, c, d and e are adjustable parameters in the model, x is a system internal state variable, v (t) represents the voltage at two ends of the memristor, i (t) represents the current flowing through the memristor, v (t) represents the current flowing through the memristorth1And vth2Representing two different threshold voltages, RL、RM、RHCorresponding to three different resistance states of the model from low to high, respectively.
Under the action of an applied voltage, the memristor model can show a threshold characteristic. When v is>vth2While the memristor is set to RL. When v isth1<v<vth2If the state of the memristor model at this time is RHWill rapidly drop to RMOtherwise, the original state is kept unchanged. When-vth1<v<vth1In time, the model will remain in its original state. When-vth2<v<-vth1If the resistance of the memristor is smaller than R at the momentMWill increase to RMOtherwise, no change occurs. When v is<-vth2When the model is set to RH。
The three NOT gate circuit models based on the three-value memristor are respectively a Standard three-value NOT gate (STI), NTI and PTI, and four different STI circuit designs are provided, namely FF-STI, BF-STI, FB-STI and BB-STI. All the three-value NOT gate circuits are composed of two three-value memristors, memristances of the memristors are used as logic state variables, asymmetric three-value logics are used, and NOT gate logic operation is achieved through '0', '1' and '2' respectively. RLRepresents a logical "2", RMLogic "1", RHRepresenting a logical "0". The various parameters of the LTSpice three-value memristor model used are set as follows, vth1And vth2Set to 0.9V and 1.1V, R respectivelyL、RMAnd RHSet to 100 Ω, 1k Ω and 10k Ω, respectively.
All three-valued not gates are driven by one excitation voltage source V. Each time, the operation of the logic gate can be divided into two stages, one is an initial stage, and the initial stage corresponds to 0-10 ms.In this phase, V outputs a smaller measurement voltage VMSThe method is used for measuring the initial state of each memristor and measuring and calculating the resistance value of the memristor by reading the voltage and the passing current at two ends of the memristor. The value of this measurement voltage should be small so that the divided voltage across each memristor does not exceed the set threshold voltage, and therefore, does not change the state of the respective memristor. The second stage is an operation stage corresponding to 10-20 ms, and a larger operation voltage V is output during the operation stageOPFor performing logical operations. In all gate circuits of this design, output memristor RoutAre all RLMeasuring the voltage VMSAre all 0.5V, but for the operating voltage VOPIn other words, different values need to be selected in different gates. The truth table for STI, NTI, PTI is shown in Table 1.
TABLE 1 truth table of STI, NTI, PTI
All the STI circuits proposed by the present design need to set the resistance of the auxiliary resistor R to 25 Ω.
For FB-STI, see FIG. 3, the operating voltage V output by the excitation voltage source VOPSet to 1.123V.
When the input is logic '0', the parallel resistance of the input memristor and the auxiliary resistor R is 24.9 omega. Output memristor RoutThe partial pressure at both ends is-0.8991V, which is greater than the threshold voltage of-0.9V, RoutDoes not change. The logic gate outputs a logic "2".
When the input is logic 1, the total parallel resistance of the input memristor and the resistor R is 24.3 omega. Output memristor RoutThe voltage at both ends is-0.9035V, and exceeds the threshold voltage RoutIs set to RM。RoutAfter the resistance value is increased, the divided voltage at the two ends is-1.0964V and does not exceed the threshold voltage of-1.1V, the state can not be changed continuously, and the output of the logic gate is logic '1'.
When the input is logic '2', memory is inputThe total resistance of the resistor and the resistor R in parallel is 20 Ω. Output memristor RoutThe divided voltage is-0.9358V, and exceeds the threshold voltage of-0.9V, RoutIs set to RM. Then, RoutThe voltage at the two ends is reduced to-1.101V, and the output memristor is further set to RH. The logic gate outputs a logic "0".
For BB-STI, see FIG. 4, the excitation voltage source V outputs an operating voltage VOPSet to 1.123V.
When the input is logic '0', the parallel resistance of the input memristor and the auxiliary resistor R is 24.9 omega. Output memristor RoutThe partial pressure at both ends is-0.8991V, which is greater than the threshold voltage of-0.9V, RoutDoes not change. The logic gate outputs a logic "2".
When the input is logic 1, the total parallel resistance of the input memristor and the resistor R is 24.3 omega. Output memristor RoutThe voltage at both ends is-0.9035V, and exceeds the threshold voltage RoutIs set to RM。RoutAfter the resistance value is increased, the divided voltage at the two ends is-1.0964V and does not exceed the threshold voltage of-1.1V, the state can not be changed continuously, and the output of the logic gate is logic '1'.
When the input is logic '2', the total resistance of the input memristor and the resistor R in parallel is 20 omega. Output memristor RoutThe divided voltage is-0.9358V, and exceeds the threshold voltage of-0.9V, RoutIs set to RM. Then, RoutThe voltage at the two ends is reduced to-1.1010V, and the output memristor is further set to RH. The logic gate outputs a logic "0".
For FF-STI, see FIG. 1, the operating voltage V output by the excitation voltage source VOPSet to-1.123V.
When the input is logic '0', the parallel resistance of the input memristor and the auxiliary resistor R is 24.9 omega. Output memristor RoutThe partial pressure at both ends is-0.8991V, which is greater than the threshold voltage of-0.9V, RoutDoes not change. The logic gate outputs a logic "2".
When the input is logic 1, the total parallel resistance of the input memristor and the resistor R is 24.3 omega. Output memristor RoutTwo endsis-0.9035V, exceeds the threshold voltage, RoutIs set to RM。RoutAfter the resistance value is increased, the divided voltage at the two ends is-1.0964V and does not exceed the threshold voltage of-1.1V, the state can not be changed continuously, and the output of the logic gate is logic '1'.
When the input is logic '2', the total resistance of the input memristor and the resistor R in parallel is 20 omega. Output memristor RoutThe divided voltage is-0.9358V, and exceeds the threshold voltage of-0.9V, RoutIs set to RM. Then, RoutThe voltage at the two ends is reduced to-1.1010V, and the output memristor is further set to RH. The logic gate outputs a logic "0".
For BF-STI, see FIG. 2, the operating voltage V output by the excitation voltage source VOPSet to-1.123V.
When the input is logic '0', the parallel resistance of the input memristor and the auxiliary resistor R is 24.9 omega. Output memristor RoutThe partial pressure at both ends is-0.8991V, which is greater than the threshold voltage of-0.9V, RoutDoes not change. The logic gate outputs a logic "2".
When the input is logic 1, the total parallel resistance of the input memristor and the resistor R is 24.3 omega. Output memristor RoutThe voltage at both ends is-0.9035V, and exceeds the threshold voltage RoutIs set to RM。RoutAfter the resistance value is increased, the divided voltage at the two ends is-1.0964V and does not exceed the threshold voltage of-1.1V, the state can not be changed continuously, and the output of the logic gate is logic '1'.
When the input is logic '2', the total resistance of the input memristor and the resistor R in parallel is 20 omega. Output memristor RoutThe divided voltage is-0.9358V, and exceeds the threshold voltage of-0.9V, RoutIs set to RM. Then, RoutThe voltage at the two ends is reduced to-1.1010V, and the output memristor is further set to RH. The logic gate outputs a logic "0".
For NTI, see FIG. 5, the auxiliary resistor R needs to be adjusted to 100 Ω, and the driving voltage source V outputs the operating voltage VOPSet to 1.75V.
When the input is logic '0', the memristor and the auxiliary resistor are inputThe total parallel resistance of R is 99 Ω. Output memristor RoutThe partial pressure at both ends is-0.879V, which is greater than the threshold voltage of-0.9V, RoutDoes not change. The logic gate outputs a logic "2".
When the input is logic 1, the total parallel resistance of the input memristor and the resistor R is 90.9 omega. Output memristor RoutThe voltage across the terminals is-0.917V, exceeding the threshold voltage, RoutIs set to RM。RoutAfter the resistance value is increased, the divided voltage at the two ends is-1.604V and less than-1.1V of threshold voltage, and the output memristor is further set to be RH. The logic gate outputs a logic "0".
When the input is logic '2', the total parallel resistance of the input memristor and the resistor R is 50 omega. Output memristor RoutThe divided voltage is-1.167V, exceeds the threshold voltage of-0.9V, RoutIs set to RM. Then, RoutThe voltage at the two ends is reduced to-1.667V, and an output memristor is further set to RH. The logic gate outputs a logic "0".
For PTI, see FIG. 6, it is necessary to adjust the auxiliary resistor R to 100 Ω and to excite the operating voltage V output by the voltage source VOPSet to 1.5V.
When the input is logic '0', the total parallel resistance of the input memristor and the auxiliary resistor R is 99 omega. Output memristor RoutThe voltage division at the two ends is-0.754V, which is larger than the threshold voltage of-0.9V, RoutDoes not change. The logic gate outputs a logic "2".
When the input is logic 1, the total parallel resistance of the input memristor and the resistor R is 90.9 omega. Output memristor RoutThe voltage at both ends is-0.786V, which is greater than the threshold voltage of-0.9V, RoutDoes not change. The logic gate outputs a logic "2".
When the input is logic '2', the total parallel resistance of the input memristor and the resistor R is 50 omega. Output memristor RoutThe voltage is divided into-1V and exceeds the threshold voltage of-0.9V, RoutIs set to RM. Then, RoutThe voltage at the two ends is reduced to-1.429V, and the output memristor is further set to RH. Logic gate outputA logic "0".
It should be appreciated by those skilled in the art that the above embodiments are only used for verifying the present invention, and are not to be construed as limiting the present invention, and that the changes and modifications of the above embodiments are within the scope of the present invention.
Claims (7)
1. The digital NOT gate implementation method based on the three-value memristor is characterized by comprising the following steps:
the adopted three-value memristor is a voltage-controlled threshold type three-value memristor, and a mathematical model of the three-value memristor is described by the following formula:
in the formula, a, b, c, d and e are adjustable parameters in the model, x is a system internal state variable, v (t) represents the voltage at two ends of the memristor, i (t) represents the current flowing through the memristor, v (t) represents the current flowing through the memristorth1And vth2Representing two different threshold voltages, RL、RM、RHThree different resistance states respectively corresponding to the model from low to high represent three-valued logic '2', '1' and '0';
the digital NOT gate is formed by adopting two ternary memristors, and comprises a standard ternary NOT gate STI, a negative ternary NOT gate NTI and a positive ternary NOT gate PTI, wherein the memristor value of the ternary memristor is used as a logic state variable, and asymmetric ternary logics are used, namely 0, 1 and 2 to realize NOT gate logic operation;
let RinInput memristor, RoutIs an outputMemristor, V is a direct current power supply; memristor RinIs the input of a digital not-gate, RoutIs RL(ii) a The truth table of the digital not gate logic is shown in the following table:
the operation of the digital not gate is divided into two stages:
the first phase is the initial phase in which the DC source V outputs a small measurement voltage VMSThe method is used for measuring the initial state of each memristor and measuring and calculating the resistance value of the memristor by reading the voltage at two ends of the memristor and the current flowing through the memristor; the measurement voltage VMSSo that the divided voltage across each memristor does not exceed the set threshold voltage, and thus the memristor does not change its state;
the second stage is an operation stage, in which the DC power supply V outputs an operation voltage VOPFor performing logical operations.
2. The digital NOT gate implementation method based on the three-valued memristor according to claim 1, wherein: let a be 10, b be 10000, c be 0.2, and the threshold voltage v beth1And vth2Set to 0.9V and 1.1V, respectively; rH、RM、RL10k omega, 1k omega and 100 omega respectively, and a memristor RinIs connected with a 25 omega auxiliary resistor R in parallel and is memristor RinBE terminal and output memristor RoutBE end connected to input memristor RinThe TE end of the voltage-stabilizing circuit is connected with the anode of a direct-current power supply V, and an output memristor RoutThe TE end of the direct current power supply V is connected with the negative electrode of the direct current power supply V, and the negative electrode of the direct current power supply V is grounded;
operating voltage V at digital not-gateOPAt 1.123V:
when the input is logic '0', the memristor R is inputinThe total resistance of the resistor and the auxiliary resistor R in parallel connection is 24.9 omega; output memristor RoutThe partial voltage at both ends is-0.8991V which is greater than the threshold voltage of-09V, output memristor RoutThe state of (2) is not changed; the logic gate outputs a logic "2";
when the input is logic '1', the memristor R is inputinThe total resistance of the auxiliary resistor R and the parallel connection is 24.3 omega; output memristor RoutThe voltage at the two ends is-0.9035V, and exceeds the threshold voltage, and the output memristor RoutIs set to RM(ii) a Output memristor RoutAfter the resistance value is increased, the divided voltage at the two ends is-1.0964V and is not more than the threshold voltage of-1.1V, the state can not be changed continuously, and the output of the logic gate is logic '1';
when the input is logic '2', the memristor R is inputinThe total resistance of the auxiliary resistor R and the auxiliary resistor R in parallel connection is 20 omega; output memristor RoutThe divided voltage is-0.9358V and exceeds the threshold voltage of-0.9V, and an output memristor RoutIs set to RM(ii) a Subsequently, the memristor R is outputoutThe voltage at two ends is reduced to-1.101V, and an output memristor RinIs further set to RH(ii) a The logic gate outputs a logic "0".
3. The digital NOT gate implementation method based on the three-valued memristor according to claim 1, wherein: let a be 10, b be 10000, c be 0.2, and the threshold voltage v beth1And vth2Set to 0.9V and 1.1V, respectively; rH、RM、RL10k omega, 1k omega and 100 omega respectively, and input memristor RinIs connected with a 25 omega auxiliary resistor R in parallel and inputs the memristor RinBE terminal and output memristor RoutTE end connected to input memristor RinThe TE end of the voltage-stabilizing circuit is connected with the anode of a direct-current power supply V, and an output memristor RoutThe BE terminal of the signal processing circuit is connected with the negative electrode of the direct-current power supply V, and the negative electrode of the direct-current power supply V is grounded;
operating voltage V at digital not-gateOPat-1.123V:
when the input is logic '0', the memristor R is inputinThe total resistance of the resistor and the auxiliary resistor R in parallel connection is 24.9 omega; output memristor RoutThe divided voltage at the two ends is-0.8991V which is larger than the threshold voltage of-0.9V, and an output memristor RoutIn a state ofChanges will occur; the logic gate outputs a logic "2";
when the input is logic '1', the memristor R is inputinThe total resistance of the auxiliary resistor R and the parallel connection is 24.3 omega; output memristor RoutThe voltage at the two ends is-0.9035V, and exceeds the threshold voltage, and the output memristor RoutIs set to RM(ii) a Output memristor RoutAfter the resistance value is increased, the divided voltage at the two ends is-1.0964V and is not more than the threshold voltage of-1.1V, the state can not be changed continuously, and the output of the logic gate is logic '1';
when the input is logic '2', the memristor R is inputinThe total resistance of the auxiliary resistor R and the auxiliary resistor R in parallel connection is 20 omega; output memristor RoutThe divided voltage is-0.9358V and exceeds the threshold voltage of-0.9V, and an output memristor RoutIs set to RM(ii) a Subsequently, the memristor R is outputoutThe voltage at the two ends is reduced to-1.1010V, and the output memristor is further set to RH(ii) a The logic gate outputs a logic "0".
4. The digital NOT gate implementation method based on the three-valued memristor according to claim 1, wherein: let a be 10, b be 10000, c be 0.2, and the threshold voltage v beth1And vth2Set to 0.9V and 1.1V, respectively; rH、RM、RL10k omega, 1k omega and 100 omega respectively, and input memristor RinIs connected with a 25 omega auxiliary resistor R in parallel and inputs the memristor RinTE end and output memristor RoutTE end connected to input memristor RinThe BE end of the input signal is connected with the positive electrode of the direct-current power supply V, and the output memristor RoutThe BE terminal of the signal processing circuit is connected with the negative electrode of the direct-current power supply V, and the negative electrode of the direct-current power supply V is grounded; BF (BF) generator
Operating voltage V at digital not-gateOPis-1.123V:
when the input is logic '0', the memristor R is inputinThe total resistance of the resistor and the auxiliary resistor R in parallel connection is 24.9 omega; output memristor RoutThe divided voltage at the two ends is-0.8991V which is larger than the threshold voltage of-0.9V, and an output memristor RoutThe state of (2) is not changed; the logic gate outputs a logic "2";
when the input is logic '1', the memristor R is inputinThe total resistance of the auxiliary resistor R and the parallel connection is 24.3 omega; output memristor RoutThe voltage at the two ends is-0.9035V, and exceeds the threshold voltage, and the output memristor RoutIs set to RM(ii) a Output memristor RoutAfter the resistance value is increased, the divided voltage at the two ends is-1.0964V and is not more than the threshold voltage of-1.1V, the state can not be changed continuously, and the output of the logic gate is logic '1';
when the input is logic '2', the memristor R is inputinThe total resistance of the auxiliary resistor R and the auxiliary resistor R in parallel connection is 20 omega; output memristor RoutThe divided voltage is-0.9358V and exceeds the threshold voltage of-0.9V, and an output memristor RoutIs set to RM(ii) a Subsequently, the memristor R is outputoutThe voltage at the two ends is reduced to-1.1010V, and the output memristor is further set to RH(ii) a The logic gate outputs a logic "0".
5. The digital NOT gate implementation method based on the three-valued memristor according to claim 1, wherein: let a be 10, b be 10000, c be 0.2, and the threshold voltage v beth1And vth2Set to 0.9V and 1.1V, respectively; rH、RM、RL10k omega, 1k omega and 100 omega respectively, and input memristor RinIs connected with a 25 omega auxiliary resistor R in parallel and inputs the memristor RinTE end and output memristor RoutBE end connected to input memristor RinThe BE end of the input signal is connected with the positive electrode of the direct-current power supply V, and the output memristor RoutThe TE end of the direct current power supply V is connected with the negative electrode of the direct current power supply V, and the negative electrode of the direct current power supply V is grounded;
operating voltage V at digital not-gateOPAt 1.123V:
when the input is logic '0', the memristor R is inputinThe total resistance of the resistor and the auxiliary resistor R in parallel connection is 24.9 omega; output memristor RoutThe partial pressure at both ends is-0.8991V, which is greater than the threshold voltage of-0.9V, RoutThe state of (2) is not changed; the logic gate outputs a logic "2";
when the input is logic '1', the memristor R is inputinThe total resistance of the auxiliary resistor R and the parallel connection is 24.3 omega; output memristor RoutThe voltage at the two ends is-0.9035V, and exceeds the threshold voltage, and the output memristor RoutIs set to RM(ii) a Output memristor RoutAfter the resistance value is increased, the divided voltage at the two ends is-1.0964V and is not more than the threshold voltage of-1.1V, the state can not be changed continuously, and the output of the logic gate is logic '1';
when the input is logic '2', the memristor R is inputinThe total resistance of the auxiliary resistor R and the auxiliary resistor R in parallel connection is 20 omega; output memristor RoutThe divided voltage is-0.9358V and exceeds the threshold voltage of-0.9V, and an output memristor RoutIs set to RM(ii) a Subsequently, the memristor R is outputoutThe voltage at the two ends is reduced to-1.1010V, and the output memristor is further set to RH(ii) a The logic gate outputs a logic "0".
6. The digital NOT gate implementation method based on the three-valued memristor according to claim 1, wherein: let a be 10, b be 10000, c be 0.2, and the threshold voltage v beth1And vth2Set to 0.9V and 1.1V, respectively; rH、RM、RL10k omega, 1k omega and 100 omega respectively, and input memristor RinIs connected with a 100 omega auxiliary resistor R in parallel and inputs the memristor RinBE terminal and output memristor RoutBE end connected to input memristor RinThe TE end of the voltage-stabilizing circuit is connected with the anode of a direct-current power supply V, and an output memristor RoutThe TE end of the direct current power supply V is connected with the negative electrode of the direct current power supply V, and the negative electrode of the direct current power supply V is grounded;
operating voltage V at digital not-gateOPAt 1.75V:
when the input is logic '0', the memristor R is inputinThe total resistance of the resistor and the auxiliary resistor R in parallel connection is 99 omega; output memristor RoutThe voltage division at the two ends is-0.879V which is larger than the threshold voltage of-0.9V, and an output memristor RoutThe state of (2) is not changed; the logic gate outputs a logic "2";
when the input is logic '1', the memristor R is inputinThe total resistance of the auxiliary resistor R and the parallel connection is 90.9 omega; output memristor RoutThe voltage at the two ends is-0.917V, and exceeds the threshold voltage, and the output memristor RoutIs set to RM(ii) a Output memristor RoutAfter the resistance value is increased, the divided voltage at the two ends is-1.604V and less than-1.1V of threshold voltage, and the output memristor RoutIs further set to RH(ii) a The logic gate outputs a logic "0";
when the input is logic '2', the memristor R is inputinThe total resistance of the auxiliary resistor R and the auxiliary resistor R in parallel connection is 50 omega; output memristor RoutThe divided voltage is-1.167V and exceeds the threshold voltage to-0.9V, and an output memristor RoutIs set to RM(ii) a Subsequently, the memristor R is outputoutThe voltage at two ends is reduced to-1.667V, and an output memristor RoutIs further set to RH(ii) a The logic gate outputs a logic "0".
7. The digital NOT gate implementation method based on the three-valued memristor according to claim 1, wherein:
let a be 10, b be 10000, c be 0.2, and the threshold voltage v beth1And vth2Set to 0.9V and 1.1V, respectively; rH、RM、RL10k omega, 1k omega and 100 omega respectively, and input memristor RinIs connected with a 100 omega auxiliary resistor in parallel and inputs a memristor RinBE terminal and output memristor RoutBE end connected to input memristor RinThe TE end of the voltage-stabilizing circuit is connected with the anode of a direct-current power supply V, and an output memristor RoutThe TE end of the direct current power supply V is connected with the negative electrode of the direct current power supply V, and the negative electrode of the direct current power supply V is grounded;
operating voltage V at digital not-gateOPAt 1.5V:
when the input is logic '0', the memristor R is inputinThe total resistance of the resistor and the auxiliary resistor R in parallel connection is 99 omega; output memristor RoutThe voltage division at the two ends is-0.754V which is larger than the threshold voltage of-0.9V, and an output memristor RoutThe state of (2) is not changed; the logic gate outputs a logic "2";
when the input is logic '1', the memristor R is inputinThe total resistance of the auxiliary resistor R and the parallel connection is 90.9 omega; output memoryResistor RoutThe voltage at the two ends is-0.786V and is greater than the threshold voltage of-0.9V, and an output memristor RoutThe state of (2) is not changed; the logic gate outputs a logic "2";
when the input is logic '2', the memristor R is inputinThe total resistance of the auxiliary resistor R and the auxiliary resistor R in parallel connection is 50 omega; output memristor RoutThe divided voltage is-1V and exceeds the threshold voltage to-0.9V, and the output memristor RoutIs set to RM(ii) a Subsequently, the memristor R is outputoutThe voltage at two ends is reduced to-1.429V, and an output memristor RoutIs further set to RH(ii) a The logic gate outputs a logic "0".
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