CN112953498B - CMOS (complementary Metal oxide semiconductor) mixed type SR (stress relief) memristor latch circuit with asynchronous setting and resetting - Google Patents

CMOS (complementary Metal oxide semiconductor) mixed type SR (stress relief) memristor latch circuit with asynchronous setting and resetting Download PDF

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CN112953498B
CN112953498B CN202110390108.6A CN202110390108A CN112953498B CN 112953498 B CN112953498 B CN 112953498B CN 202110390108 A CN202110390108 A CN 202110390108A CN 112953498 B CN112953498 B CN 112953498B
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memristor
mos transistor
asynchronous
inverter
latch
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CN112953498A (en
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林弥
陈俊杰
王旭亮
罗文瑶
韩琪
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Hangzhou Dianzi University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors

Abstract

The invention discloses a CMOS mixed type SR memristor latch circuit with asynchronous setting and resetting, which comprises two modules: the SR memristor latch module comprises an SR memristor latch module and a memristor asynchronous setting and resetting function module. The SR memristor module comprises a first MOS transistor T1A second MOS transistor T2And a third MOS transistor T3And a fourth MOS transistor T4A fifth MOS transistor T5Sixth MOS transistor T6First memristor M1A first inverter N1And a second inverter N2And a first resistor R1(ii) a The memristor asynchronous setting and resetting functional module comprises a second memristor M2The third memristor M3The fourth memristor M4The fifth memristor M5And a third inverter N3(ii) a The SR memristor latch module is formed by mixing a memristor and a CMOS, and the circuit is nonvolatile. The memristor asynchronous setting and resetting functional module is formed by constructing an AND gate and an OR gate formed by memristors, and the number of components is reduced by utilizing a memristor logic gate circuit to maximally simplify the circuit structure.

Description

CMOS (complementary Metal oxide semiconductor) mixed type SR (stress relief) memristor latch circuit with asynchronous setting and resetting
Technical Field
The invention belongs to the technical field of circuit design, relates to a fully functional SR memristor latch circuit, and particularly relates to a CMOS hybrid SR memristor latch circuit with asynchronous set reset, which realizes level trigger, has the characteristic of nonvolatility and the function of asynchronous set reset.
Background
Memristors were first proposed in 1971 and have gained increasing attention as new devices. The memristor has the characteristics of nonvolatility, hysteresis and the like, can be applied to the fields of chaotic circuits, neural networks, digital logic circuits and the like by utilizing the characteristics, particularly to storage circuits, has great advantages in the application of the nonvolatile characteristics of the memristor to the storage circuits, and achieves a series of achievements, such as digital circuit basic triggers and the like. However, most of the existing memristors are designed in a trigger circuit and are improved based on a traditional storage circuit, although memristor devices are used, the number of the devices of the whole circuit is not reduced to a great extent, the characteristics that the memristors can enable the circuit structure to be simpler are not reflected, and the problems of overlarge power consumption caused by circuit complexity still exist.
Disclosure of Invention
Aiming at the problems in the prior art and research cost, the invention provides a CMOS hybrid SR memristor latch circuit with asynchronous set reset, which is composed of a CMOS and a memristor, wherein the memristor adopts a Biolek threshold type memristor model, and the maximum resistance R of the model can be designedoffMinimum resistance RonParameter beta (for controlling the resistance change rate of the memristor model), threshold voltage VtAnd directly adjusting key parameters.
The technical scheme adopted by the invention for solving the technical problem is as follows:
a CMOS mixed type SR memristor latch circuit with asynchronous setting and resetting comprises an SR memristor latch module and a memristor asynchronous setting and resetting function module. Wherein, SR memristor module comprises a first MOS transistor T1A second MOS transistor T2And a third MOS transistor T3And a fourth MOS transistor T4The fifth MOS transistor T5And a sixth MOS transistor T6First memristor M1A first inverter N1And a second N2And a first resistor R1(ii) a The memristor asynchronous setting and resetting functional module comprises a second memristor M2The third memristor M3The fourth memristor M4The fifth memristor M5And a third inverter N3Wherein T is1、T2、T3、T4And T6Is an NMOS transistor, T5Is a PMOS transistor, M1、M2、M3、M4、M5Both are Biolek threshold type memristor models. In the SR memristor module, a first MOS tube T1And a third MOS transistor T3The fifth MOS transistor T5And a sixth MOS transistor T6The grid of the SR memristor latch module is connected with a control end CP of the SR memristor latch module; first MOS transistor T1The drain electrode of the first MOS transistor T is connected with the input end S1The source electrode of the first MOS transistor is connected with a second MOS transistor T2A gate electrode of (1); second MOS transistor T2Is connected with a DC voltage V1Second MOS transistor T2The source electrode of the first MOS transistor is connected with a fourth MOS transistor T4Drain electrode of, first memristor M1Negative terminal of (1), first resistor R1One terminal of (1), a first inverter N1And a second inverter N2An output terminal of (a); third MOS transistor T3Is connected with the input end R and the third MOS tube T3The source electrode of the first MOS transistor is connected with a fourth MOS transistor T4A gate electrode of (1); fourth MOS transistor T4The source of the first transistor is connected to the ground terminal; fifth MOS transistor T5Is connected with a DC voltage V2Fifth MOS transistor T5Is connected with a first memristor M1Positive terminal and sixth MOS transistor T6A source electrode of (a); sixth MOS transistor T6Is connected to the first inverter N1And a second inverter N2An input terminal of (1); second inverter N2The output end of the latch is used as the output end Q of the SR memristor latch module1And connected to subsequent circuitry. In the memristor asynchronous setting and resetting functional module, a second memristor M2The negative end of the SR memristor latch module is connected with the output end Q of the SR memristor latch module1(second inverter N)2Output terminal of) the second memristor M2The positive end of the second memristor M is connected with the first memristor M3Positive terminal and fourth memristor M4A positive terminal of; third memristor M3The negative end of the asynchronous reset circuit is connected with an asynchronous SET end SET; fifth memristor M5Is connected with the third inverter N3The fifth memristor M5Is connected with a fourth memristor M4The negative terminal of the circuit is used as the output terminal Q of the whole circuit; third inverter N3Is connected with an asynchronous RESET terminal RESET.
Further, the voltage V1、V2Is a DC voltage, a DC voltage V1Is the same as the high level value of the SR latch input terminals S and R, a direct voltage V2Is slightly less than V1The value of (c).
Further, the first resistor R1The resistance value of (a) is required to satisfy: ron<<R1<<Roff(RonFor memory resistor M1Low resistance value of (2), RoffIs a memristor M1High resistance value of).
Further, the input terminals S and R of the SR latch and the asynchronous SET terminal SET and the asynchronous RESET terminal RESET cannot be high at the same time, and the above ports are all active high in the circuit.
Further, a second memristor M2And a third memristor M3Form a memristor gate, a fourth memristor M4And the fifth memristor M5Form a memristive AND gate, M1、M2、M3、M4And M5Is set at the minimum resistance value RonAnd maximum resistance value RoffThereafter, the resistance value is switched according to the voltage applied across the memristor.
Furthermore, a sixth MOS transistor T6The effect of (1) is that when the CP is logic 1, the voltage at two ends of the memristor is influenced, so that the resistance value of the memristor is changed, and when the CP is logic 0, the sixth MOS transistor T6Off, with no effect on memristor state.
Further, the invention has the advantages that: the circuit expands the application of the memristor in the digital logic circuit, adopts a circuit structure which is completely different from the traditional SR latch, has a simple structure and few required components, and adds additional logic functions (asynchronous setting and resetting) for the memristor-based digital logic circuit by using the memristor logic gate circuit on the basis of realizing basic functions compared with the digital logic circuit design based on the memristor of the same type, thereby further expanding the application scene of the circuit and guiding the road for the subsequent hardware design.
Compared with the prior art, the invention provides a CMOS hybrid type SR memristor latch with asynchronous set reset, which is designed by the idea that 1 level SR memristor latch module and one memristor asynchronous set reset module form an SR memristor latch circuit. The SR memristor latch module is formed by mixing a memristor and a CMOS, and the circuit has non-volatility, so that the circuit has a power-off storage function. The memristor asynchronous setting and resetting module is formed by constructing an AND gate, an OR gate and a phase inverter which are formed by memristors, is simple in circuit structure, and enables the SR memristor to have the asynchronous setting and resetting functions. According to the invention, a Biolek threshold memristor model is adopted, the threshold memristor and a CMOS are utilized to realize the mixed SR memristor latch with the asynchronous setting and resetting functions, and the circuit has non-volatility and has the asynchronous setting and resetting functions. Compared with the existing similar design, the asynchronous reset circuit has the advantages that the circuit structure is greatly simplified, the asynchronous reset circuit can be applied to other circuits, and an additional asynchronous set reset function is provided on the basis of realizing basic functions.
Drawings
Fig. 1 is a block diagram of the circuit configuration of the present invention.
FIG. 2 is a circuit diagram of a memristor employed by the present invention.
FIG. 3 is a current-voltage graph of a threshold-type memristor model employed by the present invention.
Fig. 4 is a specific circuit configuration diagram of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described below with reference to the accompanying drawings and examples of the present invention.
Fig. 1 is a circuit structure block diagram of the invention, the whole circuit comprises an SR memristor latch module and a memristor asynchronous setting and resetting module, wherein the SR memristor latch module is formed by mixing a memristor and a CMOS transistor, the circuit structure is simple, the number of devices is greatly reduced compared with the conventional SR latch, and the functions are complete. The memristor asynchronous setting and resetting module is formed by constructing an AND gate and an OR gate formed by memristors, and the asynchronous setting and resetting functions of the circuit are achieved. The whole circuit uses a small number of devices, has complete functions and is nonvolatile
FIG. 2 is a circuit diagram of the present invention using the threshold-type memristor model proposed by Biolek, assumingOne end of the black line segment is a negative end, and the other end of the black line segment is a positive end. FIG. 3 is a current-voltage waveform of a Biolek threshold memristor under an applied sinusoidal excitation signal. As can be seen in fig. 3, the memristor model has hysteresis characteristics and threshold characteristics, and has 1 threshold value under positive and negative voltages: + Vtand-Vt. When the applied forward excitation voltage of the memristor is larger than the forward threshold value + VtThe time memory resistor is converted into a high resistance value; when the reverse excitation voltage is greater than the negative threshold-VtThe memristor is converted into a low resistance value, and after the change, if the voltage is unchanged or the change range is smaller than the threshold voltage, the memristor keeps the previous resistance value until the difference of excitation voltages applied to two ends of the memristor is larger than the threshold value, and the memristor in the SR memristor module utilizes the characteristics to realize nonvolatile characteristics.
FIG. 4 is a specific circuit diagram of the CMOS hybrid SR memristor latch with asynchronous set-reset function according to the present invention, wherein V is1And V2Is a direct current working power supply. As shown in FIG. 4, the hybrid SR memristive latch includes a first memristor M1The second memristor M2The third memristor M3Fourth memristor M4The fifth memristor M5(ii) a 5 NMOS transistors: first MOS transistor T1A second MOS transistor T2And a third MOS transistor T3And a fourth MOS transistor T4And a sixth MOS transistor T6(ii) a 1 PMOS transistor: fifth MOS transistor T5；M1、M2、M3、M4、M5Are Biolek threshold type memristors. First MOS transistor T1And a third MOS transistor T3A fifth MOS transistor T5And a sixth MOS transistor T6The grid of the grid is connected with a control end CP, and the CP is the control end of the whole circuit; input terminal S and first MOS transistor T1Is connected with the drain electrode of the first MOS transistor T1The source electrode of the first MOS transistor is connected with a second MOS transistor T2A gate electrode of (1); second MOS transistor T2Is connected with a DC voltage V1Second MOS transistor T2The source electrode of the first MOS transistor is connected with a fourth MOS transistor T4Drain electrode of, first memristor M1Negative terminal of (1), first resistor R1One terminal of (1), a first inverter N1And a second inverterN2An output terminal of (a); input end R and third MOS tube T3Is connected with the drain electrode of the third MOS transistor T3The source electrode of the first MOS transistor is connected with a fourth MOS transistor T4A gate electrode of (1); fourth MOS transistor T4The source of the first transistor is connected to the ground terminal; fifth MOS transistor T5Is connected with a DC voltage V2Fifth MOS transistor T5Is connected with a first memristor M1Positive terminal and sixth MOS transistor T6A source electrode of (a); sixth MOS transistor T6Is connected to the first inverter N1And a second inverter N2An input terminal of (1); second memristor M2Is connected with a second inverter N2Output terminal of, the second memristor M2The positive end of the second memristor M is connected with the first memristor M3Positive terminal and fourth memristor M4A positive terminal of (a); third memristor M3The negative end of the first memristor M is connected with an asynchronous SET end SET and a fifth memristor M5Is connected with the third inverter N3The fifth memristor M5Negative terminal and fourth memristor M4Is connected with the negative terminal of the whole circuit, and the output is used as the output end Q of the whole circuit; asynchronous RESET end RESET and third phase inverter N of whole circuit3Are connected to each other. The working principle of the SR memristor latch is analyzed by combining a circuit structure:
1. when the asynchronous SET RESET terminals SET and RESET are both low level, i.e. logic 0, and CP is high level:
(1) if SR latch S is equal to 1 and R is equal to 0, CP is equal to 1, such that the first MOS transistor T is connected to the first MOS transistor T1A second MOS transistor T2And a third MOS transistor T3And a sixth MOS transistor T6Conducting, fourth MOS tube T4The fifth MOS transistor T5Cut-off, DC voltage V1Passing through a second MOS transistor T2To the first memristor M1And the first inverter N1Input terminal of, at this time, the first memristor M1Negative terminal is high level and has a magnitude of approximately V1The voltage passes through a first inverter N1Is converted into low level and passes through a sixth MOS transistor T6To the first memristor M1Due to the specific shape of the threshold-type memristor, the voltage difference between the negative terminal and the positive terminal is greater than the absolute value of the threshold, resulting inFirst memristor M1The resistance value is changed from the initial resistance value to the low resistance value RonAnd maintains the current resistance value, the first inverter N1The high level of the input end passes through the first phase inverter N1And a second inverter N2Input to output terminal Q1At this time, the output Q of the SR memristor latch module11. Second memristor M2And a third memristor M3Form a memristor gate, a fourth memristor M4And the fifth memristor M5The memristor AND gate is formed, and the asynchronous setting and resetting ends are all logic 0, so that the final output is realized
Figure BDA0003016436140000071
(2) When S is 0 and R is 1, CP is 1, such that the first MOS transistor T is connected to the first MOS transistor T1And a third MOS transistor T3And a fourth MOS transistor T4And a sixth MOS transistor T6Conducting, second MOS transistor T2The fifth MOS transistor T5And (6) cutting off. Because the second MOS transistor T2Cut-off and fourth MOS transistor T4On, first memristor M1Negative terminal and first inverter N1Is connected with the input end of the first MOS transistor through a fourth MOS transistor T4Ground, when the terminal is at low level, the level is at the first inverter N1Is converted into high level through a sixth MOS tube T6To the first memristor M1The resistance of the memristor is converted into a high resistance R at the momentoffAnd maintains the current resistance value, the first inverter N1The low level of the input end passes through the first phase inverter N1And a second inverter N2To Q1Terminal, output Q of SR memristor latch module at this time1When the value is 0, the asynchronous RESET end SET/RESET is logic 0, so the final output is
Figure BDA0003016436140000072
(3) When S is 0 and R is 0, CP is 1, such that the first MOS transistor T is connected to the first MOS transistor T1And a third MOS transistor T3And a sixth MOS transistor T6Conducting, second MOS transistor T2And a fourth MOS transistor T4The fifth MOS transistor T5Cut off due to the second MOS transistor T2And a fourth MOS transistor T4Is off and the first inverter N1And a second inverter N2Output terminal Q of1Connected together to form a latch loop, resulting in the first memristor M at this time1And the first inverter N1So that the voltage at the input terminal of (1) does not change, and the output terminal of (Q) does not change1Outputting the previous state, the first memristor M1The change of the corresponding resistance value also occurs according to the latch state (when S and R change to S-0, R-0 is not reached, and the time Q is not reached1The output is logic 1, and the output end Q is at the moment1Output logic 1 and first memristor M1The resistance value is changed into R from the same value as (1)on(ii) a If the output at the moment before the change is logic 0, the output is output at the moment. Output end Q1Output logic 0 and first memristor M1The resistance value is changed into R from the same value as (2)off) Since the asynchronous setting and resetting terminals are all logic 0, the final output is realized
Figure BDA0003016436140000073
The three conditions (1), (2) and (3) respectively realize the 1 setting, 0 setting and holding functions of the SR latch. The method is characterized in that: the memory and threshold characteristics of the memristor are used for storing the corresponding resistance value, the working steps of the circuit are simplified, the power consumption is reduced, the output is stable, and the resistance value stored in the memristor is kept unchanged when the system is powered off, so that the power-off keeping capability is realized.
2. When the asynchronous SET RESET terminals SET/RESET are all logic 0 and CP is low:
(1) time output Q if CP changes from 1 to 01Outputting a high level:
CP 0 results in a first MOS transistor T1A second MOS transistor T2And a third MOS transistor T3And a fourth MOS transistor T4And a sixth MOS transistor T6All are cut off, the fifth MOS transistor T5Is turned on due to V2The voltage is slightly less than V1Value of (c), then assume V2Is also slightly less than the threshold voltage of the memristor, at this time V2Voltage failure to make first memristor M1Resistance valueChange occurs due to the output terminal Q at the previous time1Outputting a high level to a first memristor M1The negative end is high level, the positive end is low level, the resistance value conversion condition of the memristor is met, and the resistance value is converted into RonAt this time, the voltage at the negative end of the memristor according to the voltage division principle is:
Figure BDA0003016436140000081
the voltage passes through a first inverter N1And a second inverter N2To the output terminal Q1High level is output, and the asynchronous SET RESET end SET/RESET is logic 0, so the final output is realized
Figure BDA0003016436140000082
(2) Time output Q if CP changes from 1 to 01Outputting a low level:
CP 0 results in a first MOS transistor T1A second MOS transistor T2And a third MOS transistor T3And a fourth MOS transistor T4And a sixth MOS transistor T6All are cut off, the fifth MOS transistor T5Is turned on due to V2The voltage is slightly less than V1Value of (c), then assume V2Is also slightly less than the threshold voltage of the memristor, at this time V2Voltage failure to make first memristor M1The resistance value changes, and the output end Q is at the previous moment1Outputting a low level to a first memristor M1The negative end is low level, the positive end is high level, the resistance value conversion condition of the memristor is met, and the resistance value is converted into RoffAt this time, the voltage at the negative end of the memristor according to the voltage division principle is:
Figure BDA0003016436140000083
the voltage passes through a first inverter N1And a second inverter N2To the output terminal Q1The output low level, and the asynchronous SET RESET end SET/RESET is logic 0, so the final output
Figure BDA0003016436140000084
The above 2 cases realize the function that the output terminal maintains the corresponding state according to the previous output state when the CP is logic 0, and the characteristic is that: the corresponding logic level is output by utilizing the resistance value stored by the prior memristor and the voltage division principle, the circuit structure is maximally simplified by utilizing the method, the working principle is not complex, and the simulation and the adjustment are easy
3. When the asynchronous SET RESET terminal SET is logic 1 and RESET is logic 0:
whenever SET is 1, no matter the output Q of the SR latch module1What value is, is given by the second memristor M2And a third memristor M3The output of the formed OR gate is logic 1, and the output of the whole circuit is at the moment
Figure BDA0003016436140000091
The above case realizes the function of asynchronous setting 1.
4. When the asynchronous SET RESET terminal SET is logic 0 and RESET is logic 1:
as long as RESET is 1, by the fourth memristor M4And the second memristor M5The formed AND gate is not influenced by the previous circuit, and the output is logic 0, namely the final output
Figure BDA0003016436140000092
The above case realizes the function of asynchronous setting of 0.
In the present invention, the voltage V1、V2Is a DC voltage, a DC voltage V1The maximum voltage of the SR latch input ends S and R is obtained; DC voltage V2Is slightly less than V1The value of (c).
In the present invention, the first resistor R1The resistance value of (a) is required to satisfy: ron<<R1<<Roff(RonFor memory resistor M1Low resistance value of (2), RoffFor memory resistor M1High resistance value of).
In the invention, the SET terminal S and the RESET terminal R, and the asynchronous SET terminal SET and the asynchronous RESET terminal RESET cannot be high level at the same time, and the above ports are all high level active in the circuit.
In the present invention, the second memristor M2And a third memristor M3Form a memristor gate, a fourth memristor M4And the fifth memristor M5Form a memristor AND gate and a memristor M1、M2、M3、M4And M5The initial resistance value needs to be set to the minimum resistance value R of the memristoronAnd maximum resistance value RoffIn the meantime. The resistance value is changed according to the voltage difference between the two ends of the memristor.
In the invention, a sixth MOS transistor T6The effect of the transistor is that when the CP is logic 1, the voltage at two ends of the memristor is influenced, so that the resistance value of the memristor is changed, and when the CP is logic 0, the sixth MOS transistor T6The transistor is off and has no effect on the memristor state.
In the invention, compared with other similar inventions, the advantages are as follows:
the structure is novel and simple, and the problems of less required components, large power consumption and the like are solved;
secondly, other digital logic circuits (edge triggers, counters and the like) can be further designed on the basis of the invention;
on the premise of realizing basic logic function, the additional logic function (asynchronous set reset) which is not available in the traditional SR latch can be realized;
the CMOS mixed type SR memristor latch with the asynchronous setting and resetting function provided by the invention has the advantages of stable circuit performance, non-volatility, asynchronous setting and resetting functions and good circuit simulation test effect. The actual sample can be made according to the specific circuit diagram of the present invention.
It should be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and any modification, replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (6)

1. A CMOS hybrid SR memristor latch circuit with asynchronous setting and resetting is characterized by comprising an SR memristor latch module and a memristor asynchronous setting and resetting function module; it is provided withIn, SR memristor module includes first MOS pipe T1A second MOS transistor T2And a third MOS transistor T3And a fourth MOS transistor T4The fifth MOS transistor T5And a sixth MOS transistor T6First memristor M1A first inverter N1And a second inverter N2And a first resistor R1(ii) a The memristor asynchronous setting and resetting functional module comprises a second memristor M2The third memristor M3The fourth memristor M4The fifth memristor M5And a third inverter N3Wherein T is1、T2、T3、T4And T6Is an NMOS transistor, T5Is a PMOS transistor, M1、M2、M3、M4、M5All are Biolek threshold type memristor models; in the SR memristor module, a first MOS tube T1And a third MOS transistor T3The fifth MOS transistor T5And a sixth MOS transistor T6The grid of the SR memristor latch module is connected with the control end CP of the SR memristor latch module; first MOS transistor T1The drain electrode of the first MOS transistor T is connected with the input end S1The source electrode of the first MOS transistor is connected with a second MOS transistor T2A gate electrode of (1); second MOS transistor T2Is connected with a DC voltage V1Second MOS transistor T2The source electrode of the first MOS transistor is connected with a fourth MOS transistor T4Drain electrode of, first memristor M1Negative terminal of (1), first resistor R1One terminal of (1), a first inverter N1And a second inverter N2An output terminal of (a); third MOS transistor T3Is connected with the input end R and the third MOS tube T3Source electrode of (2) is connected to T4A gate electrode of (1); fourth MOS transistor T4The source of the transistor is connected to the ground; fifth MOS transistor T5Is connected with a DC voltage V2Fifth MOS transistor T5Is connected with a first memristor M1Positive terminal and sixth MOS transistor T6A source electrode of (a); sixth MOS transistor T6Is connected to the first inverter N1And a second inverter N2An input terminal of (1); second inverter N2The output end of the latch is used as the output end Q of the SR memristor latch module1Connected to a subsequent circuit; memristor asynchronous setting and resetting functional moduleWithin the Block, the second memristor M2The negative end of the SR memristor latch module is connected with the output end Q of the SR memristor latch module1I.e. the second inverter N2Output terminal of, the second memristor M2The positive end of the second memristor M is connected with the first memristor M3Positive terminal and fourth memristor M4A positive terminal of; third memristor M3The negative end of the asynchronous reset circuit is connected with an asynchronous SET end SET; fifth memristor M5Is connected with the third inverter N3The output terminal of (1), the fifth memristor M5Is connected with a fourth memristor M4The negative terminal of the circuit is used as the output terminal Q of the whole circuit; third inverter N3Is connected with an asynchronous RESET terminal RESET.
2. The CMOS hybrid SR memristor latch circuit with asynchronous set-reset function according to claim 1, wherein a voltage V is1、V2Is a DC voltage, a DC voltage V1Is the same as the high level value of the SR latch input terminals S and R, a direct voltage V2Is slightly less than V1The value of (c).
3. The CMOS hybrid SR memristor latch circuit with asynchronous set-reset function according to claim 1, wherein the first resistor R is1The resistance value of (a) is required to satisfy: ron<<R1<<RoffWherein R isonFor memory resistor M1Low resistance value of (2), RoffFor memory resistor M1High resistance value of (1).
4. The CMOS hybrid SR memristor latch circuit with asynchronous SET-RESET function according to claim 1, wherein the input terminals S and R of the SR latch and the asynchronous SET terminal SET and the asynchronous RESET terminal RESET cannot be high simultaneously, and the above ports are all active high in the circuit.
5. The CMOS hybrid SR memristor latch circuit with asynchronous set-reset function according to claim 1, wherein the second memristor M is2And a third memristor M3Form a memristor gateFourth memristor M4And the fifth memristor M5Form a memristive AND gate, M1、M2、M3、M4And M5Is set at the minimum resistance value RonAnd maximum resistance value RoffIn the meantime.
6. The CMOS hybrid SR memristor latch circuit with asynchronous set-reset function according to claim 1, wherein a sixth MOS transistor T6The effect of (1) is that when the CP is logic 1, the voltage at two ends of the memristor is influenced, so that the resistance value of the memristor is changed, and when the CP is logic 0, the sixth MOS transistor T6Off, with no effect on memristor state.
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CN112332813A (en) * 2020-11-17 2021-02-05 杭州电子科技大学 CMOS mixed type edge memristor D trigger circuit with asynchronous setting and resetting

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