CN113067577A - Digital NOR gate implementation method based on ternary memristor cross array - Google Patents
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Abstract
The invention discloses a digital NOR gate implementation method based on a ternary memristor cross array. The invention adopts a three-value memristor cross array with a 3 multiplied by 2 structure, wherein two of the three-value memristor cross array are used as input memristors, and one is used as an output memristor. The logic state of the three-value NOR gate is represented by the resistance value of the memristor, and the three-value digital NOR gate circuit based on the three-value memristor cross array is clear and simple in structure and easy to achieve. The crossed array of the NOR gate has important significance for application research in multiple fields such as multi-value digital logic operation and storage integration.
Description
Technical Field
The invention belongs to the technical field of circuit design, and relates to a digital NOR gate implementation method based on a ternary memristor cross array.
Background
Since birth, modern computers bring great convenience to the development of human society. At present, most of computers used by people are von neumann architectures, in the architecture, calculation and storage are separated, that is, control signals and data transmission between a processor and a memory need to be transmitted through a bus, so that the power consumption for transmitting data between the processor and the memory is far larger than the power consumption of the actual calculation of the computer, that is, the development bottleneck of the von neumann architectures.
The appearance of the memristor provides a new idea for solving the problem. The concept of memristors was originally proposed by professor zeitchy begonia, chinese scientist, in 1971, but did not raise much attention from technologists due to the absence of actual physical devices. In 2008, the hewlett packard laboratory manufactured the first memristor element, and then the research interest of many technologists was aroused in the related field of memristors. A series of researches show that the memristor is high in switching speed, low in operation power consumption and compatible with a CMOS (complementary metal oxide semiconductor) process, and a digital logic circuit formed by the memristor has excellent characteristics. More importantly, the memristor is small in size, simple in structure and nonvolatile, and can realize a very compact array structure, which is the key to large-scale data storage. By combining the characteristics, the memristor cross array is adopted to design the corresponding circuit, the resistance change characteristic of the memristor can be considered to participate in logic operation, the operation result is stored by the resistance state of the memristor, and the logic operation is directly carried out on the storage state, so that the step of carrying out data transmission by using a bus is omitted, a large amount of circuit consumption is saved, and a new solution is provided for the development of a new architecture of a computer.
With the further development of modern information technology, the integration level of devices is continuously increased, problems such as interconnection circuits, excessive power consumption and the like are further highlighted, and the ternary logic has a good effect on improving the problems. The ternary logic carries a larger amount of information than the binary logic unit, and thus can improve the data density of the memory. The three-value memristor has three stable resistance states, and can easily realize three-value logic by using only a single device. Some progress has been made in the related research based on the binary memristor crossbar array, and the related research of the three-value memristor in the field is still few, so that it is important to design a new circuit implementation method.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a digital NOR gate implementation method based on a three-value memristor cross array.
The technical scheme adopted by the invention for solving the technical problem is as follows: a three-value NOR gate circuit is designed by a cross array constructed by using a threshold type three-value memristor.
The three-value memristor cross array with the 3 x 2 structure is adopted, namely 6 memristors are needed in total, each memristor is located at the cross point of a transverse line and a longitudinal line, the anodes of the memristors are connected with the longitudinal lines, and the cathodes of the memristors are connected with the transverse lines. Memristor M1,1、M2,1、M3,1Are all connected on the same longitudinal line which passes through a switch S1And a DC power supply V1Are connected. M1,2、M2,2、M3,2Are all connected on the same longitudinal line which passes through a switch S2And a DC power supply V2Are connected. M1,1、M1,2The negative pole of the switch is connected on the same transverse line which passes through the switch S3And a DC power supply V3Are connected. M2,1、M2,2The negative pole of the switch is connected on the same transverse line which passes through the switch S4And a DC power supply V4Are connected. M3,1、M3,2The negative pole of the switch is connected on the same transverse line which passes through the switch S5And a DC power supply V5Are connected. In addition, the 6 memristors are respectively connected with a fixed resistor with the same resistance in parallel through a switch. The three resistance states of the memristor represent "0", "1", "2" of the three-valued logic, respectively. Among 6 memristors, memristor M1,1And M2,1Is an input memristor, M3,2Is an output memristor.
The invention designs a novel ternary digital logic NOR gate circuit based on a ternary memristor cross array, which is clear and simple in structure and easy to realize. The crossed array of the NOR gate has important significance for application research in multiple fields such as multi-value digital logic operation and storage integration.
Drawings
FIG. 1 is a three-value NOR gate circuit of the present invention based on a three-value memristor crossbar array.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
The three-value memristor model adopted by the design is a pressure-controlled threshold type three-value memristor, and the mathematical model of the three-value memristor is described by the following formula:
in the formula, a, b, c, d and e are adjustable parameters in the model, x is a system internal state variable, v (t) represents the voltage at two ends of the memristor, i (t) represents the current flowing through the memristor, v (t) represents the current flowing through the memristorth1And vth2Representing two different threshold voltages, RL、RM、RHCorresponding to three different resistance states of the model from low to high, respectively.
Under the action of an applied voltage, the memristor model can show a threshold characteristic. When v is>vth2While the memristor is set to RL. When v isth1<v<vth2If the state of the memristor model at this time is RHWill rapidly drop to RMOtherwise, the original state is kept unchanged. When-vth1<v<vth1In time, the model will remain in its original state. When-vth2<v<-vth1If the resistance of the memristor is smaller than R at the momentMWill increase to RMOtherwise, no change occurs. When v is<-vth2When the model is set to RH。
The three-value NOR gate circuit designed by the invention is realized by adopting a 3 multiplied by 2 cross array formed by three-value memristors, wherein two of the three-value NOR gate circuits are used as input memristors, and one of the three-value NOR gate circuits is used as an output memristor. The logic state of a three-valued NOR gate is represented by the resistance value of a memristor, RH、RM、RLRespectively, represent "0", "1", "2" of the ternary logic. In this design, M1,1And M2,1Are all input memristors, M3,2Is an output memristor, and V is a direct current power supply. Memristor M1,1And M2,1Is the two inputs A and B, M of the logic gate3,2Is RLThe final state is the output of the logic gate
M3,1Is RH. The truth table for the three-valued nor gate logic is shown in the following table:
the working process of the three-value NOR gate designed by the invention can be divided into three steps, wherein the first stage is an initial stage, and the second stage and the third stage are operation stages.
First stage, switch S3、S4、S5And the other switches are closed and opened. Voltage source V3And V4Output VREADAnd the other voltage sources output 0V. This phase is used to read the input memristor M1,1And M2,1I.e. the input of the logic gate.
In the second stage, all switches are not changed, and the voltage source V3And V4Output VORAnd the other voltage sources output 0V. At this time M1,1、M2,1Equivalent to parallel connection and then M3,1Are connected in series. Via M1,1、M2,1And M3,1The OR gate circuit is formed to perform an OR operation of the logic variables A and B, wherein M1,1、M2,1Is a two input memristor, M3,1Is that the output memristor, or the result of the operation, is stored in M3,1In (1).
Third stage, S1、S2And S3,1Closed, the rest openThe switch is off. Voltage source V1Output VNOTAnd the other voltage sources output 0V. Via M3,1Fixed resistance and M3,2A Standard Ternary Inverter (STI) is formed to perform a NOT operation, where M is3,1Is an input memristor, M3,2Is an output memristor, the result of the NOT operation being stored in M3,2In (1).
Since the parameters of the two input memristors in the tri-valued nor logic gate circuit and the locations in the circuit are the same, partially repeated results are omitted in the following analysis.
Preferably, for the designed three-value nor circuit, the relevant parameters of the three-value memristor model are a-e-10, b-10000, c-d-0.2, and the threshold voltage vth1And vth2Set to 0.9V and 1.1V, respectively; rH、RM、RL10k omega, 1k omega and 100 omega respectively; the fixed resistance is 25 Ω; vREADIs 0.3V, VORIs 1.25V, VNOTIt was 1.123V.
In the operation phase, firstly, an OR logic operation is carried out, when the input is all logic 0, the parallel total resistance of the input memristor is 5k omega, and in this case, M is3,1The partial voltage at both ends is 0.833V, and does not exceed the threshold voltage by 0.9V, so M3,1Is kept unchanged, i.e., is logic "0"; then, the logical operation of "not" is performed, at this time M3,1Is logic 0, M3,1The parallel resistance value of the output memristor M and the fixed resistor is 24.9 omega3,2The divided voltage at both ends is-0.8991V, which is greater than the threshold voltage of-0.9V, so M3,2The state of (c) remains unchanged, i.e., the final logic gate output is a logic "2".
When the input is logic '0' and '1', the parallel total resistance of the input memristor is 909 omega in the OR operation stage, and M is at the moment3,1The partial pressure across was 1.146V. When the inputs are all '1', the input memristor parallel total resistance is 500 omega, so M3,1The partial pressure at both ends was 1.19V. In both cases, M3,1The divided voltages at both ends exceed the threshold voltage of 0.9V, so M3,1Will be set to RM. At M3,1After the resistance value of (1) is changed, the voltage is redistributed among the memristors, for the former, M3,1The new partial voltage at two ends is 0.655V, the latter is 0.833V, and the threshold voltage is not exceeded by 1.1V, so M3,1Does not change any further, i.e. the final state of the or operation is "1".
In the "not" operation phase, M3,1Is logic 1, the parallel resistance value of the logic 1 and the fixed resistor is 24.3 omega, and the output memristor M3,2The partial pressure at two ends is-0.9035V and exceeds the threshold voltage of-0.9V, M3,2Is set to RMAfter the resistance value changes, the voltage division of the two ends is-1.0964V and does not exceed the threshold voltage of-1.1V, so that the state cannot be changed continuously, and the output memristor finally outputs logic 1.
When the input is logic '0' and '2', the total parallel resistance of the input memristors in the OR operation stage is 99 omega, and M is at the moment3,1The partial pressure across was 1.238V. When the input is logic '1' and '2', the parallel total resistance of the input memristor is 90.9 omega, and M is in the process3,1The partial pressure at both ends was 1.239V. When the inputs are all logic '2', the parallel total resistance of the input memristor is 50 omega, and M is at the moment3,1The partial pressure across was 1.244V. In the above three cases, M3,1The divided voltages at both ends exceed the threshold voltage of 0.9V, so M3,1Will be set to RM. At M3,1After the resistance value of the memristor is changed, the voltage is redistributed among the memristors, and M is under the three conditions3,1The new partial pressure values at two ends are respectively 1.137V, 1.146V and 1.19V, and all exceed the threshold voltage of 1.1V, so M3,1Is finally switched to RLI.e., logic "2". In the non-operation phase, M3,1Is logic 2, the parallel resistance value of the logic 2 and the fixed resistor is 20 omega, and the output memristor M3,2The partial voltage at the two ends is-0.9358V and exceeds the threshold voltage of-0.9V, M3,2Is set to RMAfter the resistance value is changed, the voltage division at two ends is-1.101V, and exceeds the threshold voltage of-1.1V, so that the state can be further switched to RHThe output memristor finally outputs a logic "0".
It should be appreciated by those skilled in the art that the above embodiments are only used for verifying the present invention, and are not to be construed as limiting the present invention, and that the changes and modifications of the above embodiments are within the scope of the present invention.
Claims (2)
1. A digital NOR gate implementation method based on a ternary memristor cross array is characterized by comprising the following steps: the adopted three-value memristor is a voltage-controlled threshold type three-value memristor, and a mathematical model of the three-value memristor is described by the following formula:
in the formula, a, b, c, d and e are adjustable parameters in the model, x is a system internal state variable, v (t) represents the voltage at two ends of the memristor, i (t) represents the current flowing through the memristor, v (t) represents the current flowing through the memristorth1And vth2Representing two different threshold voltages, RL、RM、RHThree different resistance states respectively corresponding to the model from low to high represent three-valued logic '2', '1' and '0';
the digital NOR gate is formed by adopting six three-value memristors, wherein two of the three-value memristors are used as input memristors, and the other one is used as an output memristor, and the following connection mode is specifically adopted:
the three-value memristor cross array with a 3 x 2 structure is adopted, each memristor is located at the cross point of a transverse line and a longitudinal line, the anodes of the memristors are connected with the longitudinal lines, and the cathodes of the memristors are connected with the transverse lines; memristor M1,1、M2,1、M3,1The positive electrodes are all connected on the same longitudinal lineThe longitudinal line passing through a switch S1And a DC power supply V1Connecting; m1,2、M2,2、M3,2Are all connected on the same longitudinal line which passes through a switch S2And a DC power supply V2Connecting; m1,1、M1,2The negative pole of the switch is connected on the same transverse line which passes through the switch S3And a DC power supply V3Connecting; m2,1、M2,2The negative pole of the switch is connected on the same transverse line which passes through the switch S4And a DC power supply V4Connecting; m3,1、M3,2The negative pole of the switch is connected on the same transverse line which passes through the switch S5And a DC power supply V5Connecting; in addition, the six memristors are respectively connected in parallel with a fixed resistor with equal resistance value through a switch; the three resistance states of the memristor represent "0", "1", "2" of a three-valued logic, respectively; among the six memristors, memristor M1,1And M2,1Is an input memristor, M3,2Is an output memristor;
memristor M1,1And M2,1Is the two inputs A and B of a logic gate, the memristor M3,2Is RLThe final state is the output of the logic gate
Memristor M3,1Is RH(ii) a The truth table of the digital nor gate is shown in the following table:
the operation of the digital nor gate is divided into three phases:
first stage, switch S3、S4、S5The switch is closed, and the other switches are opened; voltage source V3And V4Output VREADThe other voltage sources output 0V; this phase is used to read the input memristor M1,1And M2,1I.e. the input of the logic gate;
in the second stage, all switches are not changed, and the voltage source V3And V4Output VORThe other voltage sources output 0V; memristor M at this moment1,1、M2,1Equivalent to being connected in parallel and then connected with the memristor M3,1Are connected in series; via memristor M1,1、M2,1And M3,1The OR gate circuit is formed to perform an OR operation of the logic variables A and B, wherein M1,1、M2,1Is a two input memristor, M3,1Is that the output memristor, or the result of the operation, is stored in M3,1Performing the following steps;
third stage, S1、S2And S3,1The switch is closed, and the other switches are opened; voltage source V1Output VNOTThe other voltage sources output 0V; via memristor M3,1Fixed resistance and memristor M3,2The standard ternary inverter is formed to perform a NOT operation, wherein M3,1Is an input memristor, M3,2Is an output memristor, the result of the NOT operation being stored in M3,2In (1).
2. The digital NOR gate implementation method based on a ternary memristor crossbar array of claim 1, wherein: let a be 10, b be 10000, c be 0.2, and the threshold voltage v beth1And vth2Set to 0.9V and 1.1V, respectively; rH、RM、RL10k omega, 1k omega and 100 omega respectively; the fixed resistance is 25 Ω; vREADIs 0.3V, VORIs 1.25V, VNOTIs 1.123V;
in the operation stage, firstly, the logical operation of OR is carried out:
when the inputs are all logic '0', the input memristor parallel total resistance is 5k omega, in this case, the memristor M3,1The partial voltage at the two ends is 0.833V, and the threshold voltage is not exceeded by 0.9V, so that the memristor M3,1Is kept unchanged, i.e., is logic "0"; then carrying out 'NOT' logic operation, at the moment, the memristor M3,1Is logic 0, memristor M3,1The parallel resistance value of the output memristor M and the fixed resistor is 24.9 omega3,2The divided voltage at both ends is-0.8991V, which is greater than the threshold voltage of-0.9V, so the memristor M3,2The state of (1) remains unchanged, i.e., the final logic gate output is logic "2";
when the input is logic '0' and '1', the parallel total resistance of the input memristor is 909 omega in the OR operation stage, and the memristor M is at the moment3,1The partial pressure at the two ends is 1.146V;
when the input is 1, the parallel total resistance of the input memristor is 500 omega, and the memristor M3,1The partial pressure at both ends is 1.19V;
in both cases, the memristor M3,1The divided voltage at both ends exceeds the threshold voltage of 0.9V, so the memristor M3,1Will be set to RM(ii) a On recall and hinder ware M3,1After the resistance value of (1) is changed, the voltage is redistributed among the memristors, for the former, the memristor M3,1The new partial voltage at two ends is 0.655V, the latter is 0.833V, and the threshold voltage is not exceeded by 1.1V, so that the memristor M3,1Does not change any further, i.e. the final state of the or operation is "1";
in the 'NOT' operation phase, the memristor M3,1Is logic 1, the parallel resistance value of the logic 1 and the fixed resistor is 24.3 omega, and the output memristor M3,2The divided voltage at the two ends is-0.9035V and exceeds the threshold voltage of-0.9V, and a memristor M3,2Is set to RMAfter the resistance value is changed, the voltage division of the two ends is-1.0964V and is not more than the threshold voltage of-1.1V, so that the state cannot be changed continuously, and the output memristor finally outputs logic 1;
when the input is logic '0' and '2', the parallel total resistance of the input memristor in the OR operation stage is 99 omega, and then the memristor M3,1The partial pressure at both ends is 1.238V;
when the input is logic 1 and 2, the parallel total resistance of the input memristor is 90.9 omega, and then the memristor M3,1The partial pressure at the two ends is 1.239V;
when the input is all logic '2', the parallel total resistance of the input memristor is 50 omega, and then the memristor M3,1The partial pressure at both ends is 1.244V;
the above three kinds ofIn case of memory resistor M3,1The divided voltages at both ends exceed the threshold voltage of 0.9V, so M3,1Will be set to RM(ii) a On recall and hinder ware M3,1After the resistance value of the memristor is changed, the voltage is redistributed among the memristors;
memristor M under the three conditions3,1The new voltage division values at the two ends are respectively 1.137V, 1.146V and 1.19V, and all exceed the threshold voltage 1.1V, so that the memristor M3,1Is finally switched to RLI.e., logic "2";
in the 'NOT' operation phase, the memristor M3,1Is logic 2, the parallel resistance value of the logic 2 and the fixed resistor is 20 omega, and the output memristor M3,2The divided voltage at two ends is-0.9358V, the threshold voltage is exceeded-0.9V, and the memristor M3,2Is set to RMAfter the resistance value is changed, the voltage division at two ends is-1.101V, and exceeds the threshold voltage of-1.1V, so that the state can be further switched to RHThe output memristor finally outputs a logic "0".
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Application publication date: 20210702 |