JP4800706B2 - Multi-value decoding means, multi-value storage circuit, and multi-value information processing means - Google Patents

Description

According to the first aspect of the invention, “F input signals obtained by dividing numerical values in N-ary notation and F-digit display for each digit and corresponding values {e.g., 0 to (N to the power of F-1)}} Is a ternary or ternary multi-value decoding means for judging whether or not it corresponds to each numerical value.
For this reason, this multi-level decoding means is, for example, a multi-level decoder, multi-level address decoder, multi-level instruction decoder, multi-level code converter or “multi-level multiplexer, multi-level demultiplexer or multi-level memory means”. It can be used as a control means (eg memory chip select control).
N ≧ 3 and F ≧ 1. It is of course possible to replace the above numerical values with respective symbols such as alphabets and handle them in substantially the same manner as the above numerical values.

A second invention (Claim 5) relates to a multi-value storage circuit of a word selection system in which the multi-value decoding means of the first invention is used as a multi-value address decoder and combined with a multi-value memory cell. However, there is a case of the second invention in which one word consists of one multi-value memory cell.
The third invention (Claim 6) and the fourth invention (Claim 7) each use two multi-value decoding means of the first invention as two multi-value address decoders and combine them with multi-value memory cells. The present invention relates to an XY selection type multi-value storage circuit.
Even in the XY selection method, a plurality of digits can be stored by combining a plurality of multi-value storage circuits. In each of the second to fourth inventions, a ROM type (fixed memory type), a semi-fixed memory type, various PROM types, a flash memory type, a RAM type (read memory) Light type).

According to a fifth aspect of the present invention (invention 8), a multilevel synchronous latch means is connected to the input side of the multilevel storage circuit of the second aspect of the present invention, and one input information (or input data) or “a plurality of input information is combined. The input content (or input value) indicated by “combination input information (or combination input data)” is associated with an address, and “corresponding to each input content and storing one output information (or output data) or“ multiple The present invention relates to a multi-value information processing means for outputting (= reading) output contents (or output values) of “combination output information (or combination output data) combining output information”.
According to a sixth aspect of the present invention (invention 9), multi-level synchronous latch means is connected to the input side of the multi-level memory circuit of the third or fourth aspect of the present invention, and one input information (or input data) or "a plurality of input information" The input content (or input value) indicated by “combined input information (or combined input data)” is associated with an address, and “one output information (or output data) corresponding to each input content and stored, or The present invention relates to a multi-value information processing means for outputting (= reading) “output contents (or output values) of combination output information (or combination output data) combining a plurality of output information”.
The processing operations of both inventions are similar to “functions” representing relationships such as “independent variable”, “independent variable value”, “dependent variable”, and “dependent variable value”.
In both the inventions, a plurality of input signals are “simultaneously or separately” based on one or a plurality of “synchronization signals, interrupt signals, or various trigger signals” corresponding to, for example, “binary or multilevel”. And G (≧ 1) output signals corresponding to these input signals are output.

Therefore, the multi-value information processing means of the fifth and sixth inventions can be applied to a “non-Neumann computer”. If you dare to name it, would it be an “input / output pattern storage computer” (or “function storage computer”)? ?
In particular, the "input / output pattern storage type decimal computer" is very promising, and if it is widely put into practical use, it does not require a program. Can solve embedded program software crisis.
The reason why the program is unnecessary is to firstly specify “each output content (or each output value) for each input content (or each input value)”, for example, “mechanical, experimental, empirical, computational or logical”, etc. This is because it can be easily guessed that it can be determined. If you dare to name it, would it be "input / output pattern (software)" {or "function (software)"}! ?
And second, when combined with “the most plentiful system for people (decimal), decimal system”, “variety of data processing of super (・ super…) and astronomical numbers” is almost infinite. There is anything. (There is no processing that can't be done ??) It is because the problem-handling response capability is born. [Detailed description will be described later. ]
For that reason, “input / output pattern storage computer” does not require program software, programmers, etc., so if it is widely put into practical use, it will not require a significant increase in the number of program software engineers. . Perhaps now (at the time of this application) it may be just before the beginning of the end of the "era when embedded program software, etc. is the center of computer software".

Accordingly, each of the present inventions can be divided into a multi-value (or multi-adic) logic circuit, a multi-value (or multi-adic) arithmetic circuit, a multi-value computer (or a multi-adic computer, especially 4, 8, “10”, 16, 32). 64, “100”, 128-base computer, etc.), wired, wireless, multi-value (or multi-adic) modulation communication means such as in an automobile, aircraft or ship, multi-value (or multi-adic) information recording It can be used as a means, a component such as a multi-value (or multi-adic) control means, a horizontal means.
Of course, each information processing means of the fifth and sixth inventions can be used as an ordinary multi-value storage circuit.

■■ Background art of the first invention ■■
So far, the configuration may change depending on the number of multi-values (N for N values, 10 for 10 values, and so on), so all multi-values (≧ 3 values) There was no multi-value coating means that could be used.
Multilevel decoding means, for example multilevel decoder chromatography, multilevel address decoder chromatography, multilevel instruction decoder, the multi-level code converter or "multi-level multiplexer, multi-level demultiplexer or multi-level memory means" of the selection control means (Example: memory chip select control), etc.

JP 2004-032702 (multi-valued logic circuit of the present inventor) JP-2005-198226 (same as above) Japanese Patent Application No. 2005-033620 (same as above)

Mathematical Sciences February Issue (1980, No.200) Special Issue Multivalued Logic, published by Science Co., Ltd. on February 1, 1980. Technical article of the Nikkei Sangyo Shimbun (Tokyo edition): “High-tech classroom multi-valued logic circuit IC integration increases and does not go binary or ternary”, Nikkei Sangyo Shimbun, Friday, November 22, 1985 Issued). Written by Ishizuka Yoshihiko. "Multi-valued information processing-post-binary electronics-", authors: Tatsuo Higuchi, Michitaka Kameyama, Shokodo in June 1989. "Transistor Technology September 1997" published by CQ Publishing Co., Ltd. on September 1, 1997. P. 374-p. 375 “Attic Resource Room Multilevel Logic”. Author: Hidekazu Inoue.

■■ Background Art of the Second Invention ■■
As a matter of course, there has never been a multi-value storage circuit of a word selection system using the multi-value decoding means of the first invention as a multi-value address decoder and combining with a multi-value memory cell.

Patent No. 2853041 (inventor's multi-value storage means) JP 2004-087763 (same as above) JP-A-2005-116168 (same as above) Japanese Patent Application No. 2005-075909 (same as above) Japanese Patent Application No. 2005-109163 (same as above) Japanese Patent Application No. 2005-195524 (same as above)

“Introduction to Transistor Circuit Lecture 5: Digital Circuits” p. 151-p. 162, “Chapter 11: Thinking about memory”. Published by Ohm Co., Ltd. on May 20, 1981. Supervised and written by Yoshifumi Amemiya and others.

■■ Background art of the third invention ■■
As a matter of course, there has never been an XY selection type multi-value storage circuit using the multi-value decoding means of the first invention as a multi-value address decoder and combining with a multi-value memory cell.

■■ Background Art of the Fourth Invention ■■
Further, as a matter of course, the multi-value storage of the XY selection system in which the multi-value decoding means of the first invention is used as a multi-value address decoder and combined with multi-value memory cells in a configuration partially different from the third invention. There has never been a circuit.

■■ Background art of the fifth invention ■■
Then, as a matter of course, the function-free setting type multi-value information processing means (or multi-value data processing means) combining the multi-value storage circuit of the second invention and one or more multi-value synchronous latch means is: Never before.
Here, a prototype of a large function information processing means that can be developed into a non-programmed, non-Neumann computer will be described.
Non-Patent Document 8 below discloses “information conversion action” which is one application example of a binary IC memory as follows. “When an address is given to a memory (RAM type, fixed storage type or semi-fixed storage type) and information is read from a memory cell group designated by the address, the address is also a kind of information. There is a conversion rule (= function of input information) in this information conversion operation, and the rule can be freely determined by the user within a range limited by the storage capacity. Examples: Display memory, keyboard encoder, serial / parallel / parallel / serial conversion. ]

ACT 2-5937

“Nikkei Electronics December 18, 1972 issue” p. 116-p. 126, “Electronic fuel injection system for engines using MOS ROM”. Author: Malcolm Williams. “Electronic Technology No. 11 1973, Vol. 15, No. 11, p. 29-p. 33 “MOS ROM”. Written by Yasumasa Iwata. → ROM application. "How to use IC memory", published by Sangyo Publishing Co., Ltd. on June 20, 1978. Authored by Matsuo Nitta and Ryoichi Oomote. “Chapter 7 Application Examples of IC Memory” p. 107-p. 108.

In practice, the information processing means is an input that becomes an address signal in a plurality of latch circuits or registers based on various synchronization signals such as event input (eg, polling, interrupt, etc.) and event output, and various trigger signals. Latching a signal, accessing a binary IC memory at the address, outputting (= reading) an (information) read signal to be an output signal according to the access, updating the input signal to be latched, etc. Will be equal.
  However, there are cases where the latch is accessed following the latch, the output is output following the access, or a plurality of other operations are almost simultaneously performed.
In this case, the important point is that each output content obtained by performing information processing (or data processing) on each input content is stored in the memory cell group at each address, and the content of the information processing is within the range allowed by the storage capacity. The user can freely set anything.
As a result, whatever the binary IC memory is RAM type, fixed storage type, semi-fixed storage type, flash type, etc., the information processing (or data processing) contents can be freely set based on the stored storage contents. The binary IC memory or the like functions as an information processing means (or data processing means) of a function-free setting type that can be set. The degree of freedom of function setting increases with an increase in the storage capacity.

"Nikkei Manufacturing March 2005 issue" published by Nikkei BP on March 1, 2005. p. 121-p. 124 “Embedded soft ball hand box 03”. Writer: Kiichiro Tamaru. Reference: Event input and event output. Relationship between input, processing, and output.

However, the disclosed technique of Non-Patent Document 8 “How to Use IC Memory” seems to be a case where there is one input information, but “combined input information combining a plurality of input information” can be made to correspond to a memory address. On the other hand, “combination output information obtained by combining a plurality of output information” can be made to correspond to the stored content. The present inventor considers that there is a patentability in the combination technique of these information if there is no precedent regarding the combination of these information.
In order to clarify the relationship with the following “extra information processing (or data processing) type (super -...) super-explosive size”, the combination input information (or combination) Input data), combination input content (or combination input value), combination output information (or combination output data), and combination output content (or combination output value) will be briefly described .

The combination input information is `` function independent variable '', the combination input content is `` the value of that independent variable '', the combination output information is `` the dependent variable '', the combination output content is `` the value of the dependent variable '', respectively It is easy to understand if it is associated.
Although the display may be in any number system, the input content 1 of the input information 1 is 3 digits of [a0 · a1 · a2] and the input content 2 of the input information 2 is 3 digits of [a3 · a4 · a5] If the input content 3 of the input information 3 is 2 digits of [a6 · a7], these three input contents are combined to obtain a combined input content [a0 · a1 · a2 · a3 · a4 · a5 · a6 · a7]. This is used as the memory address as it is, and the memory is accessed.
The storage cell group at the address has “eight digits of combination output contents [b0, b1, b2, b3, b4, b5, b6, b7] corresponding to the combination input contents (although it is not necessary to have the same number of digits). )] Is stored, and the stored contents are output. That is, it is read out.
In this combined output content, for example, the output content 1 of the output information 1 is 2 digits of [b0 · b1], the output content 2 of the output information 2 is 4 digits of [b2, b3, b4, b5], and the output information 3 The output content 3 is 2 digits of [b6 · b7].
At this time, the input content 1 [a0 · a1 · a2], the input content 2 [a3 · a4 · a5] and the input content 3 [a6 · a7] are processed by the memory, and the output content 1 [b0 · b1 ], Output content 2 [b2, b3, b4, b5] and output content 3 [b6, b7] are output.
Similarly, “one combination output content corresponding to the combination input content” is stored one by one at each address determined by each combination input content, and is output in response to the access.

As long as the storage capacity of the memory allows both the input information side and the output information side, the number of digits and the way of combination are arbitrary.
Of course, there is a case where each input content is converted into a numerical value and then used as a memory address. For example, each input content (or input data) of “minus 40 degrees C to plus 59 degrees C” of the input information (or input data) “temperature” is converted into numerical values of “00 to 99 (decimal number)” ( In this case, 40 addition processing) is performed to correspond to two digits of the address. Of course, “output content (or output data) for minus 40 degrees C” is stored at address 00 of the 10-value memory, and “output contents for plus 59 degrees C” is stored at address 99 thereof. On the other hand, depending on the type of input information, the subtraction process may be performed in the opposite direction.
Then, for example, in the case of engine control, if the engine speed 0 to 9999 may be input in increments of 10 instead of in increments of 1 revolution, input information “engine speed” is input. The input contents can be compressed from the range of “0 to 9999 (decimal number)” to the range of “0 to 999 (decimal number)” (in this case, almost 10 division processing), so the memory address is not 4 digits. Three digits are enough. On the other hand, when “something minute or minute (eg, concentration, displacement, mass, energy)” or the like is used as input information, it may be multiplied in the opposite direction in order to enlarge.

Now, against the problem-handling capability of programming with Neumann computers, the function setting freedom of the information processing means (or data processing means) of the function free setting type described above may be said to be “infinite” in practice. In order to expand to the rank (about) and lead to the development of non-Neumann type computers, the conventional binary memory is multi-valued, and the multi-value number (N for N value, N for 10 value, 10 for 10 value). ) Needs to be increased.
Mathematically, from here on, "Super- (super -...) super-explosive bow size" of "Type of multi-value information processing (or multi-value data processing)" (that is, "Type of multi-valued logic function") Explained. The numerical explosion occurs from binary to multivalue and as the multivalue increases.
In that case, the present inventor feels that the meaning and nature are narrow and small in the concept of “logic of logic function”. This is because the multi-value information processing includes, for example, output patterns of more complicated calculation formulas from addition / subtraction remainder, exponent / logarithmic calculation, trigonometric function calculation, and the like. Perhaps it may include things that cannot be expressed by the algorithm.

For example, in the case of binary logic with one digit and two inputs, there are two combinations of input variables, that is, the square of 2 = 4 sets, and there are two ways of output in each of the four sets, numerical values “0” and “1”. Therefore, there are two kinds of information processing or logic functions, that is, the fourth power of 2 = 16. That is, there are 16 different output patterns for the four input variables “0 and 0”, “0 and 1”, “1 and 0”, and “1 and 1”, which are two sets of binary one digit and two inputs. That is. Among the 16 types, there are AND, OR, NOT, NAND, NOR, exclusive OR, and the like.

"Introduction to Transistor Circuit Lecture 5: Digital Circuit Concept" published by OHM Co., Ltd. on May 20, 1986. Supervision: Yoshifumi Amemiya, Norii Koshiba. Author: Kenshi Shimizu, Masatomo Kazuwa. See: p. 34 “Table 3. 8 Logical functions consisting of two input variables”.

Similarly, in the case of ternary logic with one digit and two inputs, there are 9 combinations of input variables, that is, the square of 3 = 9 sets. For each of the 9 sets, for example, numerical values “0” and “1” are used for output. , “2”, the number of types of multi-value information processing or multi-valued logic functions increases to 3 9 = 19,683 at once. That is, nine sets of input variables “0 and 0”, “0 and 1”, “0 and 2”, “1 and 0”, “1 and 1”, “1 and 2”, which are ternary 1-digit 2-input, There are 19,683 different output patterns for the input patterns “2 and 0”, “2 and 1”, and “2 and 2”.
Similarly, in the case of quaternary logic with one digit and two inputs, the combination of input variables is the square of 4 = 16 sets. For each of the 16 sets, for example, numerical values “0”, “1”, “ Since there are four ways of “2” and “3”, there are 4 kinds of multi-value information processing (or multi-value logic functions) of 4 16 = 4,294,968,000.
Similarly, in the case of 5-digit logic with 1 digit and 2 inputs, 5 to the 25th power = 2.9980233 × (10 to the 17th power) type, and in the case of 10-value logic with 1 digit and 2 inputs, the “10 to the 100th power” type.

And the type of multi-value information processing (or multi-value logic function) becomes “super-super -... super-explosive size” by increasing the number of digits and the number of inputs. For example, in the case of 10-value 1-digit 3-input, "10 to the 1000th power" type, in the case of 10-value 2-digit 2-input, the "10 to 10,000 power" type, 10-value 3-digit 2-input or 10-value 2-digit In the case of 3 inputs, there is multi-value information processing (or multi-valued logic function) of “10 million to the power” type.
Furthermore, in the case of 10-digit 4-digit 2-input, "10 100 million power" type, in the case of 10-value 4-digit 3-input or 10-value 6-digit 2-input, "10 trillion power" type, 10 value 4 There are multi-value information processing (or multi-valued logic functions) of the type “10 1K (= 10,000 trillion) / multiplier” in the case of 4 digits input or 10 values 8 digits 2 input. It is exactly “super (super) ... super-astronomical numbers”.
Surprisingly, there were so many enormous numbers buried in the 10-value 8-digit 2-input "just this thing"! ! ! It is. It is no longer necessary to say “infinite” practically, there is nothing, and there is no multi-value information processing that cannot be done (???). The number of types of information processing by Neumann type computers is lightly exceeded (????).
Incidentally, in the case of binary 8-digit 2-input, there are 65,636 types, which is less than 10 to the fifth power. In order for the number of types of binary information processing to be equal to the number of types of 10-value information processing, 10 = approximately 2 to the power of 3.322. Therefore, the product of the number of digits on the input side of the former and the number of inputs is that of the latter. It is necessary to make it about 3.322 times. The same applies to the product of the number of digits on the output side and the number of inputs.

In this way, as the number of multi-values (for example, N for N, N for 10 or 10 for 10) increases, the type of multi-value information processing is "super- (super -...) super-explosively" To increase.
This means that a multi-value information processing means having a multi-value information processing function that is optimal for “necessary information processing (or data processing)” can be realized and selected. Or "information processing", which means that it is similar to software programming in terms of problem-handling ability, and a completely new and huge possibility is buried in multi-valued logic and multi-valued logic. "It may be."
Perhaps multi-digit computers, especially decimal computers, may outperform future binary quantum computers. (The basis and reason will be described later.)

One method for enabling the above-mentioned "realization and selection of multi-value information processing means having a multi-value information processing function optimal for necessary information processing (or data processing)" is described above (paragraph numbers 0014 to 0021). ) Function free setting type information processing means ”and“ multi-value ”, that is,“ function free setting type multi-value information processing means ”.
In addition, even if the number of multi-values, the number of digits, or the number of inputs is small, it can be used as a system component such as a logic circuit or a calculation circuit.
For this reason, “a function-free setting type multi-value information processing means (or multi-value data processing means) in which the multi-value storage circuit of the second invention and one or more multi-value synchronous latch means are combined is desired.

■■ Background art of the sixth invention ■■
Naturally, the function-free setting type multi-value information processing means (or multi-value information processing means) combining one or more multi-value storage circuits of the third or fourth invention and one or more multi-value synchronous latch means. There has been no value data processing means). Details are the same as described above (paragraph numbers 0014 to 0028).

■■ Problems to be solved by the first invention ■■
Therefore, “the configuration may be changed according to the number of multi-values (≧ 3). Therefore, a multi-value coating means capable of dealing with any multi-value with a small number of parts and a simple configuration is desired. There is a problem that. (Task)
Accordingly, the first invention is to provide a multi-level decoding means that “the configuration may be changed according to the multi-level number, so that it can cope with any multi-level with a small number of parts and a simple configuration”. It is said. (Object of the first invention)

■■ Problems to be solved by the second invention ■■
Therefore, “a multi-value storage circuit of the word selection system using the multi-value decoding means of the first invention as a multi-value address decoder and combining with a multi-value memory cell is desired. There is a problem that. (Task)
Accordingly, the second invention aims to provide a multi-value storage circuit "of a word selection method using the multi-value decoding means of the first invention as a multi-value address decoder and combining with a multi-value memory cell". Yes. (Object of the second invention)
However, there are cases where one word is composed of one multi-level memory cell.

■■ Problems to be solved by the third invention ■■
Therefore, an XY selection type multi-value storage circuit using the multi-value decoding means of the first invention as a multi-value address decoder and combined with a multi-value memory cell is desired. There is a problem that. (Task)
Therefore, the third invention aims to provide a multi-value storage circuit "of the XY selection method using the multi-value decoding means of the first invention as a multi-value address decoder and combined with a multi-value memory cell". Yes. (Object of the third invention)

■■ Problems to be solved by the fourth invention ■■
Therefore, “an XY selection type multi-value storage circuit is desired in which the multi-value decoding means of the first invention is used as a multi-value address decoder and combined with a multi-value memory cell in a partly different configuration from the third invention. . There is a problem that.
(Task)
Therefore, the fourth invention has a configuration that is partly different from the third invention, which is an “XY selection method using the multi-value decoding means of the first invention as a multi-value address decoder and combined with a multi-value memory cell”. An object is to provide a memory circuit. (Object of the fourth invention)

■■ Problems to be solved by the fifth invention ■■
Therefore, there is a problem that “a function-free setting type multi-value information processing means (or multi-value data processing means) combining the multi-value storage circuit of the second invention and one or a plurality of multi-value synchronous latch means is desired”. There are points. (Task)
Accordingly, the fifth aspect of the invention provides a multi-value information processing means (or a multi-value data processing means) of “a function free setting type combining the multi-value storage circuit of the second invention and one or a plurality of multi-value synchronous latch means”. The purpose is to provide. (Object of the fifth invention)

■■ Problems to be solved by the sixth invention ■■
Therefore, “function-free setting type multi-value information processing means (or multi-value data) combining one or more multi-value storage circuits of the third or fourth invention and one or more multi-value synchronous latch means” The processing means) is desired ”. (Section
Title)
Accordingly, the sixth invention provides a “multi-value information processing of a function free setting type combining one or more multi-value storage circuits of the third or fourth invention and one or more multi-value synchronous latch means”. The object is to provide means (or multi-value data processing means).
(Object of the sixth invention)

■■ Means for the first invention to solve the problem ■■
That is, the first invention is a multilevel decoding means as described in claim 1. For each digit, the first to Nth numerical value identification means for that digit are based on “a positive or negative threshold potential based on each of the N potentials” and “a numerical value corresponding to the input signal for that digit”. Is “corresponding” to the first to Nth numerical values for each numerical value, and the identification result is output as an identification output signal one by one.
For each digit, the first to Nth signal conversion means for that digit convert the identification output signal into a “signal based on a common reference potential”, and the conversion result is converted into a conversion output signal. Output one by one.
The first to the first (Nth power of F) determination means determine that “for each digit, a combination of F converted output signals obtained by extracting and combining one of the N converted output signals for that digit”. Create different combinations (N to the power of F) and determine whether each of the F conversion output signals indicates “applicable” for each set based on the common reference potential. The results are output as judgment output signals one by one.
Of course, one component means may serve as a plurality of the above means.

■■ Means for the second invention to solve the problem ■■
That is, the second invention is a multi-value storage circuit according to claim 5. By using the multilevel decoding stage of the first invention as an address decoder, G (≧ 1) pieces of “multilevel memory cells formed by the multilevel storage means and the selection switching means” are designated. The total designated number is the same as the total number of the corresponding determination means.
Normally, there are a plurality of G, but there are cases where the number is 1. Therefore, one word may be composed of one multilevel memory cell.

■■ Means for the third invention to solve the problem ■■
That is, the third invention is a multi-value storage circuit as set forth in claim 6. Two multi-level decoding means of the first invention are used as two address decoders to designate "multi-level memory cells formed by multi-level storage means and selection switching means" one by one. The total designated number is the same as the product of the total number of all corresponding determination means of the former and the total number of all corresponding determination means of the latter.
Even in the XY selection method, a plurality of digits can be stored by combining a plurality of multi-value storage circuits.

■■ Means for the fourth invention to solve the problem ■■
That is, the fourth invention is a multi-value storage circuit as set forth in claim 7. Two multi-level decoding means of the first invention are used as two address decoders, one by one with a configuration partially different from that of the third invention "multi-level memory cell formed by multi-value storage means and selective switching means" Is specified. The total designated number is the same as the product of the total number of all corresponding determination means of the former and the total number of all corresponding determination means of the latter.
Even in the XY selection method, a plurality of digits can be stored by combining a plurality of multi-value storage circuits.

■■ Means for the fifth invention to solve the problem ■■
That is, the fifth invention is the multi-value information processing means as described in claim 8. The input content (or input value) indicated by one piece of input information (or input data) or “combination input information (or combination input data) combining a plurality of input information” is “the above-mentioned N-ary system treated as an address, Since each of the input contents and each address correspond to each other one by one.
Further, the multi-value storage means G (≧ 1) of each address has “one output information (or output data) corresponding to“ input contents corresponding to the address ”or“ a plurality of output information combined. The output contents of “combined output information (or combination output data)” are stored one by one.The “output contents corresponding to the input contents” is “information freely determined by the user of this multi-value information processing means” "Content of the result of processing the input content". The user determines the content of the information processing as, for example, “experimental, empirical, automatic by machine, computational or logical”.
On the other hand, in terms of electrical signals, the F multi-level synchronous latch means are treated as address signals based on various synchronization signals such as event input (eg, polling, interrupt, etc.) and event output, various trigger signals, etc. The F input signals are latched "simultaneously or separately" to fix each address signal at the time of access, to access the multi-value storage circuit with the address signal, or one or more according to the access The “output signal (multi-value information) read signal” is output (= read), each input signal to be latched is updated, and the like.
However, there are cases where a plurality of operations are almost simultaneous, such as an access following a latch or an output following an access.

■■ Means for the sixth invention to solve the problem ■■
That is, the sixth invention is multi-value information processing means as described in claim 9. The input content (or input value) indicated by one piece of input information (or input data) or “combination input information (or combination input data) combining a plurality of input information” is “the above-mentioned N-ary system treated as an address, Therefore, each input content and each address correspond to each other one by one.
Then, the multi-value storage means G (≧ 1) of each address has “one output information (or output data) corresponding to“ the input content corresponding to the address ”or“ a combination of a plurality of output information. The output contents of “combined output information (or combination output data)” are stored one by one.The “output contents corresponding to the input contents” is “information freely determined by the user of this multi-value information processing means” "Content of the result of processing the input content". The user determines the content of the information processing as, for example, “experimental, empirical, automatic by machine, computational or logical”.
On the other hand, in terms of electrical signals, the F multi-level synchronous latch means are treated as address signals based on various synchronization signals such as event input (eg, boring, interrupt, etc.) and event output, various trigger signals, and the like. The F input signals are latched “simultaneously or separately” to fix each address signal at the time of access, to access the multi-value storage circuit with the address signal, or to one or more according to the access The “output signal (multi-value information) read signal” is output (= read), and each input signal to be latched is updated.
However, there are cases where a plurality of operations are almost simultaneous, such as an access following a latch or an output following an access.

■■ Effects of the first invention ■■
As a result, a plurality of "multi-value numerical identification means optimal for identifying whether or not the numerical value corresponding to each input signal corresponds to each numerical value of the first numerical value to the Nth numerical value" Multiple "appropriate judgment means suitable for judging whether or not it corresponds to" and "signal conversion means for potential matching between input and output of both means group to make use of both means group" Therefore, the multi-level decoding means of the first invention has the effect that “the configuration may be changed according to the multi-level number, so that it can handle all multi-levels”.
In addition, since the reference potential used by all the corresponding determining means is made common, it has the effect of “the number of parts is small and the configuration is simple”.
This is because, for example, if the reference potential is different for each corresponding determination means, a “converted output signal for one identification output signal” must be prepared for each corresponding determination means, resulting in an increase in the number of parts and a complicated configuration. Because.

■■ Effects of the second invention ■■
As a result, each of the G multi-value storage means at the address designated by the numerical value of the N-ary notation and F-digit display corresponds to “the stored data signal transmission means”. Since the "read signal" can be output, the circuit of the second invention can function as a word selection type multi-value storage circuit.

■■ Effects of the third invention ■■
As a result, the multi-value storage means of the address designated by the numerical value of the N-ary notation and (Fx + Fy) digit display can output a “read signal according to the stored contents” to the data signal transmission means. The circuit of the invention can function as an XY selection type multi-value storage circuit.

■■ Effects of the fourth invention ■■
As a result, the multi-value storage means of the address designated by the numerical value of the N-ary notation and (Fx + Fy) digit display can output a “read signal according to the stored contents” to the data signal transmission means. This circuit can function as an XY selection type multi-value storage circuit.

■■ Effects of the fifth invention ■■
As a result, “the output content obtained by performing multi-value information processing (or multi-value data processing) on the input content corresponding to the address” is stored in the G multi-value storage means G of each address. The contents of the value information processing can be freely set by the user as long as the storage capacity allows.
As a result, regardless of whether the multi-value storage circuit is a RAM type, a fixed memory type, a semi-fixed memory type, a flash type, etc., the contents of the multi-value information processing (or multi-value data processing) based on the stored contents to be written Therefore, the means of the fifth invention can function as a function-free setting type multi-value information processing means (or multi-value data processing means). The degree of freedom of function setting increases with an increase in the storage capacity.

■■ Effects of the sixth invention ■■
As a result, “the output content obtained by performing multi-value information processing (or multi-value data processing) on the input content corresponding to the address” is stored in the G multi-value storage means G of each address. The contents of the value information processing can be freely set by the user as long as the storage capacity allows.
As a result, regardless of whether the multi-value storage circuit is a RAM type, a fixed memory type, a semi-fixed memory type, a flash type, etc., the contents of the multi-value information processing (or multi-value data processing) based on the stored contents to be written Therefore, the means of the sixth invention can function as a function-free setting type multi-value information processing means (or multi-value data processing means). The degree of freedom of function setting increases with an increase in the storage capacity.

In order to explain each invention in more detail, these will be described with reference to the accompanying drawings. Note that the potential of the power supply line V (-1) is represented by the potential v (-1), the potential of the power supply line V0 is represented by the potential v0, the potential of the power supply line V1 is represented by the potential v1, and thereafter the power supply line V2 is similarly represented. From the power supply line Vn to the power supply line Vn, the potentials v2 to vn are used.
Further, the potential increases in order from the potential v (−1) to the potential vn, where n corresponds to N in claim 1 and is described above as each potential from potential v0 to potential (n−1). The numerical values of the first numerical value to the nth numerical value correspond to each other one by one in numerical order.

The embodiment 1 shown in FIG. 1 is an example of a circuit block diagram of the multi-value decoding means of the first invention, and the input numerical value represented by 10-digit three digits is “corresponding” for each numerical value ranging from a numerical value 000 to 999. Whether each of the determination results is output as a binary value.
Each of FIGS. 2 to 8 is an example of each constituent means (numerical identification means, signal conversion means, and corresponding determination means) that constitutes each constituent means (each example will be described later).
Therefore, the above-mentioned N is 10, the above-mentioned F is 3, and each constituent means shown in FIG. 1 etc. corresponds to each constituent means in Claim 1 as follows.
★ a) The potential v0 to the potential v9 are sequentially changed from the first potential to the Nth (= 10) potential in the same paragraph.
* B) Each of the numerical value 0 to the numerical value 9 is sequentially changed to the first numerical value to the Nth (= 10) numerical value in the same paragraph.
● Thus, the number 0 corresponds to the potential v0, numerical 1 corresponds to the potential v1, "the potential of the potential v2 to a potential v9" After likewise as "each number from the value 2 to a value 9" each other One-to-one correspondence.
* C) The power supply line V0 to the power supply line V9 are sequentially supplied to the first potential supply means to the Nth (= 10) potential supply means in the same paragraph.
★ d) The first digit input signal of the input terminal Flin, the second digit input signal of the input terminal F2in, and the third digit input signal of the input terminal F3in are the F (= 3) input signals described in the same paragraph.

★ e) Each of the numerical identification means D10 to D19 is assigned to each of the first numerical identification means to the Nth numerical identification means (N = 10) in the first digit described in the same paragraph.
* F) Each of the numerical value identifying means D20 to D29 is assigned to each of the first numerical value identifying means to the Nth numerical value identifying means (N = 10) in the second digit in the same paragraph.
* G) Each of the numerical identification means D30 to D39 is assigned to each of the first numerical identification means to the Nth numerical identification means (N = 10) in the third digit in the description.
* H) Each of the signal conversion means C10 to C19 is respectively applied to the first digit conversion means to the Nth signal conversion means (N = 10) in the first digit in the same paragraph.
* I) Each of the signal conversion means C20 to C29 is applied to the first digit conversion means to the Nth signal conversion means (N = 10) in the second digit in the description.
★ j) Each of the signal conversion means C30 to C39 is respectively in the first digit conversion means to the Nth signal conversion means (N = 10) in the third digit in the same paragraph.
★ k) Each of the corresponding determination means J000 to J999 is each of the first corresponding determination means to the (Nth power of F) 1000 corresponding determination means in the same paragraph.
● However, N to the power of F = 1,000. N = 10, F = 3.

■■ First example of composition means used in invention ■■
In the first example of the configuration means shown in FIG. 2, the binary CMOS / NOT circuit serves as both the first numerical value identification means and the first signal conversion means of the first invention.
“A binary three-input AND circuit connected between two power supply lines V1 and V0” corresponds to one of the determination means for inputting a conversion output signal of the binary CMOS / NOT circuit.
The potential v0 of the power supply line V0 corresponds to a common reference potential in claim 1, and n corresponds to N in claim 1.

■■ Second example of composition means used in invention ■■
In the second example of the configuration means shown in FIG. 3, the binary CMOS / NOT circuit corresponds to the first numerical value identification means of the first invention, and “a series of a grounded PMOS and its load resistance (= pull-down resistance) in series. The “circuit” corresponds to the first signal converting means of the first invention.
2. The “binary three-input AND circuit connected between two power supply lines V0 and V (−1)” corresponds to one of the determination means for inputting the conversion output signal of the series circuit, and n is in claim 1. Is equivalent to N.
In this case, the potential v (−1) of the power supply line V (−1) corresponds to the common reference potential in the first aspect.

■■ Third example of composition means used in invention ■■
In the third example of the configuration means shown in FIG. 4, n corresponds to N in claim 1 and there is a relationship of n-1>m> 0. That is, the third example of the constituent means is used as at least one of “second numerical value identifying means for identifying an intermediate numerical value between the first numerical value and the nth numerical value to (n−1) th numerical value identifying means”.
“Connected body of 3MOSFET of gate ground, drain ground and source ground to power supply line Vm and gate-source resistance” corresponds to the (m + 1) th numerical value identifying means of the first invention, and the potential vm is the (m + 1) th numerical value. Correspond.
“Connected body of pull-down resistor connected to power supply line V0 and binary NOT circuit” corresponds to the (m + 1) th signal converting means of the first invention.
The “binary three-input AND circuit connected between the two power supply lines V1 and V0” corresponds to one of the determination means for inputting the conversion output signal of the binary NOT circuit or the like.
Further, since the potential v0 of the power supply line V0 corresponds to the common reference potential in the first aspect, it is used together with the first example of the configuration means of FIG.

■■ Fourth example of composition means used in invention ■■
In the fourth example of the constituent means shown in FIG. 5, n corresponds to N in claim 1 and there is a relationship of n-1>m> 0. In other words, the fourth example of the constituent means is also used as at least one of “second numerical value identifying means for identifying an intermediate numerical value between the first numerical value and the nth numerical value to (n−1) th numerical value identifying means”.
“Connected body of 3MOSFET of gate ground, drain ground and source ground to power supply line Vm and gate-source resistance” corresponds to the (m + 1) th numerical value identifying means of the first invention, and the potential vm is the (m + 1) th numerical value. Correspond.
“Connected body of pull-down resistor connected to power supply line V (−1) and binary NOT circuit” corresponds to the (m + 1) th signal converting means of the first invention.
“A binary three-input AND circuit connected between two power supply lines V0 and V (−1)” corresponds to one of the determination means for inputting a conversion output signal of the binary NOT circuit or the like.
Further, since the potential v (-1) of the power supply line V (-1) corresponds to the common reference potential in claim 1, it is used together with the second example of the configuration means of FIG.

■■ Fifth example of component means used in invention ■■
In the fifth example of the configuration means shown in FIG. 6, n corresponds to N in claim 1, and naturally there is a relationship of n ≧ 3, and the binary CMOS / NOT circuit is the Nth numerical identification of the first invention. Corresponds to means.
Further, “a connected body of the second-stage PMOS with the source grounded to the power supply line V (n−1) and the pull-down resistor connected to the power supply line V0” corresponds to the N-th signal conversion means of the first invention.
The “binary three-input AND circuit connected between the two power supply lines V1 and V0” corresponds to one of the determination means for inputting the conversion output signal such as the second-stage PMOS.
Further, since the potential v0 of the power supply line V0 corresponds to the common reference potential in claim 1, it is used together with, for example, the first example of the configuration means of FIG. 2 or the third example of the configuration means of FIG.

■■ Sixth example of composition means used in invention ■■
In the sixth example of the configuration means shown in FIG. 7, n corresponds to N in claim 1, and naturally there is a relationship of n ≧ 3, and the binary CMOS / NOT circuit is the Nth numerical identification of the first invention. Corresponds to means.
In addition, the “connected body of the second-stage PMOS with the source grounded to the power supply line V (n−1) and the pull-down resistor connected to the power supply line V (−1)” corresponds to the Nth signal conversion means of the first invention. To do.
The “binary three-input AND circuit connected between the two power supply lines V0 and V (−1)” corresponds to one of the determination means for inputting the conversion output signal such as the second-stage PMOS.
Further, since the potential v (-1) of the power supply line V (-1) corresponds to the common reference potential in claim 1, for example, the second example of the configuration means of FIG. Used with 4 examples.

■■ Seventh example of composition means used in invention ■■
In the seventh example of the configuration means shown in FIG. 8, n (≧ 3) corresponds to N in the first aspect, and there is a relationship of n−2 ≧ m ≧ 1. That is, the seventh example of the configuration means is similar to the fourth example of the configuration means of FIG. 5, “second numerical identification means for identifying intermediate numerical values between the first numerical value and the nth numerical value to (n−1) th numerical identification means. As at least one of
The “connected body of the 3MOSFET connected to the two power supply lines V (m + 1) · V (m−1) and the resistance between the source and gate” corresponds to the (m + 1) numerical identification means of the first invention, and the power supply line Vm (FIG. Potential vm of (not shown) corresponds to the (m + 1) th numerical value.
“Pull-down resistor connected to power supply line V (−1)” corresponds to the (m + 1) th signal conversion means of the first invention, and “binary 3 connected between two power supply lines V0 and V (−1)”. The “input CMOS / NAND circuit” corresponds to one of the determination means for inputting the converted output signal of the pull-down resistor.
Further, since the potential v (-1) of the power supply line V (-1) corresponds to the common reference potential in claim 1, for example, the second example of the configuration means of FIG. 3 and the second example of the configuration means of FIG. Used with four examples or a sixth example of the configuration means of FIG.
Of course, in the seventh example of the configuration means in FIG. 8, the pull-down resistor is reconnected from the power supply line V (-1) to the power supply line V0, and the CMOS / NAND circuit is connected to the two power supply lines V0.V (-1). An example of a configuration is also possible in which the common reference potential is changed from v (−1) to v0 by reconnecting between the two power supply lines V1 and V0.

In the seventh example of the configuration means of FIG. 8, the “on / off threshold potential of the PMOS that is grounded on the power supply line V (m + 1)” is larger than those in the configuration examples 1 to 6, and the power supply line Although not shown, Vm is set between “the middle potential of potential vm and potential v (m + 1)” and potential vm.
In addition, the “on / off threshold potential of the source-grounded NMOS for the power supply line V (m−1)” is also larger than those in the structural examples 1 to 6, and the power supply line Vm is not shown. It is set between the potential vm and the “potential v (m−1) and the middle potential of the potential vm”.
That is, whether or not the numerical value corresponding to the input signal corresponds to the (m + 1) th numerical value (for example, numerical value m) based on the positive threshold potential and the negative threshold potential based on the potential vm is shown. A seventh example of the eight constituent means identifies. Similarly, the third example of the configuration unit of FIG. 4 and the fourth example of the configuration unit of FIG. 5 are similarly identified based on the positive side threshold potential and the negative side threshold potential with reference to the potential vm. To do.
On the other hand, in the first example of the configuration means of FIG. 2 and the second example of the configuration means of FIG. 3, the numerical value corresponding to the input signal is based on the positive side threshold potential with respect to the potential v0. 6 is identified, and the sixth example of the configuration means in FIG. 6 and the sixth example of the configuration means in FIG. 7 have negative threshold potentials based on the potential v (n−1). Based on this, the numerical value corresponding to the input signal is the nth numerical value {example: numerical value (n-1). } Is identified.

In the second embodiment (first invention) shown in FIG. 9, for example, "0", "1", "2" ternary two-digit display numerical values from decimal display "0" to "8" 2 is a multi-level decoding unit according to the first aspect of the present invention, which determines whether each value is “applicable” and outputs the determination result as a determination output signal one by one. The third example of the configuration means and the fifth example of the configuration means of FIG. 6 are used, and all the binary AND circuits are connected between the two power supply lines V1 and V0. Note that nine binary NAND circuits can be used instead of nine binary AND circuits.
In addition, the numerical value of the ternary system may be “−1”, “0”, “+1”, etc.

In the third embodiment (first invention) shown in FIG. 10 as well, for example, "0", "1", "2" ternary two-digit numerical values from "0" to "8" in decimal notation are displayed. The multi-value decoding means of the first invention for judging whether or not “applicable” for each numerical value and outputting the judgment result as a judgment output signal one by one. The fourth example of the configuration means of FIG. 5 and the sixth example of the configuration means of FIG. 7 are used, and all binary AND circuits are connected between the two power supply lines V0 · V (−1).
Note that nine binary NAND circuits can be used instead of nine binary AND circuits. In addition, the numerical value of the ternary system may be “−1”, “0”, “+1”, etc. Further, although the fourth example of the configuration means of FIG. 5 is used, the seventh example of the configuration means of FIG. 8 can be used one by one instead.

In the fourth embodiment (first invention) shown in FIGS. 11 to 12, for example, “0”, “1”, “2”, “3”, a four-digit two-digit numerical value is displayed in decimal notation. The multi-value decoding means of the first invention for judging whether or not “applicable” for each numerical value from “00” to “15”, and outputting the judgment result as a judgment output signal one by one, Conductors with the same reference numerals are in a connected state.
In order to use 16 positive-logic NOR circuits as negative-logic NAND circuits, the inventor makes the first numerical value identifying means of numerical value “0” different from the second example of the structural means of FIG. The fourth numerical value identifying means of “3” is different from the sixth example of the constituent means of FIG. 7, and the second and third numerical value identifying means of numerical value “1” and numerical value “2” are changed to “constituent means of FIG. In the fourth example, the configuration is such that the binary NOT circuit is removed.

A fifth embodiment shown in FIG. 15 is an example of the multilevel storage circuit of the second invention, and the first embodiment of the first invention of FIG.
F1 to F3 are three input lines to which three input signals corresponding to numerical values in decimal three-digit display are input.
The word lines 000 to 999 correspond to the same number of selection signal transmission means in claim 5, g corresponds to G (≧ 1) in the description, and the data lines DL0 to DL (g−1) have the same number. This corresponds to the data signal transmission means described in the section.
Further, each of the 1,000 × g pieces of squares is a multi-level memory over cells (= multilevel memory cell). Are using an eighth example of the configuration means 13 to be described below to the respective multilevel memory over cells.

■■ Eighth example of component means used in the invention ■■
Eighth example of the configuration unit shown in FIG. 13, one example of a multi-level memory over cells as a constituting unit of the second aspect of the invention, used in Example 5 of FIG.
The left half of the figure shows a 10-value multi-value storage means, which corresponds to the multi-value storage means according to claim 5, and is “from two MOSFETs and one resistor connected between the data line and the input / output terminal Tio. that bidirectional switching means (= multilevel transfer over gate means) "corresponds to the selection switching means in Description 5 claims.
Its 10 value storage means "below Numbered 0067], etc was 10 value storage means for connecting input and output terminals of the multi-level buffer over means and output terminal Tio shown in FIG. 1 7" is .

Embodiment 6 shown in FIG. 16 is an example of the multi-value storage circuit of the third invention or the fourth invention, and each of the multi-value decoding means 2 and 3 is simplified as “Embodiment 1 of the first invention of FIG. "Decimal system, 2-digit display type" is used.
Both Fx1 to Fx2 and Fy1 to Fy2 are two input lines to which two input signals corresponding to numerical values in decimal two-digit display are input.
The X selection lines X00 to X99 correspond to the same number of first selection signal transmission means as in claim 6 or 7, and the Y selection lines Y00 to Y99 correspond to the same number of second selection signal transmission means as described in claim 6 or 7. The data line DL corresponds to the data signal transmission means in the sixth or seventh aspect.
The 100 × each 100 square multi-valued memory over cells (= multilevel memory cell). Selection switching means for connecting between the input and output terminal Tio and the data line in the eighth example of the configuration unit of the ninth embodiment or "Figure 13 configuration means 14 to be described below to the respective multilevel memory over cell 1 (= Tenth example of the following constituent means) ”is used.

■■ Ninth example of composition means used in invention ■■
Ninth example of the configuration unit shown in FIG. 14, one example of a multi-level memory over cells as a constituting unit of the third aspect of the present invention, used in Example 6 in Figure 16.
The left half of the figure shows a 10-value multi-value storage means, which corresponds to the multi-value storage means in claim 6, “4 MOSFETs and 1 diode connected between the data line and the input / output terminal Tio”. and bidirectional switching means (= multilevel transfer over gate means) consisting of resistor one "corresponds to the selection switching means in claim 6.
The X selection signal corresponds to the first selection signal in claim 6, the Y selection signal corresponds to the second selection signal in claim 6, and its 10-value storage means “will be described later [paragraph number 0067] . a by connecting the input terminal and the output terminal of the multi-level buffer over means shown in FIG. 1 7 10 value storing means was equal to the input-output terminal Tio. "

■■ Tenth example of composition means used in the invention ■■
The multilevel memory over-cells "eighth example output terminal Tio to that adds one selected switching means for connecting between the data line in the configuration means 13" becomes a constituting unit of the fourth aspect of the present invention 1 As an example, it is used in Example 6 of FIG.
The two selection signals correspond to the first and second selection signals in claim 7.

■■ Multi-value buffer means based on the 10-value storage means described above
FIG. 17 shows “the multi-value buffer means that is the basis of the 10-value storage means described above [paragraph numbers 0063, 0065]” .
The connection body of nine sets of binary CMOS / NOT circuits at the left end of the figure corresponds to the input potential discrimination means, and is connected to each of the power supply lines V0 to V9 and the first output terminal Out1 one by one. Corresponds to “N pulling means performing pull -up or pull-down operation”.
However, the pull means between the power supply line V9 and the first output terminal Out1 is one PMOS, and the pull means between the power supply line V0 and the first output terminal Out1 is one NMOS. Each pulling means between one output terminal Out1 has one NMOS and PMOS series circuit.
In the case of a series circuit of NMOS and PMOS, pull-up or pull-down operation is performed when both MOSs are turned on at the same time, but neither pull-up nor pull-down is performed when only one of them is turned on. For example, when the potential of the input terminal In is the potential v7, the pulling means of the potential v7 is bi-directionally on and the output potential is also the potential v7, but in each pulling means of the potentials v1 to v6, the PMOS is on. The NMOS is off, and on the contrary, in each pulling means of potentials v8 to v9, the NMOS is on, while the PMOS is off. This is the same regardless of the output potential between v1 and v8. When the output potential is v0 or v9, the pulling means of both MOS series circuits operate in the same manner.
Note that the positions of the serial connection of both MOSs may be interchanged with each other with respect to each “pull means in which NMOS and PMOS are connected in series” as in the multi-value storage means shown in FIGS.

  Embodiment of the fifth invention. 15 is connected to each of the input lines F1 to F3 of the multi-value storage circuit of the fifth embodiment (second invention) at the output terminal Out, one by one at the output terminal Out. The multi-value information processing means of the fifth invention is provided. The multilevel synchronous latch of FIG. 18 corresponds to the multilevel synchronous latch means in the eighth aspect.

  Embodiment of the sixth invention. Each of the input lines Fx1 to Fx2 and Fy1 to Fy2 of the sixth embodiment (third or fourth invention) of the multi-value storage circuit of FIG. 16 has “multi-value synchronous latch of FIG. If the connection is made at Out, it becomes the multi-value information processing means of the sixth invention. The multilevel synchronous latch of FIG. 18 corresponds to the multilevel synchronous latch means in the ninth aspect.

■■ Eleventh example of component means used in the invention ■■
The eleventh example of the configuration means in FIG. 18 is an example of the multi-level synchronous latch means that constitutes the respective configuration means of the fifth and sixth inventions. Although it is a type, either one may be used.
Each of the “bidirectional switches in which a 4-terminal PMOS and NMOS are connected in parallel” includes two “three-terminal switches composed of two NMOSs, a diode and a resistor (reference: Japanese Patent Laid-Open No. 50-98763)” and “two power supply lines V1. "Controlled by a binary NOT circuit connected between V0 or between two power supply lines V0 and V (-1)".
Multilevel memory over that shown in Figure 19 is prepared two multilevel buffer over means shown in "Figure 1 7, collectively or both binary CMOS · NOT circuit 9 to one made common, one of the output terminals It is connected to the input terminal as a new input terminal In, and the other output terminal is used as it is as a new output terminal Out ”. Patent Document 9: Japanese Patent Application No. 2005-195524
As a result, the output signal can be prevented from affecting the input signal with a reduced number of parts and a simplified configuration. For example, the read signal current can be set larger than the write signal current.
Note that SSin in FIG. 18 is an input terminal for inputting various synchronization signals such as event input (eg, polling, interrupt, etc.) or event output, and various trigger signals (eg, clock signal, single pulse, etc.). is there.

■■■ Last supplementary explanation ■■■
★ a) For convenience of explanation, it is called an input terminal, an output terminal (corresponding to the entry means or the exit means in the claims) or an input / output terminal, but it does not actually exist as a terminal, it is simply a lead wire or electrode Or it is often a conductive plate. This is the same as what is called “base terminal of transistor, base electrode, base lead wire or simply base”, for example.
★ b) In each embodiment, instead of each diode, “bipolar transistor with its collector and base directly connected”, “junction FET with its drain and source directly connected”, “bipolar mode with its drain and gate directly connected” SIT or GTBT "," Normally-off type MOS FET with its gate, back gate and source connected "or" Back gate so that there is no conduction between its drain and back gate and between its source and back gate " It is possible to use one normally-off type MOS FET that maintains the potential and connects its drain and gate.
★ c) In each embodiment, the level of each power supply potential is reversed, and each controllable switching means is defined as “controllable switching means in a complementary relationship (eg, P-channel MOS • FET with respect to N-channel MOS • FET). "Embodiment having a symmetrical relationship with respect to voltage direction or voltage polarity with respect to the original embodiment" in which each component (eg, diode) having directionality or polarity is reversed one by one. It is also possible.
However, in that case, the function may be the same as the original or may be different.

★ d) The input contents [a0 to a7] described above (paragraph number 002 0 ) may not be arranged in order, and may be random (eg, [a3, a7, a4, a0, a6, a2, a5, a1). ])), But it is necessary to fix the random order. Eventually, the “combination output content corresponding to the combination input content” only needs to be output regardless of the storage cell group in the memory.
Of course, it is easier to handle the arrangement of a0 to a7 in order, and it is normal, but it may be possible not to arrange the arrangement in order for saving the storage capacity of the multilevel memory.
For example, when the input content 1 is limited to a range of 0 to 500, the input content 2 is limited to a range of 0 to 600, and the input content 3 is limited to a range of 0 to 50 in decimal notation, each input The highest contents a0, a3, and a6 may not be 10 values, but may be 6 values. In this case, "a0, a3, a6" and "a1, a2, a4, a5, a7" collectively respectively, combining the 3-digit 6 value memory and the 7-digit 10 value memory over the address line number is the same.

★ e) considered in the foregoing (paragraph number 0004) of the "O pattern storage type (abbreviated I / O pattern storage type) decimal or binary computer" and the like do not apply common sense von Neumann computer.
First, in terms of energy consumption, the former has an extremely small number of transistors that are turned on during the information processing operation. This is because the on-transistor is because the multi-level latch, is limited to a part and a specific multi-level memory over cells of the multi-level decoder. Therefore, energy consumption due to charge / discharge such as gate-source capacitance of MOS / FET is extremely small. For this reason, since each power supply voltage can be increased, the on / off threshold voltage of each MOS • FET can be increased to reduce the leakage current, and the energy consumption due to the leakage current can be extremely reduced. As a result, the amount of generated heat is reduced, which is advantageous in terms of cooling and three-dimensional IC.
Secondly, the relative processing speed of the I / O pattern storage type with respect to the Neumann type increases as the number of digits of information processing increases in terms of increasing the relative information processing speed. This is because the time required for information processing by an I / O pattern storage computer is only "latch time" and "time from access to reading", and the total time is almost constant regardless of the number of digits of information processing. Because it is considered. As a result, the greater the number of digits of information processing, the higher the relative processing speed for a normal Neumann computer that is not a quantum type. In addition, the I / O pattern storage type is completely free from information processing delay due to an increase in the number of lines of the source code of the program. Strong against time constraints (inter-input constraints, inter-output constraints, input-output constraints) and is advantageous for real-time processing.
● Non-Patent Document 9: “Nikkei Manufacturing March 2005 Issue” published by Nikkei BP on March 1, 2005. p. 121-p. 124 “Embedded soft ball hand box 03”. Writer: Kiichiro Tamaru. Reference: Event input and event output. Relationship between input, processing, and output.
Thirdly, in terms of the number of transistors, in the case of an I / O pattern storage type computer, it is certainly necessary to increase the storage capacity compared to a Neumann type computer. However, in the first place, since there is no need for a CPU or related IC, the amount of transistors used for them can be turned toward the storage capacity, so it is not known what the total number of transistors will ultimately be. However, it is easy to design with a monotonous IC pattern.

★ f) Three-dimensional IC technology and low voltage technology strongly assist the practical application of “Multi-ary logic circuit, Multi-ary arithmetic circuit, Multi-ary memory circuit, Multi-ary computer, etc.”.
If three-dimensional IC technology, low voltage drive and withstand voltage maintenance technology, energy saving technology, cooling technology, etc. will continue to advance in the future, 64 base, 100 base, 128 base logic circuits, arithmetic circuits, memory Circuits, computers, etc. will also be possible, and there may be 64, 100, 128, super, super, super, ultra, and super computers.
★ g) In the mathematical explanation regarding the number of types of multi-value information processing of the multi-value information processing described above (paragraph number 00 26 ), the 10-value 3-digit 2-input or 10-value 2-digit 3-input As a multi-valued information processing of the kind of "1 million-squared", it is "super-astronomical number". In practical terms, it can be said to be “infinite”, there is anything, and there is no information processing that cannot be done (???).
On the other hand, in the case of "future binary quantum computer", which is said to be very difficult to maintain quantum coherency, even if it says "the calculation speed is fast", "about 200 (?) Quanta The elements are only 10's to the power of 10's while maintaining quantum coherency with each other.
For this reason, "various diversity of multi-value information processing of super-astronomical numbers" and "computation speed of several tens of powers of 10" are not subject to direct comparison with each other. May be advantageous. Grounds and reason for the above (paragraph number 00 27 ).
★ h) Decimal system does not always have 10 values. In addition to the numbers “0” to “9”, there is an “output method of releasing the output”. In this case, the radix part is “11” instead of “10”. 2-input or 10-value 2-digit 3-input becomes "11-value 3-digit 2-input or 11-value 2-digit 3-input", and becomes multi-value information processing of the type "11 million / multiple".

It is a circuit block diagram which shows one example of the multi-value decoding means of 1st invention. Thru (or) Each figure is a view to circuit diagram One not a few of the configuration means used in the multi-level decoding means in the first invention. It is a circuit diagram showing one embodiment of the multi-value decoding means of the first invention. It is a circuit diagram showing one embodiment of the multi-value decoding means of the first invention. Thru (or) In both figures, it is a circuit diagram showing one embodiment of the multilevel decoding means of the first invention. Is a circuit diagram showing an example of a multi-level memory over cells used in the multi-value memory circuit of the second invention. Is a circuit diagram showing an example of a multi-level memory over cells used in the multi-level memory circuit of the third aspect of the present invention. It is a circuit diagram showing one embodiment of the multi-value storage circuit of the second invention. It is a circuit diagram which shows one Example of the multi-value memory circuit of 3rd or 4th invention. It is a circuit diagram which shows the multi-value buffer means used as the origin of the 10-value storage means. It is a circuit diagram showing an example of multi-value synchronous latch means used in the multi-value information processing means of the fifth or sixth invention. Is a circuit diagram showing an example of a multi-level memory over cells used in multilevel synchronous latching means of Figure 18.

Claims (9)

When a predetermined plurality of 3 or 3 is represented by N and the first predetermined natural number is represented by F,
“The potential increases in numerical order from the first potential to the Nth potential, and the numerical values increase or decrease in numerical order from the first numerical value to the Nth numerical value, one by one in numerical order. “First potential supply means to N potential supply means for supplying N potentials defined to correspond”;
“F input signals that are associated with numerical values in N-ary notation and F digits and divided for each digit”,
“Based on the positive threshold potential or the negative threshold potential based on each of the N potentials,“ the numerical values corresponding to the potentials of the F input signals ”is calculated from the first numerical value. The first numerical value from the first digit to the F-th digit that identifies whether the value is “applicable” to the numerical value up to the Nth numerical value for each digit, and outputs the identification result as an identification output signal one by one "Identification means to Nth numerical value identification means"
“For each of the numerical identification means, the identification output signal is converted into a signal based on a common reference potential, and the conversion result is used as a conversion output signal, and the conversion result signal is output one by one. Conversion means to Nth signal conversion means ",
““ Combination of F conversion output signals obtained by extracting and combining one of the N conversion output signals for each digit ”and combining them in different combinations (N to the power of F) To determine whether all of the F conversion output signals indicate “applicable” with reference to the reference potential, and output the determination result as a determination output signal one by one. Multi-value decoding means comprising “(Nth power of F) corresponding judgment means”. 2. The multi-value decoding means according to claim 1, wherein the first numerical value to the Nth numerical value are numerical values 0 to (N-1) in order. 3. The multi-level decoding unit according to claim 1, wherein each of the first corresponding determination unit to the (Nth power of F) corresponding determination unit is an AND circuit or a NAND circuit having an F input binary value. 4. The multi-value decoding means according to claim 1, wherein all of said first corresponding determination means to said (Nth power of F) corresponding determination means are absent, and only a predetermined number of them is present. When the second predetermined natural number is represented by G,
The multi-value decoding means according to claim 1, 2, 3 or 4 is used as a multi-value address decoder,
Treats the numerical value of the above-mentioned N-ary system and F digits as an address,
Providing the same number of selection signal transmission means for transmitting all the judgment output signals as the same number of selection signals;
“Data signal transmission means for transmitting data signals” and “selection switching means equal in number to the selection signals, all of which are connected to the data signal transmission means and are turned on one by one by each of the selection signals” G combination is provided,
Multi-value storage means having "the output means for storing the stored contents corresponding to one potential of the first potential to the Nth potential and outputting a read signal therefrom" at the other end of each of the selection switching means Are connected one by one at their output means. The multi-value decoding means according to claim 1, wherein F is represented by Fx, is used as the first multi-value address decoder,
The multi-value decoding means according to claim 1, wherein F is represented by Fy, is used as a second multi-value address decoder,
Treat the former N-ary, Fx digit display as an address,
The latter N-ary, Fy digit display numerical value is treated as an address,
Providing the same number of first selection signal transmission means for transmitting all of the judgment output signals of the former as the same number of first selection signals;
Providing the same number of second selection signal transmitting means for transmitting all of the latter judgment output signals as the same number of second selection signals;
Both ends are connected to the “data signal transmission means for transmitting data signals” and are turned on one by one by a combination of one first selection signal and one second selection signal. The same number of selection switching means as the product of the total number of the selection signals is provided,
Multi-value storage means having "the output means for storing the stored contents corresponding to one potential of the first potential to the Nth potential and outputting a read signal therefrom" at the other end of each of the selection switching means Are connected one by one at their output means. The multi-value decoding means according to claim 1, wherein F is represented by Fx, is used as the first multi-value address decoder,
The multi-value decoding means according to claim 1, wherein F is represented by Fy, is used as a second multi-value address decoder,
Treat the former N-ary, Fx digit display as an address,
The latter N-ary, Fy digit display numerical value is treated as an address,
Providing the same number of first selection signal transmission means for transmitting all of the judgment output signals of the former as the same number of first selection signals;
Providing the same number of second selection signal transmitting means for transmitting all of the latter judgment output signals as the same number of second selection signals;
The same number of combinations of “the same number of first selection switching means as the first selection signals that are turned on one by one by each of the first selection signals” and the second selection signals,
One end of all the first selection switching means is connected to a “data signal transmission means for transmitting a data signal”,
“Different second selection signal” is selected for each combination, and the other end of each of the first selection switching means of the set is “the first selection signal that is simultaneously turned on by the selected second selection signal; The same number of second selection switching means "are connected one by one at one end of the second selection switching means,
A multi-value having “output means for storing the stored contents corresponding to one potential of the first potential to the Nth potential and outputting a read signal therefrom” at the other end of each of the second selection switching means A multi-value storage circuit characterized in that "storage means" are connected one by one at the output means. The multi-value storage circuit according to claim 5, wherein
There are “F multi-level synchronous latch means corresponding one-to-one with the F input signals”, and each of the input signals is transferred to the multi-level via the “corresponding multi-level synchronous latch means”. Input to the value decoding means,
The input content indicated by one input information or “combination input information obtained by combining a plurality of input information” is made to correspond to the numerical value in the N-ary system and F-digit display,
For each of the input contents, “one output information corresponding to the input contents” or “multiple outputs” is assigned to the G multi-value storage means designated by the “corresponding N-ary number and the address indicated by the F-digit numerical value”. Multi-value information processing means for storing "output contents of combination output information combining information". When the second predetermined natural number is represented by G,
The multi-value storage circuit according to claim 6 or 7, wherein each of the input signals is the same as Fx and Fy,
“(Fx + Fy) multi-level synchronous latch means corresponding one-to-one with the (Fx + Fy) input signals”,
Each of the input signals is input to the multi-level decoding unit of the input signal via the “corresponding multi-level synchronous latch unit”,
One input information or the input content indicated by “combined input information combining a plurality of input information” is made to correspond to the numerical value of the N base, (Fx + Fy) digit display;
For each of the input contents, "one output information corresponding to the input contents or" plurality of the plurality of multi-value storage means G "designated by" the address indicated by the corresponding N-ary notation, (Fx + Fy) digit display ") Multi-value information processing means for storing “output contents of combined output information” combining the output information of

Images