JP6167258B2 - Multilevel logic circuit and multilevel hazard elimination circuit with synchronous latching function - Google Patents

Description

The first invention relates to a “multilevel logic circuit having a synchronous latching function” in which a multilevel logic circuit in a potential mode (or voltage mode) based on the following “Fuji algebra (= multilevel logic)” has a synchronous latching function. .
Rather than using multi-value synchronous latching means with "all-value latching function that can latch any numerical value used in multi-valued logic", the above-mentioned "synchronous latching function" Latching in units of “multi-valued logic circuit ” has the following effects and features.
1) Since a binary synchronous flip-flop means is built in, each trigger method (eg, edge trigger, level trigger, pulse trigger) can be used as it is.
★ Reference materials on “each trigger method”: 79-88 of Non-Patent Document 1 below.
● 2) “Output open or signal state corresponding to open output” can be latched.
* Note: The “Fuji algebra” below has a unique output method of “releasing output”.
● 3) There is no latching function for "signal state corresponding to each integer other than the output specific integer among all multi-values". That is, there is no extra / useless latching function.
→→ Since there are no useless parts and useless configurations, parts and circuits can be used efficiently and power consumption can be saved.
● 4) It is possible to increase the number of options of the latching location “where to latch in the entire circuit in which multiple multi-value circuits are connected”.
Conventionally, it has been considered to provide a multi-value synchronous latching means between a multi-value circuit and a multi-value circuit in the entire circuit . This is because the conventional “multi-valued logic circuit based on the Fuji algebra” does not have a synchronous latching function as described above.
The multi-value circuit includes, for example, a multi-value logic circuit, a multi-value arithmetic circuit (or multi-ary arithmetic circuit), a multi-value storage means, a multi-value memory means, and a multi-value digital circuit.
P. Of "Introduction to Illustrated Digital Circuit". 79-88 (binary pulse trigger method). Published 4th edition on April 25, 2008 by Nippon Riko Publishing Co., Ltd. Author: Tsuguo Nakamura.

● Because the flip-flop originally has only two states, the term “multi-value flip-flop” does not match, so the term “multi-value latching means” has been unified.
● Also, the multi-value logic circuit that constitutes each invention is a materialization and realization of “multi-value logic created by the inventor”. Since it is inconvenient if there is no name, we decided to name it “★ Houji Algebra” (paragraph numbers [0125 to 0127] described later in detail).
The reason for this was “Since the inventor is Japanese, it is related to the symbol of Japan, Mt. Fuji,” and “Bool” of Boolean Algebra. ”And“ the ability, possibility, practicality, expandability, future potential, etc., anyway, huge {= very large, tremendously large, huge.} Since the present inventor strongly judges that it is, the language is adjusted to the English huge. (Reference: The following patent documents 1-3)
JP 2004-032702 (Multi-valued logic circuit based on Fuji algebra) JP 2005-198226 (same as above) JP 2005-236985 (same as above)

● In addition, in the field of logic mathematics, “the concept of“ open output ”or“ open output (eg open collector, open drain) ””, which is well known as a basic technology in electronic circuits, It was not before "Fuji Algebra". However, with the advent of this “Fuji algebra,” the concept had to be adopted. This is because “Fuji algebra” has several “advantageous and unique effects” that are not found in conventional multi-valued logic. →→ Paragraph number [0126] described below.
On the other hand, in the field of electronic circuits, “all one or several types of basic / multi-valued logic circuits” or “a combination or combination thereof” can be used regardless of the multi-value number N (N of N values). `` Function that can realize and embody multi-valued logic functions '', that is, `` completeness '', it is also `` perfect '', and it is built independently without relying on the multivalued logic system published in the field of logical mathematics There was no multi-valued logic system / circuit before the above-mentioned Patent Documents 1-3. The “perfect” of the “★ Fuji algebra” is proved in paragraph numbers [0138 to 0148] described later.
★ Reference material on "complete system, completeness, completeness": Non-patent documents 2-4 below.
In the present invention, each integer of N value and each constant potential supply means (eg, power supply line, power supply plate, etc.) correspond to each other one by one in order, but as the integer increases, From the 1st constant potential to the Nth constant potential, these constant potentials correspond to the positive logic when they become higher, and the case where they become lower correspond to the negative logic.
"Introduction to Logic Circuits", authors: Ryuji Hamabe, published by Morikita Publishing Co., Ltd. on September 28, 2001. “Chapter 2 Logic Functions” → “2.1 Basic Logic Operations” → “2.1.4 Basic Logic Operations and Logic Symbols” → “(8) Complete System” (p.31 to p.32). "Multi-valued information processing-post-binary electronics-", authors: Tatsuo Higuchi, Michitaka Kameyama, Shokodo in June 1989. p. 16-p. 17. “Digital Digital Circuits Understandable”, p. 9 line 14 to p. "Complete system" on the first line of 10. Author: Keitaro Sekine, published by OHM Co., Ltd. on July 25, 1997.

The second invention relates to a multi-value hazard elimination circuit utilizing the “multi-value logic circuit having a synchronous latching function” of the first invention, regardless of the multi-value number N (= N of N values). It is possible to remove a multi-value hazard that has occurred before or during the input of the multi-value hazard removal circuit .
In the multi-value circuit (eg, multi-value logic circuit, multi-value arithmetic circuit (or multi-ary arithmetic circuit), multi-value storage means, multi-value memory means, multi-value digital circuit, etc.), “same as binary hazard” In addition to “multi-value hazards that occur due to various mechanisms”, there are three or more “logical values, logic levels and potentials (or voltages) that correspond one-to-one with each other”, so “multi-value specific hazards” Occur.

■■■ Background Art of the First Invention ■■■
As a conventional multi-value synchronous latching means, a level-trigger multi-value synchronous latch circuit is disclosed in Example 10 (paragraph 0035) of Japanese Patent Application Laid-Open No. 2006-345468, and Japanese Patent Application Laid-Open No. 2007-35233. FIG. 18 and FIG. 19 of this publication disclose a pulse-trigger type (= master / slave type) multilevel synchronous latching circuit .
However, “each multi-level synchronous latching circuit of the method corresponding to each of the binary flip-flop means of the positive edge trigger method and the negative edge trigger method” has not yet been realized and put into practical use. Naturally, the positive and negative edge trigger methods cannot be used.
If the synchronous multi-value circuit can be triggered at the rising edge or falling edge of the synchronization signal, the choices of trigger timing and trigger method are increased, which is very convenient. For example, if each of the edge trigger methods can be used, the stepwise multi-level synchronization signal (reference: the following, Patent Document 7 ) considered by the present inventor can be used more effectively. There are more trigger timing options in one cycle, which is very convenient.
Therefore, the conventional technique has a problem that “positive and negative edge trigger methods cannot be used”. (Issue 1)
Japanese Patent Laid-Open No. 2006-345468 (multi-level synchronization signal generating means, etc.). In the step-like multi-level synchronization signal waveform of FIG. 4, there are a plurality of rising or falling portions in one cycle. For example, one of the “plurality of rising or falling points” can be selected depending on which two power supply lines of the entire multi-level circuit are provided with one synchronous binary flip-flop means. it can. It is also possible to provide one synchronous binary flip-flop means at each of the plurality of locations.

  In addition, in the case of the multi-value logic circuit in the potential mode (or voltage mode) based on the “Fuji algebra” described above, there is an important output method of “output open or open output”. There is also a problem that the type latching means cannot latch the signal state corresponding to [output open or open output]. (Section 2)

Furthermore, there is a problem that “the latching function corresponding to [output numerical value] is not provided, and waste is generated”. (Third issue)
For example, both of the multi-level synchronous latching circuits have “all-number latching function used in multi-level logic and capable of latching any numerical value”. If the (input / output) numerical value is over all numerical values, the use efficiency of the latching function is good, but “If only a part of the numerical values (input / output) is output (= the numerical value to be latched is a part of it) In the case of limitation), the use efficiency of the latching function deteriorates both in terms of effective use of components and circuits and in terms of power use efficiency.
In other words, because “the latching function part corresponding to the numerical value that is not output” is not used, the circuit of the function part is wasted, and “when all the transistors etc. are switched on / off due to the rewriting of the latching contents” "Total switching loss" increases by the amount of "switching loss of the unused latching function portion that is not used".
In other words, the number of parts is increased by the “latching function part for the numerical value that is not output”, and the circuit configuration becomes complicated. Therefore, the effective utilization rate of the part / circuit deteriorates, and the extra latching function. Extra power is consumed by the switching loss of the part on / off switching.
Moreover, if all of the transistors are voltage-driven, such as MOS / FET or insulated gate type transistors, there is charge / discharge energy loss due to the capacitance between the gate and source, etc. More power is consumed by the amount of energy loss.
As a result, the latching function / usage efficiency deteriorates both in terms of effective use of the parts / circuits and in terms of power use efficiency. If the effective utilization rate of the parts / circuits is low, the occupied area of the multi-level synchronous latching circuit in the two-dimensional IC or two-dimensional LSI is naturally large if the three-dimensional IC or LSI is occupied. This increases costs.
As described above, the reason why the latching function / use efficiency is poor is that “there is an extra latching function for each numerical value other than the output numerical value”.
Therefore, there is a problem that “the latching function corresponding to [output numerical value] is not provided and waste occurs”. (Section 3)

Then, conventionally, a multi-value synchronous latching circuit must be provided between the multi-value circuit and the multi-value circuit in the entire circuit, and the latching location is fixed. If there are many choices of the latching location, the configuration of the entire circuit is flexible.
Therefore, it is desirable that there are many choices of the latching location “where to latch in the entire circuit”. (Section 4)

The multi-value circuit to be used includes, for example, a multi-value logic circuit, a multi-value arithmetic circuit (or multi-ary arithmetic circuit), a multi-value storage means, a multi-value memory means, a multi-value digital circuit, and the like.

■■■ Background Art of the Second Invention ■■■
First, "multi-valued logic levels", "each threshold potential (or each threshold voltage) at each logic level" and "continuity of potential (or voltage) change" will be described as preliminary knowledge.
■■ Multi-level logic levels ■■
In the case of a binary circuit (eg, binary logic circuit, binary arithmetic circuit, binary memory, binary storage means, binary digital system, etc.), for example, “0” and “1” are used as the two logical values. Therefore, the term “L level and H level” can be used to express each logic level regardless of positive logic or negative logic. In the positive logic, the L level substantially means “logical level of logical value 0”, and the H level means “logical level of logical value 1”, whereas in negative logic, the L level is substantially “logical value 1”. "Logic level" means H and "H level" means "logic level of logical value 0".
In the case of a ternary circuit, the three logical values include, for example, “0”, “1”, and “2”. The terms “level, H level” can be used.
Further, in the case of a quaternary circuit, the four logical values include, for example, “0”, “1”, “2”, “3”. The terms “L level, M0 level, M1 level, H level” can be used.
Similarly, in the case of a quinary circuit, the five logical values include, for example, “0”, “1”, “2”, “3”, “4”. For example, the terms “L level, M0 level, M1 level, M2 level, H level” can be used.
However, in the case of a “composite multi-value digital circuit in which a plurality of multi-value circuits having different multi-value numbers (= N of N values) are mixed” or “multi-value logic functions having different multi-value numbers” And the term “anomalous multi-value digital circuit that includes a plurality of logic variables” or “one or more logic variables thereof” (explained in paragraph number [0154] described later)). .
For example, the H level of the ternary circuit corresponds to the M1 level of the quaternary circuit, and the H level of the quaternary circuit corresponds to the M2 level of the quinary circuit.
If that is the case, then “the largest multi-value number N (= N of N values) to be used” is used as a reference for the entire circuit, and “logic level name and logic value” corresponding to each power line. Is fixed and unified to “the logical level name and logical value of the largest multi-level number N to be used”, for example, “logical level of logical value 2” corresponding to the power supply line V2 is abbreviated to “logical It is called “2 level”, and the abbreviated “L2 level” is somewhat clearer.
Therefore, in the case of a 10-value circuit, for example, “logic levels 0 to 9” that correspond one-to-one with “power supply line V0 to power supply line V9” are called “L0 level to L9 level”. Each “constant potential or constant voltage” corresponding to 1 to 1 increases from the L0 level toward the L9 level, increasing in the positive logic state and decreasing in the negative logic state.
For this reason, when configuring a binary circuit in the 10-value circuit, for example, the “required two power supply lines” are selected from the “power supply lines V0 to V9” and used. In the entire circuit of 10 values, not only the numerical values “0 and 1” but also numerical values “4 and 5”, numerical values “8 and 9”, numerical values “3 and 7”, numerical values “5 and This means selection of various combinations of numerical values such as “9” and numerical values “0 and 9” and the magnitude of the power supply voltage for the binary circuit.
However, since there are only L level and H level in the binary circuit after all, if only in the binary circuit, the L level can be considered as a numerical value 0 and the H level can be considered as a numerical value 1. The entire circuit including the 10-value circuit is considered as “L0 level to L9 level”.
In short, there is no confusion if you think about these things with purely electronic circuits. In consideration of the correspondence relationship, it becomes easy to be confused because elements such as “the difference in each multi-value number” and “which power line corresponds to the reference value 0” are included.
Hereinafter, the logical levels of the multi-valued numerical values will be referred to as “L0 level, L1 level, L2 level...” For the time being.
★★★ Name of each logical level corresponding to each logical value one-to-one (provisional)

“Introduction to Transistor Circuit Lecture 5: Digital Circuits”, p. 46-p. 47 “4.6 Notes on using logic circuits [1] Logic voltage level and noise margin”. Supervision: Yoshifumi Amemiya and Nori Koshiba. Authors: Kensuke Shimizu and Masahiro Masakazu. Issued on May 20, 1981 by Ohm Co., Ltd. “Digital Digital Circuits Understandable”, p. 76-p. 80 [[1] logic level to [2] noise margin]. Author: Keitaro Sekine, published by OHM Co., Ltd. on July 25, 1997. “Introduction to Logic Circuits”, p. 126-p. 128 “6.4 IC characteristics (1) Signal voltage value and noise margin”. Author: Ryuji Hamabe, published by Morikita Publishing Co., Ltd. on September 28, 2001. “Pulse Digital Circuit”, p. 125-p. 130 “5. Basic characteristics of circuit 5.1 Amplitude characteristics of pulse digital circuit ”. Author: Akira Kawamata. Published by Nikkan Kogyo Shimbun on February 15, 1995. “Pulse and digital circuit”, p. 128 “Threshold Level” and p. 129 “Logical Level”. Edit: Masao Yoneyama. Author: Shigeyuki Ohara, Sumio Yoshikawa, Toshio Shinozaki, Shiro Takahashi. Published by Tokai University Press on April 5, 2001. “Practical Introduction Series: How to Use CMOS Circuit [1]”, “Element Threshold Voltage” on page 44 and “Circuit Threshold Voltage” on page 50. Author: Yasoji Suzuki. Published on October 15, 1997 by the Industrial Research Committee.

■■ Numeric discrimination and each threshold potential (or each threshold voltage) ■■
A positive logic numerical discrimination method will be described. In a binary circuit, “L-level input voltage (or input potential)” is essentially a plus based on the power supply voltage zero (or power supply potential zero) determined in advance by international standards, international standard specifications, etc. Side threshold voltage (or positive side threshold potential) "and" H level input voltage (or input potential) "is substantially determined in advance by the international standard, international specification, etc. , Minus threshold voltage (or minus threshold voltage) based on plus power supply voltage + V (or plus power supply potential + V) ”.
In the binary circuit, what is usually called “threshold voltage (or threshold potential)” is, for example, in the case of CMOS “a boundary where the operating state of PMOS and NMOS is inverted”, that is, “circuit threshold voltage (or Threshold potential) ”. There is an on / off threshold voltage of the semiconductor element. These threshold values are uniquely determined by the magnitude of the power supply voltage and the characteristics of each semiconductor element. (Reference: Above / Non-Patent Document 8)
Therefore, the method for determining whether the multi-value input numerical value is “a numerical value defined as corresponding to the lowest logic level” is that the signal potential corresponding to the input numerical value is “a constant potential corresponding to the lowest logical level”. If the value is lower than the “predetermined positive side threshold potential”, the input value is determined to be “the value of the lowest logic level”.
However, since the multi-value “plus-side threshold potential” has not yet been determined in advance by international standards, international standard specifications, etc. (?), It is natural that the multi-value circuit. Each researcher / designer in the field will determine their own “plus-side threshold potential” in advance. If the “multi-value circuit in potential mode (or voltage mode)” will be used for general purposes in the future, the “positive side threshold potential” will be determined in advance according to international standards and specifications. Will be. This is also true for the following “each threshold potential”.
In addition, the method of determining whether a multi-value input value is a “number defined as corresponding to the highest logic level” is that the signal potential corresponding to the input value is “a constant potential corresponding to the highest logic level”. If it is higher than “a negative threshold potential determined in advance with reference to”, the input numerical value is determined to be “the numerical value of the highest logic level”.
Further, a method for determining whether a multi-valued input numerical value is “each numerical value defined to correspond one-to-one with each intermediate logical level other than the lowest and highest logical levels”. One of the potentials between “a positive threshold potential and a negative threshold potential” determined in advance with reference to each of the constant potentials corresponding to the one or more intermediate logic levels. , It is determined that the input numerical value is “the numerical value of the corresponding one intermediate logic level”.
Specifically, in the case of a 10-value circuit with numerical values 0 to 9, if positive logic, it is as follows.
* The L0 level region is a region lower than “the positive side threshold potential based on the first constant potential of the lowest potential (eg, power supply potential zero, etc.)”.
The regions of each level of L1 to L8 are regions between “plus side threshold potential and minus side threshold potential with reference to each of the second constant potential to the ninth constant potential” in order.
★ L9 level region is higher than “minus threshold potential with reference to 10th constant potential of maximum potential”.
In general, it is usually set as follows in “International Standards / International Standard Specifications”, etc., but there are exceptions that are not so (for example, when using bipolar transistors etc. like TTL, it becomes vertically asymmetric) .) Is also available. The negative threshold potentials of the L1 level to the L9 level are “constant potential of the logic level”, “constant potential of the logic level, and“ constant potential of the logic level one level lower than the constant potential of the logic level ”. Each of the positive side threshold potentials of the L0 level to L8 level is “a constant potential of a logic level one higher than the constant potential of the logic level” and its logic. One is set between “the middle potential of the constant potential of the level” and “the constant potential of the logic level”.

By the way, “threshold potential (or threshold voltage) when discriminating“… ”is a numerical value” ”and“ threshold potential when discriminating “not that numeric value” and “clearly” (Or threshold voltage) "is not the same and does not match. The reason for this is to eliminate a potential region (or a voltage region without any), since it is not necessary to have either a numerical value 0 or 1 at the time of digitization.
Although binary circuit is commonplace, if positive logic, "" Number 0 is ", the threshold voltage at the time of determination (or threshold voltage)" is L-level input potential (or input voltage) while becomes "" not a number 0 "and" clear "threshold potential (or threshold voltage) at the time of determination" is the threshold voltage at the time of determination as "" is a numerical value 1 "( Or threshold voltage) ”, that is, the same as the H level input potential (or input voltage), the two threshold potentials do not match.
For this reason, for example, in order to determine “clearly” that the input numerical value of the 10-value circuit is not the numerical value “0”, the input numerical value is determined to be any one of the numerical values “1 to 9”. Therefore, it must be determined that the signal potential of the input numerical value is always higher than the negative threshold potential of the L1 level.
In this case, “potential region without numerical value 1, 2”, “potential region without numerical value 2, 3”,..., “Potential region without numerical value 7, 8” and “numerical value 8”. , “None of the potential regions” is included in the “potential region for determining that it is any one of the numerical values“ 1 to 9 ””, but there is no problem at all. This is because any “potential region without any” is “a potential region that is not a numerical value 0”.
That is, although "the threshold voltage for the input number is to be numerical value" 0 "," clearly "determination" is the L0-level positive threshold potential, "the input value is the value" 0 The threshold potential for “clearly discriminating” is not “” is the negative threshold potential of the L1 level, and the two threshold potentials do not match.
Similarly, in order to determine “clearly” that the input value of the 10-value circuit is not the numerical value “9”, the input numerical value is determined to be any one of the numerical values “0 to 8”. Since it is necessary, it must be determined that the signal potential of the input numerical value is always lower than the positive threshold potential of the L8 level.
In other words, "the input numerical value and is a number" 9 "," clearly "threshold potential for the determination" is a L9 level of negative threshold potential, "the input value is the value" 9 The threshold potential for “clearly discriminating” that is not “” is the L8 level positive threshold potential, and the two threshold potentials do not match.
● Similarly, in order to determine “clearly” that the input value of the 10-value circuit is not the numerical value “1”, the input numerical value is any one of the numerical values “0, 2 to 9”. Since the signal potential of the input numerical value is always determined to be lower than the positive threshold potential of the L0 level or higher than the negative threshold potential of the L2 level. I have to do it.
In other words, "the input value" clearly and is a number "1", "threshold potential two for the determination" is L1 level plus, is a threshold potential of the negative sides, "the input “Two threshold potentials for“ clearly ”discrimination when the numerical value is not “ 1 ”” is “L0 level positive threshold potential” and “L2 level negative threshold potential”. Both “two threshold potentials” do not match.
In exactly the same way, both of the “threshold potentials” that are “clearly” determined for each of the numerical values “2 to 8” do not match.
→→→ “Two threshold potentials of ● a) to ● d) in claim 1”

■■ Continuity of potential (or voltage) change ■■
“Logical mathematics” has no concept of “continuity” or is not constrained by “continuity”, and there is no need to consider it at all, but its logical action (= logical thinking activity) is a physical action (= Example: electronic circuit operation etc.)), the replacement logical operation is always restricted by its physical properties. For example, a continuity of the capacitor voltage V _C (when the electrostatic capacitance C is constant.) And continuity of the coil current I _L (when the inductance L is constant.).
Both continuities are attributed to the “Energy Conservation Law” and “Energy conversion and movement takes time”. Energy or discontinuously generated and extinction by the energy saving law, because it will not be increased or decreased discontinuously, stored energy E _{C =} C-V C ^_2/2 by If C is a constant capacitor voltage V _C of the capacitor or also discontinuous generation and extinction, to never be increased or decreased discontinuously, the coil current I _L if L by magnetic energy (= exciting energy) E L _{= L} · I L ^_2/2 coils is constant Will not discontinuously occur or disappear, nor will it increase or decrease discontinuously.
Even if C is continuously (slightly) changed, since constant left-hand side of the stored energy type, also the capacitor voltage V _c only varies continuously (somewhat), the change is not a discontinuous. Since this is the same in the magnetic energy equation, even if L changes continuously (somewhat), the coil current _IL also changes only continuously (somewhat), and the change does not become discontinuous. This also applies to the case where the sum of the stored energy E _C and the magnetic energy E _L is constant.
Also, since there are always floating “capacitance, inductance, resistance” in the circuit and “internal capacitance, internal inductance, internal resistance” in each circuit component, “capacitor stored energy E _C ” and “ It takes time to convert the coil's magnetic energy E _L "to another energy or to move it to another location via the conductors and other circuit components in the circuit. For example, electromagnetic conversion due to resonance operation in the circuit, Joule heat generation due to resistance in the circuit, time delay due to each time constant, and the like. Therefore, it takes time to change both the coil current I _L capacitor voltage V _C. Neither changes at “time zero” or “discontinuously”.
This is why, with the exception of the following, the capacitor voltage V _C becomes always continuously when changing also the coil current I _L, it is not take a discontinuous discrete values.

However, when the primary side current of the transformer is interrupted by a flyback type power conversion circuit or a current interrupt type ignition circuit and the current starts to flow on the secondary side, in general, (inductance) ２ (2 turns) Since the change from the primary inductance value to the secondary inductance value becomes discontinuous unless the turns ratio is 1, the natural current conservation law naturally changes the primary current value to the secondary side. The change to the current value also becomes discontinuous.
If there are cases in addition to that positively discontinuously change the dielectric constant of permeability and capacitor C of the coil L is also the capacitor voltage V _C and the coil current I _L is also changed discontinuously. However, such circuit operations are not performed in a logic circuit or the like.

Of course, the (paragraph number [0014].) Because continuity of the capacitor voltage V _C is directly connected to the voltage continuity, such as the gate-source capacitance of the voltage-driven transistors such MOS-FET, its The “gate potential or gate voltage” or the like always changes continuously and does not take a discontinuous value.
→→ Digital circuit in potential mode (or voltage mode) (= 2-value to multi-value circuit)
On the other hand, lead in continuity and electronic circuitry of the coil current I _L, since directly linked to the continuity of the stray inductance current such as wiring, bipolar transistor or the like as long as the continuity of the current escape (the can) and are not The base current of the current driven transistor always changes continuously and does not take a discontinuous value.
→→ Digital circuit in current mode (= 2-value to multi-value circuit)
As a result, when the “logic level indicated by a certain multi-level signal” changes from “L0 level to L3 level”, for example, the logic level always passes “L1 level” and “L2 level” on the way.
If this is expressed in a logical numerical value, when the “logical numerical value indicated by the multi-level signal” changes from “0” to “3”, for example, the physical restriction described above, that is, “each continuity described above” indicates that The logical value always takes each value of “1” and “2” in the middle (passes these values).

■■■ Well, here is the main topic (background art of the second invention). In general, “hazard” is equivalent to false “ghost signal, ghost data, or ghost information” as “signal noise” in both conventional binary circuit and multi-value circuit, and transmits true “signal, data, or information” To make it difficult to understand where and where, or from where to where is the real “signal, data or information”. The “hazard” adversely affects other circuit operations (malfunctions, useless circuit operations, etc.).
In addition to these problems , the five problems of the conventional multilevel logic circuit are summarized as follows. Detailed description thereof will be described later.
However, since the following problems 1a to 1d can be solved by removing the multi-value hazard itself, it can be summarized as one problem that “it is desirable to be able to remove the multi-value hazard”.
◇ 1a ) In addition to the hazard problem that occurs in the same mechanism as the conventional binary hazard, there are three or more logical values and logic levels, so “when the logic level of a multilevel signal changes, A multi-level inherent circuit failure and a multi-level hazard that “transient hazards occur by passing through the logic level” are particularly significant issues. (No. 1a issue)
★ Reference: 13th to 10th lines from the back of the bottom of Non-Patent Document 9 below. Multi-valued inherent hazard.
◇ 1b) "Likewise, when the logic level of a multi-level signal is changed, the direction from reaching the logic level of the neighboring past the original of logic levels to go too shake in over over sheet Yutingu and undershoot over sheet Yutingu A multi-valued circuit failure and a multi-valued hazard such as “transient hazards are generated by returning to the power level” are particularly serious problems.
(Problem 1b )
1c ) In multi-level circuits, there is a problem that “multi-level hazards lead to amplification and increase of power loss”. (Problem 1c )
1d ) The larger the multi-value number, the greater the adverse effect of each of the first to third problems. Therefore, “the larger the multi-value logic circuit, the greater the adverse effect of the multi-value hazard”.
(Problem 1d )
◆ 1) Therefore, there is a problem that “it is desirable to be able to eliminate multi-value hazards”.
(Issue 1)
◆ 2) Even if a possible conventional multi-value hazard removal circuit is used, the effect of the multi-value hazard is unavoidable in the previous circuit part before removing the multi-value hazard. Want to be as small as possible.
Therefore, there is a problem that “if possible, I would like to narrow the range in the circuit affected by the generated multi-value hazard as much as possible”. (Section 2)
"High-tech classroom, multi-value logic circuit, IC density increases and binary and ternary do not go", published by Nikkei Sangyo Shimbun (Tokyo version) on November 22, 1985. Written by Ishizuka Yoshihiko.

■■ The 1 a, detailed description of the 1c problem ■■
From here, “Generation of multi-value specific hazard due to first factor” will be described as an easy-to-understand example. For example, when the multi-value number N = 4 and the input value of the first multi-value circuit changes from the minimum value “0” to the maximum value “3”, it always passes the intermediate values “1 and 2”. The output side of the circuit changes from “output numerical value corresponding to input numerical value 0” to “output numerical value corresponding to input numerical value 1” and “output numerical value corresponding to input numerical value 2” to “output numerical value corresponding to input numerical value 3”. Become. At this time, depending on the value of each output numerical value, a multi-value hazard occurs as follows.
If the “output numerical value corresponding to the input numerical values 1 and 3” is “3” and the “output numerical value corresponding to the input numerical values 0 and 2” is “0”, the input numerical value is changed from “0” to “ Since the output value changes unnecessarily three times as “0” → “3” → “0” → “3” while changing to “3” once, the number of changes on the input side is amplified by three times. The first extra pulse appears on the output side. (Occurrence →→ ● No. 1 a challenge of the first multi-level hazard)
And if the same thing happens in the second multi-value circuit in the subsequent stage that inputs the output numerical value, not only “while the input numerical value changes once from“ 0 ”to“ 3 ”” The same thing happens when the input numerical value changes once from “3” to “0”.
That is, while the input value changes once from “3” to “0” in the second multi-value circuit, the output value is “3” → “0” → “3” → “0”. Since the number of times of change changes, the number of changes on the input side is amplified by a factor of 3, and one second extra pulse appears on the output side. (Occurrence →→ ● No. 1 a challenge of the second multi-level hazard)
As a result, for each change of the input value of the second multi-value circuit, that is, three changes of “0 → 3”, “3 → 0” and “0 → 3”, the change of the input value for each time Since (every) the output side has a three-time value change and one extra pulse appearance, after all, the one-time change in the input numerical value of the first multi-value circuit is the second multi-value circuit. On the output side, there are nine numerical changes and three extra pulses. No, there are a total of four extra pulses. Actually, if you draw the 9 numerical changes on paper, you can see it.
In this way, if the same thing happens in the second multi-level circuit in the subsequent stage, the “number of wasteful changes” and the “number of extra pulses” are the number of connected stages of the multi-level circuit. The more you add, the more you add. As a result, the circuit operation becomes extremely complicated / abnormal as the circuit becomes a subsequent stage, and further adversely affects other circuit operations. It will no longer be useful for the end.
Examples of the adverse effects are “appearance of signal noise”, that is, “making it difficult to understand where and where or from where to where the true“ signal, data or information ””, “malfunction due to hazard noise”, For example, “useless circuit operation”.
(Amplifying and increasing the number of multi-value hazard occurrences,
Increased adverse effects →→ ● No. 1 a )
Moreover, even if one hazard pulse is generated, it will naturally be ignored if the hazard pulses in the multi-valued circuit are summed up because “the dust accumulates,” but in addition, “ “Amplification / Increase”, that is, “Amplification / Increase in the number of multi-value hazard occurrences within an almost fixed period (= High-frequency multi-value hazard / Pulse generation frequency)” -In the case of FET, it means that the power loss due to charging / discharging such as capacitance between gate and source is further amplified and increased.
(Further increase in power loss →→ ● Problem 1c )

■■ Detailed explanation of issues 1b and 1c ■■
Next, “Generation of multi-value specific hazard due to second factor” will be described as an easy-to-understand example. If the multi-value number N = 4 and the output numerical value of the first multi-value circuit changes from the minimum value “0” to the numerical value “2”, the input part of the second multi-value circuit in the subsequent stage “if positive logic over over Shi Yutingu, negative logic if the under-over sheet Yutingu "occurs. Meanwhile, when the output value is changed maximum value "3" to the numerical value "1" is diametrically "If positive logic under-over sheet Yutingu negative logic if over over sheet Yutingu" occurs.
Although these damped oscillations are the second cause of multi-value hazards, the output resistance of the first multi-value circuit is usually small, and the input impedance of the second multi-value circuit is capacitive (for example, MOS · FET . the gate-source capacitance), and the small-induced (example impedance of the signal line of the internal resistance between the circuit:. stray inductance) is relatively often a, over over sheet Yutingu and undershoot easy over Shi Yutingu occurs. In other words, if an attempt is made to transmit a signal from the preceding stage to the subsequent stage with high energy efficiency, these damping vibrations are likely to occur.
If too runout over over shea Yutingu or under-over sheet Yutingu of the input signal, to the input signal is directed from reaching the logic level of the neighboring past the "original of logic level should be headed" of its "original logic When returning to the “level”, a hazard pulse is transiently generated. Such a hazard pulse often occurs even in a ternary circuit.
(Generated →→ ● No. 1b problem of multi-level hazard by over-over sheet Yutingu etc.)

Here it will be briefly described how the over-over sheet Yutingu and undershoot over sheet Yutingu occurs. Consider the operation of a circuit in which a series resonant circuit is connected to both ends of a DC power source via a bidirectional switch. Stored energy in the series resonant circuit as an initial condition is zero, turning on its bidirectional switch as energy loss zero at the resonant operation, the voltage of the resonance capacitor voltage zero around the power source voltage V _E And 2V _E oscillate endlessly. If the direction of the power supply voltage is opposite, the voltage of the resonance capacitor oscillates between zero voltage and negative 2V _E around the power supply voltage minus V _E.
In short, if there is no energy loss in the resonance operation, the voltage of the resonance capacitor will easily reach twice the power supply voltage (= twice the power supply potential difference).
In a general digital circuit, for example, the resonance capacitor is the capacitance between the gate and source of a MOS / FET, and the resonance coil is a floating inductance of a signal line / wiring between the preceding circuit and the succeeding circuit. The output resistance of is relatively small.
Similarly, when the input signal potential changes from the lowest power supply potential to the intermediate power supply potential in the ternary circuit, the input signal potential easily reaches the maximum power supply potential if there is no power loss in the resonance operation. (over-over sheet Yutingu). Even when the input signal potential changes from the highest power supply potential to the intermediate power supply voltage, if there is no power loss in the resonant operation, the input signal potential would lightly reached its minimum supply voltage (under-over sheet Yutingu ).
However, since the resonance operation actually has power loss, the resonance operation becomes a damped oscillation, so that the input signal potential reaches only “before the maximum power supply potential” or “before the minimum power supply potential”. There are many cases where this is not possible. However, for example, if the ternary circuit of numerical values 0, 1, and 2 is positive logic, the threshold potential of the logical level of numerical value 2 is “a negative threshold potential based on the highest power supply potential”. is one, for the logic level threshold potential of the numeric 0 is "positive threshold potential relative to the its lowest power supply potential", the input signal potential is a number 2 by the over-over sheet Yutingu logic or reached level, it is often also a ternary circuit ends up reaching or logic level of numerical 0 by the under-over sheet Yutingu.
(Generated →→ ● No. 1b problem of multi-level hazard by over-over sheet Yutingu etc.)
For example, if this is a quaternary circuit of numerical values 0 to 3, the “potential difference corresponding to the numerical value 0 and the numerical value 2” is usually twice the “potential difference corresponding to the numerical value 2 and the numerical value 3”. and numerical 3 corresponding potential difference between "usually" numeric 3-numeric 4 to become a 3-fold potentiometrically "corresponding to the space between, the input signal potential during the numerical changed by very easily its over-over sheet Yutingu It is possible to pass the “logical level of the numerical value that should be headed” to reach the next logical level. Then, the over-over sheet Yutingu or The more the number of vibrations of the under over shea Yutingu becomes many times to reach the logic level of its neighbors, its occurrence hazard number of pulses increases.
(Generated →→ ● No. 1b problem of multi-level hazard by over-over sheet Yutingu etc.)
Moreover, even if one hazard pulse is generated, it will become a mountain if dust accumulates. If the hazard pulses in the multi-value circuit are summed up, it is naturally not negligible, but in addition, the number of generated hazard pulses increases. Means “increase in switching (power) loss during on / off switching” and “in the case of MOS / FET, increase in power loss due to charge / discharge of gate-source capacitance”. (Further increase in power loss →→ ● Problem 1c )

In the case of a binary circuit, since there are only two values, 0 and 1, that is, there are only two types of maximum power supply potential and minimum power supply potential, the input signal potential is “the highest power supply potential side and the lowest power supply potential side” it can be absorbed over over sheet Yutingu and undershoot over sheet Yutingu of the input unit by one by one diode clamp in one direction in each above such over-over sheet Yutingu and undershoot over sheet Yutingu problem There is no.
However, in the case of a multi-value circuit, since there is at least one intermediate power supply potential, the technique of “clamping the input signal potential to the intermediate power supply potential” cannot be used. This is because if the input signal potential of the subsequent circuit is diode-clamped in one direction even to one of its intermediate power supply potentials, the output circuit of the preceding circuit will have a voltage other than the intermediate power supply potential so that the forward voltage of the diode is obtained. This is because when the power supply potential is output, the output section and the clamp diode cause a power supply short circuit.

■■ Detailed explanation of the 1d issue ■■
First, the larger the multi-value number, the more “the number of logic levels that are in the middle of passing when the logic level of the multi-value signal changes”, and the greater the number of multi-value hazards. As the number of stages of the multi-value circuit is increased, the amplifying / increasing action of the number of occurrences becomes stronger, so that the adverse effects of the first 1a and 1c problems also increase.
***
Secondly, the larger the multi-value number, the greater the change in the potential difference corresponding to the change in the numerical value, such as “change from a small numerical value to a large numerical value, or change from a large numerical value to a small numerical value. becomes, so that if the amplitude of the over-over sheet Yutingu and undershoot over sheet Yutingu increases "increases, rather than the logic level of the next by too the deflection should originally having directed from further reaching the logic level of the next adjacent its Returning to the logic level will cause “more transient hazards”.
In addition, since the adjacent logic level is often on both the high-potential side and the low-potential side of the logic level to which it is to go, further “more transient hazards” often occur. Therefore, the adverse effects of the 1b and 1c tasks are also increased.
Of course, "the over-over sheet Yutingu or undershoot over sheet Yutingu, number of vibrations until convergence" The more, the more even number of times reaches the logic level like its neighboring, increases the number of generated hazard pulses. The adverse effect spreads depending on the number of connection stages of the multi-value circuit.
***
Therefore, in terms of both the “magnitude and number of vibrations”, “the larger the multi-value number, the greater the problems and adverse effects of multi-value hazards”. (● 1d task)

■■ Detailed explanation of the second issue ■■
Then, another multilevel hazard removal method is disclosed in the above-mentioned “Example 10 (paragraph number 0035) of Japanese Patent Laid-Open No. 2006-345468 or FIGS. 18 and 19 in Japanese Patent Laid-Open No. 2007-35233”. One conventional multi-level synchronous latching circuit is provided between each of “multi-level logic circuit based on“ new multi-value logic [Fuji algebra] ”connected in multiple stages before and after” one by one and removed in the same manner. However, in addition to the “problem to be solved by the first invention” which will be described later (paragraph number [0026]), “I want to narrow the range in the circuit affected by the multi-value hazard that has occurred. There is a problem.
First, since the source that generates the multi-valued hazard (explained in paragraphs [0018 to 0021]) is the numerical value determining means of the multi-value logic circuit, the multi-value hazard generated by the numerical value determining means. The value hazard is transmitted to the output switch section through the on / off driving means in the circuit and the subsequent stage, and the propagation is blocked by the multi-level synchronous latching circuit outside and subsequent to the circuit .
If the numerical value judging means starts to generate the multi-value hazard, it is a time when the output of the multi-value synchronous latching circuit outside the circuit and in the previous stage changes.
Therefore, the multi-level logic circuit and the middle stage between the multi-level logic type latching circuits in the first stage and the latter stage of the multi-level logic circuit, that is, the multi-level logic circuit and the middle (the tenth) show the influence of the multi-level hazard. However, it will be received as described above (the previous paragraph). This applies to all of the “multi-value logic circuits sandwiched between two multi-value synchronous latching circuits connected to the preceding and succeeding stages”.
For this reason, there is a problem that “if possible, I would like to narrow the range in the circuit affected by the generated multi-value hazard as much as possible”. (● Second issue)

Japanese Patent Application Laid-Open No. 2004-032702 (Multi-valued logic circuit based on new multi-valued logic “Fuji algebra”, ◆ deemed withdrawal) →→ Reference: paragraph number [0125] described later. JP 2005-198226 (Multi-valued logic circuit based on new multi-valued logic “Fuji algebra”) →→ ● Patent No. 4900758 and ◎ The following is divided into Patent Literature 9 below. Japanese Patent Laying-Open No. 2005-236985 (multi-value logic circuit based on new multi-value logic “Fuji algebra”) →→ Patent No. 4643297 JP-A-2006-190239 ("Information processing means having an illegal intrusion operation prevention function" applying multi-valued logic, ◆ Self withdrawal) →→ JP-A-2006-228388 →→ Patent No. 4800642 (multi-value storage means and multi-stable circuit). In addition, Japanese Patent Application Laid-Open No. 2005-116168 of the same invention as the prior application is withdrawn spontaneously. JP-A-2006-252742 →→ ● Patent No. 4800657 (multi-value storage means and multi-stable circuit) Japanese Patent Laid-Open No. 2006-345468-> Patent No. 4643376 (multi-value storage means, multi-value transfer gate means, multi-value synchronous latch means and multi-value synchronization signal generating means). Japanese Patent Laid-Open No. 2007-035233 →→ Patent No. 4,800,706 (multi-value decoding means, multi-value storage circuit, and multi-value information processing means) Japanese Patent Application Laid-Open No. 2011-097637 (multi-value logic circuit, under examination), divisional application of the above and Patent Document 2. Japanese Patent Application Laid-Open No. 2011-103124 (“Information Processing Means with Function of Preventing Unauthorized Intrusion Operation” Applying Multi-valued Logic, ◆ Spontaneous withdrawal), the above-mentioned patent application 4 divisional application. Japanese Patent Application Laid-Open No. 2011-172254 (bi-directional switching means for multi-value, ◆ under examination), divisional application of the above and Patent Document 6. Furthermore, it is divided into the following and patent document 15. Japanese Patent Application Laid-Open No. 2011-204349 (multi-state buffer means, multi-value multiplexer means and multi-value demultiplexer means, voluntary withdrawal), above-mentioned divisional application of Patent Document 8. JP2011-229069 (Multi-value hazard elimination circuit, ◆ Deemed withdrawal) JP 2012-034345 (Multi-value hazard removal circuit. Released on February 16, 2012) Japanese Patent Laid-Open No. 2012-069236 →→ Patent No. 5139568 (multi-value buffer means), divisional application of the above-mentioned Patent Document 11. Japanese Patent Application Laid-Open No. 2012-075084 (multi-value logic means having a synchronous latching function, etc., the same invention published on April 12, 2012)

P. Of "Introduction to Illustrated Digital Circuit". 79-88 (binary pulse trigger method). Published 4th edition on April 25, 2008 by Nippon Riko Publishing Co., Ltd. Author: Tsuguo Nakamura. “Introduction to Logic Circuits”, p. 126-p. 128 “6.4 IC characteristics (1) Signal voltage value and noise margin”. Author: Ryuji Hamabe, published by Morikita Publishing Co., Ltd. on September 28, 2001. "Multi-valued information processing-post-binary electronics-", authors: Tatsuo Higuchi, Michitaka Kameyama, Shokodo in June 1989. “Digital Digital Circuits Understandable”, p. 76-p. 80 [[1] logic level to [2] noise margin]. Author: Keitaro Sekine, published by OHM Co., Ltd. on July 25, 1997. “Introduction to Transistor Circuit Lecture 5: Digital Circuits”, p. 46-p. 47 “4.6 Notes on using logic circuits [1] Logic voltage level and noise margin”. Supervision: Yoshifumi Amemiya and Nori Koshiba. Authors: Kensuke Shimizu and Masahiro Masakazu. Issued on May 20, 1981 by Ohm Co., Ltd. “Pulse Digital Circuit”, p. 125-p. 130 “5. Basic characteristics of circuit 5.1 Amplitude characteristics of pulse digital circuit ”. Author: Akira Kawamata. Published by Nikkan Kogyo Shimbun on February 15, 1995. “Pulse and digital circuit”, p. 128 “Threshold Level” and p. 129 “Logical Level”. Edit: Masao Yoneyama. Author: Shigeyuki Ohara, Sumio Yoshikawa, Toshio Shinozaki, Shiro Takahashi. Published by Tokai University Press on April 5, 2001. “Practical Introduction Series: How to Use CMOS Circuit [1]”, “Element Threshold Voltage” on page 44 and “Circuit Threshold Voltage” on page 50. Author: Yasoji Suzuki. Published on October 15, 1997 by the Industrial Research Committee. "High-tech classroom, multi-value logic circuit, IC density increases and binary and ternary do not go", published by Nikkei Sangyo Shimbun (Tokyo version) on November 22, 1985. Written by Ishizuka Yoshihiko. Mathematical Sciences February Issue (1980, No.200) Special Issue Multivalued Logic, published by Science Co., Ltd. on February 1, 1980. “Attic Resource Room Multi-valued Logic” on pages 374-375 of “Transistor Technology September 1997”. Published on September 1, 1997 by CQ Publishing Co., Ltd. Author: Hidekazu Inoue.

■■■ Problems to be solved by the first invention ■■■
For that reason (paragraph numbers 0005 to 0009), the conventional multilevel synchronous latching circuit has the following four problems.
◆ 1) Positive and negative edge trigger methods cannot be used.
→→ For example, if each edge trigger method can be used, in particular, the stepwise multilevel synchronization signal considered by the present inventor (the waveform of FIG. 4 of Patent Document 7; a plurality of rising portions, falling portions, or horizontal portions thereof) Can be used more effectively, which increases the number of trigger timing options during one synchronization period.
◆ 2) “Output open or signal status corresponding to open output” cannot be latched.
* Note: The "Fuji algebra" mentioned above has a unique output method of "releasing output".
◆ 3) It does not have a latching function according to the “output numerical value”, resulting in waste.
→→ When only a part of the all-number latching function is used, waste is generated both in terms of effective use of the parts / circuits and power loss.

◆ 4) choice of latching positions "plurality of where to latching of the overall circuit connected multilevel circuit" is often desired.
→→ Conventionally, a multi-value synchronous latching circuit must be provided between the multi-value circuit and the multi-value circuit in the entire circuit, and the latching location is fixed. If the choice of the latching portion is large, flexibility is generated in the configuration of the overall circuit.
The multi-value circuit to be used includes, for example, a multi-value logic circuit, a multi-value arithmetic circuit (or multi-ary arithmetic circuit), a multi-value memory circuit, a multi-value digital circuit, and the like.
Japanese Patent Laid-Open No. 2006-345468 (multi-level synchronization signal generating means, etc.). In the step-like multi-level synchronization signal waveform of FIG. 4, there are a plurality of rising or falling portions in one cycle. For example, one of the “plurality of rising or falling points” can be selected depending on which two power supply lines of the entire multi-level circuit are provided with one synchronous binary flip-flop means. it can. It is also possible to provide one synchronous binary flip-flop means at each of the plurality of locations.

■■ Purpose of the first invention ■■
Accordingly, the first invention aims to provide a “multilevel logic circuit having a synchronous latching function” having the following four effects.
◆ 1) Each trigger method (eg, edge trigger, level trigger, pulse trigger) of binary synchronous flip-flop means can be used.
(First effect)
◆ 2) “Output open or signal state corresponding to open output” can be latched.
(Second effect)
◆ 3) Since there is no latching function for “Each numerical value other than the output numerical value (= specific integer for output)”, a latching function corresponding to the “output numerical value” is provided, and no waste occurs.
(Third effect)
→→ Since there are no useless parts and useless configurations, parts and circuits can be used efficiently and power consumption can be saved.

◆ 4 ) The number of options for the latching location “where to latch in the entire circuit” increases and becomes convenient. Flexibility occurs in the configuration of the entire circuit. ( 4th effect)
→→ Since the multi-value logic circuit of the first invention itself has a synchronous latching function, it is not necessary to provide a multi-value synchronous latching circuit between the multi-value circuit and the multi-value circuit in the entire circuit. Is added.
The multi-value circuit to be used includes, for example, a multi-value logic circuit, a multi-value arithmetic circuit (or multi-ary arithmetic circuit), a multi-value memory circuit, a multi-value digital circuit, and the like.
In addition, in the case of each multi-value logic circuit based on the “Fuji algebra”, the “numerical value” latched by the constant potential supply means (eg, power line, power plate, etc.) connected to this circuit can be easily changed. The circuit to be used can be selected from the various multi-value logic circuits. Since the first invention is “because each multi-level logic circuit has a synchronous latching function”, the options for the multi-level synchronous latching circuit increase after all.
Further, for example, each of the various multi-value logic circuits is referred to as “(multi-value) AND circuit, (multi-value) OR circuit, OVER circuit, EVEN circuit, UNDER circuit, IN circuit, OUT circuit, etc.” There is a circuit.

■■■ Problems to be solved by the second invention ■■■
As described above (paragraph numbers [0017 to 0023]), “hazard” generally becomes a “ghost signal, ghost data or ghost information” as “signal noise” in both conventional binary circuits and multi-value circuits. Correspondingly, it prevents the transmission of the real “signal, data or information” and “where” and “where” or “where” to “where” is the real “signal, data or information”. Make it difficult to understand. The “hazard” adversely affects other circuit operations (malfunctions, useless circuit operations, etc.).
In addition to these problems , the five problems of the conventional multilevel logic circuit are summarized as follows. However, since the following problems 1a to 1d can be solved by removing the multi-value hazard itself, it can be summarized as one problem that “it is desirable to be able to remove the multi-value hazard”.
◇ 1a ) In addition to the hazard problem that occurs in the same mechanism as the conventional binary hazard, there are three or more logical values and logic levels, so “when the logic level of a multilevel signal changes, A multi-level inherent circuit failure and a multi-level hazard that “transient hazards occur by passing through the logic level” are particularly significant issues. (No. 1a issue)
★ Reference: 13th to 10th lines from the back of the bottom of Non-Patent Document 9 below. Multi-valued inherent hazard.
◇ 1b) "Likewise, when the logic level of a multi-level signal is changed, the direction from reaching the logic level of the neighboring past the original of logic levels to go too shake in over over sheet Yutingu and undershoot over sheet Yutingu A multi-valued circuit failure and a multi-valued hazard such as “transient hazards are generated by returning to the power level” are particularly serious problems.
(Problem 1b )
1c ) In multi-level circuits, there is a problem that “multi-level hazards lead to amplification and increase of power loss”. (Problem 1c )
1d ) The larger the multi-value number, the greater the adverse effect of each of the first to third problems. Therefore, “the larger the multi-value logic circuit, the greater the adverse effect of the multi-value hazard”.
(Problem 1d )
◆ 1) Therefore, there is a problem that “the multi-value hazard is desired to be removed” by combining the above problems 1a to 1d into one. (Issue 1)
◆ 2 ) Even if a possible conventional multi-value hazard removal circuit is used, the effect of the multi-value hazard is unavoidable in the previous stage of the circuit before removing the multi-value hazard. Want to be as small as possible.
Therefore, there is a problem that “if possible, I would like to narrow the range in the circuit affected by the generated multi-value hazard as much as possible”. (Section 2 )
"High-tech classroom, multi-value logic circuit, IC density increases and binary and ternary do not go", published by Nikkei Sangyo Shimbun (Tokyo version) on November 22, 1985. Written by Ishizuka Yoshihiko.

■■ Purpose of the second invention ■■
Therefore, the second invention is that “in addition to multi-value hazards generated by the same mechanism as binary hazards, multi-value hazards inherent to multi-values can be removed” The purpose of the present invention is to provide a multi-value hazard elimination circuit that can narrow the range in the circuit that receives the signal as much as possible.

■■■ “Means for solving the problems” of the first invention ■■■
That is, the first invention is
When a predetermined plural number of 3 or 3 is represented by N and a predetermined natural number is represented by S,
“N constant potentials that increase or decrease in numerical order from the first constant potential to the Nth constant potential” are supplied, and each constant potential and 0 to (N -1), the first constant potential supply means to the Nth constant potential supply means defined as one-to-one correspondence with the first constant potential in order from the integer 0, "
“First to Sth Inlet Means for Incoming S Input Potential Signals”,
“Exit means for exiting output potential signal”;
“When connected between the“ first constant potential supply means to one predetermined constant potential supply means for output among the first constant potential supply means to the Nth constant potential supply means ”and the outlet means, "Pull switching means that is turned off in one or both directions";
“ The S input potential signals are supplied from the first to S-th inlet means, “ when S = 1, an input integer corresponding to one of the input potential signals, and when S ≧ 2, [S All of the S input integers corresponding one-to-one with each of the input potential signals] or [at least one of the S input integers corresponding one-to-one with each of the S input potential signals. ]] [[Is equal to or not equal to one input specific integer predetermined in integer 0 to (N-1)], [predetermined in integer 0 to (N-2) Or larger than one input specific integer], [whether smaller than one predetermined input integer in integers 1 to (N−1)], [integer 0 to ( N-1), the difference determined in advance is at least 2. 2 or 4 threshold potentials (in paragraph numbers [0031 to 0032] below) applied to “any one of the two specified input integers or not” ”Based on the numerical value determination means for determining whether the determination is positive or negative, and outputting the determination result as a determination result signal”,
"Since" is directly or matching a hold signal the determination result signal based on the synchronizing signal supplied from outside "type, binary outputs a" positive output signal or the complement output signal "corresponding to the holding signal Synchronous flip-flop means "

“The pull switching means is driven on and off based on“ the positive output signal or the complementary output signal ”, but“ the determination result at the time of input indicated by the output signal based on that is positive. If it is negative, drive it off, or if it is negative, drive it off ”or“ If it is affirmative, drive it off, and if it is negative, drive it on ”on / off drive means”,
Is a multi-value logic circuit having a synchronous latching function.
However, the meaning of “less than one input specific integer” does not include the one input specific integer, and the meaning of “greater than one input specific integer” means that one input. The specific integer for use is not included, and the meaning of “between two input specific integers” does not include the two input specific integers.

■■ Two or four threshold potentials ■■
(1) When these constant potentials increase in numerical order from the first constant potential to the Nth constant potential,
● a) “Equal or not”:
* In the case of “equal to”, “a positive threshold potential and a negative threshold potential determined in advance with reference to an input specific constant potential corresponding to the input specific integer”. However, when the specific integer for input is 0, only the positive threshold potential is obtained, and when the specific integer for input is (N-1), only the negative threshold potential is obtained.
* In the case of “not so”, “a negative threshold potential determined in advance with reference to a constant potential one of the first constant potential to the Nth constant potential that is one higher than the specific constant potential for input” “A positive threshold potential determined in advance with reference to a constant potential one lower than the specific constant potential for input among the first constant potential to the Nth constant potential”. However, when the specific integer for input is 0, only the negative threshold potential is obtained, and when the specific integer for input is (N-1), only the positive threshold potential is obtained.
● b) If “Large or not”:
* In the case of “larger”, “the predetermined constant of the first constant potential to the Nth constant potential is determined in advance with reference to a constant potential that is one higher than the“ specific constant potential for input corresponding to the specific integer for input ”. Negative threshold potential ”.
* In the case of “not so”, “a positive threshold potential determined in advance on the basis of the specific constant potential for input”.
● c) “Small or not”:
* “It is small” is “predetermined on the basis of a constant potential one lower than the“ specific constant potential for input corresponding to the specific integer for input ”among the first constant potential to the Nth constant potential”. “Positive side threshold potential”.
* "If not" is "a negative threshold potential determined in advance with reference to the input specific constant potential".
D) In the case of “whether or not between two specific integers for input”:
* “Is it between the two?” Means that “of the first constant potential to the Nth constant potential, the lower constant of the two input specific constant potentials corresponding to the two input specific integers. Among the first constant potential to the Nth constant potential, “of the two input specific constant potentials”. “Higher constant potential” is a positive threshold potential determined in advance based on a constant potential one level lower than “the higher constant potential”.
* In the case of “not”, “the positive threshold potential determined in advance with respect to the lower constant potential of the two input specific constant potentials” and “the two specific input constant potentials” The negative threshold potential determined in advance based on the higher constant potential.

(2) When these constant potentials decrease in numerical order from the first constant potential to the Nth constant potential,
● a) “Equal or not”:
* In the case of “equal to”, “a positive threshold potential and a negative threshold potential determined in advance with reference to an input specific constant potential corresponding to the input specific integer”. However, when the specific integer for input is 0, only the negative threshold potential is obtained, and when the specific integer for input is (N-1), only the positive threshold potential is obtained.
* In the case of “not so”, “a negative threshold potential determined in advance with reference to a constant potential one of the first constant potential to the Nth constant potential that is one higher than the specific constant potential for input” “A positive threshold potential determined in advance with reference to a constant potential one lower than the specific constant potential for input among the first constant potential to the Nth constant potential”. However, when the specific integer for input is 0, only the positive threshold potential is obtained, and when the specific integer for input is (N-1), only the negative threshold potential is obtained.
● b) If “Large or not”:
* In the case of “larger”, “it is determined in advance from the first constant potential to the Nth constant potential based on a constant potential that is one lower than the“ input specific constant potential corresponding to the input specific integer ”. Plus threshold potential.
* "If not" is "a negative threshold potential determined in advance with reference to the input specific constant potential".
● c) “Small or not”:
* In the case of “smaller”, “it is determined in advance from the first constant potential to the Nth constant potential, based on a constant potential one level higher than“ the specific constant potential for input corresponding to the specific integer for input ”. Negative threshold potential ”.
* In the case of “not so”, “a positive threshold potential determined in advance on the basis of the specific constant potential for input”.
D) In the case of “whether or not between two specific integers for input”:
* “Is it between the two?” Means that “of the first constant potential to the Nth constant potential, the lower constant of the two input specific constant potentials corresponding to the two input specific integers. Among the first constant potential to the Nth constant potential, “of the two input specific constant potentials”. “Higher constant potential” is a positive threshold potential determined in advance based on a constant potential one level lower than “the higher constant potential”.
* In the case of “not”, “the positive threshold potential determined in advance with respect to the lower constant potential of the two input specific constant potentials” and “the two specific input constant potentials” The negative threshold potential determined in advance based on the higher constant potential.

This allows the "means for solving the problem" in the first invention and the like Komu viewing set the binary synchronous flip-flop means in "multi-valued logic circuit based on the" Fuji Algebra "," the conventional " A multi-value logic circuit having a synchronous latching function ”.
The conventional multi-value logic circuit includes the “first constant potential supply means to Nth constant potential supply means”, the “first inlet means to Sth inlet means”, the “exit means”, the “pull Switching means "," numerical value discrimination means "and" on / off drive means ". In this conventional multi-value logic circuit, the on / off drive means is the pull switching means based on the discrimination result signal. Is driven on and off.
The can be incorporated binary circuit in the multi-level circuit in this manner, later (● paragraphs [0039 to 0040].) As "the multi-level signal transmission way (eg the said numerical identifying means on Even if a binary circuit is inserted and connected in the off-drive means), the connectivity between this binary circuit and the preceding stage and the subsequent stage is extremely good, and [between the preceding stage and the binary circuit] [ "There is no need for a special interface (eg binary / multi-value code conversion means, multi-value / binary code conversion means) between the binary circuit and the latter stage" ). This is because it is in a “multi-value logic circuit”.
However, there are cases where both can be connected as they are, but there are also cases where they are connected by matching. (⇒ Matching between binary signals.)
Also, the end of the later (paragraph number [0045] ◇ 1). In some cases, the binary synchronous flip-flop means also serves as the on / off driving means.
Further, “determining whether or not the S input integers (= S integers corresponding to each of the S input potential signals on a one-to-one basis) is equal to or not equal to the one input specific integer. Is the same as “determining whether or not the S input integers are between“ two integers on both sides of the one input specific integer ”” and “the S input integers” "Determining whether the input integer of is equal to or not equal to 0" is the same as "determining whether the S input integers are less than or not 1" and " “Determining whether an input integer is equal to or not equal to (N−1)” is the same as “determining whether the S input integers are greater than (N−2)” or not. Numerous discrimination is difficult, and these discriminations are redundant. There.

As a result, since the binary synchronous flip-flop means can be built in between the numerical value discriminating means and the on / off driving means, each binary trigger method (eg, plus, minus edge)・ Triggers, level triggers, and pulse triggers can be used as they are. (First effect)
In particular, the step-like multi-level synchronization signal (the waveform of FIG. 4 of Patent Document 7 considered by the present inventor. There are a plurality of rising portions, falling portions, or horizontal portions) can be used more effectively. Since this is possible, the trigger timing options increase during one period of the synchronization signal, which is very convenient.
This is because, depending on which of the two constant potential supply means (for example, two power supply lines) the binary synchronous flip-flop means is connected, a plurality of “rising points or falling points or horizontal portions” are used. This is because one can be selected.
If the binary synchronous flip-flop means satisfies the requirements of the on / off drive means, such as the output current capacity of the binary synchronous flip-flop means is large, the binary synchronous flip-flop Of course, the flop means may also serve as the on / off driving means.
In addition, the binary synchronous flip-flop means only latches either “signal state corresponding to a specific integer for output of the multi-value logic means” or “signal state corresponding to output open or open output”. Of course, the "signal state corresponding to the output open or open output" can be latched. (Second effect)
◆ Furthermore, since there is no latching function for “each numerical value other than the output numerical value (= specific integer for output)”, a latching function corresponding to “output numerical value” is provided, so that no waste occurs. (Third effect)
→→ Since there are no useless parts and useless configurations, parts and circuits can be used efficiently and power consumption can be saved.

Then, choices of "a plurality of where to latching of the overall circuit was connected to the multi-level circuit" that the latching place is convenient increasing. Flexibility occurs in the circuit configuration of the entirety.
( 4th effect)
→→ Since the multi-value logic circuit of the first invention itself has a synchronous latching function, it is not necessary to provide a multi-value synchronous latching circuit between the multi-value circuit and the multi-value circuit in the entire circuit. Is added.
The multi-value circuit to be used includes, for example, a multi-value logic circuit, a multi-value arithmetic circuit (or multi-ary arithmetic circuit), a multi-value memory circuit, a multi-value digital circuit, and the like.
Further, in the case of a multi-value logic circuit based on “Fuji algebra”, a specific integer for its input by means of constant potential supply means (eg, power supply line, power supply plate, etc.) connected to each of its numerical discrimination means and pull switching means, Both the output specific integers can be easily changed, and the circuit to be used can be selected from the various multi-value logic circuits. Since the first invention is “because each multi-level logic circuit has a synchronous latching function”, the options for the multi-level synchronous latching circuit increase after all.
Further, for example, each of the various multi-value logic circuits is referred to as “(multi-value) AND circuit, (multi-value) OR circuit, OVER circuit, EVEN circuit, UNDER circuit, IN circuit, OUT circuit, etc.” There is a circuit.

Note that N (≧ 3) indicates a multi-value number N of N values, and the integer used is 0 to (N−1). The first constant potential is an integer 0, the second constant potential is an integer 1, the third constant potential is an integer 2, and so on. The Nth constant potential is defined as corresponding to an integer (N-1). [Potential mode (or voltage mode)]
Therefore, it is defined as follows in relation to the logic level on the input side. However, since the expression “H level, L level” in a binary circuit cannot be used in a multi-value circuit, for example, “numerical level… a logical level” or “specific integer… a logical level” is used to express a specific numerical value. I have to express it. As a matter of course, the logical level areas do not overlap each other, and one margin area between the two areas is set between each of the “two logical level areas adjacent to each other”.
◆ When these constant potentials “go higher” in numerical order from the first constant potential to the Nth constant potential:
The “first constant potential region lower than the positive side threshold potential with reference to the first constant potential” is the logic level region of the integer 0, and “the negative side threshold potential with reference to the second constant potential. The second constant potential region between the positive-side threshold potential and the logic level region of integer 1. In the same manner, “the third constant potential between the negative threshold potential and the positive threshold potential with reference to each constant potential from the third constant potential to the (N−1) th constant potential in order. The (N-1) th constant potential region from the potential region is sequentially “the logic level region of integer 2 to the logic level region of integer (N−2)”. The “Nth constant potential region higher than the negative threshold potential with reference to the Nth constant potential” is an integer (N−1) logic level region.
◆ When these constant potentials “go down” in numerical order from the first constant potential to the Nth constant potential:
The “first constant potential region that is higher than the negative threshold potential with reference to the first constant potential” is the logic level region with an integer 0, and “the positive threshold potential with reference to the second constant potential. The second constant potential region between the negative-side threshold potential and the logic level region of integer 1. Hereinafter, in the same manner, “a third constant potential between a positive threshold potential and a negative threshold potential with reference to each constant potential from the third constant potential to the (N−1) th constant potential in order. The (N-1) th constant potential region from the potential region is sequentially “the logic level region of integer 2 to the logic level region of integer (N−2)”. The “Nth constant potential region lower than the positive threshold potential with respect to the Nth constant potential” is an integer (N−1) logic level region.
As a result, if the input potential signal is in the first constant potential region in either case of “increase” or “increase”, “the corresponding input integer” is 0. If the input potential signal is within the second constant potential region, it is determined that “the corresponding input integer” is 1. Similarly, if the input potential signal is in order from the third constant potential region to the Nth constant potential region, the “corresponding input integer” is sequentially reduced from 2 to (N−1). It is determined that

However, the above-mentioned determination content of “how is it with respect to one or two predetermined input specific values” (e.g., whether it is equal or not, larger or not, smaller or not, There are only two or four of these threshold potentials to be applied every time. However, “the one specific integer for input can take any one integer value of“ integer 0 to integer (N−1) ””, that is, “when taking integer 0, when taking integer 1, integer 2” ..., And when taking an integer (N−1), each case is assumed. After all, “the relationship between each integer, each logic level, and each threshold potential” described above. Is derived.
The two input specific integers can also be any one of integer 0 to integer (N-3), while the smaller input specific integer can have the value of the larger input specific integer " Since any one of integers 2 to (N-1) can be taken according to the “specific integer for input”, the above-described “relationship between each integer, each logic level, and each threshold potential” is the same as above. Is derived.
By the way, when it is determined whether or not the S input integers (= S integers corresponding to each of the S input potential signals on a one-to-one basis) are between 2 and 5. For example, even if the S input integers are between 3 and 4, for example, and “do not get any”, it can be clearly determined that they are “between 2 and 5.” Similarly, when it is determined whether the S input integers are greater than 5 or not, even if the S input integers are between 7 and 8, for example, “Neither”, of course, “5 Greater than ". Similarly, when it is determined whether or not the S input integers are smaller than 6 or not, even if the S input integers are between 2 and 3, for example, and “do not get stuck”, “6 It is possible to determine that it is “smaller”.

Now, a specific integer for output is represented by m, and the logic level on the output side will be described. In the case of the multi-value logic means of the first invention, the output is either one of the output specific integer m or the output release, but “one end of the pull switching means which is one constituent means is connected. Since the output specific constant potential supply means is selected from among the first constant potential supply means to the Nth constant potential supply means, the output specific integer m is an integer 0 to (N−1). Any one integer value can be taken. Whichever integer value the output specific integer m takes, the logic level region of the output specific integer m always includes a margin and is included in the “input-side logic level region of integer m” in the subsequent circuit. It is set to be One or two margin areas are “noise margin against noise (or noise margin)”. This can be easily understood by considering the extension of the binary circuit.
Here, considering the (international) standardization and standardization of the standard and specification of each threshold potential, "what can be said about each input side logic level region of the subsequent circuit " is that of each multi-value logic circuit . Since the input side logic level region can also be said, after all, the explanation of the output side and the logic level is the multi-valued logic circuit itself, “the logic level region of the output specific integer m” and “each input side logic level region” "Will be explained. Then, as the output specific integer m may take any integer value of “integer 0 to integer (N−1)”, the output side also sets each integer of 0 to (N−1). It is necessary to determine the corresponding logical level area.
Therefore, when these constant potentials “go higher” in numerical order from the first constant potential to the Nth constant potential, the negative thresholds of the input side logic levels of the integers 1 to (N−1) respectively. The “negative threshold potential of the output logic level” is higher than the potential by the noise margin on the minus side, and the positive threshold of the input logic level of each of the integer 0 to integer (N−2). The “positive side threshold potential of the output side logic level” is lower than the value potential by the noise margin on the positive side. Each threshold potential is as described above (paragraph numbers [0031 to 0032]).
On the other hand, when these constant potentials are “decreasing” in numerical order from the first constant potential to the Nth constant potential, the positive side threshold values of the input side logic levels of the integers 1 to (N−1). The positive threshold potential of the output logic level is lower than the potential by the noise margin on the plus side, and the negative threshold of the input logic level of each of integer 0 to integer (N-2). The “negative threshold potential of the output logic level” is higher than the value potential by the noise margin on the negative side. Each threshold potential is as described above (paragraph numbers [0031 to 0032]).
These things are the relationship between the “H level input potential (or input voltage), the H level output potential (or output voltage), and the H level noise margin” of the binary circuit and the “L level input potential (or It is easy to understand by considering “the relationship between the input voltage), the L level output potential (or output voltage), and the L level noise margin”. In the positive logic of the binary circuit, “the lower limit values of the H level input potential and the output potential are the negative side threshold potentials of the input side logic level and the output side logic level of the numerical value 1”, “The upper limit values of the L-level input potential and output potential are the positive-side threshold potentials of the input-side logic level and output-side logic level of numerical value 0”.
In spite of this, what is commonly referred to as “threshold potential (or voltage)” in a binary circuit is, for example, in the case of a CMOS inverter circuit, “a boundary where the operating state of PMOS and NMOS is reversed”, ie “circuit threshold potential (or Voltage) ”. There is an on / off threshold voltage of the semiconductor element.

“Introduction to Transistor Circuit 5: Digital Circuit Concept”, “4.6 Notes on Using Logic Circuits [1] Logic Voltage Level and Noise Margin” on pages 46-47. Supervision: Yoshifumi Amemiya and Nori Koshiba. Authors: Kensuke Shimizu and Masahiro Masakazu. Issued on May 20, 1981 by Ohm Co., Ltd. “A well understood digital electronic circuit”, “[1] Logic level to [2] Noise margin” on pages 76-80. Author: Keitaro Sekine, published by OHM Co., Ltd. on July 25, 1997. “Introduction to Logic Circuits”, “(1) Signal Voltage Value and Noise Margin” on pages 126-128. Author: Ryuji Hamabe, published by Morikita Publishing Co., Ltd. on September 28, 2001. “Pulse digital circuit”, “5-1. Amplitude characteristics of pulse digital circuit” on pages 125-130. Author: Akira Kawamata. Published by Nikkan Kogyo Shimbun on February 15, 1995. “Pulse and digital circuits”, “Threshold level” on page 128 and “Logic level” on page 129. Edit: Masao Yoneyama. Author: Shigeyuki Ohara, Sumio Yoshikawa, Toshio Shinozaki, Shiro Takahashi. Published by Tokai University Press on April 5, 2001. “Practical Introduction Series: How to Use CMOS Circuit [1]”, “Element Threshold Voltage” on page 44 and “Circuit Threshold Voltage” on page 50. Author: Yasoji Suzuki. Published on October 15, 1997 by the Industrial Research Committee.

Then, the “multi-valued logic circuit on which the first invention was based” is a realization and implementation of a new multi-valued logic “Fuji algebra”. In the three stages of the circuit part in the middle of signal transmission (for example, the numerical value determining means, the on / off driving means, and the pull switching means) [means for the previous stage (eg, the numerical value determining means or the on / off state) Between the output side of the driving means.) And the binary circuit] and [the latter side means (eg, the on / off driving means or the pull switching means) and the binary circuit. connectivity between] is extremely not good. As a result, there is a special interface between the “between the numerical value discriminating means and the on / off driving means” and “between the on / off driving means and the pull switching means” (eg, binary / multi-value). Code conversion means, multi-value / binary code conversion means) is not necessary ”.
(Unique effects and features of the multi-value logic circuit on which the first invention is based)
The reason is as follows. The signal in the middle of transmission in the circuit is “at each output side of the numerical discriminating means and the on / off driving means“ affirmative or negative [the discrimination result signal and its on / off driving signal] ”, that is, a binary signal. “High / Low signal”, and “on each input side of the on / off drive means and the pull switching means,“ output a specific integer for that output (on drive) and open output (off) [The on / off signal and the on / off drive signal] corresponding to (at the time of driving) ”, that is, a binary signal, such as a High / Low signal”, the signal transmission middle part in the multi-value logic circuit is Excellent compatibility with binary circuits.

However, “the determination result signal and the on / off drive signal (both are like a binary signal, a high / low signal)” are “when they are the same as the“ H level and L level ”of a normal binary signal”. There are “provisional binary signals“ like H level and L level ”and different from the normal binary signals“ H level and L level ”. The “binary” and “provisional” binary signals are different from each other only in “potential level height” or “amplitude magnitude at level change”.
For example, even in a binary circuit, if the magnitude of each power supply voltage is different as in TTL and CMOS, the “height of the H level potential (or voltage)” and the “magnitude of the amplitude when the level changes” are different. In the positive logic, even if the potential level is different, the H level remains at the H level, and the numerical value 1 also remains at the numerical value 1.
On the other hand, when handling the H level and L level of a “normal or provisional” binary signal in a multi-value circuit, “three or more constant potentials corresponding to each integer one to one” or “ It is selected which two constant potentials are to be used from the added constant potentials {example: power supply potential v _-1 of the power supply line V _{-1 in} FIG. According to the entire multi-value circuit, “the constant potential corresponding to the H level and L level” and “the level change” depending on “which constant potential is selected to be the power source for the binary circuit”. “Magnitude of time” is different.
If the constant potentials corresponding to the H level and L level are different from each other, the corresponding numerical values in the multi-value circuit are also different. The “2 numerical values corresponding to the H level and L level” are, for example, “9 and 0”, “8 and 5”, and “3 and 1”, which are not normally “1 and 0” of the binary circuit. There are many cases. This is because the multi-value circuit is considered as the center and reference, and the relationship between each constant potential and each integer is defined in the first part of claim 1. Alternatively, in the case of “a completely different added constant potential”, the corresponding integer itself is not defined.
However, in general, a binary circuit of positive logic is originally considered based on itself as the center and reference. “While an input potential signal higher than the lower limit value of its own H level is determined as H level, It has a function of “determining an input potential signal lower than the upper limit value as an L level”. The first invention effectively uses this discrimination function in the multi-value circuit. For this reason, the binary synchronous flip-flop means has a (voltage) matching function (eg, a voltage dividing function by a voltage dividing resistor connected to the input unit) if necessary in addition to the discrimination function. The provisional binary signal can be converted into a normal binary signal. The necessity of the matching depends on the withstand voltage of the input part of the binary synchronous flip-flop means.
Alternatively, the potential (or voltage) clamping means (for example, two clamping diodes) at the input part of the binary synchronous flip-flop means sets the temporary upper limit of the binary signal. While clamping to the positive constant potential of the binary circuit power supply, the lower limit of the temporary binary signal is clamped to the negative constant potential of the binary circuit power supply, and the temporary binary signal is normally Can be converted into a binary signal. In the first invention, this conversion function is also effectively used in the multi-value circuit. In this case, if necessary, by having a kind of (impedance / matching) matching function (for example, insertion connection of a power supply short-circuit prevention resistor, the resistor 28 in FIG. 1), the output part of the previous stage is connected to the power supply via the clamp means Prevent short circuit.
The same applies to the case of a general negative logic binary circuit.

As mentioned above, taking into account the correspondence with the logical values, it is complicated to grasp the binary circuit and the multi-value circuit, but the above story is a matter of course if only a pure electronic circuit is considered. It is easy to grasp.
As for the synchronization signal of the binary synchronization flip-flop means, the synchronization signal supply means supplies a “synchronization signal that can be used by the binary synchronization flip-flop means”. The signal supply means has the above-described matching functions, or uses the above-described binary circuit discrimination function or “conversion function by clamping”.
If the binary synchronous flip-flop means satisfies the requirements of the on / off driving means, such as the output current capacity of the binary synchronous flip-flop means is sufficiently large, the binary synchronous type Of course, the flip-flop means may also serve as the on / off driving means.

■■ “Means for solving the problems” of the second invention ■■
Above the "means for solving the problems" of (paragraph numbers 0030 to 0032) was the first invention or "multivalued logic circuit having a synchronous latching function",
"Synchronization signal supply means for supplying the synchronization signal to the binary synchronization flip-flop means"
The S input potential signals are inputted to the first to S-th inlet means from the outside, and based on the synchronization signal, “a period in which no hazard appears in the discrimination result signal and the discrimination result signal is stable” is a multi-valued hazard removal circuit for inputting "were allowed to directly or matching" as the holding signal is the discrimination result signal the binary synchronous flip-flop means.

As a result, the conventional binary hazard removal technique can be used for the “binary multi-value hazard appearing in the discrimination result signal”, so that the multi-value hazard can be removed.
(Effect)
The reason is as follows. Even if a certain multilevel signal is input to the multilevel hazard elimination circuit , it can be handled like a binary signal as described above (paragraph numbers 0039 to 0040) during signal transmission in the circuit. Even if a multi-value hazard occurs before or at the time of input, the multi-value signal can be handled like a binary signal including a binary hazard during the signal transmission. The binary hazard removal circuit and method can be utilized during the signal transmission.
In addition, since the period in which the multi-value hazard appears can be grasped in advance at the circuit design stage or the operation check stage, the timing of the multi-value hazard occurrence and the timing of the synchronization signal (or clock pulse signal, etc.) Can be matched. For this reason, during the “period in which the binary hazard appears in the discrimination result signal”, the binary synchronous flip-flop means ignores the discrimination result signal based on the synchronization signal and holds the previous holding signal (or (Retained data) is retained.
On the other hand, the “binary synchronous flip-flop means incorporates the discrimination result signal based on the synchronization signal during a period when the binary hazard does not appear in the discrimination result signal and the discrimination result signal is stable”. Is held as a new / holding signal (or new / holding data), and the on / off driving is performed with the “positive output signal or complementary output signal” based on the new / holding signal (or holding data) as the on / off signal. Output to the means.
Similarly, the binary-synchronous flip-flop means rewrites the holding signal (or holding data) based on the synchronizing signal and reads “a positive output signal or a complementary output based on the holding signal (or holding data). Since the binary synchronous flip-flop means outputs a "binary signal obtained by removing a binary hazard from the binary signal being transmitted", the subsequent on / off driving means. Can be supplied to. As described above, the multi-value hazard removal circuit (= multi-value logic circuit having a multi-value hazard removal function) of the second invention changes the multi-value hazard into a binary hazard during the signal transmission. It can be removed by applying a binary hazard removal method. As a result, only the true “signal, data or information” portion can be extracted from the “multilevel signal including multilevel hazard”.
By the way, in the case of most conventional multi-value logic circuits, the multi-value hazard removal method in which a binary circuit (eg, flip-flop, etc.) is provided in the middle of signal transmission in this way cannot be applied. This is because in most cases, the signal in the middle of signal transmission is also a complete multi-value signal.

Then, since the binary-synchronous flip-flop means is immediately behind the “numerical value discrimination means that is one source of multi-valued hazards”, the binary-synchronous flip-flop means Since the “multi-value hazard generated by the numerical discrimination means” is immediately cut off, the multi-value hazard does not propagate to the on / off drive means and the pull switching means in the multi-value logic circuit and the subsequent stage. .
As a result, since “the range in the multi-value logic circuit affected by the generated multi-value hazard” is limited only to the numerical discriminating means, “in the multi-value logic circuit affected by the generated multi-value hazard” The range can be reduced as much as possible.

■■ Effects of the first invention ■■
The effects of the first invention are summarized as follows.
1) Since the binary synchronous flip-flop means can be built in between the numerical value discriminating means and the on / off driving means, each binary trigger method (eg, positive and negative edges)・ Triggers, level triggers, and pulse triggers can be used as they are. (First effect)
In particular, the step-like multi-level synchronization signal (the waveform of FIG. 4 of Patent Document 7 considered by the present inventor. There are a plurality of rising portions, falling portions, or horizontal portions) can be used more effectively. Since this is possible, the trigger timing options increase during one period of the synchronization signal, which is very convenient. This is because, depending on which of the two constant potential supply means (for example, two power supply lines) the binary synchronous flip-flop means is connected, a plurality of “rising points or falling points or horizontal portions” are used. This is because one can be selected.
If the binary synchronous flip-flop means satisfies the requirements of the on / off drive means, such as the output current capacity of the binary synchronous flip-flop means is large, the binary synchronous flip-flop Of course, the flop means may also serve as the on / off driving means.
2) Since the binary synchronous flip-flop means only latches either “signal state corresponding to a specific integer for output of the multi-value logic circuit ” or “signal state corresponding to output open or open output”. Of course, the "signal state corresponding to the output open or open output" can be latched. (Second effect)
◆ 3) Since there is no latching function for each numerical value (= each integer) other than “output numerical value (= specific integer for output)”, a latching function corresponding to “output numerical value” is provided. There is no waste. (Third effect)
→→ Since there are no useless parts and useless configurations, parts and circuits can be used efficiently and power consumption can be saved.

◆ 4) choice of latching point "plurality of where to latching of the overall circuit was connected to the multi-level circuit" has come in handy more and more. Flexibility occurs in the circuit configuration of the entirety.
( 4th effect)
→→ Since the multi-value logic circuit of the first invention itself has a synchronous latching function, it is not necessary to provide a multi-value synchronous latching circuit between the multi-value circuit and the multi-value circuit in the entire circuit. Is added.
The multi-value circuit to be used includes, for example, a multi-value logic circuit, a multi-value arithmetic circuit (or multi-ary arithmetic circuit), a multi-value memory circuit, a multi-value digital circuit, and the like.
Further, in the case of a multi-value logic circuit based on “Fuji algebra”, a specific integer for its input by means of constant potential supply means (eg, power supply line, power supply plate, etc.) connected to each of its numerical discrimination means and pull switching means, Both the output specific integers can be easily changed, and the circuit to be used can be selected from the various multi-value logic circuits. Since the first invention is “because each multi-level logic circuit has a synchronous latching function”, the options for the multi-level synchronous latching circuit increase after all.
Further, for example, each of the various multi-value logic circuits is referred to as “(multi-value) AND circuit, (multi-value) OR circuit, OVER circuit, EVEN circuit, UNDER circuit, IN circuit, OUT circuit, etc.” There is a circuit.

■■ Effects of the second invention ■■
The effects of the second invention are summarized as follows.
In addition to multi-value hazards generated by the same mechanism as binary hazards, multi-value hazards inherent to multi-values can also be removed. (First effect)
→→ Only the true “signal, data or information” part can be extracted from the “multilevel signal including multilevel hazard”.
In addition, the range in the circuit affected by the generated multi-value hazard can be narrowed even a little. (Second effect)
These effects lead to reduction of multi-value hazard noise and power loss.

It is a circuit diagram which shows Example 1 common to 1st, 2nd invention. It is a circuit diagram which shows Example 2 common to 1st, 2nd invention. It is a circuit diagram which shows Example 3 common to 1st, 2nd invention. It is a circuit diagram which shows Example 4 common to 1st, 2nd invention. It is a circuit diagram which shows Example 5 common to 1st, 2nd invention. It is a circuit diagram which shows Example 6 common to 1st, 2nd invention. It is a circuit diagram which shows Example 7 common to 1st, 2nd invention. It is a circuit diagram which shows Example 8 common to 1st, 2nd invention. It is a circuit diagram which shows Example 9 common to 1st, 2nd invention. It is a circuit diagram which shows Example 10 common to 1st, 2nd invention. It is a circuit diagram which shows Example 11 common to 1st, 2nd invention. It is a circuit diagram which shows Example 12 common to 1st, 2nd invention. It is a circuit diagram which shows Example 13 common to 1st, 2nd invention. It is a circuit diagram which shows Example 14 common to 1st, 2nd invention. It is a circuit diagram which shows Example 15 common to 1st, 2nd invention. It is a circuit diagram which shows Example 16 common to 1st, 2nd invention. It is a circuit diagram which shows Example 17 common to 1st, 2nd invention. FIG. 6 is a circuit diagram for explaining an equivalent circuit and duality of “(basic / multi-value logic circuit based on new multi-value logic“ Fuji algebra ”” ”. A circuit diagram showing a synthesis / multi-value logic circuit (= first 10-value complete circuit) that supports “very flexible completeness” of the new multi-value logic “Hooji algebra” on which each invention is based It is. →→ Complete circuit means of multi-valued logic functions. FIG. 20 is a truth table / diagram showing a truth table simplified for explanation of the synthesis / multi-value logic circuit of FIG. 19. A composite / multi-value logic circuit (= second 10-value complete circuit) in which the multi-value wired OR circuit is introduced into the composite / multi-value logic circuit (= first 10-value complete circuit) in FIG. FIG. FIG. 5 is a circuit diagram showing a “ternary complete circuit incorporating a multi-value wired OR circuit” that also supports “very flexible completeness” of the new multi-valued logic “Fuji algebra”. FIG. 23 is a truth table / diagram illustrating a truth table of the synthesis / multi-value logic circuit of FIG. 22; FIG. 23 is a circuit diagram showing an example of an asynchronous multi-value (specific value) AND circuit based on a new multi-value logic “Fuji algebra” used in each circuit of FIGS. 19, 21, and 22. 19, 21, used in the circuit of FIG. 22 is a circuit diagram showing an example of asynchronous-multilevel (specific value) NOT circuits based on New multi-value logic "Fuji Algebra". 19, 21, used in the circuit of FIG. 22 is a circuit diagram showing an example of asynchronous-multilevel (specific value) NOT circuits based on New multi-value logic "Fuji Algebra".

In order to explain the first and second inventions in more detail, these will be described with reference to the accompanying drawings. The following seven points of caution are stated first.
◆ 1) There are “explanations from the viewpoint of electronic circuits” and “explanations from the viewpoint of logic mathematics”, and there are also descriptions that are a mixture of both.
2) Each embodiment will be described mainly in the case where these constant potentials “go higher” in numerical order from the first constant potential to the Nth constant potential.
On the other hand, each example in the case where these constant potentials “become lower” is “each power source potential (corresponding to each of these constant potentials) in“ Embodiments to be described or their derivatives ”). Each controllable switching means is replaced one by one with “controllable switching means in complementary relationship (eg, P-channel MOS • FET with respect to N-channel MOS • FET)” one by one. This corresponds to “an embodiment having a symmetrical relationship with respect to the voltage direction or the voltage polarity with respect to the original embodiment” in which the direction of each component having a voltage polarity (eg, diode) is reversed. However, in that case, the multi-value logic function may be the same as or different from the original circuit.
3) In each embodiment, n corresponds to the aforementioned N (predetermined plural).
◆ 4) The integer m corresponds to a specific integer for output, and corresponds to the above-mentioned specific constant potential for output of the output specific constant potential supply means (eg, power supply line V _m ) (eg, specific power supply potential v _m ). Is an integer. The relationship is “n−1 ≧ m ≧ 0”.
◆ 5) expressed in capital letters V _{"V G, V H, V m} , V -1, V 0, V 1~ V n-1, V n " in the power supply line, respectively, such as, represented by a lower case v etc. “V _G , v _H , v _m , v ₋₁ , v ₀ , v _{1 to} v _n−1 , v _n ” and the like represent the potentials (= constant potential) of these power supply lines in order, and the power supply potential The power supply potentials of v _{−1 to} v _n increase in this order. Of course, the power supply line V ₀ or other power supply line is “the main body of the circuit” or “the main body of the circuit device” or “the body of an automobile, motorcycle, bicycle, etc.” or “the hull of a ship” or “ "Body of hovercraft, etc. for two-purpose use" or "Body of airplane, helicopter, etc." or "Main body of space navigation, space station, etc." The potential of the main body, the vehicle body, the hull, and the celestial body becomes a reference potential such as a ground potential.
However, although one DC power supply for supplying DC voltage is connected between each of “two power supply lines adjacent to each other at the level of the power supply potential”, it is not shown.
◆ 6) For example, diodes 10, 12, 35, 36, “a pair of Zener diodes in which two Zener diodes are connected in series in the opposite direction”, etc. In the case of showing, it means that there are cases where the connection or insertion / connection is present and not.
7) “Two gate terminals or common gate terminals of the transistors 41, 47, and 48 are drawn, and each gate terminal is connected to the Q terminal (positive output terminal) of the D-type flip-flop 27. , “Is connected to the Q bar terminal (complementary output terminal)”.
Naturally, “change in connection from the Q terminal to the Q bar terminal” or “change in connection from the Q bar terminal to the Q terminal” means that the circuit after the connection change is different from the circuit before the connection change. It means that it becomes a negative circuit.
As a precaution, “Q bar” means a character in which a line is drawn on the letter Q.

In the first embodiment of FIG. 1 (a multi-value logic circuit having a synchronous latching function and a multi-value hazard removal circuit ), each component corresponds to each component described above (paragraph numbers [0030 to 0032]). , S = 1, and “n ≧ 3” and “n−1 ≧ m ≧ 0”. Since the one output specific integer m also serves as the one input specific integer m, the output specific power supply potential v _m also serves as the input specific constant potential (→ paragraph number [0031]).
However, as described above (last nine lines of paragraph number [0033]), “determining whether the one input integer is equal to or not the one input specific integer m” means “the one input integer. Is the same between the two input specific integers (m−1) and (m + 1) ”. The power supply line V _n, etc. When n> m + 1 will be not shown.
A) The power supply potential v ₀ to the power supply potential v _n−1 are changed from the first constant potential to the Nth constant potential as described above (paragraph numbers [0030 to 0032]).
B) The power supply line V ₀ to the power supply line V _n−1 are the first constant potential supply means to the Nth constant potential supply means described above.
However, further or there is a power supply line _{V -1} supply potential _{v -1} under the power potential _{v 0,} or there is a further power supply line _{V n} of the power supply potential _{v n} on the power potential _{v n-1} Sometimes, there are cases. FIG. 1 shows only a part of the power supply lines.
C) The input terminal T _in serves as the first (S = 1) inlet means described above.
◆ d) The output terminal T _out is the outlet means described above.
E) The power supply line V _m serves as the above-mentioned output specific constant potential supply means (= input specific constant potential supply means).
◆ f) to a specific power supply voltage v _m is "specific input described above constant potential" and "specific constant potential output supplies its output a specific constant potential supply unit".
G) The series circuit of the transistors 3 and 4 is the aforementioned (bidirectional) pull switching means. ☆ Reference: JP 2005-236985 (Patent Document 3)
◆ h) “The circuit portion formed by the transistors 1, 2, 17, the diode 35 and the resistors 20, 21” is the numerical value discrimination means described above.
I) “Circuit part formed of transistors 41 and 37, diode 39 and resistor 15” is the on / off driving means described above.
J) The D-type flip-flop 27 is the binary synchronous flip-flop means described above.
◆ k) “Synchronous signal generating means 60, transistor 61, and circuit portion constituted by resistors 26 and 28” are the above-described synchronizing signal supply means.

If “D-type flip-flop 27, synchronization signal generating means 60, transistor 61 and resistors 26, 28” are removed and the gate of transistor 41 is directly connected to the anode of diode 35, “{power supply line V ₋₁ ,} Power supply line V ₀ to power supply line V _n−1 {, power supply line V _n }, transistors 1, 2, 3, 4, 17, 37, 41, diodes 35, 39, resistors 15, 20, 21 and the like (DC "Multi-valued logic circuit configured by a power supply not shown") is an asynchronous multi-valued logic circuit based on the aforementioned "Fuji algebra".
Further, the gate of the transistor 41 is connected to the Q terminal (positive output terminal) of the D-type flip-flop 27, but of course, it may be connected to the Q bar terminal (complementary output terminal).
Further, the transistor is changed by “changing the connection of each portion of the power supply lines V _{m−1 to} V _{m + 1} to which the transistors 1, 2, 17, 41 and the D-type flip-flop 27 are connected to the same high potential at the same time”. If the source of 41 is changed to the power line V _{m + 2} or “any power line having a higher potential”, a resistor or “two zener diodes are connected in series in reverse direction for voltage drop instead of the diode 39” Things can be used. In this case, the transistor 37 may be normally on (depletion mode).
Then, D-type sync signal input of the flip-flop 27 "identify the lower limit of the potential of the CP terminal power supply potential v clamping diode for clamping the _m (not shown.)" It is connected and the particular power supply potential v _{When m} is higher than the power supply potential v ₀ , the resistor 28 prevents the clamp diode and the transistor 61 from short-circuiting between both power supply lines V _m · V ₀ . When the specific power supply potential v _m = power supply potential v ₀ , the resistance value of the resistor 28 may be zero.
Of course, one DC power supply means (not shown) is connected between each “two power supply lines adjacent to each other at the level of the power supply potential”.

As described above, the output specific integer (= integer corresponding to the output specific constant potential) m also serves as the input specific integer (value), and the power supply line V _m is the input specific constant potential supply means and the output specific constant potential supply. also serves as a means, certain power potential v _m doubles as a certain constant potential output with a particular input constant potential.
"Input voltage v _{in (=} the potential of the input terminal T _in)", the relationship "the logic level of the threshold potential of the input specific integer m" and "input numerical value N _in corresponding to the input voltage v _in" following Street.
◆ 1) When specific integer m = 0:
If lower than the input potential v _in is the power supply potential v ₀ to the reference positive threshold potential, input numerical value N _in is determined that the integer 0, the input voltage v _in the one above "supply potential v ₀ of If it is higher than the negative threshold potential with reference to the power supply potential v ₁ ”, it is determined that the input numerical value N _in is not an integer 0.
◆ 2) When the specific integer m is “n−2 ≧ m ≧ 1”:
If there input potential v _in is a "between the positive side threshold potential and the negative side threshold potential relative to the specific power supply potential v _m", the input numeric N _in is determined that the integer m, the input potential v _in the "" specific power supply potential v power supply potential on the one than _m v _{m + 1} "higher than the negative threshold voltage relative to the" or "" specific power supply potential v below one than _m power supply potential v _{m- In the} case of “lower than the plus-side threshold potential with reference to ₁ ” ”, it is determined that the input numerical value N _in is not an integer m.
◆ 3) When a specific integer m = (n−1):
Is higher than the minus side threshold potential input potential _{v in} is the power supply potential _{v n-1} to the reference, the input numerical value _{N in} is determined that the integer (n-1), the input potential _{v in} the "power supply potential _{v n} If it is lower than the plus-side threshold potential with reference to the power supply potential v _n-2 that is one lower than _−1, it is determined that the input numerical value is not an integer (n−1).
Incidentally, normally taking into account the respective-noise margin (degrees), the negative side threshold potential of the input side logical level of a particular integer m certain supply potential v _m and a "specific supply potential v _m and a" specific power supply potential v while being set between the middle potential "of one power supply potential v _m-1 of below" _m, the plus side threshold potential of the input side logical level of a particular integer m is from "" specific power supply potential v _m 1 One power supply potential v _{m + 1} "on the middle potential" of a particular power supply potential v _m is set during a particular power supply potential v _m.
Of course, each noise margin (degree) is taken into consideration, but such a setting may be used instead of such a setting as “each threshold potential of binary TTL having no vertical symmetry”.

■ First, the operation of the original asynchronous / multi-valued logic circuit ■
“In the embodiment of FIG. 1, there is no insertion or connection of the D-type flip-flop 27, and the gate of the transistor 41 is directly connected to the anode of the diode 35. Reference: First in paragraph number 0050.) The logical operation is as follows.
Input numerical value _{N in} the input terminal _{T in} the transistor 1,2,17,37 is turned on when a particular integral m, since the transistor 41,3,4 is turned off, the output from the output terminal _{T out} is opened . On the other hand, "On the other hand either 1, 2," when the transistor input numerical value _{N in} the other than the specific integer m, 17,37 is turned off, in order to transistor 41,3,4 is turned on, the potential of the output terminal _{T out} becomes the specific supply potential v _m, the specific integer m is output. For this reason, the present inventor calls this asynchronous / multi-value logic circuit “(asynchronous /) multi-value (specific value) NOT (= knot) circuit”.
Therefore, when the gate of the transistor 41 is connected to the Q terminal of the D-type flip-flop 27 in the first embodiment, the present inventor calls the first embodiment a “synchronous multi-value (specific value) NOT circuit”. .
However, in the asynchronous multi-valued logic circuit, the drain signal of the transistor 17 is inverted by using a “binary NOT circuit (not shown) that takes its power supply from both power supply lines V _{m + 1} · V _m ”. 41, since the on / off operations of the transistors 41, 3 and 4 are opposite to each other, in this case, the present inventor designates the asynchronous type / multilevel logic circuit as "(asynchronous type) multilevel". (Specific value) EQUAL (= equal) circuit ”.
Alternatively, there are “circuits that the inventor has already called an asynchronous (multi-value specific value) OVER (= over) circuit” or an asynchronous type (multi-value specific value) UNDER (= under) circuit ”. The present inventors refer to the term “asynchronous (multi-value specific value) EVEN (= even) circuit” in golf terms. In this case, this negative circuit may be called an “asynchronous (multi-value specific value) NEVEN (= neven) circuit” instead of the “(asynchronous type) multi-value (specific value) NOT (= knot) circuit”.
Therefore, in the first embodiment, when the gate of the transistor 41 is connected to the Q bar terminal of the D-type flip-flop 27, the first embodiment is referred to as a “synchronous EQUAL circuit or a synchronous EVEN circuit”.
Incidentally, the specific power supply potential v _m that satisfies "n-1 ≧ m ≧ 0" corresponds to a specific output integer m, the pull-open output of the output terminal T _out in which the power supply potential, for example, "the output terminal T _out up or pull-down or "or" is either "or the like for connecting the output terminal T _out and the output terminal T _out of another similar multivalued logic circuit, the output terminal Tout in any case the" multi-level Corresponding constant potential "can be output.

■ To a synchronous / multi-valued logic circuit ■
The functions of the first embodiment shown in FIG. 1 are as follows. The “drain output signal of the transistor 17” and the “gate input signal of the transistor 41” are substantially signals like a binary circuit using the voltage between the power supply lines V _{m + 1} and V _m as a power source.
For this reason, as described above (paragraph numbers 0039 to 0040), the multi-value logic circuit based on the “Fuji algebra” has “excellent connectivity with a binary circuit in the middle of signal transmission in the circuit, and special A unique interface (e.g., binary / multi-value code conversion means, multi-value / binary code conversion means) is not necessary ”.
(Unique effects of multi-valued logic circuits based on the "Fuji algebra")
The combination of the resistors 26 and 28 and “a means such as a binary / numerical value discriminating means or two clamp diodes in the CP input section of the D-type flip-flop 27” originally has a “deemed or converted” function. Yes. The “deemed or converted” function is to swing a “High / Low signal like a binary signal swinging between the power supply potential v ₀ and the power supply potential v _{m + 1”} between “the specific power supply potential v _m and the power supply potential v _{m + 1”.} This is a function that can be easily regarded as “normal binary signal” or can be easily converted into the normal binary signal.
However, a High / Low signal such as the binary signal can be regarded as a multi-level signal depending on numerical interpretation. →→ First half of paragraph number [0040].
The “deemed or converted” function is “a numerical discriminating unit of a general binary circuit always outputs all“ (multi-value) potential signals or (multi-value) voltage signals ”higher than the lower limit value of the H level” to “H Binary circuit with unique operating characteristics that distinguishes all “(multi-valued) potential signals or (multi-valued) voltage signals” that are lower than the upper limit value of the L level ”and always distinguishes them from“ L level ”. Due to Alternatively, this is due to a binary circuit and a specific operation characteristic of “determining whether the rise from the L level to the H level or the fall from the H level to the L level”.
Alternatively, the “deemed or converted” function means that “the two clamp diodes in the input part of a general binary circuit have an upper limit of“ (multi-value) potential signal or (multi-value) voltage signal ””. while clamped to positive constant potential (or positive power supply voltage) v m _{+ 1,} the lower limit on the operating characteristics of the negative constant potential (or minus side power supply voltage) v is clamped to _m "of the binary circuit of the binary Is attributed.
In the first embodiment shown in FIG. 1, the CP terminal / input unit of the D-type flip-flop 27 is used as the “numerical value determination unit or input unit of the binary circuit”. The same applies to the D terminal / input section.
→→ Description of paragraph (10) in paragraph number [0116] described later.
In this embodiment 1, both the power supply line as supplied is selected power of the binary circuit (= D-type flip-flop 27) from the power supply line V _{m + 1} and the power source line V _m.

Further, the multi-value logic circuit based on the new multi-value logic “Hooji algebra” has extremely unique effects and features. This means that “connectivity with the binary circuit in the previous stage”, “connectivity with the binary circuit in the middle of signal transmission in the multi-level logic circuit”, and “connectivity with the binary circuit in the subsequent stage” are extremely good. Regardless of the multi-valued number N, all multi-valued logic functions can be expressed by a single basic multi-valued logic circuit or a combination thereof (complete system) (= completeness itself Reference: Non-Patent Document 3).
The proof of “complete” in “Hooji algebra” is explained in paragraph numbers [013 8 to 014 8 ] described later.
For this reason, a certain multi-value signal is input to the one type of multi-value logic circuit, and is handled as a binary (target) signal as described above (paragraph numbers [0039 to 0040]) during signal transmission in the circuit. be able to. Even if a multi-value hazard occurs before or at the time of input, it can be treated as a binary (target) signal including a binary (target) hazard during the signal transmission. The hazard removal circuit and method can be utilized during the signal transmission.
Then, the period in which the multi-value hazard appears can be predicted or grasped in advance in the circuit design stage or the operation check stage, so that the appearance timing of the multi-value hazard and the “synchronization signal (or clock pulse signal etc.) input to the transistor 61” Can be rubbed together.
For example, during the “period in which the binary hazard appears in the drain output signal of the transistor 17”, the input synchronization signal of the transistor 61 is set to a low level or a high level. Ignore the output signal and continue to hold the previous hold signal (or hold data).
On the other hand, the D-type flip-flop is set so that the input synchronization signal of the transistor 61 falls during “a period in which the binary hazard does not appear in the drain output signal of the transistor 17 and the drain output signal is stable”. 27 takes in the drain output signal, holds it as a new holding signal (or holding data), and outputs it to the transistor 41 as it is.
Similarly, the D-type flip-flop 27 is configured to “rewrite its holding signal (or holding data)” and “hold / hold the new / holding signal (or new / holding data) based on the output synchronization signal of the transistor 61. Since the “output” is performed, the D-type flip-flop 27 outputs the “binary signal in which the binary hazard is removed from the binary signal being transmitted” to the subsequent on / off driving means. (Transistors 41, 37, etc.).
As described above, the first embodiment of FIG. 1 can treat a multi-value hazard as a binary hazard in the middle of signal transmission, so that it is removed by applying the conventional binary hazard removal circuit and method. Can do.

■ Explanation of operation of synchronous type multi-value logic circuit ■
In the first embodiment shown in FIG. 1, when the gate of the transistor 41 is connected to the Q terminal of the D-type flip-flop 27, the present inventor has described the first embodiment as “synchronous NEVEN circuit” or “synchronous NOT”. Circuit ". The circuit operation is as follows.
The “synchronizing signal generating means 60, the transistor 61 and the synchronizing signal supplying means comprising the resistors 26 and 28” supply the synchronizing signal to the CP terminal of the D-type flip-flop 27. The flop 27 takes in the determination result signal from the transistor 17.
If shows a positive output signal of the intake discrimination result signal, that Q terminals may "input terminal T _in the input integer N _in the is an integer equal to the integer m", "on the transistor 41,37, etc. to form Since the “off driving means” drives the transistors 3 and 4 off, the output from the output terminal T _out is released.
However, if the positive output signal indicates that it is not, the on / off driving means drives the transistors 3 and 4 on, so that the specific power supply potential v _m is output from the output terminal T _{out in} terms of circuit. In terms of logical values, the output specific integer m is output.
Thereafter, the output state continues until the D-type flip-flop 27 takes in the next discrimination result signal from the transistor 17 based on the synchronization signal. Thereafter, similarly, the next determination result signal is taken in, and the same thing is repeated.

On the other hand, when the gate of the transistor 41 is connected to the Q-bar terminal of the D-type flip-flop 27 in the first embodiment shown in FIG. Circuit ".
Since this circuit operation is a negative operation of the “synchronous NEVEN circuit”, the output from the output terminal T _out is just the opposite.

● Instead of the D-type flip-flop 27, a combination of “binary 3-state buffer improved to be conductive / non-conductive by edge trigger” and “binary memory means at the subsequent stage” or “ “Two stages connected to the preceding stage and the subsequent stage” (→→ substantially binary flip-flop means) may be used. (Derived Example)
● Also, there are three types of trigger methods in which the binary synchronous flip-flop means and binary three-state buffer means operate based on the synchronous signal (or clock pulse signal, etc.). It is also possible to change to another trigger method. (Derived Example)
B) Level trigger method b) Plus / minus edge trigger method c) Pulse trigger method (= master / slave method)
Furthermore, by reconnecting the drain of the transistor 3 from the power line V _m to any _one of the other power lines V _{0 to} V _m−1 , the specific integer for output is changed from m to 0 to (m−1). It can be changed to any one of these.
These things (the above combination, the above trigger methods, and the above-described connection change of the power supply line) are the same for the other embodiments.
P. Of "Introduction to Illustrated Digital Circuit". 79-p. 88. The 4th edition was published on April 25, 2008 by Nippon Riko Publishing Co., Ltd. Author: Tsuguo Nakamura. Reference: Each trigger method.

The second embodiment shown in FIG. 2 is derived from the first embodiment shown in FIG. 1 or its derivative embodiments. As described above (6th to 10th lines of paragraph number [0049]), “determining whether the one input integer N _in is equal to or not the one input specific integer m” means “the one It is the same as “determining whether or not the input integer N _in is between the two input specific integers (m−1) and (m + 1)”.
The first embodiment of FIG. 1 is a case where the number of integers between the two input specific integers is one, but the second embodiment of FIG. 2 is a case where the number is two or more . For this reason, “whether the one input integer N _in is one of the integers between the two input specific integers (= is equal to) or neither (= is equal to either) In other words, the second embodiment of FIG.
The second embodiment of FIG. 2 is “in the first embodiment of FIG. 1 or its derivatives, the connection between the source and back gate of the transistor 1 and the back gate of the transistor 17” and the power supply line V _{m + 1} is temporarily disconnected, and the source, etc. _{Is “} reconnected to any one power supply line V _H of the power supply line V _{m + 2} to the power supply line V _n−1 ”. That is, m + 2 ≦ H ≦ n−1.
However, if there is a “built-in clamp diode whose one end is connected to the power supply line V _{m + 1} ” at the D terminal, a power supply short-circuit prevention resistor is provided between the drain of the transistor 17 and the “connection point between the resistor 21 and the D terminal”. Need to be inserted and connected. (A kind of matching)
As a result, in the case of the following NIN circuit or IN circuit, two specific integers for input in the second embodiment are an integer (m−1) and “the number of the reconnected power line, that is, an integer (m + 2) ˜ (N−1) ”becomes one integer H” corresponding to the power supply line. Details of this will be described later (paragraph numbers [0062 to 0066]).
Note that by reconnecting the drain of the transistor 3 from the power line V _m to any _one of the other power lines V _{0 to} V _m−1 , the output specific integer is changed from m to 0 to (m−1). It can be changed to any one.

In the second embodiment shown in FIG. 2, when the gate of the transistor 41 is connected to the Q terminal of the D-type flip-flop 27, the present inventor described the second embodiment as “synchronous (multi-value specific value) NOBETWEEN (= no. "Between. Negation of BETWEEN." Or "Synchronization type (multi-value specific value) NIN (= Nin. IN negation.) Circuit" or "Synchronization type (multi-value specific value) OUT ( = Out) circuit ”. Of course, if the D-type flip-flop 27 and the like are removed in these circuits and the gate of the transistor 41 is directly connected to the anode of the diode 35, these circuits become asynchronous.
However, in this case, the two specific integers of the IN circuit and the NIN circuit are (m−1) and H, but the two specific integers of the OUT circuit are m and (H−1). These will be described in detail later (paragraph numbers [0062 to 0066]) .
The circuit operation is as follows. The “synchronizing signal generating means 60, the transistor 61 and the synchronizing signal supplying means comprising the resistors 26 and 28” supply the synchronizing signal to the CP terminal of the D-type flip-flop 27. The flop 27 takes in the determination result signal from the transistor 17.
Long as the positive output signal of the intake discrimination result signal, i.e. Q terminal indicates that the "input integer N _in the input terminal T _in is an integer there between the integer H integer (m-1)", " Since the on / off driving means formed by the transistors 41 and 37 etc. drives the transistors 3 and 4 off, the output from the output terminal T _out is released.
However, if the positive output signal indicates that it is not, the on / off driving means drives the transistors 3 and 4 on, so that the specific power supply potential v _m is output from the output terminal T _{out in} terms of circuit. In terms of logical values, the output specific integer m is output.
Thereafter, the output state continues until the D-type flip-flop 27 takes in the next discrimination result signal from the transistor 17 based on the synchronization signal. Thereafter, similarly, the next determination result signal is taken in, and the same thing is repeated.

On the other hand, in the second embodiment, when the gate of the transistor 41 is connected to the Q-bar terminal of the D-type flip-flop 27, the present inventor described the second embodiment as “synchronous (multi-value specific value) BETWEEN (= Between). Circuit ”or“ Golf terminology, “synchronous type (multi-value specific value) IN circuit” or “synchronous type (multi-value specific value) NOUT (= Now, negation of OUT) circuit” ”.
Since this circuit operation is a negative operation of the “synchronous NIN circuit”, the way of output from the output terminal T _out is just opposite.

Of course, in these synchronous “ N IN , O UT” circuits, the D-type flip-flop 27 and the like are removed, and the power supply from both power supply lines V _{m + 1} and V _m is taken between the gate of the transistor 41 and the anode of the diode 35. If the binary inverter circuit "is connected and the drain signal of the transistor 17 is inverted, these circuits become asynchronous" IN, NOUT "circuits.
However, in the case of the synchronous OUT circuit and the synchronous NOUT circuit, the two specific integers for input are the integer m and ““ the number of the power line reconnected, that is, [of integers (m + 2) to (n−1). , An integer (H−1) ”obtained by subtracting 1 from one integer H]” corresponding to the power supply line. This is true even for asynchronous types. Details of this will be described later (paragraph numbers [0064 to 0065]).

The reason why the IN circuit and the NIN circuit are referred to based on the IN logic and the NIN logic is that “a specific integer a, b (where N−1 ≧ b ≧ a + 2 ≧ 2) If two are specified, the integer string is “an inner integer part consisting of [one or more integers] sandwiched between the two specified integers”, ie, each of the two specified integers. Of the three integers separated by the two specific integers, the inner integer part consisting of [one or more integers] inside it and the inner part not included in the inner integer part This is because it can be divided into “negative integer parts (including integers a and b)”.
Therefore, the present inventor uses the inner integer part of the former as a numerical discriminant criterion, “multi-value BETWEEN logic (Between) logic or multi-value IN (in) logic”, abbreviated “BETWEEN logic or IN logic”. On the other hand, the inner negative integer part of the latter is used as a numerical discriminant criterion, and “multi-valued NOBETWEEN (no Between) logic or multi-valued NIN (nin) logic” is abbreviated as “NOBETWEEN logic or NIN logic”. I decided to call it.
Note that “IN” has a smaller number of characters, and since it begins with a vowel, the negation is convenient because it is sufficient to add “N” in front of it to “NIN”. In addition, the present inventor already has a multi-value specific value OVER logic (abbreviated OVER logic), a multi-value specific value UNDER (under) logic (abbreviated UNDER logic), a multi-value specific value EVEN (abbreviated) logic (abbreviated). EVEN logic) is used, so it is convenient to unify the golf terms so that it is easy to remember.

Here, the relationship between each of the IN logic and the NIN logic and the numerical value discrimination criteria and each of the logic outputs is summarized as follows.
● IN logic (also known as BETWEEN logic):
It is determined whether the one input integer N _in is one of its inner integer parts. That is, it is determined whether or not the one input integer N _in is an integer between the specific integers a and b. However, N is a multi-value number (N of N values), and N−1 ≧ b ≧ a + 2 ≧ 2.
Therefore,
If b> N _in > a, output a predetermined output specific integer,
If N _in ≧ b or a ≧ N _in , the output is released.
NIN logic (also known as NOBETWEEN logic):
Since it is negative of IN logic, it is determined whether or not that one input integer N _in is one of its inner negative integer parts. That is, the output method is opposite to the IN logic.
Therefore,
If b> N _in > a, release the output,
If N _in ≧ b or a ≧ N _in , a predetermined specific integer for output is output.

There is another way of calling, thinking. Specific integers a and b (where N-1> b ≧ a + 2> 2) in an integer string in which integers 0 to (N−1) are sequentially arranged. ) If two are specified, the integer string is expressed as follows: “If each of the two specific integers is regarded as a trap, it consists of a plurality of integers outside the three parts separated by the two specific integers. It can also be divided into “outer integer part” and “outer negative integer part not included in the outer integer part (including two specific integers)”.
Therefore, the present inventor uses the former outer integer part as a numerical discrimination criterion and calls it “multi-valued OUT (out) logic, abbreviated as OUT logic”, while the latter outer negative integer part is used as a numerical discrimination criterion. We decided to call it "multi-valued NOUT logic".
Note that the difference between OUT logic and NIN logic is that the two specific integers do not include OUT but include NIN. The difference between the IN logic and the NOUT logic is that the two specific integers do not include the IN, but include the NOUT. That is, how to determine the values of both specific integers differs between the former multi-valued logic (OUT and NIN) and between the latter multi-valued logic (IN and NOUT) as follows.
For example , OUT (a, b) = NIN (a−1, b + 1), IN (a, b) = NOUT (a + 1, b−1), that is, NOUT (a, b) = IN (a−1, b + 1). It holds. However, two integer values in each parenthesis (parentheses) represent two specific integers for input. Of course, these things are true for both the asynchronous type and the synchronous type. However, the synchronous condition and the latching condition are the same for the synchronous type.

Here, the relationship between each (numerical value) discrimination criterion of OUT logic and NOUT logic and each logic output is summarized as follows.
● OUT logic:
It is determined whether the one input integer N _in is one of its outer integer parts. However, N is a multi-value number (N of N values), and N-1> b ≧ a + 2> 2 (* Note: this inequality is different from the case of IN logic).
Therefore,
If N _in > b or a> N _in , output a predetermined integer for output,
・ If b ≧ N _in ≧ a, the output is released.
● NOUT logic:
Since the OUT logic is negated, it is determined whether or not the one input integer is one of the outer negative integer parts. That is, the output method is the opposite of OUT logic.
Therefore,
If N _in > b or a> N _in , release the output,
If b ≧ N _in ≧ a, a predetermined specific integer for output is output.

The synchronous multi-value logic circuit described so far is of course included in the “multi-value logic means having a synchronous latching function” of the first invention. These are summarized below.
☆ Synchronous EVEN circuit (also known as synchronous EQUAL circuit)
☆ Synchronous NEVEN circuit (also known as synchronous NOT circuit)
☆ Synchronous IN circuit (also known as synchronous BETWEEN circuit)
☆ Synchronous NIN circuit (also known as synchronous NOBETWEEN circuit)
☆ Synchronous OUT (out) circuit ☆ Synchronous NOUT (now) circuit

The third embodiment shown in FIG. 3 is also derived from the first embodiment shown in FIG. As described above (6th to 10th lines of paragraph number [0049]), “determining whether the one input integer N _in is equal to or not the one input specific integer m” means “the one It is the same as “determining whether or not the input integer N _in is between the two input specific integers (m−1) and (m + 1)”.
In the first embodiment, the number of integers between the two input specific integers is one, but in the third embodiment, the number is two or more . For this reason, “whether the one input integer N _in is one of the integers between the two input specific integers (= is equal to) or neither (= is equal to either) In other words, the third embodiment can determine.
The third embodiment of FIG. 3 is “in the first embodiment of FIG. 1 or its derivative embodiments, the connection between the“ source and back gate of the transistor 2 ”and the power supply line V _m−1 is once disconnected, Reconnected to any one power supply line V _{G of} V ₀ to power supply line V _m-2 ”. That is, 0 ≦ G ≦ m−2.

In the third embodiment, when the gate of the transistor 41 is connected to the Q terminal of the D-type flip-flop 27, the present inventor described the third embodiment as “synchronous NIN circuit” or “synchronous NOBETWEEN circuit” or “synchronous type”. It is called “OUT circuit”.
The circuit operation is as follows. The “synchronizing signal generating means 60, the transistor 61 and the synchronizing signal supplying means comprising the resistors 26 and 28” supply the synchronizing signal to the CP terminal of the D-type flip-flop 27. The flop 27 takes in the determination result signal from the transistor 17.
Long as the positive output signal of the intake discrimination result signal, i.e. Q terminal indicates that "an integer there between the input integer N _in an integer G and an integer input terminal T _in (m + 1)", "the transistor 41 , 37, etc. "drives the transistors 3 and 4 off, so that the output from the output terminal _Tout is released.
However, if the positive output signal indicates that it is not, the on / off driving means drives the transistors 3 and 4 on, so that the specific power supply potential v _m is output from the output terminal T _{out in} terms of circuit. In terms of logical values, the output specific integer m is output.
Thereafter, the output state continues until the D-type flip-flop 27 takes in the next discrimination result signal from the transistor 17 based on the synchronization signal. Thereafter, similarly, the next determination result signal is taken in, and the same thing is repeated.

On the other hand, when the gate of the transistor 41 is connected to the Q-bar terminal of the D-type flip-flop 27 in the third embodiment shown in FIG. Circuit "or" Synchronous NOUT circuit ".
Since this circuit operation is a negative operation of the “synchronous NIN circuit”, the way of output from the output terminal T _out is just opposite.

In the case of the IN circuit or the NIN circuit, the two specified integers for input are an integer (m + 1) and “the number of the reconnected power line, that is,“ integer 0 to (m−2) ”. One integer G "corresponding to the line. On the other hand, in the case of the OUT circuit and the NOUT circuit, the two specific integers for input are the integer m and ““ the number of the reconnected power line, that is, among the integers 0 to (m−2), Corresponding one integer G] ”plus one (G + 1)”.
Further, by reconnecting the drain of the transistor 3 from the power line V _m to any _one of the other power lines V _{0 to} V _m−1 , the output specific integer is changed from m to 0 to (m−1). It can be changed to any one.

The fourth embodiment shown in FIG. 4 is also derived from the first embodiment shown in FIG. "Part one input integer N _in is possible to determine or not equal and its one input for a specific integer m", "" one of its inputs the integer N _in is for the first input before the description It is the same as “determining whether it is larger than the specific integer (m−1) and smaller than the second input specific integer (m + 1)” or not.
Then, “determining whether the one input integer N _in is between the two input specific integers a and b (≧ a + 2) or two integers” is “the one input integer. It is the same as “determining whether N _in is larger than the first input specific integer a and smaller than the second input specific integer b” or not.
Therefore, a part of the discriminating function of “Embodiment 1 of FIG. 1 or its derivative embodiments”, that is, “determines whether the one input integer N _in is greater than or less than the first input specific integer a. The fourth embodiment in which “function” is eliminated can be a synchronous UNDER (under) circuit or a synchronous NUNDER circuit (= negation of a synchronous UNDER circuit).
Therefore, the fourth embodiment of FIG. 4 is “in the first embodiment of FIG. 1 or its derivatives, the transistors 2 and 17, the diode 35 and the resistor 20 are removed, The “connection point” is reconnected to the drain of the transistor 1 ”.

In the fourth embodiment shown in FIG. 4, when the gate of the transistor 41 is connected to the Q terminal of the D-type flip-flop 27, the inventor described the fourth embodiment as “synchronous NUNDER circuit” or “synchronous OVER (over)”. It is called a circuit. Of course, both and input specific integers are different.
The circuit operation is as follows. The “synchronizing signal generating means 60, the transistor 61 and the synchronizing signal supplying means constituted by the resistors 26 and 28” supply the synchronizing signal to the CP terminal of the D-type flip-flop 27. Based on this synchronizing signal, the D-type flip flop 27 is the transistor 1 or we adopt the determination result signal.
If positive output signal of the intake discrimination result signal, i.e. Q terminal indicates that the "input integer N _in the input terminal T _in is an integer (m + 1) is smaller than the integer", the transistor 41,37, etc. to form Since the “on / off driving means” drives the transistors 3 and 4 off, the output from the output terminal T _out is released.
However, if a positive output signal is "otherwise" or "input integer N _in the input terminal T _in is an integer (m + 1) is greater than or equal to an integer" indicates the its on-off driving means transistor Since the circuits 3 and 4 are turned on, the specific power supply potential v _m is output from the output terminal T _{out in} terms of a circuit, and the output specific integer m is output in terms of a logical value.
Thereafter, the output state continues until the D-type flip-flop 27 takes in the next discrimination result signal from the transistor 1 based on the synchronization signal. Thereafter, similarly, the next determination result signal is taken in, and the same thing is repeated.

On the other hand, when the gate of the transistor 41 is connected to the Q-bar terminal of the D-type flip-flop 27 in the fourth embodiment shown in FIG. (Now bar) circuit (= negation of synchronous OVER circuit). Of course, both and input specific integers are different.
Since this circuit operation is a negative operation of the “synchronous NUNDER circuit” or “synchronous OVER circuit”, the output method from the output terminal T _out is just opposite.

The difference between UNDER logic and NOVER logic is that UNDER does not include one specific integer for its own use, and NOVER includes one specific integer for its own use. The difference between the OVER logic and the NUNDER logic is “OVER does not include one specific integer for its own use, and NUNDER includes one specific integer for its own use”. Therefore, UNDER (m + 1) = NOVER (m) and NUNDER (m + 1) = OVER (m) hold. However, one integer value in each parenthesis represents one specific integer for input.
In addition, these things are valid for both the asynchronous type and the synchronous type, but naturally, the synchronous condition and the latching condition are the same in the synchronous type.
Furthermore, by reconnecting the “source and back gate of transistor 1” from the power supply line V _{m + 1} to any _one of the other power supply lines V _{m + 2 to} V _n−1 , each of the UNDER circuit and the NUNDER circuit is specified for each input. The integer can be changed from (m + 1) to “any one of (m + 2) to (n−1)”. However, when a “built-in clamp diode having one end connected to the power supply line V _{m + 1} ” is connected to the D terminal of the D-type flip-flop 27, the power supply short-circuit prevention resistor is connected to the drain of the transistor 1 It is necessary to connect between the “connection point of the D terminal and the resistor 21”.
Then, by reconnecting the drain of the transistor 3 from the power line V _m to any _one of the other power lines V _{0 to} V _m−1 , the output specific integer is changed from m to 0 to (m−1). It can be changed to any one.

The fifth embodiment shown in FIG. 5 is also derived from the first embodiment shown in FIG. "Part one input integer N _in is possible to determine or not equal and its one input for a specific integer m", "" one of its inputs the integer N _in is for the first input before the description It is the same as “determining whether it is larger than the specific integer (m−1) and smaller than the second input specific integer (m + 1)” or not.
Then, “determining whether the one input integer N _in is between the two input specific integers a and b (≧ a + 2) or two integers” is “the one input integer. It is the same as “determining whether N _in is larger than the first input specific integer a and smaller than the second input specific integer b” or not.
For this reason, a part of the discriminating function of “Embodiment 1 of FIG. 1 or its derivative embodiments”, that is, “a function of discriminating whether the one input integer is smaller or smaller than the second input specific integer b” The fifth embodiment that eliminates the above can be a synchronous OVER circuit or a synchronous NOVER circuit (= negation of the synchronous OVER circuit).
Therefore, the fifth embodiment of FIG. 5 is “the transistor 1 is removed in the first embodiment of FIG. 1 or its derivative embodiments, and“ the connection point between the source of the transistor 17 and the resistor 20 ”is directly connected to the power line V _{m + 1} ”. It is.

When the gate of the transistor 41 is connected to the Q terminal of the D-type flip-flop 27 in the fifth embodiment shown in FIG. Or “synchronous UNDER circuit”. Of course, both and input specific integers are different.
The circuit operation is as follows. The “synchronizing signal generating means 60, the transistor 61 and the synchronizing signal supplying means comprising the resistors 26 and 28” supply the synchronizing signal to the CP terminal of the D-type flip-flop 27. The flop 27 takes in the determination result signal from the transistor 17.
If positive output signal of the intake discrimination result signal, i.e. Q terminal indicates that the "input integer N _in the input terminal T _in is an integer (m-1) integer greater than", transistors 41,37 etc. Since the “on / off driving means to be formed” drives the transistors 3 and 4 off, the output from the output terminal T _out is released.
However, if a positive output signal is "otherwise" or "input integer N _in the input terminal T _in is an integer (m-1) is less than or equal to the integer" indicates the its on-off driving means Since the transistors 3 and 4 are turned on, the specific power supply potential v _m is output from the output terminal T _{out in} terms of a circuit, and the output specific integer m is output in terms of a logical value.
Thereafter, the output state continues until the D-type flip-flop 27 takes in the next discrimination result signal from the transistor 17 based on the synchronization signal. Thereafter, similarly, the next determination result signal is taken in, and the same thing is repeated.

On the other hand, when the gate of the transistor 41 is connected to the Q-bar terminal of the D-type flip-flop 27 in the fifth embodiment shown in FIG. It is called a circuit. Of course, both and input specific integers are different.
Since this circuit operation is a negative operation of the “synchronous NOVER circuit” or the “synchronous UNDER circuit”, the output method from the output terminal T _out is just opposite.

The difference between UNDER logic and NOVER logic is that UNDER does not include one specific integer for its own use, and NOVER includes one specific integer for its own use. The difference between the OVER logic and the NUNDER logic is “OVER does not include one specific integer for its own use, and NUNDER includes one specific integer for its own use”. Therefore, OVER (m−1) = NUNDER (m) and NOVER (m−1) = UNDER (m) hold. However, one integer value in each parenthesis represents one specific integer for input.
In addition, these things are valid for both the asynchronous type and the synchronous type, but naturally, the synchronous condition and the latching condition are the same in the synchronous type.
Furthermore, by reconnecting the source of the transistor 2 from the power supply line V _m-1 to any _one of the other power supply lines V _{0 to} V _m-2 , specific integers for input and input of each of the OVER circuit and the NOVER circuit ( m-1) can be changed to “any one of 0 to (m-2)”.
Then, by reconnecting the drain of the transistor 3 from the power line V _m to any _one of the other power lines V _{0 to} V _m−1 , the output specific integer is changed from m to 0 to (m−1). It can be changed to any one.

The synchronous multi-value logic circuit described so far is of course included in the “multi-value logic circuit having a synchronous latching function” of the first invention. These are summarized below.
☆ Synchronous OVER circuit ☆ Synchronous EVEN circuit = Synchronous EQUAL circuit ☆ Synchronous UNDER circuit ☆ Synchronous NOVER circuit ☆ Synchronous NEVEN circuit = Synchronous Type NOT circuit ☆ Synchronous type NUNDER circuit

It can derive from Example 1 of FIG. 1 to Example 6 of FIG. In Example 6 of FIG. 6, the diode 10 in FIG. 6 may or may not be connected.
“Embodiment 6 in FIG. 6 when the diode 10 is not connected” refers to “the connection point between the source of the transistor 4, the drain of the transistor 37, and one end of the resistor 15” in the embodiment 1 of FIG. the directly connected to the power supply line V _m, in the above (paragraph [0030] in) example was changed to the reverse conducting pull-down switching means pull switching means from the bidirectional controllable pull switching means that " is there.
(Derived Example of Example 1 in FIG. 1)
“Furthermore, a diode was inserted and connected between the drain of the transistor 4 and the output terminal T _out , and the above-described pull switching means was changed from the bidirectional controllable pull switching means to the reverse blocking pull down switching means. “Example” is “Example 6 of FIG. 6 when the diode 10 is connected”. (Derived Example of Example 1 in FIG. 1)
As with these circuit configuration changes, the “reverse conduction type pull down / down” is similarly applied from “Embodiment 2, 3, 4 or 5, or Embodiment 8 described later, or their respective derivatives”. Each of the embodiments can be derived from “with either switching means or reverse blocking pull-down switching means”.
In each of the embodiments of the sixth embodiment of FIG. 6 and its derivatives, the connection of the pull switching means is changed from the power supply line V _m to any _one of “power supply line V ₀ to power supply line V _m−1”. , The new specific embodiments in which the input specific integer (value) and the output specific integer (value) are different from each other are possible. (New and derived examples)
“Electrical Society of Electrical Technical Terminology No. 9 Power Electronics, Author: “The Electrotechnical Society, Electrical Terminology Standards Special Committee”, “The Institute of Electrical Engineers, Semiconductor Power Converter Terminology Subcommittee”, Editor: The Institute of Electrical Engineers of Japan, Corona Corp. Issued the first revised edition of Japan. "Bidirectional switch, bidirectional controllable switch, reverse conducting switch, reverse blocking switch". “Valve” has almost the same meaning as “switch”.

It can derive from Example 1 of FIG. 1 to Example 7 of FIG. In the seventh embodiment shown in FIG. 7, the diode 12 in FIG. 7 may be connected or not connected.
“Embodiment 7 in FIG. 7 when the diode 12 is not connected” refers to “the connection point between the source of the transistor 3, the drain of the transistor 37, and one end of the resistor 15” in the embodiment 1 of FIG. _{Is an} embodiment in which a reverse conduction type pull-up switching means is configured by connecting the output terminal _Tout to the "." (Derived Example of Example 1 in FIG. 1)
Meanwhile, in Example 1 of "Figure 1" Embodiment 7 of Fig. 7 when the diode 12 is connected "to connect the diode 12 instead of the transistor 4, and the cathode terminal and the output terminals T _out, An embodiment in which a reverse blocking type pull-up switching means is constituted by a series circuit of a diode 12 and a transistor 3 ”. (Derived Example of Example 1 in FIG. 1)
Similar to these circuit configuration changes, the “reverse conduction type pull- up circuit ” is similarly applied from “Embodiment 2, 3, 4 or 5, or Embodiment 8 described later, or a derivative embodiment thereof”. Each of the embodiments can be derived from “with either switching means or reverse blocking pull- up switching means”.
Then, in each of the seventh embodiment of FIG. 7 and each of its derivatives, the connection of the pull switching means is changed from the power line V _m to any _one of “power line V ₀ to power line V _m−1”. , The new specific embodiments in which the input specific integer (value) and the output specific integer (value) are different from each other are possible. (New and derived examples)

The eighth embodiment shown in FIG. 8 is a “multi-value logic circuit having a synchronous latching function” or a “multi-value hazard removal circuit ” in which the numerical value discriminating means in the first embodiment shown in FIG. is there. “The circuit portion of the transistors 31 to 33, the diode 34, and the resistors 20 to 21, 62, and 67” is the new and numerical value discriminating means replaced.
However, when S = 1, the relationship of “n−1> H ≧ G ≧ m + 1” and “m ≧ 0 (zero)”, that is, “n-2> H−1 ≧ G-1 ≧ m ≧ 0 (zero)”. There is a relationship.

When H = G, the determination content of the eighth embodiment in FIG. 8 is “equal or not equal” in the above (in paragraph numbers 0030 to 0032). For the sake of clarity, the logical operation in which the D input signal and the Q output signal of the D-type flip-flop 27 coincide with each other while ignoring the time delay associated with the synchronous operation is as follows.
Its input numerical value _{N in} becomes the transistor 31～33,37 is off when the H, the transistor 41,3,4 is turned on, the output terminal _{T out} outputs the specific power supply potential _{v m.} On the other hand, when the input numerical value N _in is other than H, the transistors “31, 33” or 32 ”, 37 are turned on and the transistors 41, 3, 4 are turned off, so that the output from the output terminal T _out is released. The After that, the normal operation of the D-type flip-flop 27 is added.
For this reason, the present inventor calls this “multi-valued logic circuit having a synchronous latching function” as a “synchronous EQUAL circuit” or “synchronous EVEN circuit”.
However, simply disconnecting and connecting the gate terminal of the transistor 41 from the Q terminal to the terminal Q, for both the on-off operation of the transistors 3 and 4 is opposite, "specific potential v _m outputs an open output of the output terminal T _out "Is also the opposite, the present inventor calls this" multi-valued logic circuit having a synchronous latching function "as a" synchronous NOT (knot) circuit "or" synchronous NEVEN (neven) circuit ".

In the case of “H ≠ G, that is, H> G”, the determination content of the eighth embodiment of FIG. 8 is “between two input specific integers (H + 1) and (G−1)” (paragraph numbers 0030 to 0032). Or not ”. For the sake of clarity, the logical operation in which the D input signal and the Q output signal of the D-type flip-flop 27 coincide with each other while ignoring the time delay associated with the synchronous operation is as follows.
When “H + 1> (input numerical value N _in )> G−1”, that is, when “H ≧ (input numerical value N _in ) ≧ G”, the output terminal T _out outputs the specific power supply potential v _m , while “( Output when “input numerical value N _in ) ≧ H + 1 or G−1 ≧ (input numerical value N _in )”, ie, “(input numerical value N _in )> H or G> (input numerical value N _in )”. The output from the terminal _Tout is opened. After that, the normal operation of the D-type flip-flop 27 is added.
For this reason, the present inventor refers to this “multi-valued logic circuit having a synchronous latching function” as “a synchronous BETWEEN circuit or a synchronous IN circuit whose two input specific integers are (H + 1) and (G−1)”. , “Synchronous NOUT circuit in which two input specific integers are H and G (= negation of synchronous OUT circuit)”.
However, simply disconnecting and connecting the gate terminal of the transistor 41 from the Q terminal to the terminal Q, for both the on-off operation of the transistors 3 and 4 is opposite, the "specific power supply potential v _m output of the output terminal T _out opening The output is also the opposite. Therefore, the present inventor refers to this “multilevel logic circuit having a synchronous latching function” as “a synchronous NOBETWEEN circuit or a synchronous NIN circuit in which two input specific integers are (H + 1) and (G−1)”. , “Synchronous OUT circuit in which two input specific integers are H and G”.

By the way, the difference between “synchronous IN circuit and synchronous NOUT circuit” in which the input specific integers of the eighth embodiment of FIG. 8 are H and G is that the former does not include the input specific integers. Is to include. Therefore, in order for the synchronous IN circuit to include H and G, the two specific integers for input are (H + 1) and (G-1).
Similarly, the difference between the synchronous OUT circuit and the synchronous NIN circuit whose two input specific integers are (H + 1) and (G-1) is that the former does not include the input specific integer two, and the latter includes it. That is. Therefore, in order for the synchronous OUT circuit to include (H + 1) and (G-1), the two specific integers for input are H and G.

In the eighth embodiment shown in FIG. 8, both the case of H = G and the case of “H ≠ G, that is, H> G”, the subsequent “pull-up resistor 26 or“ 26, 28 ”and D-type flip-flop 27”. These operations are the same as those in the first embodiment shown in FIG. 1 (paragraph numbers [0055 to 0056]).
Further, what is described in paragraph numbers [0057, 0071 to 0081] can be similarly applied to Example 8. The same applies to each of the other embodiments using the numerical value discriminating means of the eighth embodiment.
Further, by reconnecting the drain of the transistor 3 from the power line V _m to any _one of the other power lines V _{0 to} V _m−1 , the output specific integer is changed from m to 0 to (m−1). It can be changed to any one.

In spite of this, the description and paragraph number [0033] of Japanese Patent Application Laid-Open No. 2005-236985 includes the asynchronous “AND”, “NAND”, “OR”, and “NOR” groups and the asynchronous “BETWEEN” and “NOBETWEEN”. ] Is described.
Similarly, a group of asynchronous “AND”, “NAND”, “OR”, “NOR” and asynchronous “IN”, “NIN”, “OUT”, “NOUT” (Naut) ”group combinations are considered as follows.
However, basically, AND means “all of the plurality of input integers are ...”, and OR means “at least one of the plurality of input integers is ...”.
In addition, when the present inventor first proposed these classifications / classification names, some of these multi-valued logic functions are given because each function has been made redundant. Although overlapping, if the Houji Algebra is widely used, these circuit names and functions will be converged for ease of use.

■■ Regarding various IN circuits and various NIN circuits ■■
● AND / IN circuit (also known as AND / BETWEEN circuit)
If all of the plurality of input integers are “integers between the two input specific integers a and b”, the output specific integer is output; otherwise, the output is released. In other words, if at least one of the plurality of input integers is “an integer less than or equal to a (≦ a), or an integer greater than or equal to b (≧ b)”, the output is released. To do.
In this case, since b ≧ a + 2, there is of course no integer with “≧ b” and “a ≧”.

☆☆☆☆☆☆☆
In the set theory, the set “is A or B” becomes the union of the set “is only A”, the set “is only B”, and the set “is A and is B (common part)”.
Therefore, if the set “A and B” is empty, the set “A or B” becomes the union of the set “only A” and the set “only B”.

NAND / IN circuit (also known as NAND / BETWEEN circuit)
Since this circuit is the negation of the AND / IN circuit, the output method is opposite. Therefore, if all of the plurality of input integers are “integers between the two / input specific integers a and b”, the output is released; otherwise, the output specific integer is output. . That is, if at least one of the plurality of input integers is “an integer less than or equal to a (≦ a), or an integer greater than or equal to b (≧ b)”, the output specification Output an integer.
● AND / NIN circuit (also known as AND / NOBETWEEN circuit)
If all of the input integers are “integer integers less than or equal to a (≦ a), or integers greater than or equal to b (≧ b)”, the output specific integer is output, otherwise , Release its output. That is, if at least one input integer among the plurality of input integers is “an integer between the two input specific integers a and b”, the output is released.
NAND / NIN circuit (also known as NAND / NOBETWEEN circuit)
Since this circuit is a negative of the AND / NIN circuit, the output method is the opposite. Therefore, if all of the input integers are “integer integers less than or equal to a (≦ a), or integers greater than or equal to b (≧ b)”, the output is released; The output specific integer is output. That is, if at least one input integer among the plurality of input integers is “an integer between the two input specific integers a and b”, the output specific integer is output.

● OR / IN circuit (also known as OR / BETWEEN circuit)
If at least one of the plurality of input integers is “an integer between the two input specific integers a and b”, the output specific integer is output; otherwise, the output is output. Open. That is, if all of the plurality of input integers are “an integer smaller than or equal to a (≦ a), or an integer larger than or equal to b (≧ b)”, the output is released.
● NOR / IN circuit (also known as NOR / BETWEEN circuit)
Since this circuit is the negation of the OR / IN circuit, the output method is opposite. Therefore, if at least one of the plurality of input integers is “an integer between the two input specific integers a and b”, the output is released. Otherwise, the output specific is set. Output an integer. That is, if all of the plurality of input integers are “an integer smaller than or equal to a (≦ a) or an integer larger than or equal to b (≧ b)”, the output specific integer is output.
● OR / NIN circuit (also known as OR / NOBETWEEN circuit)
If at least one of the plurality of input integers is “an integer less than or equal to a (≦ a), or an integer greater than or equal to b (≧ b)”, the output specific integer is output, Otherwise, the output is released. That is, if all of the plurality of input integers are “integers between the two / input specific integers a and b”, the output is released.
NOR / NIN circuit (also known as NOR / NOBETWEEN circuit)
Since this circuit is the negation of the OR / NIN circuit, the output method is opposite. Therefore, if at least one of the plurality of input integers is “an integer less than or equal to a (≦ a), or an integer greater than or equal to b (≧ b)”, the output is released, and so on. Otherwise, the output specific integer is output. In other words, if all of the plurality of input integers are “an integer between the two / input specific integers a and b”, the output specific integer is output.

■■ Regarding various OUT circuits and various NOUT circuits ■■
When both the input specific integers are a and b, they are as follows.
AND / OUT circuit If all of the input integers are "integer less than a (<a) or integer greater than b (>b)", it outputs a specific integer for output, and so on The output is released. That is, if at least one of the plurality of input integers is “an integer equal to a or b, or an integer between a and b”, the output is released.
NAND / OUT circuit This circuit is the negation of the AND / OUT circuit, so the output method is the opposite. Therefore, if all of the plurality of input integers are "integer less than a (<a) or integer greater than b (>b)", the output is released, otherwise the output specific Output an integer. That is, if at least one of the plurality of input integers is “an integer equal to a or b, or an integer between a and b”, the output specific integer is output.
AND / NOUT circuit If all of the multiple input integers are "an integer equal to a or b, or an integer between a and b", a specific integer for output is output; otherwise, Release the output. That is, if at least one of the plurality of input integers is “an integer smaller than a (<a) or an integer larger than b (> b)”, the output is released.
NAND / NOUT circuit Since this circuit is the negation of the AND / NOUT circuit, the output method is the opposite. Therefore, if all of the plurality of input integers are "an integer equal to a or b, or an integer between a and b", the output is released, and if not, the output specific integer is output. To do. That is, if at least one of the plurality of input integers is “an integer smaller than a (<a) or an integer larger than b (> b)”, the output specific integer is output.

OR / OUT circuit If at least one of the multiple input integers is "an integer less than a (<a) or an integer greater than b (>b)", a specific integer for output is output. Otherwise, open its output. That is, if all of the plurality of input integers are “an integer equal to a or b, or an integer between a and b”, the output is released.
NOR / OUT circuit Since this circuit is the negation of the OR / OUT circuit, the output method is the opposite. Therefore, if at least one of the plurality of input integers is “an integer smaller than a (<a) or an integer larger than b (> b)”, the output is released, otherwise, The output specific integer is output. That is, if all of the plurality of input integers are “an integer equal to a or b, or an integer between a and b”, the output specific integer is output.
OR / NOUT circuit If at least one of the input integers is “an integer equal to a or b, or an integer between a and b”, a specific integer for output is output. Otherwise, the output is released. That is, if all of the plurality of input integers are “an integer smaller than a (<a) or an integer larger than b (> b)”, the output is released.
NOR / NOUT circuit Since this circuit is the negation of the OR / NOUT circuit, the output method is the opposite. Therefore, if at least one of the plurality of input integers is “an integer equal to a or b, or an integer between a and b”, the output is released; otherwise, the output is output. Output a specific integer. That is, if all of the plurality of input integers are “an integer smaller than a (<a) or an integer larger than b (> b)”, the output specific integer is output.

The identities that hold for these multilevel logic circuits are summarized as follows. As a matter of course, “each of a plurality of logical variables, each of two specific integers for input, each of specific integers for output” and the like of each circuit are the same. Furthermore, if each circuit is synchronous, the synchronization conditions such as the synchronization frequency and the latching conditions are the same.
However, in the “IN circuit, NIN circuit” and “OUT circuit, NOUT circuit” that are the basis of each circuit, as described above, these two specific integers for input are shifted by one each.
* A) AND / IN circuit = NOR / NIN circuit * b) NAND / IN circuit = OR / NIN circuit * c) AND / NIN circuit = NOR / IN circuit * d) NAND / NIN circuit = OR / IN circuit * e ) AND / OUT circuit = NOR / NOUT circuit * f) NAND / OUT circuit = OR / NOUT circuit * g) AND / NOUT circuit = NOR / OUT circuit * h) NAND / NOUT circuit = OR / OUT circuit

These identities also mean "synchronously, mutually or synchronously, just call the same multi-value logic circuit with two names", but multi-value logically Has an important meaning.
For example, because NAND · IN logic is the negation of AND · IN logic, AND · IN logic and NAND · IN logic are complementary to each other, and NAND · IN logic and OR · NIN logic are the same. NIN logic is also complementary to each other. Similarly, NAND · IN logic and NOR · NIN logic are complementary to each other.
In this case, the “complementary relationship” is “when a predetermined number of logic variables are simultaneously given to the two logics, one of the logics always becomes the value of the specific integer for output, and the other logic is It means that the output is the opposite, that is, an open output ”.
Incidentally, for example, from the above item * a), AND / IN logic means “the combination of OR / NIN logic and NOT logic”, so that the synchronous AND / IN circuit is placed “after the synchronous OR / NIN circuit”. An asynchronous NOT circuit is connected, and a matching pull-up resistor or pull-down resistor is connected between both circuits "or" Synchronous NOT circuit is connected to the subsequent stage of the asynchronous OR / NIN circuit " However, it can be alternatively configured with a matching pull-up resistor or pull-down resistor connected between both circuits. However, “time delay, power loss, and multi-value hazard” However, it is also conceivable to use it for “time adjustment, timing adjustment, or matching of two logic signals”. In this case, both circuits can be considered to be synchronous.

FIG. 9 shows the “on / off drive means” and “bidirectional pull switching means” according to the ninth embodiment. As the pre-stage circuit portion including the D-type flip-flop 27, “Embodiments 1 to 5 shown in FIGS. 1 to 5” or “Embodiment 8 shown in FIG. 8” or “FIG. The pre-stage circuit portion in “Embodiment 14 shown” or “Embodiment 15 shown in FIG. 15 to be described later” is connected. “The circuit portion of the transistors 41, 22 to 25 (and the diode 36) and the resistor 15” is the on / off driving means, and the series circuit of the transistors 3 and 5 is the bidirectional pull switching means.
However, there is a case where there is no diode 36 indicated by a dotted line. In the case where there is no diode 36, when the potential of the output terminal T _out is higher than the power supply potential v _{m + 1} when the transistor 5 is driven off, the charging current of the gate-source capacitance of the transistor 5 Flows from the output terminal T _out to the power supply line V _{m + 1} through the transistor 5 built-in diode and the transistor 22.

Incidentally, remove the transistor 22～25,3,5 and the resistor 15 may be an output terminal _{T out} of the drain terminal of the transistor 41. In this case, the transistor 41 may be used as reverse conduction type pull-up switching means by forming the built-in diode, or a reverse blocking diode is connected in series with the transistor 41 as reverse blocking type pull-up switching means. Sometimes used. (Another example)
Alternatively, as in the sixth embodiment of FIG. 6, “a diode 10 is used instead of the transistor 5 to form a reverse blocking pull-down switching means together with the transistor 3” or “the transistor 5 is removed and the drain terminal of the transistor 3 is removed. Can be used as an output terminal T _out to constitute reverse conducting pull-down switching means ”. (Derived Example)
Or, "remove the transistor 3 constitutes a reverse conduction-type pull-up switching means is directly connected to the source of the transistor 5 to the power supply line V _m" as in the seventh embodiment of FIG. 7 or remove the "transistor 3, The source of the transistor 5 is directly connected to the power supply line V _m , and a diode is inserted and connected between the drain of the transistor 5 and the output terminal T _out , and this diode and the transistor 5 are connected in reverse blocking pull-up switching. Can also constitute "means". (Derived Example)
The same applies to “Embodiment 10 shown in FIG. 10” described later.

Furthermore, if the negative power supply terminal of the D-type flip-flop 27 is connected to the power supply line V _m-1, rather than power line V _m, D-type flip-flop 27 of the binary operates at its power supply voltage doubles, The transistor 41 and the resistor may be removed, and the Q terminal or the Q bar terminal may be connected to the common gate terminal of the transistors 22 and 23.
Moreover, the D-type flip-flop 27 may directly drive the transistors 3 and 5 on and off as long as the output current capacity of the Q terminal and the Q bar terminal is sufficiently large. That is, of the transistors 3 and 5, one gate is connected to the Q terminal and the other gate is connected to the Q bar terminal. In this case, the D-type flip-flop 27 also serves as the on / off driving means described above (paragraph number [0030]).
→→ Derived example of Example 17 of FIG. 17 to be described later (paragraph number [0112]).
The same applies to “Embodiment 10 shown in FIG. 10” and “Embodiment 11 shown in FIG. 11” described later.

FIG. 10 shows the “on / off drive means” and “bidirectional pull switching means” according to the tenth embodiment. As the pre-stage circuit portion including the D-type flip-flop 27, “Embodiments 1 to 5 shown in FIGS. 1 to 5” or “Embodiment 8 shown in FIG. 8” or “FIG. The pre-stage circuit portion in “Embodiment 14” or “Embodiment 15 shown in FIG. 15 described later” is connected.
9 differs from the ninth embodiment in that “the connection order of the transistors 3 and 5”, “how to connect the gates of the transistors 3 and 5” and “the on / off operation of the transistors 3 and 5 are opposite to each other”. Therefore, the logic is negative of the ninth embodiment ”.
However, in both the ninth embodiment of FIG. 9 and the tenth embodiment of FIG. 10, the gate is connected to the binary inverter circuit on the preceding stage in order to speed up the off-drive of the output terminal T _out side transistor first.

FIG. 11 shows the “on / off driving means” and the “bidirectional pull switching means” in the eleventh embodiment. As the pre-stage circuit portion including the D-type flip-flop 27, “Embodiments 1 to 5 shown in FIGS. 1 to 5” or “Embodiment 8 shown in FIG. 8” or “FIG. The pre-stage circuit portion in “Embodiment 14” or “Embodiment 15 shown in FIG. 15 described later” is connected.
In order to increase the off speed of the “bidirectional pull switching means formed by the transistors 3 to 6 and the diodes 9 to 12”, each gate can be reverse-biased.
If the transistors 3 and 6 and the diodes 9 and 12 are removed, the bidirectional switching means becomes reverse blocking pull-down switching means. On the other hand, if the transistors 4 and 5 and the diodes 10 and 11 are removed, the bidirectional switching means becomes reverse blocking pull-up switching means.
Japanese Patent No. 3423780 (bidirectional switching means and unidirectional switching means)

FIG. 12 shows “on / off drive means” and “bidirectional pull switching means” in the twelfth embodiment. As the pre-stage circuit portion including the D-type flip-flop 27, “Embodiments 1 to 5 shown in FIGS. 1 to 5” or “Embodiment 8 shown in FIG. 8” or “FIG. The pre-stage circuit portion in “Embodiment 14” or “Embodiment 15 shown in FIG. 15 described later” is connected. However, the power line V _m and the power line IV _m may be the same or completely different.
In the twelfth embodiment, since the “fully insulated bidirectional switching means” is used as the “pull switching means described above (paragraph number [0030]”), “the power supply line IV _m to which one of the switch terminals is connected”. "I may be either of the power supply line _{V 0} ~ power supply line _{V n-1.} In short, the power supply potential iv _m of the power supply line IV _m can be set freely.
The reason is as follows. When the transistors 41, 23, 24, 47 are on, the transistors 24, 47 and the diodes 49-50, 65-66 simultaneously gate reverse-bias “transistors 3-6 forming their bidirectional switching means” respectively. The forward bias capacitor 45 is charged. At this time, since the transistors 3 to 6 are turned off, the power supply line IV _m and the output terminal T _out are bidirectionally blocked from the gate-source portion, so that the power supply line V _{m + 1} and the power supply line V Both _m-1 are blocked in both directions.
On the other hand, when the transistors 41 and 23 are off and the transistor 22 is on, the “transistors 24 and 47 and the diodes 49 to 50 and 65 to 66” are off in both directions. due to being blocked in the power supply line V _{m + 1} and the power supply line V _m-1 two-way, completely trouble no it is in a conductive state a gate-source unit and the power supply line IV _m and the output terminal T _out. At this time, the capacitor 45 for gate forward bias simultaneously turns on all the “transistors 3 to 6 forming the bidirectional switching means”.
Patent No. 3423780 (fully insulated bidirectional switching means)

In the thirteenth embodiment shown in FIG. 13, “conditionally isolated bidirectional switching means” is used as “bidirectional pull switching means”. Potential of "subsequent circuit input and load the like connected to the output terminal T _out" certain power potential v _m and the power supply line V _m are both power supply potential v ₀ higher required there. Specific supply potential v _m as long as this potential condition is satisfied, it is possible to freely set the height of the particular power supply potential v _m.
Therefore, the value of the output specific integer m is not restricted to the values of the input specific integers “H and G”, and the output specific integer m is set to a free value between n−1 ≧ m ≧ 1. be able to.
The reason is as follows. When the transistors 47 and 48 are on, together with the diodes 49 and 50, the “bidirectional pull switching means formed by the transistors 3 and 4” is reverse-biased to drive off, and at the same time, the gate forward bias capacitor 45 is charged. . At this time, as long as the specific power source potential v _m and the potential of the output terminal T _out are higher than the power source potential v ₀ , the gate-source portion of the transistors 3 and 4 is disconnected from the power source line V _m and the output terminal T _out .
On the other hand, when the transistors 47 and 48 are off, the capacitor 45 is turned on by turning on the bidirectional pull switching means, that is, the transistors 3 and 4, so that the reverse voltage is _dioded from the power line V _m through the transistor 3. 49 and 50, both diodes are turned off. For this reason, since the gate-source portion is cut off from both power supply lines V ₀ and V ₋₁ , there is no problem even if the gate-source portion is electrically connected to the power supply line V _m and the output terminal T _out .
Japanese Patent No. 3321203 (conditional insulation type switching means)

Example 14 shown in FIG. 14 is an application of “Embodiment 8 shown in FIG. 8”. Although not shown, “Drawing 8” shown in FIG. The on / off driving means formed by the transistors 41 and 37, the diode 39 and the resistor 15 and the “bidirectional pull switching means in which the transistors 3 and 4 are connected in series” are connected. Alternatively, after the D-type flip-flop 27, the “on / off drive means and bidirectionality” shown in any one of “Embodiment 9 shown in FIG. 9” to “Embodiment 12 shown in FIG. 12” are provided. A "pull switching means" is connected.
14 includes “ON / OFF drive means and bidirectional pull switching” in “Embodiment 8 shown in FIG. 8”, “Embodiment 9 shown in FIG. 9”, or “Embodiment 11 shown in FIG. 11”. Consider the following four cases when "means" are connected.
◆ ◇ ◆ 1) When H = G:
In order to facilitate understanding now, "ignoring the time delay associated with the synchronous operation, logical operation was the D input signal and the Q output signal matches of the D-type flip-flop 27" or "original asynchronous “ Non-inversion / logic operation of multi-value logic circuit ” and “ its inversion / logic operation” are as follows.
◆ a) Non-inversion / logical operation;
Therefore one input for a specific integer is H, the input integer _{N in1, N in2} certain integer m output from the output terminal _{T out} if integer both H at the input terminal _{T in1, T in2} is output, if not The output from the output terminal _Tout is opened. (In the case of the original asynchronous / multi-valued logic circuit)
Therefore, the present inventor further calls the “multi-valued logic circuit having a synchronous latching function” of the fourteenth embodiment as a synchronous (multi-valued) AND circuit. (In the case of the synchronous multi-value logic circuit of the fourteenth embodiment)
◆ b) Inversion / logical operation;
If the input integers N _in1 and N _in2 are both integers H, the output from the output terminal T _out is released, otherwise the output specific integer m is output from the output terminal T _out .
(In the case of the original asynchronous / multi-valued logic circuit)
For this reason, when the gate terminal of the transistor 41 (in FIG. 8, FIG. 9, and FIG. 11) is reconnected from the Q terminal to the Q bar terminal in the fourteenth embodiment, The “logic circuit ” becomes “a circuit called by the present inventor a“ synchronous (multi-value) NAND circuit in which the input specific integer is H ””. (In the case of the synchronous multi-value logic circuit of the fourteenth embodiment)

◆ ◇ ◆ 2) If H> G:
In order to facilitate understanding now, "ignoring the time delay associated with the synchronous operation, logical operation was the D input signal and the Q output signal matches of the D-type flip-flop 27" or "original asynchronous “ Non-inversion / logic operation of multi-value logic circuit ” and “ its inversion / logic operation” are as follows.
◆ a) Non-inversion / logical operation;
Input integer _{N in1, N in2} are both _{"H ≧ N in1, N in2 ≧} G " of the input terminal _{T in1, T in2} if certain integer m output from the output terminal _{T out} is output, the output terminal _{T out} if not The output from is released. (In the case of the original asynchronous / multi-valued logic circuit)
For this reason, the present inventor calls the fourteenth embodiment shown in FIG. 14 "a synchronous AND / NOUT circuit (or synchronous NOR / OUT circuit) having two input specific integers (values) H and G".
(In the case of the synchronous multi-value logic circuit of the fourteenth embodiment)
◆ b) Inversion / logical operation;
If both the input integers N _in1 and N _in2 are “H ≧ N _in1 and N _in2 ≧ G”, the output terminal T _out is opened, and if not, the output specific integer m is output from the output terminal T _out .
(In the case of the original asynchronous / multi-valued logic circuit)
For this reason, when the gate terminal of the transistor 41 (in FIG. 8, FIG. 9, in FIG. 11) is reconnected from the Q terminal to the Q bar terminal in the fourteenth embodiment, the fourteenth embodiment states “ A circuit called “synchronous (multi-value) NAND D / NOUT circuit (or synchronous OR / OUT circuit)” having two input specific integers (values) H and G ”.
(In the case of the synchronous multi-value logic circuit of the fourteenth embodiment)

◆ ◇ ◆ 3) When transistors 32a and 32b, diode 34, and resistor 67 are removed:
In order to facilitate understanding now, "ignoring the time delay associated with the synchronous operation, logical operation was the D input signal and the Q output signal matches of the D-type flip-flop 27" or "original asynchronous “ Non-inversion / logic operation of multi-value logic circuit ” and “ its inversion / logic operation” are as follows.
◆ a) Non-inversion / logical operation;
Input integer _{N in1, N in2} certain integer m output from the output terminal _{T out} if both integers H less than or equal to the input terminal _{T in1, T in2} is outputted, the output from the output terminal _{T out} if not open Is done. (In the case of the original asynchronous / multi-valued logic circuit)
Therefore, the inventor calls the fourteenth embodiment shown in FIG. 14 as “a synchronous AND / NOVER circuit (or a synchronous NOR / OVER circuit) in which one input specific integer is H”.
(In the case of the synchronous multi-value logic circuit of the fourteenth embodiment)
◆ b) Inversion / logical operation;
If at least one of the input integers N _in1 and N _in2 is greater than the integer H, the output specific integer m is output, otherwise, if the input integers N _in1 and N _in2 are both less than or equal to the integer H, the output terminal the output from the T _out is opened.
(In the case of the original asynchronous / multi-valued logic circuit)
For this reason, in Example 14, when the gate terminal of the transistor 41 (in FIG. 8, FIG. 9, and FIG. 11) is reconnected from the Q terminal to the Q bar terminal, Example 14 says “ It becomes a circuit called “synchronous NAND / NOVER circuit (or synchronous OR / OVER circuit) in which one specific input integer is H.” (In the case of the synchronous / multi-value logic circuit of the fourteenth embodiment)

◆ ◇ ◆ 4) When transistors 31a, 31b, 33a, 33b, diodes 35a, 35b and resistors 20a, 20b, 62 are removed:
In order to facilitate understanding now, "ignoring the time delay associated with the synchronous operation, logical operation was the D input signal and the Q output signal matches of the D-type flip-flop 27" or "original asynchronous “ Non-inversion / logic operation of multi-value logic circuit ” and “ its inversion / logic operation” are as follows.
◆ a) Non-inversion / logical operation;
Input integer _{N in1, N in2} certain integer m output from the output terminal _{T out} if both greater than or equal to an integer G input terminal _{T in1, T in2} is outputted, the output from the output terminal _{T out} if not open Is done. (In the case of the original asynchronous / multi-valued logic circuit)
Therefore, the present inventor calls the fourteenth embodiment shown in FIG. 14 as “a synchronous AND / NUNDER circuit (or a synchronous NOR / UNDER circuit) having one input specific integer G”.
(In the case of the synchronous multi-value logic circuit of the fourteenth embodiment)
◆ b) Inversion / logical operation;
If at least one of the input integers N _in1 and N _in2 is smaller than the integer G, the output specific integer m is output. If not, that is, if the input integers N _in1 and N _in2 are both greater than or equal to the integer G, the output terminal the output from the T _out is opened.
(In the case of the original asynchronous / multi-valued logic circuit)
For this reason, in Example 14, when the gate terminal of the transistor 41 (in FIG. 8, FIG. 9, and FIG. 11) is reconnected from the Q terminal to the Q bar terminal, Example 14 says “ A circuit called “synchronous NAND • NUNDER circuit (or synchronous OR • UNDER circuit)” in which one input specific integer is G.
(In the case of the synchronous multi-value logic circuit of the fourteenth embodiment)

The identities that hold for these multilevel logic circuits are summarized as follows. As a matter of course, “each of a plurality of logical variables, input specific integers, mutual output specific integers” and the like of each circuit are the same. Furthermore, if each circuit is synchronous, the synchronization conditions such as the synchronization frequency and the latching conditions are the same.
However, in the “OVER circuit, NOVER circuit” and “UNDER circuit, NUNDER circuit” that are the basis of each circuit, the input specific integers are shifted by 1 as described above (the first half of paragraph [0078]) .
* A) AND / NUNDER circuit = NOR / UNDER circuit * b) NAND / NUNDER circuit = OR / UNDER circuit * c) OR / UNDER circuit = NAND / UNDER circuit * d) NOR / NUNDER circuit = AND / UNDER circuit * e ) AND / NOVER circuit = NOR / OVER circuit * f) NAND / NOVER circuit = OR / OVER circuit * g) OR / NOVER circuit = NAND / OVER circuit * h) NOR / NOVER circuit = AND / OVER circuit

These identities also mean "synchronously, mutually or synchronously, just call the same multi-value logic circuit with two names", but multi-value logically Has an important meaning.
For example, since NAND / NUNDER logic is the negation of AND / NUNDER logic, AND / NUNDER logic and NAND / NUNDER logic are complementary to each other, and NAND / NUNDER logic and OR / UNDER logic are the same. The UNDER logic is also complementary to each other. Similarly, the NAND · NUNDER logic and the NOR · UNDER logic are also complementary to each other.
In this case, the “complementary relationship” is “when a predetermined number of logic variables are simultaneously given to the two logics, one of the logics always becomes the value of the specific integer for output, and the other logic is It means that the output is the opposite, that is, the open output.
Incidentally, for example, from the above item * b), the OR / UNDER logic means “the combination of AND / NUNDER logic and NOT logic”, so that the synchronous OR / UNDER circuit is replaced by “the latter stage of the synchronous AND / NUNDER circuit” A non-synchronous NOT circuit is connected to this circuit, and a matching pull-up resistor or pull-down resistor is connected between the two circuits "or" synchronous NOT circuit after the asynchronous AND NUNDER circuit. It can be alternatively configured with "Connecting and connecting pull-up or pull-down resistor for matching between both circuits", but "time delay, power loss and multi-value This is disadvantageous in terms of hazards.No (No), but it can be used in reverse to make use of “time adjustment, timing adjustment, or matching of two logic signals”. It is also conceivable to. In this case, both circuits can be considered to be synchronous.
Exactly in the same manner, for example, from the above item * a), AND / NUNDER logic means “the combination of OR / UNDER logic and NOT logic”. Therefore, the synchronous AND / NUNDER circuit is changed to “the synchronous OR / UNDER circuit An asynchronous NOT circuit is connected to the subsequent stage, and a matching pull-up resistor or pull-down resistor is connected between the two circuits "or" synchronous NOT circuit to the subsequent stage of the asynchronous OR / UNDER circuit Can be configured alternatively by connecting a pull-up resistor or a pull-down resistor for matching (matching) between both circuits. It is disadvantageous from the aspect. No (no), conversely, it may be used for “time adjustment, timing adjustment, or matching of two logic signals”. In this case, both circuits can be considered to be synchronous.

Then, instead of “on / off drive means and bidirectional pull switching means” such as “Eighth embodiment shown in FIG. 8” as a subsequent stage of the D-type flip-flop 27 in Embodiment 14 of FIG. When the “on / off drive means and bidirectional pull switching means” of “Embodiment 10” shown in FIG. 12 or “Embodiment 12 shown in FIG. 12” are connected, the operation is as follows.
“Contents when the gate terminal of the transistor 41 is connected to the Q terminal in the above (paragraph numbers [0103 to 0106]” in ◇◇◇ 1) to ◇◇◇ 4) When the gate terminal is connected to the Q bar terminal (= inverted logic), and when the gate terminal of the transistor 41 is connected to the Q bar terminal in the above-mentioned ◇◇◇ 1) to ◇◇◇ 4) The contents of (= inverted logic) ”only become“ here the contents when the gate terminal is connected to the Q terminal (= non-inverted logic) ”.
And in each of Examples 8-12 shown in FIGS. 8-12, although each Example which changed the specific integer for an output was demonstrated, Example 14 shown in FIG. Since the “off drive means and bidirectional pull switching means” are used, the specific integer for output can naturally be changed also in the fourteenth embodiment.

  A fifteenth embodiment shown in FIG. 15 is a combination of the transistors 33a and 33b and the like in the fourteenth embodiment shown in FIG. For this reason, the “on / off drive means and bidirectional pull switching means” and the like are exactly the same as those in the fourteenth embodiment of FIG.

In the sixteenth embodiment shown in FIG. 16, the synchronizing signal generating means 60 (= synchronizing signal supplying means) and the D-type flip-flop 70 are supplied with power from the same power supply lines V ₀ and V ₋₁ .
Further, the transistors 71 and 72, the diode 39, and the resistor 15 constitute the on / off driving means, and the transistors 73 and 74 constitute the bidirectional pull switching means.
Furthermore, instead of “numerical value discriminating means composed of transistors 1, 2, 17 and resistors 20, 62”, “numerical value discriminating means composed of transistors 31 to 33, diode 34 and resistors 20, 62, 67 in FIG. 8”. , “Numerical discrimination means constituted by transistors 31a to 33a, 31b to 33b, diodes 34, 35a, 35b and resistors 20a, 20b, 62, 67 in FIG. 14”, “transistors 31a to 32a, 31b to FIG. Embodiments using “numerical value discriminating means comprising 32b, 33, diodes 34, 68a, 68b and resistors 20, 62, 67” are also possible.
Then, instead of the “power supply lines V ₋₁ and V ₀ shown in FIG. 16”, the power supply lines V ₀ and V ₁ are used, that is, the respective power supply potentials are increased by one, and the transistors 72 to 74, diodes 39 and the resistor 15 can be removed, and the drain terminal of the transistor 71 can be used as the output terminal _Tout . In this case, there is a case where the transistor 71 is used as a reverse conduction type pull-down switching means by forming the built-in diode, and a case where a reverse blocking diode is connected in series to the transistor 71 to reverse block this series circuit. There is also a case of using as a type pull-down switching means. (Another example)
Or, although there is a difference between the N-channel type and the P-channel type, as in the seventh embodiment of FIG. 7, “a diode 12 is used instead of the transistor 74 and the transistor 73 forms a reverse blocking pull-down switching means. Or “the transistor 74 is removed and the source terminal or the like of the transistor 73 is used as the output terminal T _out to constitute a reverse conduction type pull-down switching means”. (Derived example)
Or, although there is a difference between the N channel type and the P channel type, as in the sixth embodiment of FIG. 6, “removing the transistor 73 and directly connecting the source of the transistor 74 and the like to the power line V _m and pulling up the reverse conduction type. switching means constituting a "or remove the" transistor 73, directly connected to the source or the like of the transistor 74 to the power supply line V _m, and inserting and connecting a diode 10 between the drain and the output terminal T _out of the transistor 74, the transistor 74 and the diode 10 can constitute reverse blocking type pull-up switching means ". (Derived example)

Embodiment 17 shown in FIG. 17 is a “multi-value logic circuit that the inventor calls a synchronous multi-value EVEN circuit or a non-inverting buffer circuit”, but the connection of both gates of the transistors 22 and 23 is connected from the Q terminal to the Q circuit. If the bar terminal is changed, the seventeenth embodiment shown in FIG. 17 becomes a “multi-value logic circuit that the inventor calls a synchronous multi-value NOT circuit or multi-value NEVEN circuit”.
In the embodiment 17 shown in FIG. 17, the D-type flip-flop 127 operates at twice the power supply voltage of the D-type flip-flop 27 (in FIG. 9), so both power lines V _m−1 and V _{m + 1} Receive power supply. For this reason, since the D-type flip-flop 127 directly drives the transistors 22 to 25 on and off, the transistor 41 and the resistor 15 in FIG. 9 are not necessary.
Further, if the output part of the D-type flip-flop 127 (= the circuit part of the Q terminal and the Q bar terminal) has the same configuration as the “on / off drive means constituted by the transistors 22 to 25 (and the diode 36)”, D The type flip-flop 127 can directly drive the transistors 3 and 5 on and off.
→→ “Derived Example of Example 9 in FIG. 9 and Derived Example of Example 10 in FIG. 10” as described above (paragraph number [0098]).

Another embodiment (not shown) will be described. “Example 1 shown in FIG. 1” described above is a case where the diode 26 and the resistor 27 are not provided in the multi-value logic circuit of FIG. 9 of “JP 2005-236985 (Patent Document 3)”. The D-type flip-flop 27 in the first embodiment of FIG. 1 is inserted and connected between the “connection point” and the “gate of the transistor 24”, and the turn-off speed of the bidirectional pull switching means is shown in FIG. "Accelerated by the transistor 37 in the first embodiment".
Similarly, in each of the multi-value logic circuits shown in FIGS. 11, 13, 17, 17, 20, 23 (b), and 25 (b) of Japanese Patent Laid-Open No. 2005-236985, the same thing is applied. Each embodiment is possible.
That is, in each of the multi-valued logic circuits of FIGS. 17 and 20 of Japanese Patent Laid-Open No. 2005-236985, among the two PMOSs, the “both power supply lines V _{m + 1} ” is similarly provided between the drain of the preceding stage PMOS and the gate of the succeeding stage PMOS. · comprising a D-type flip-flop 27 'which is powered from V _m to equal to the insertion and connection.
In the multi-valued logic circuit of FIG. 23B of Japanese Patent Laid-Open No. 2005-236985, “both power supply lines V _{m + 1} .multidot.m” are similarly provided between the drain of the “PMOS having the input terminal In4” in the preceding stage and the gate of the PMOS in the succeeding stage. It will be equal to inserting and connecting the D-type flip-flop 27 'which is powered from V _m.
Further, in the multi-value logic circuit shown in FIG. 25B of Japanese Patent Laid-Open No. 2005-236985, “power is supplied from both power supply lines V _{m + 1} · V _m similarly between the drain connection points of the four preceding PMOSs and the gate of the subsequent PMOS. The inserted D-type flip-flop 27 "is inserted and connected.
Similar to “Derived from the first embodiment shown in FIG. 1 to the second to seventh embodiments shown in FIGS. 2 to 7”, the numerical value and the number of specific integers for input are changed, or the pull switching is performed. By changing the means to reverse conduction type or reverse blocking type, or by changing the power line connecting one switch terminal of the pull switching means, each of the above-mentioned JP-A-2005-236985 The respective embodiments derived from the embodiments of the present invention derived from the embodiments are possible. In each of the embodiments of the present invention or each of the embodiments thereof, the present invention and each of the embodiments in which the turn-off of the bidirectional switching means is accelerated by the transistor 37 or the like as in “Embodiment 1 shown in FIG. 1”. Derived embodiments are possible. (Derived Example)
In other words, there are derivative examples with and without the transistor 37 and the like.

*** *** *** *** *** *** *** ***
◆◆◆ ＊＊＊＊＊＊＊＊＊ Finally, we will supplement the following. ＊＊＊＊＊＊＊＊＊ ◆◆◆
*** *** *** *** *** *** *** ***
1) For convenience of explanation, it is called an input terminal or an output terminal (corresponding to the inlet means and outlet means in claim 1), but it does not actually exist as a terminal, but may be a simple conductor or electrode. Many. This is similar to what is called a transistor base terminal, base electrode, base lead, or simply base, for example.
2) In each embodiment or each derivative embodiment thereof, the back gate is not “its source” but “the lowest constant potential supply means of the circuit {example: power supply” with respect to “each NMOS having its back gate and source connected” It may be connected to the line V ₀ or V ₋₁ } ”. Alternatively, it may be connected to other constant potential supply means whose potential is lower than its source potential. (Derived Example)
Further, in each embodiment or each derivative embodiment thereof, the back gate is not “its source” but “the highest constant potential supply means of the circuit {example: power supply line” for “each PMOS having its back gate and source connected” V _n−1 or V _n } ”. Alternatively, it may be connected to other constant potential supply means having a higher potential than the source potential. (Derived Example)
3) Instead of the resistors 15, 20, 21, 26, 28, 62 to 64, 67, etc. in each embodiment or each derivative embodiment thereof, “junction FET or normally on type in which the gate and the source are directly connected” "MOS.FET" or "normally-off type MOS.FET with its drain and gate connected" can be used one by one as the resistance means. (Derived Example)
Furthermore, if there is no hindrance to the circuit operation, in each embodiment or each of its derivatives, a constant current diode instead of each resistor, “two constant current diodes connected in series in reverse direction”, current mirror One circuit or two-terminal constant current means can be used as the resistance means one by one. However, when using a constant current diode, constant current means, etc., pay attention to the voltage division ratio.
(Derived Example)
4) In each of the embodiments or its derivatives, instead of each diode, “bipolar transistor with its collector and base directly connected”, “junction FET with its drain and source directly connected”, “its drain and gate” Bipolar mode SIT or GTBT directly connected "," Normally-off type MOS-FET with its gate, back gate and source connected "or" Drain-back gate, source-back gate is not conductive. Thus, the normally-off type MOS FET having its back gate potential maintained and its drain and gate connected can be used one by one. (Derived Example)
5) In each embodiment or each derivative embodiment, the level of each power supply potential is reversed, and each controllable switching means is defined as “controllable switching means in a complementary relationship with it (eg, P for N-channel type MOS • FET). “Channel type MOS · FET)” is replaced one by one, and the direction of each component (eg, diode) having a voltage direction or voltage polarity is reversed. Naturally, an “embodiment having such a relationship” is also possible. Each embodiment having this symmetric relationship corresponds to “a case where these constant potentials decrease in numerical order from the first constant potential to the Nth constant potential” in claim 1. However, in that case, since it corresponds to negative logic relative to positive logic, the multi-value logic function may be the same as or different from the original circuit.

6) As an additional effect of the present invention, synchronous latching can be performed in multi-value logic circuits / units, so that the whole circuit assembly method is flexible, and the options of the entire circuit configuration are increased and convenient.
Conventionally, a multi-level synchronous latching circuit must be provided between the multi-level circuit and the multi-level circuit.
7) In each embodiment or each derivative embodiment thereof, the power supply line V ₀ or another power supply line is “the main body case of the circuit” or “the main body of the circuit device” or “the body of an automobile, motorcycle, bicycle, etc.” Or "Hulls such as ships" or "Main bodies of amphibious hovercraft" or "Main bodies of flying means such as airplanes and helicopters" or "Main bodies of space navigation means such as spacecraft and space stations" Or, it is often connected to a “celestial body such as the earth, the moon, and Mars”, and the potential of the main body, the vehicle body, the hull, and the celestial body becomes the reference potential of a large book such as a ground potential. However, although one DC power supply for supplying DC voltage is connected between each of “two power supply lines adjacent to each other at the level of the power supply potential”, it is not shown.
● 8) Although “Beyond the CMOS” has been proposed, various devices such as quantum devices have been proposed, but ☆☆☆ CMOS will also evolve! ! ! ☆☆☆ CMOS evolves toward 3D IC, multi-value, new concept computer (→→ paragraph numbers [0129, 0165 to 0167] described later)! ! !
One example thereof is “bidirectional switch combining transistors 3 and 5” or “bidirectional switching means combining transistors 3, 5, 22 to 25 (and diode 36)” in FIG. -> The following and patent document 6 (Unexamined-Japanese-Patent No. 2006-252742).
Another example is the multi-value memory shown in FIG. 19 of the following patent document 8 (Japanese Patent Laid-Open No. 2007-035233).
Moreover, even if a certain circuit does not have a complete CMOS structure, there is no problem if the power consumption of the entire circuit is fundamentally low. For example, even in the case of using a pull-up resistor or a pull-down resistor, in the circuit, “such as a MOS FET that pulls the pull-up (or pull-down) resistor in the ON state during operation” This is the case of a circuit in which the total number is always small and “the total number of MOS / FETs that are turned on / off during the operation is always small”. This is expected to be the case with an input / output pattern storage type decimal computer which will be described later. →→ Paragraph number [0129, 0165-0167].
On the other hand, despite the fact that the current CPU is a block of CMOS circuits, the total number of “MOS / FETs that are switched on and off at a high switching frequency” is extremely large. The current situation is that the CPUs are like heaters due to the "total switching loss including power loss due to power" and "total power loss due to charging / discharging of each gate-source capacitance". .
JP-A-2006-252742 (bidirectional switching means, multi-value buffer means, multi-value storage means) JP 2007-035233 (multi-value decoding means, multi-value information processing means, etc.)

9) Regarding normally-off type MOS FETs used in the present invention, the withstand voltage between the drain and the source and the withstand voltage between the gate and the source are kept to a certain level (and increased if possible), while at the off time If the on / off threshold voltage can be made smaller and smaller while keeping the leakage drain current small, 100-value computers and even 1000-value computers (!?) Will come into view.
10) The data input part (for example, the input part of the D terminal) of the binary synchronous flip-flop means that is one constituent means of the present invention is “whether the input integer is larger than the one input specific integer. Of course, the binary synchronous flip-flop means may also serve as the numerical determination means as long as it satisfies the requirement of the numerical determination means for determining whether it is “not large” or “not small”.
11) Each of the multi-value logic circuits shown in FIGS. 12 to 13 can be used as a multi-value transfer gate means by separating one end of the bidirectional switching means from the power supply line V _m or IV _m .
These insulation switches seem to be applied to “voltage detection means for detecting voltages of a plurality of batteries connected in series” together with “insulation power supply means of Patent Documents 30 to 37 described later”.
JP-A-6-196991 (fully insulated switching means) Patent No. 3,423,780 (fully insulated switching means) Patent No. 3,321,203 (conditional insulation type switching means) Patent No. 3,321,218 (conditional insulation type switching means) Patent No. 3,333,643 (conditional insulation type switching means) Patent No. 3,553,666 (conditional insulation type switching means) Japanese Patent Laid-Open No. 9-252582 (conditional insulation type switching means) Japanese Patent Application Laid-Open No. 11-164546 (conditional insulation type switching means)

◆◆◆ ＊＊＊＊＊＊＊＊＊＊＊ Resolve power supply issues ＊＊＊＊＊＊＊＊＊＊＊ ◆◆◆
***
● 12) In a multi-valued logic circuit in potential mode (or voltage mode), each DC voltage supply is a big problem (refer to Non-Patent Document 9). Yes. If more precise constant voltage control is required, an analog type constant voltage means such as a three-terminal regulator may be connected to the subsequent stage of the “constant voltage controlled DC-DC converter circuit” or the like.
Patent No. 2,717,963 ☆ a) Constant voltage control by intermittent oscillation control using a Schmitt trigger circuit. ☆ b) The point that the self-oscillation type DC-DC converter circuit (non-resonant type) and the Schmitt trigger circuit are combined is completely different from “Hysteresis control before this invention (see: Non-patent document 17) described later”. is there. ☆ c) The device is designed to prevent "abnormal oscillation, abnormal overheating and abnormal power loss" caused by the Schmitt trigger circuit. ☆ d) Application date: May 19, 1987, Priority date: June 25, 1986, August 25, the same year.

Patent No. 3,187,470 ☆ a) Composite resonance type DC-DC converter circuit (complete, zero current switching, zero switching loss when switching on / off). Prior to this invention technology, the realization of a complete “zero current switching operation or zero voltage switching operation” to reduce switching noise (such as countermeasures against radio wave noise) and switching loss (⇒ improve power conversion efficiency). It was a technical problem to be solved that was extremely practical. →→ Non-Patent Document 13 (Nikkei Sangyo Shimbun [Tokyo edition] switching power supply advertisement feature) ☆ b) Normally, the series resonant current oscillates around zero current, so the resonant current is its minimum or maximum. The value cannot be zero. However, the present inventor has discovered by examining and considering "a unique effect of the combination of the series resonant circuit, the parallel resonant circuit, and the bidirectional constant voltage means" through experiments. The unique effect is that the resonance current can be set to zero at the minimum value or the maximum value. (⇒ This increases the time during which the resonance current stays at zero, facilitating zero current switching.) At this time, something like a unique filter switching action (or impedance switching action) It works and the effect is shown.

☆ c) For example, when using “two power diodes connected in anti-parallel” as the bidirectional constant voltage means, the bidirectional constant voltage means and the parallel resonant circuit are connected in parallel. Since the forward voltage of each diode and the parallel resonant capacitor voltage are the same, the parallel resonant capacitor voltage directly controls each forward current based on the forward voltage-forward current characteristics. Become. On the other hand, the bidirectional constant voltage means suppresses the amplitude of the parallel resonant capacitor voltage by the constant voltage action and clamps. If the series resonant frequency and the parallel resonant frequency are the same, the parallel resonant circuit has an impedance ∞ (during ideal operation) with respect to the series resonant voltage. is there. On the other hand, “two power diodes connected in anti-parallel” normally would allow any amount of current to flow in both directions based on its constant voltage characteristics.
However, since the parallel resonant capacitor voltage controls each forward current, the impedance of the “parallel circuit of the parallel resonant circuit and the bidirectional constant voltage means” is “Switching from zero to ∞” or “From ∞ to zero” with each current value (= current value in one direction and current value in the opposite direction) determined based on forward voltage-forward current characteristics as a boundary It is thought that the “thing like a filter switching action (or impedance switching action)” works on the series resonance voltage. For this reason, the present inventor thinks that “the series resonance current does not oscillate damped around the current zero”. Each current value varies with the parallel resonant capacitor voltage, and between the positive and negative current values, the series resonant current can pass through the parallel circuit. It is “a new action / new effect like an alloy”. It seems that a circuit configuration means having a new property has been created by combining two circuit configuration means having properties opposite to each other with respect to the series resonance current.

☆ d) The circuit constants and parts used in the patent gazette are “not the best choice because of the available parts,” but it is easy for a third party to verify the circuit operation.
☆ e) In the case of an ordinary resonance type DC-DC converter circuit, the switching period is usually about 1/2 resonance period, but in the case of the technology of the present invention, the switching period is about 3/4 resonance period. Since the switching frequency is low, for example, “switching loss due to charge / discharge of each of“ capacitance between drain, source and gate ”of power MOS / FET” is reduced, so from the aspect of reducing the switching loss. Is also advantageous.
☆ f) By the way, when considering on / off operation of a general diode, the above-mentioned manufacturer specification of the power diode (non-patent document 14 described later) includes “the turn-on delay” and “the turn “Off delay” describes the actual measurement method, actual measurement conditions, and actual measurement values (forward recovery time and reverse recovery time). However, in the case of this complex resonance type DC-DC converter circuit, the two diodes connected in reverse parallel operate in an analog manner, and the on / off operation is not applied to this circuit.
Even if this circuit is considered as an on / off operation, the use conditions are considerably loose. For example, comparing 1 kilohertz “V _max 1 volt AC voltage and V _max 100 volt AC voltage”, the voltage change rate (= slope of the AC voltage waveform) when each of the instantaneous values is zero is The former is much smaller. In addition, with respect to the voltage of the parallel resonant capacitor, the slope of the sine wave is zero near the positive peak value and the negative peak value in each case of π / 2 and 3π / 2 in terms of sine waves. Is almost zero, that is, the voltage change is so small that it takes time for the voltage to change, enough for each power diode to turn on and off. It is thought that time will be given.
☆ g) The following and non-patent documents 15 and 16 also confirm the certainty and usefulness of the technology of the present invention.
☆ h) Application date: June 1, 1991, Priority date: June 1, 1990.

Patent No. 3,187,411 (resonance type DC-DC converter circuit) [Patent Document 28: Self-oscillation type improved technology, saving driving power by sharing driving transformer and output transformer, parts Reduction in points] Patent No. 3,333,504 (same as above) [Self-oscillation type, bi-directional constant voltage means (eg, anti-parallel connected diode) and simple driving means using a driving transformer, stabilization of resonance voltage, etc. ] Patent No. 3,477,136 ☆ a) Constant voltage control by intermittent oscillation control using a Schmitt trigger circuit. ☆ b) The point that combines the resonant / self-oscillating DC-DC converter circuit and the Schmitt trigger circuit is completely different from “Hysteresis control before the present invention (see: Non-patent document 17)”. ☆ c) For this reason, the resonance period and the intermittent period are independent of each other, so that the switching frequency becomes a constant switching frequency by the resonance operation. ☆ d) The effect brought about by zero current switching eliminates the need for contrivance and configuration means necessary in the invention technology of the above-mentioned Patent Document 25, and has a high degree of freedom in circuit configuration and input / output voltage relationships. ☆ e) Divisional application of the original application of Patent Document 26. ☆ f) Before this invention technology, “constant voltage control and standby power reduction during no load” of the resonance type DC-DC converter circuit was a very big technical problem to be solved. We were able to solve it at the same time. →→ Non-Patent Document 13 (Nikkei Sangyo Shimbun [Tokyo edition])

Patent No. 3,494,303 (resonance type DC-DC converter circuit) [small number of windings] Patent 3,521,055 (same as above) [Reduction of control means] Japanese Patent No. 3,645,274 (same as above) [Assists in starting oscillation in a resonant DC-DC converter circuit of Patent Document 27 technology] Patent No. 3,730,354 (Non-controllable switching means = transistor type diode means) [reducing forward voltage, reducing power loss] JP-A-9-51677 (resonance type DC-DC converter circuit) [small number of windings] {highest priority date: October 17, 1994, deemed withdrawal} [many examples disclosed]. This main circuit is a simplification of the main circuit of the technique of Patent Document 26, but one example of this main circuit and the main circuit of the following Non-Patent Document 15 technique are the same. Patent No. 4,450,295 (resonance type AC-DC converter device, excitation type). Plus alpha technology is required for perfect power factor improvement. Patent No. 4,694,690 (resonance type AC-DC converter device, diode clamp type). Plus alpha technology is required for perfect power factor improvement.

"Special issue on switching power supply advertising" in the Nikkei Sangyo Shimbun (Tokyo edition) dated January 12, 1990, "Switching power supply used in communication equipment and satellites", author: Koki Tsuki) Akihiko (Faculty of Engineering, Kyushu University) Description of “Forward Recovery Time” and “Reverse Recovery Time” in “TOSHIBA Rectifier / Thyristor Medium-to-Small 1989” (p. 56 to p. 57), Power Semiconductor Manual Specific examples of each recovery characteristic of the diode (p.383 to p.384). J. et al. G. Hayes, et al. : "Full-Bridge, Series-Resonant Converter Supplementing the SAE J-1773 Electric Vehicle Inductive Charging Interface", PESC '96 Record, 1913 (1996). [Rapid charger for electric vehicle storage battery considered to have applied the above-mentioned technology of the composite resonance type DC-DC converter circuit of Patent Document 26]. “The Technical Report of the Institute of Electrical Engineers of Japan, No. 687, High Performance Switching Technology for Power Converters”, p. 46 [Fig. 4.14 [DC-DC converter using double current resonance]]. Author: Power Converter High-Performance Switching Technology Research Committee, published by the Institute of Electrical Engineers of Japan on August 25, 1998. [Introduction of Circuit Technology of Non-Patent Document 15 above]. “Nikkei Electronics June 15th (2009), No. 1006”, p. 78-p. 86 “Analog Reinforcement School 6th Hysteresis Control Characterized by High Speed Jumps to the Lead of Power Supply Control System”, published by Katsumi Yamashita and Nikkei BP on June 15, 2009.

It is also conceivable to use a charge pump circuit for each DC voltage supply.
Patent 3,657,623 (charge pump circuit) JP-A-6-225518 (Insulated power supply means using a capacitor and Insulated power supply means using a coil) {Deemed withdrawal} Japanese Patent Laid-Open No. 8-23671 (insulated power supply means using a series resonance circuit) {deemed withdrawal} Japanese Patent Laid-Open No. 9-98567 (insulated power supply means using a series resonance circuit) {Self-collection} JP-A-9-182414 (Step-down circuit using a capacitor) {Deemed withdrawal} Japanese Patent Laid-Open No. 10-164826 (Step-down circuit using a capacitor) {Deemed withdrawal} Japanese Patent Laid-Open No. 11-164546 (Step-down circuit using a capacitor) {Deemed withdrawal} JP 2000-60112 (Step-down circuit using capacitor) {Deemed withdrawal}

◆◆◆ ＊＊＊＊ Explanation of new multi-valued logic “Hooji algebra” ＊＊＊＊ ◆◆◆
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● 13) The potential mode (or voltage mode) multi-value logic circuit on which the present invention is based embodies “a completely new world-first new multi-value logic that the inventor originally conceived at the time of 2002” It has been realized. However, it is inconvenient if there is no name in the new multi-valued logic, so we decided to name it “Hooji Algebra”.
The reason for this is “Since the present inventor is Japanese, it is related to the symbol of Japan, Mt. Fuji,” and “Bool” of Boolean Algebra. ”And“ the ability to include its fuzzy expression ability, possibility, practicality, expandability, future, etc. Since the inventor strongly determined that it is tremendously large and huge.}, The language is aligned with the English huge.
***
JP 2004-032702 (Multi-valued logic circuit based on “Fuji algebra”) [Application date: March 10, 2003, Priority date: March 11, 2002, also May 7], (Deemed under). Japanese Patent Application Laid-Open No. 2005-198226 (patent document 1 patent re-enlarged application. Patent registration) Japanese Patent Laying-Open No. 2005-236985 (improvement of Patent Document 2 patent registration)

The reason for this determination is that the multi-value logic circuit based on the new multi-value logic “Fuji algebra” is as follows: ““ No matter how many multi-value numbers N ”, the conventional multi-value logic circuit This is because there are a number of advantageous and unique effects (⇒ the world's first in 2002). However, there was an effect that was not noticed in 2002.
◆ a) When a binary circuit is connected to the preceding stage, the connectivity is extremely good and no special interface is required between them. [Paragraph number 0155]
B) When connecting a binary circuit to the subsequent stage, the connectivity is extremely good and no special interface is required between them. [Paragraph number 0156]
C) As described in the present invention, the connectivity with the binary circuit is very good even during signal transmission in the multi-value logic circuit, and no special interface is required between them. [Paragraph numbers 0039 to 0040]
◆ d) Therefore, unlike the conventional multi-value circuit, the multi-value hazard can be removed as in the present invention without needing to convert to binary.
E) Binary and Boolean algebra (non-inverted logic) AND logic, OR logic, NOT logic, NAND logic, NOR logic, and basic logic circuits are included and compatible. [Paragraph numbers 0135 to 0136]
◆ f) Depending on the multi-value number N, there may be a case where a plurality of “same kind of basic / multi-value logic circuits with different specific integers” are used. “Connected power lines” are just different from each other, their basic configuration is exactly the same and compatible. [Paragraph numbers 0133 to 0134]
◆ g) Therefore, it is possible to assemble a synthesis / multi-value logic circuit having a large multi-value number N using a synthesis / multi-value logic circuit having a small multi-value number N as it is. [Paragraph number 0137]
◆ h) The multi-value number N can be changed very easily. [Paragraph number 0137]
◆ i) Have duality that “the duality is true”. [Paragraph numbers 0130 to 0132]
J) Regardless of the multi-value number N, all multi-value logic functions can be expressed by one type of multi-value logic circuit (complete system). ⇒⇒ Completeness, also “complete”. [Paragraph numbers 0138 to 0148]
◆ k) It is very easy to “unitize or modularize” the basic or composite / multi-valued logic circuit. [Paragraph numbers 0133 to 0134, 0137]
◆ l) Each of the multi-value numbers N (≧ 2) of the plurality of logical variables “..., X, y, z,. However, it must be flexible enough to respond flexibly without any problems. [Paragraph number 0154]
◆ m) Since a multi-value wired OR circuit is formed in the same manner as a binary wired OR circuit, it is very advantageous in simplifying the entire circuit configuration and reducing the total number of parts. [Paragraph numbers 0149 to 0151]
N) It is possible to make (complete) circuit (3D) programmable logic array, semi-order (3D) IC / LSI, etc. [Paragraph numbers 0151 to 0152]
◆ o) Eight new multi-value logics created by the inventor, “OVER logic, NOVER logic, UNDER logic, NUNDER logic, IN logic, NIN logic, OUT logic, “Ambiguity” can be easily and freely defined and expressed by using each multi-valued logic circuit such as “NOUT logic”. [Paragraph numbers 0157 to 0158]

None of these multi-valued logic systems and circuits prior to the advent of “Fuji Algebra” had any distinctive advantageous effects or features.
For that reason, “New multi-valued logic 'Fuji algebra” is' the most faithful and orthodox expansion and extension of Boolean algebra to date 'and so far.' The present inventor believes that it is huge in any case such as ability, possibility, practicality, expandability, and future potential.

The first major reason why multi-valued computers have not been widely and deeply put into practical use like binary computers and has not been developed is as follows. There was a binary logic system that can withstand "Boolean algebra", but in the case of multi-value, there was no multi-value logic system that would firmly support multi-value circuits and that could withstand practical use The inventor believes that it is from the body. In addition, three-dimensional IC technology and “low voltage drive (= absolute value of on / off threshold voltage is small) and high withstand voltage technology” are particularly important, such as energy saving and cooling technology. It is also important.
In order to become the basis of such a multi-valued computer, it is “compatible with binary logic,“ Boolean algebra ”, completely including it”,・ Multi-valued logic circuits are compatible with each other, and the larger one of the multi-valued number N completely includes the smaller one. Further, “regardless of binary or multi-valued,“ the logical function and The number of multi-value numbers N (≧ 2) ”of“ one or a plurality of logical variables] ”is not influenced at all, and each function can be exhibited freely and flexibly. Thinks.

By the way, the larger the multi-value number N, the greater the “number of types of multi-valued logic functions that can be expressed”, that is, the “number of types of information processing that can be expressed”, as shown below. Furthermore, if the number of digits is also used, it will become super -... excessively explosive, and can easily exceed the "program memory type (= built-in type) computer type of information processing by programming" !! Therefore, for example, a new concept computer system that does not use a program on a 10-value / decimal computer becomes possible.
◇◇ Example of the number of types such as 10-valued logic functions ◇◇
However, the number of each (multi-valued) logical variable is two.
* Binary value, 1 digit, 2 logical variables →→ 4th power of 2 types = 16 types.
* 3 values 1 digit 2 logical variables →→ 9 to the 9th power / type = 19,683 types.
* 4 values, 1 digit, 2 logical variables →→ 4 to the 16th power / type ≒ 4,294,968,000 types.
* 5 1-digit 2-logical variable →→ 5 to the 25th power / type.
* 6 values, 1 digit, 2 logical variables →→ 6 to the 36th power / type.
* 7 value 1 digit 2 logical variable →→ 7 to the 49th power / type.
* 8 values, 1 digit, 2 logical variables →→ 8 to the 64th power / type.
* 9 values, 1 digit, 2 logical variables →→ 9 to the power of 81, type.
* 10 value 1 digit 2 logical variable →→ 10 to the 100th power / type.
* 10-value 2-digit 2-logical variable →→ 10 to the 10th power / type.
* 10-value 3-digit 2-logical variable →→ 10 millionth power / type.
* 10-value 4-digit 2-logical variable-> 10 to the 100 millionth power / type.
* 10-value 5-digit 2-logical variable →→ 10 to the 10 billionth power / type.
* 10-value 6-digit 2-logical variable →→ 10 to the power of 1 trillion / type.
* 10-value 7-digit 2-logical variable →→ 10 to 100 trillion / type.
* 10-value 8-digit 2-logical variable →→ 10th power (= 10,000 trillion) / type.
→→ Reference: Patent Document 8 below.
Speaking correctly, it is the opposite of the above-mentioned “can be lightly exceeded (!!!!)”, and the number of multi-values N (≧ 2) is “the number of types of information processing by programming”. Can never exceed "the number of types of logical functions that can be expressed using the number of digits".
The reason is as follows. Also in “information processing by program”, the function content as the information processing means can be determined only from the entry / exit of the “data or information” regardless of the process of the information processing. In addition, both the “each input“ data or information ”” and the “individual information processing result” must be a combination of numbers! In other words, since it can be expressed by a truth table, the information processing content can never exceed “the number of types of logical functions that can be expressed by the truth table”.
Moreover, the number of types of “information created by programming, useful to humans, and actually used” does not seem to be as many as 10 to the 100th power.
Paragraph number [0029 to 0033] of JP2007-035233 A

◆◆◆ ＊＊＊＊＊＊ “Hooji Algebra” Duality ＊＊＊＊＊＊ ◆◆◆
***
● 14) The duality of the new multivalued logic “Fuji algebra” that “a duality holds regardless of the multivalued number N” will be described below.
"Fuji algebra" is "a binary Boolean algebra that has been expanded and expanded to multi-value faithfully to the present inventor and the present invention", so of course, its multi-value (specific value) NOT logic, multi-value (specific value) “Dual” holds for AND logic and multi-value (specific value) OR logic.
“Duality in Boolean algebra” means “in the identity of an arbitrary logic function composed of NOT logic, AND logic, or OR logic, swapping“ 1 ”and“ 0 ”on both sides, and simultaneously AND logic and OR logic Even if they are replaced, the identity holds. "
FIG. 18 shows that “theorem corresponding to the double negation theorem in the Boolean algebra, the de Morgan's theorem, and the dual theorem” also holds in “Fuji algebra”.
***
“Introduction to Transistor Circuit Lecture 5: Digital Circuits”, p. 27-p. 31 “3.3 Boolean Algebra [1] Axiom [2] Theorem [3] Duality”, supervised by Yoshifumi Amemiya, Norii Koshiba, author: Kensuke Shimizu, Masatoshi Kazuwa (Masahiro), issued by Ohm Co., Ltd. on May 20, 1986.

First, an equivalent circuit of each of an OR circuit and an AND circuit already known in the Boolean algebra will be described.
★★ Equivalent circuit of OR circuit:
* From the double negation theorem "OR logic of A and B" = A + B
= “Double negation of (A + B)”
* From the de Morgan theorem "Double negation of (A + B)" = "Negation of (Negation of A) and (Negation of B)"
= "Negation of AND logic of (Negation of A) and (Negation of B)"
* Therefore,
“OR logic of A and B” = “Negation of AND logic of (Negation of A) and (Negation of B)” ……
………………………………………… Formula (1)
★★ Equivalent circuit of AND circuit:
* From the double-negative theorem "AND logic of A and B" = A · B
= "Double negation of A and B"
* From the de Morgan theorem "Double negation of A and B" = "Negation of {(Negation of A) + (Negation of B)}"
= "Negation of OR logic between (Negation of A) and (Negation of B)"
* Therefore,
“AND logic of A and B” = “Negation of OR logic of (Negation of A) and (Negation of B)” ……
………………………………………… Equation (2)
★ ◆ ★ Duality in Boolean Algebra;
In the equations (1) and (2), if “1” and “0” on both sides of the self are exchanged, and AND logic and OR logic are exchanged at the same time, they become identities of each other and duality is established.

★ ◆ ★ New multivalued logic [duality in Hooji algebra:
Next, based on the multi-value logic circuit of FIG. 18, “a duality is established regardless of the multi-value number N in the new multi-value logic [Hooji algebra]” and the like will be described.
Where m = a specific integer for input = a specific integer for output, v _m is “a potential corresponding to the specific integer m”, and v _Cm (≠ v _m ) is “a potential corresponding to an integer other than the specific integer m” or “which “Independent additional potential that does not correspond to an integer”, that is, “any potential as long as the multi-value AND, OR, and NOT circuits cannot determine that the input numerical value is the specific integer m”. Note that represents the power line of the power supply potential _{v m} in _{V m,} represents the power line of the power supply potential _{v Cm} at _{V Cm.}
Also, “NOT (m) = m” is abbreviated as a specific integer for input = specific integer for output = m, a multi-value NOT circuit, and “AND (m) = m” is abbreviated as a specific integer for input = specific for output A multi-value AND circuit with integer = m, and “OR (m) = m” is abbreviated to mean a specific integer for input = specific integer for output = m.
To be sure, the definitions of multi-value {specific value (= specific integer)} NOT logic, multi-value (specific value) AND logic, and multi-value (specific value) OR logic are as follows.
Multi-value NOT logic: “Open the output” when the input numerical value is equal to the specific integer m, otherwise output the specific integer m.
Multi-value AND logic: When all the input numerical values are equal to the specific integer m, the specific integer m is output. Otherwise, the output is released.
Multi-valued OR logic: When the at least one input numerical value is equal to the specific integer m, the specific integer m is output. Otherwise, the output is released.
In the equivalent circuit of the multi-valued OR (m) circuit of FIG. 18A, “when at least one of the input logical variables x and y is an integer m, the logical function f (x, y) outputs a specific integer m, while If not, the output is released ". Moreover, the value of m is a free value from a negative integer to a positive integer.
On the other hand, in the equivalent circuit of the multi-value AND (m) circuit of FIG. 18B, “when the input logic variables x and y are all integers m, the logic function f (x, y) outputs a specific integer m, Otherwise, the output is released ". Again, the value of m is a free value from a negative integer to a positive integer.
In addition, since the multi-valued number N can be changed very easily as described in paragraph (17), which will be described later (paragraph number 0137), the “new multi-valued logic [Fuji algebra] has at least double negation regardless of the multi-valued number N. Theorem, De Morgan theorem, and duality theorem hold ”.

◆◆◆ ＊＊＊＊＊ Easiness to change specific integers not affected by multi-valued number N ＊＊＊＊＊ ◆◆◆
***
15) Multi-valued logic circuit based on “Fuji algebra” has no influence on multi-value number N at all [Easily change specific integer value m] and [Easily unitized or modularized circuit (unique) The following two features will be described.
◆ Each embodiment of the EQUAL (or determination) circuit, AND circuit, OR circuit, NOT circuit, NAND circuit, NOR circuit and its derivatives disclosed in the following patent publications of Patent Documents 1, 2, and 3 In this case, when the output switch unit is bidirectional, the specific integer m is (n−2) ≧ m ≧ 1, but even if “m = n−1” or “m = 0”, There is no problem in terms of operation and logic operation, and the value of the specific integer m can be freely set in the range of (n−1) ≧ m ≧ 0. However, it is only necessary to change the potential supply means (for example, a power supply line) to be connected.
However, in the case of m = n-1, may become a potential v _n require power supply line V _n or the like supplied to the top of the potential v _n-1, or discriminates on the basis of the threshold potential of "positive It just has an extra function or component.
When m = 0, the power supply line V _-1 for supplying the potential v ₋₁ under the potential v ₀ is necessary, or an extra “determining based on the minus threshold potential” is performed. There are various functions and components.
In addition, the specific integer m may take a free value from a negative integer to a positive integer (for example, in the case of sign-symmetric expression). In any case, the value of the specific integer m can be freely changed simply by changing the “potential supply means to be connected (eg, power supply line)”.
For this reason, it is not necessary to consider the difference of the specific integer m between the same multi-valued logics, and the same circuit configuration can be maintained. Become. (Unique effect)
☆ Specific example of circuit: multi-value AND circuit of FIG. 24 and each multi-value NOT {or NEVEN (neven or neven)} circuit of FIGS. 25 and 26.
JP 2004-032702 (New multi-value logic circuit based on multi-value logic “Fuji algebra”) JP 2005-198226 (same as above) JP 2005-236985 (same as above)

◆ Also, “IN circuit, OUT circuit, NIN circuit, NOUT” described above (paragraph numbers 0062 to 0066), “OVER circuit, UNDER circuit, NOVER circuit, NUNDER circuit”. Even in the case of “circuit”, the integer can be freely set within the limited setting range of “one or two specific integers for input”. However, the potential supply means to be connected (for example, a power supply line or the like) is simply changed in the same manner.
Here too, it is not necessary to consider the difference of each specific integer m between the same multi-valued logics, and the same circuit configuration can be used, so the circuit can be “unitized or modularized” for each type of multi-valued logic. become. (Unique effect)
In addition, in any case, as described later (paragraph number 0137), it has a feature that “change of the multi-value number N is extremely easy”, and therefore “changeability of a specific integer” is also “ Unitization or modularization] ”is not affected at all by the multi-valued number N.

◆◆◆ ＊＊＊＊＊＊＊＊ “Fuji Algebra” including Boolean Algebra ********
***
16) The following explains that the new multi-valued logic “Hooji algebra” includes binary logic Boolean algebra and is compatible.
The new multi-valued logic "Fuji algebra" is a Boolean algebra faithfully expanded and expanded to multi-values in the manner of the present inventor, completely including Boolean algebra, and compatible with Boolean algebra. .
For example, each output of a multi-value specific value EQUAL {or EVEN (even) or non-inverted} circuit having a specific integer value of 1, an AND circuit, an OR circuit, a NOT {or NEVEN (neven)} circuit, a NAND circuit, or a NOR circuit If the terminal is pulled down to the potential v ₀ of the power supply line V ₀ with a resistor and each input numerical value is limited to “1” and “0”, these multi-value logic circuits can use a binary / positive logic buffer (or The non-inverting circuit, the AND circuit, the OR circuit, the NOT circuit, the NAND circuit, and the NOR circuit perform the same logical operation and are compatible.
Each output of the multi-value specific value EQUAL {or EVEN (even) or non-inverted} circuit having a specific integer value of 0, an AND circuit, an OR circuit, a NOT {or NEVEN (neven)} circuit, a NAND circuit, and a NOR circuit By pulling up the terminal to the potential v ₁ of the power supply line V ₁ with a resistor and limiting each input numerical value to “1” and “0”, these multi-valued logic circuits can use binary / negative logic buffers ( (Or non-inverted) circuit, AND circuit, OR circuit, NOT circuit, NAND circuit, and NOR circuit have the same logical operation and are compatible.
On the other hand, a Boolean algebra composed of “AND circuit (= Min circuit), OR circuit (= Max circuit), inversion (complement circuit), literal circuit and cycling circuit” is expanded to multi-value. In the case of the conventional multi-valued logic circuit (Ukashevich type) that has been expanded, any multi-value circuit is a Boolean algebra with respect to the “invert circuit, literal circuit, and cycling circuit” that expands and expands the binary NOT circuit to multi-value. The binary NOT circuit is not included, and there is no compatibility.
Therefore, it goes without saying that the conventional multi-level NAND circuit and multi-level NOR circuit do not include a Boolean algebraic binary NAND circuit and a binary NOR circuit, and are not compatible at all.
* Reference: Non-Patent Document 3 p. 18-p. 20.
"Multi-valued information processing-post-binary electronics-", authors: Tatsuo Higuchi, Michitaka Kameyama, Shokodo in June 1989.

In addition, for example, in a 10-value logic circuit based on “Fuji algebra”, “an AND circuit with a specific integer value 8 corresponding to the power supply potential v ₈ ” is defined as “the potential v ₀ of the power supply line V ₀ corresponds to the integer 0, etc.” Although "it becomes 8 that particular integer value from that," if it potential v ₇ of the power supply line V ₇ is redefined as such and the corresponding integer 0 ", the particular integer value becomes 1. In this case, a “binary AND compatible circuit based on a Boolean algebra” is formed between the power supply lines V ₇ and V ₈ , and an AND circuit based on “Fuji algebra” is a “binary AND circuit based on a Boolean algebra ( In particular, open drain type and open collector type) ”.
Similarly, if the power supply potential to turn from the power supply line V ₆ to the power supply line V ₁ is redefined as such and the corresponding integer 0, integer value corresponding to the potential v ₈ of the power supply line V ₈ below It becomes like this.
・ Power supply line V ₆ potential v ₆ →→ integer value 2
・ Power supply line V ₅ potential v ₅ →→ integer value 3
・ Power supply line V ₄ potential v ₄ →→ integer value 4
・ Power supply line V ₃ potential v ₃ →→ integer value 5
And potential of the power supply line _{V 2 v 2} →→ integer value 6
・ Power supply line V ₁ potential v ₁ →→ integer value 7
During these redefinitions, the circuit configuration of the electronic circuit has not changed or changed at all, and is completely the same.
This is because, in the case of various / multi-valued logic circuits based on “Fuji algebra”, as described above (paragraph numbers 0133 to 0134), the change of the specific integer m is “one or more connected to the multi-value logic circuit”. This is because it is only necessary to change the plurality of power supply lines.

◆◆◆ ＊＊＊＊＊＊＊＊＊＊＊ Easiness to change multi-value number N ＊＊＊＊＊＊＊＊＊＊ ◆◆◆◆
***
17) Regarding the unique effects and features of the new multi-valued logic “Hooji algebra” that “it is very easy to change the multi-valued number N”:
As described above (paragraph numbers 0133 to 0134, 0136), the change of the specific integer m is extremely easy, so that the change of the multi-value number N is also very easy.
For example, in each basic / multi-value logic circuit such as an AND circuit, an OR circuit, a NOT circuit, etc., the same kind of basic / multi-value logic circuit groups having different multi-value numbers N are compatible with each other, and the multi-value number N The larger one includes the smaller one. This is because the multi-value number N can be obtained by adding “basic / multi-value logic circuit having the same basic configuration even if the specific integers are different (= only the power supply lines to be connected are different from each other)” as necessary. This can be easily changed.
Further, for example, if a combination / multi-value logic circuit is assembled with four values using a basic / multi-value logic circuit such as an AND circuit, OR circuit, NOT circuit, etc., if it is desired to change to five values, a potential supply means (eg: "One power supply and power line.)" And added the specific integer for input or the specific integer for output to "5" (that is, the power line to be connected, etc.) The multi-value number N can be changed very easily by simply adding a multi-value logic circuit or multi-value logic circuit unit or multi-value logic circuit module and making the necessary connections.
That is, it is possible to configure a “composite / multi-valued logic circuit with a large multi-value number N” as it is based on “a composite / multi-valued logic circuit with a small multi-value number N”.
***
On the other hand, in the case of a multi-value logic circuit based on “multi-valued logic such as Ukasevich's cocoon that expands / expands Boolean algebra to multi-value” as a conventional technique, binary NOT as described above (two previous paragraphs). Regarding “inverting circuits, literal circuits, and cycling circuits”, which are expanded and expanded to multi-valued circuits, not all multi-valued logic circuits include binary NOT circuits and are not interchangeable at all, and the multi-valued number N The same kind of basic / multi-valued logic circuits of different types cannot be included, and there is no compatibility.
For example, “a ternary inverting circuit and a quaternary inverting circuit”, “a ternary literal circuit and a quaternary literal circuit”, and “a ternary cycling circuit and a quaternary cycling circuit”. The same applies to other multivalued numbers.
For this reason, it is impossible to construct a “basic / multi-valued logic circuit with a large multi-value number” based on the “basic / multi-valued logic circuit with a small multi-valued number” as it is for these basic / multi-valued logic circuits. Of course, the same can be said for a multi-value NAND circuit and a multi-value NOR circuit to which these basic and multi-value logic circuits are applied.
As a result, it is possible to construct a “composite / multi-value logic circuit having a larger multi-value number” based on “a composite / multi-value logic circuit using at least one of these basic / multi-value logic circuits”. Since it is not possible to change the multi-value number N, it is extremely difficult. It is necessary to reassemble from scratch.

◆◆◆ ＊＊＊＊＊＊＊＊ Completeness of “Fuji Algebra”
***
18) About the unique effect / feature of "completeness by one kind of multi-valued logic circuit that is completely unaffected by the multi-valued number N, that is also [perfect]" in the new multivalued logic "Hooji algebra" This will be described below.
As described above (paragraph numbers [0130 to 0132]), “multi-value NAND logic or multi-value NOR logic, one kind of multi-values” due to “duality that duality holds regardless of multi-value number N” or the like. The perfection that can realize all multi-valued logic functions regardless of the multi-valued number N by [single] or [by combining a plurality of logics], and the effect / feature of [perfect] Algebra ”.
“Digital Digital Circuits Understandable”, p. 9 line 14 to p. "Complete system" on the first line of 10. Author: Keitaro Sekine, published by OHM Co., Ltd. on July 25, 1997. “Introduction to Logic Circuits”, p. 31 “(8) Complete system”. Author: Ryuji Hamabe, published by Morikita Publishing Co., Ltd. on September 28, 2001. "Multi-value information processing-Post binary electronics-", p. 16-p. 17 “completeness, complete system, complete” description. Author: Tatsuo Higuchi, Michitaka Kameyama, Shokodo published in June 1989.

“Easy to understand in terms of electronic circuit engineering” based on the composite / multi-valued logic circuit of FIG.
◆ However, in multi-level number N = 10 (10 decimal), the-specific integer m (= input specific integer = output for a particular integer) each Power line potential _{(eg: v 0 ~v 9,} v _C0 ˜v _C9 , v _C0 ≠ v ₀ ,..., V _C9 ≠ v ₉ ), each integer m (= 0, 1, 2,..., 8, 9) is specifically written from the beginning. The definition of each basic / multi-valued logic circuit is as described above (first half of paragraph number 0132). Note that represent each power line of the power supply potential _v 0 to v ₉ at _V 0 ~V _9, represent the respective power line of the power supply potential _v C0 _{to v C9} in _V C0 _{~V C9.}
Also, as in the case of the binary logic circuit, “all the input terminals of the multi-level NAND circuit are connected and combined into one input terminal” or “the other input is left with one input terminal of the multi-level NAND circuit. If all the input terminals are connected to the power supply line or the like of the input specific potential v _m of the NAND circuit (= the power supply potential corresponding to the input specific integer m), the multi-level NAND circuit is “multi-level NOT. Circuit ".
* Reference: Japanese Patent Application Laid-Open No. 2005-236985 / multi-value (specific value) NAND circuit (3 inputs) of FIG.
Furthermore, the output terminal of the multi-level NAND circuit is pulled up or down with a resistor or the like to a power supply potential v _Cm (≠ v _m ) other than the input specific potential (= output specific potential) v _m of the NAND circuit If the “multi-level NOT circuit” is connected to the subsequent stage of the output terminal, the multi-level NAND circuit becomes a multi-level AND circuit.
◆ Or, as in the case of the binary logic circuit, “all the input terminals of the multi-value NOR circuit are connected to one input terminal” or “one other input terminal of the multi-value NOR circuit is left. The multi-value NOR circuit is “a multi-value NOT circuit” by connecting all of the input terminals to a power line of a power supply potential v _Cm (≠ v _m ) other than the input specific potential v _{m of the} NOR circuit. become.
★ Reference: Japanese Patent Application Laid-Open No. 2005-236985 / multi-value (specific value) NOR circuit of FIG.
◆ Then, the output terminal of the multi-value NOR circuit is pulled up or down with a resistor to a power supply potential v _Cm (≠ v _m ) other than the input specific potential (= output specific potential) v _m of the NOR circuit. If the “multi-value NOT circuit” is connected to the subsequent stage of the output terminal, the multi-value NOR circuit becomes a multi-value OR circuit.
In addition, as described above (FIG. 18 and paragraph numbers [0130-0132]), a multi-valued OR circuit can be constructed from a multi-valued OR circuit due to the feature of “duality of new multivalued logic“ Fuji algebra ”” Or, conversely, a multi-value OR circuit or the like can be constructed from a multi-value AND circuit.
Therefore, a multi-value NOR circuit, a multi-value AND circuit, a multi-value NOT circuit, and a multi-value NAND circuit are constructed from one type of multi-value NOR circuit, or a multi-value OR circuit and a multi-value AND circuit are constructed from one type of multi-value NAND circuit. A multi-value NOT circuit and a multi-value NOR circuit can be configured.
As a result, the new multi-valued logic “Fuji algebra” has the feature of “ease of changing the specific integer m, which is not influenced by the multi-valued number N”, as described above (paragraph numbers [0133 to 0134]). It can be seen that the composite / multi-valued logic circuit of FIG. 19 can be configured with only one type of basic / multi-valued logic circuit based on the “multi-valued NAND circuit or multi-valued NOR circuit”.

19 is a circuit capable of realizing and realizing “all the multi-value logic functions represented by the truth table of the multi-value logic function f (x, y) shown in FIG. 20”. is there. However, FIG. 20 is considerably omitted and simplified for easy understanding.
The truth table of f (x, y) shown in FIG. 20 is obtained by rewriting the numerical pattern, that is, by rewriting the numerical value of each 升 (mass), decimal notation, and 2 (multi-valued) logical variable x. , Y can be expressed as all-multi-valued logic functions (10 to the power of 100 / variable).
Because there are 10 numbers of integers “0-9” that can be taken by one square, and the total number of squares is 100, so the numerical patterns that 100 squares can take are all. (10 ways) × (10 ways) × …… ≪ << Product of 100 (10 ways) >> ≫ ………… (10 ways) × (10 ways) = 10 to the 100th power Because it becomes.
In addition, in the truth table of f (x, y) shown in FIG. 20, the N-ary system and the two logical variables are changed by changing the “multi-value number N” and “each logical variable range of logical variables x and y”. Can express all / multi-valued logic functions For example, 6 ≧ x ≧ 0, 6 ≧ y ≧ 0 in N = 7 octal system. In this case, there are a total of 7 cells in the x horizontal direction and 7 cells in the y vertical direction in FIG. 20, so the total number of cells is 49, and the numerical pattern is 7 to the 49th power.・ It becomes a kind.
Japanese Unexamined Patent Application Publication No. 2007-035233 paragraph number [0030-0031] explains the number of types of multi-valued logic functions.

By the way, the item {D> in paragraph number [0146] described later. } "As the combination of each value of the input logic variables x and y can be expressed by a 2-input multi-value AND circuit," etc., "A combination of input logic variables w, x, y, and z can be expressed by a 4-input multi-value AND circuit" and " The combination of the values of the input logical variables u, w, x, y, and z can be expressed by a multi-input AND circuit with five inputs, etc., and so on, according to the number of the input logical variables. By increasing or decreasing the number of inputs of the circuit, it is possible to cope with the increase or decrease of the number.
However, according to the increase or decrease in the number of input logical variables (the way the truth table is written changes), the “total number of cells in the corresponding truth table” also increases or decreases. It corresponds to the total number / increase / decrease of the squares of the truth table according to "."
For example, in the case of 6 inputs of 10-digit 1-digit input logical variables u, w, x, y, z, and a, the place of x is replaced with uwx and the place of y is replaced with yza in the truth table of FIG. . For this reason, the uwx horizontal direction becomes 1,000 squares of “numerical value 000 to 999”, and the yza vertical direction also becomes 1,000 squares of “numerical value 000 to 999”. The number pattern is 10 to the 1 millionth power / type. Of course, at this time, each of the input logical variables u, w, x, y, z, and a represents an integer of 10 values and 1 digit. By this representation, the number of input logical variables is 6 The truth table can be represented by a truth table (although it is quite difficult from the total number of cells), and can be expressed by a vertical, horizontal, or simple mechanism.
Here, furthermore, the uwx can be replaced with x ₂ x ₁ x ₀ , and the x ₂ x ₁ x ₀ can represent the three digits of x. At this time, it can be interpreted that the input logical variable x is expressed by 10 values and 3 digits, or can be interpreted as expressed by 1000 values and 1 digit.
It may sound strange to say "1000 values represented by one digit", but we already have 16 values "0, 1, 2, ..., 8, 9, A, B, C, D, E. , F "is represented by one digit of 16 characters. “Numerical value 10 corresponds to A, numerical value 11 corresponds to B,..., Numerical value 14 corresponds to E, and numerical value 15 corresponds to F”. Similarly, if each numerical value of 10 to 999 is replaced with one character at a time, it can be expressed with one digit of 1000 values. On the other hand, in the case of 10-value 3-digit expression, the three characters x ₂ x ₁ x ₀ represent independent numbers, so if x ₂ x ₁ x ₀ is represented by one character, it is 10-digit 3-digit・ The meaning of expression is lost. Further, at least 1000 power supply potentials are required for 1000 values, but at least 10 are required for 10 values.
The remaining yza side can also replace the yza with y ₂ y ₁ y ₀ and express the three digits of y with this y ₂ y ₁ y ₀ . At this time, similarly, the input logical variable y can be interpreted as being expressed by 10 values and 3 digits, or can be interpreted as being expressed by 1000 values and 1 digit.
For this reason, if the synthesis / multi-value logic circuit of FIG. 19 is expressed by “the truth table of the logic function f (x, y) shown in FIG. If it can be proved that the "value logic function" can be realized and embodied, the "completeness" of the multi-valued logic "Hooji Algebra", or "completeness", regardless of the number of logical variables and the number of digits It will be proved.

The synthesis / multi-value logic circuit of FIG. 19 is one configuration example of “a circuit that can realize all the multi-value logic functions of two logic variables”, and most of the configuration means are indicated by dotted lines. Although not shown, it is as follows.
However, “NOT (m) = m” is a specific integer for input = specific integer for output = m, and “AND (m) = m” is a specific integer for input = specific integer for output = m. In the multi-value AND circuit, “OR (m) = m” means a multi-value OR circuit in which a specific integer for input = a specific integer for output = m, respectively. In FIG. m (= 0, 1, 2,..., 8, 9) is written.
In FIG. 19, between the multi-value “OR (0) = 0” circuit and the multi-value “OR (9) = 9” circuit, the multi-value “OR (1) = 1” circuit to the multi-value “OR (8) ) = 8 ”circuit, and there are multi-value“ AND (0) = 0 ”circuit group (= circuits represented by“ AND (0) = 0 ”) and multi-value“ AND (9) = ”. 9 ”circuit groups (= circuits represented by“ AND (9) = 9 ”/ all) are usually multivalued“ AND (1) = 1 ”circuit group to multivalued“ AND (8) = 8 ”. There are 8 circuit groups of circuit groups. Each multi-value “AND (...) =...” Circuit group is connected with a necessary number of multi-value “NOT (...) =.
In addition, again, the operations of the multi-value “OR (m) = m” circuit, multi-value “AND (m) = m” circuit, and multi-value “NOT (m) = m” circuit are as follows. Street.
Multi-value “OR (m) = m” circuit: outputs a specific integer m when at least one of a plurality of input numerical values is a specific integer m, and releases the output otherwise.
Multi-value “AND (m) = m” circuit: outputs a specific integer m when all of a plurality of input numerical values are a specific integer m, and releases the output otherwise.
Multi-value “NOT (m) = m” circuit: When one input numerical value is a specific integer m, the output is released, and when not, a specific integer m is output.

■■ Rough explanation of circuit and function ■■
In FIG. 19, a specific integer value m (= 0, 1, 2,..., 8, 9) is written in each specific integer m, and the function of each circuit is as follows.
◆ A multi-value “OR (m) = m” circuit group (drawing / longitudinal group; total of 10 circuits) is an integer m described in the truth table of f (x, y) shown in FIG. = 0, 1, ..., 8, 9 are output.
Accordingly, the number of multi-valued “OR (m) = m” circuits and the “number of types of integers described in the truth table of f (x, y) shown in FIG. 20” are the same. For this reason, if only 9 types of integers are described, there are only 9 circuits corresponding to the remaining 9 integers, excluding the integers not described. If there are 8 types, there are only 8 circuits. The same applies to the following, but for the sake of clarity, the description will be made assuming that m = 0 to 9.
◆ Multi-valued “OR (m) = m” circuit and multi-valued “AND (m) = m” belonging to the same multi-valued OR-AND-NOT circuit group (drawing / horizontal direction group in total 10 groups) Each value (= 0-9) of both m of the circuit is the same. Naturally, the number of groups and the total number of multi-valued “OR (m) = m” circuits are the same.
◆ Each multi-value “AND (m) = m” circuit group (drawing / vertically extending group, m = 0 to 9) is “as per each relationship shown in FIG. 20 truth table” f (x , Y) and each value of x, y are linked.
For this reason, the number of the logical variables and the number of input terminals of each multi-value “AND (m) = m” circuit are the same.
The number of “AND (m) = m” circuits belonging to each multi-valued OR-AND-NOT circuit group is “integer number unique to the circuit group” in the truth table of f (x, y) shown in FIG. Is the same as the total number of cells in which the value m ”is written.
Each multi-value “NOT (m) = m” circuit group (drawing / longitudinal group; m = 0 to 9) discriminates each value of x and y.
The reason for this is that the m value of each multi-value “AND (m) = m” circuit may be different from the “specific integer value m that should be originally compared when discriminating”. For this reason, the m value of each AND circuit and the m value of the “NOT circuit connected thereto” are necessarily different.
If both m values match, the multi-value “NOT (m) = m” circuit is unnecessary, and the multi-value “AND (m) = m” circuit directly determines the value of x or y. The input terminal Tx or the input terminal Ty is directly connected to the input part of the multi-value “AND (m) = m” circuit.
That is, when the value of f (x, y) and the value of x are the same m value, the multi-value “AND (m) = m” circuit directly determines the value of x, and the value of f (x, y) If the values of y and y are the same m value, the multi-value “AND (m) = m” circuit directly determines the y value.
◆ Pull-up resistor or pull-down resistor connected between each multi-value “AND (m) = m” circuit and each multi-value “OR (m) = m” circuit is the former. In order to make each output signal each input signal of the latter, both signals are matched. Each power supply potential has a relationship of v _C0 ≠ v ₀ , v _C1 ≠ v ₁ , v _C2 ≠ v ₂ ,..., V _C9 ≠ v ₉ , but each power line of the power supply potentials v _{0 to} v _9. the expressed as _V 0 ~V _9, it represents the respective power line of the power supply potential _v C0 _{to v C9} in _V C0 _{~V C9.}
◆ A pull-up resistor or pull-down resistor connected between each multi-value “NOT (m) = m” circuit and each multi-value “AND (m) = m” circuit is also the former. In order to make each output signal each input signal of the latter, both signals are matched.

■■ Details of each function are as follows. ■■
◆ 1) In the multi-level OR-the AND-NOT circuit group configured to identify an integer m = 0 multilevel OR circuit, multi-level "OR (0) = 0" input of the circuit shown in FIG. 20 f (x, In the truth table of y), all cases where f (x, y) = 0 are satisfied are covered. Therefore, “the total number of cells in which m = 0 is written” = the total number of input terminals of the multi-value “OR (0) = 0” circuit (= the total number of multi-value “AND (0) = 0” circuits). .
It should be noted that both m values of “OR (m) = m” and “AND (m) = m” belonging to the same multi-valued OR-AND-NOT circuit group are the same, but each “NOT (m ) = M ”is always different from the m value.
Also, if there are only two “total cells in which m = 0” is written in the truth table, the number of input terminals of the multi-value “OR (0) = 0” circuit is also two. If there are a total of 70 “cells in which m = 0” are written, the number of input terminals is also 70.
2) Each multi-value “AND (0) = 0” circuit set to a specific integer m = 0 “each value / combination of logical variables x and y satisfying f (x, y) = 0” Cover it. In other words, each multi-value “AND (0) = 0” circuit has a one-to-one correspondence with “each combination of x value and y value of a square in which m = 0 is written”.
In the truth table of FIG. 20, each combination of (5, 0) and (8, 3) is illustrated, and f (5, 0) = 0 and f (8, 3) = 0.
In this way, each multi-value “AND (m) = m” circuit covers (returns) “each combination of values of logical variables x and y satisfying f (x, y) = m”.
◆ 3) Each “NOT (m) = m” circuit connected to the input terminal Tx determines the logical variable x = m (= 0, 1, 2,..., 8, 9) and connects to the input terminal Ty. Each “NOT (m) = m” circuit thus determined determines the logical variable y = m (= 0, 1, 2,..., 8, 9).
However, when the value of the logical variable x to be determined is the same as the m value of the multi-value “AND (m) = m” circuit, the multi-value “AND (m) = m” is not used without using the “NOT (m) = m” circuit. The “m” circuit directly determines whether the logical variable x = m.
For example, if the value of the logical variable x satisfying f (x, y) = 0 is 0 (that is, when the f value = x value), the “NOT (0) = 0” circuit is not necessary, so the input terminal Tx The potential signal is input as it is to the multi-value “AND (0) = 0” circuit.
If the value of the logical variable y satisfying f (x, y) = 0 is 0 (that is, when the f value = y value), the “NOT (0) = 0” circuit is not necessary, so that the input terminal Ty Since the potential signal is input to the multi-value “AND (0) = 0” circuit as it is, both are directly connected by a conducting wire as shown in FIG.
→→ When f (5,0) = 0, the input terminal Ty is directly connected to the second input terminal of the lowest multi-value “AND (0) = 0” circuit.
→→ Similarly, when f (7,9) = 9, the input terminal Ty is directly connected to the second input terminal of the lowest multi-value “AND (9) = 9” circuit.
◆ 4) Pull-up or “up or down” connected one by one between the multi-value “OR (0) = 0” circuit set to a specific integer m = 0 and each multi-value “AND (0) = 0” circuit A “down” resistor provides input / output signal matching. Therefore, the potential v _C0 ≠ v ₀ .
5) Each combination of “multi-value“ NOT (...) =... Circuit ”and pull /“ up or down ”resistance in the same circuit group is each potential signal of the input terminals Tx and Ty and each multi-value“ AND ”. (0) = 0 ”Match the input part of the circuit.
6) Similarly, each of the multi-value circuit groups (= multi-value OR, AND, and NOT circuit groups) set to “specific integer m = 1 to 9” has the same function. Fulfill.

The above is the case of the decimal system. However, in the case of the N-base system, the cell value = 0 is as described above, and only the above-mentioned “similar integers m = 1 to 9” are also used. “Hereafter,“ specific integer m = 1 to (N−1) ”respectively” (in the case of normal multi-value numerical expression) or “hereinafter, similarly“ specific value m = − (N−1) to −1, 1 ”. ˜ (N−1) ”” (in the case of code-symmetric expression), etc.
***
As described above, the synthesis / multi-value logic circuit of FIG. 19 can realize and embody “all multi-value logic functions represented by the truth table of f (x, y) shown in FIG. 20 ”.・ The "completeness" of the multi-valued logic "Fuji algebra" is proved. In addition, since all the multi-valued logic functions can be realized and realized by using only one type of basic / multi-valued logic circuit as described above (paragraph number 0 139 ) without using a “logic constant input circuit”. The "perfect" of the multi-valued logic "Fuji algebra" is proved.
★★ “Complete” of “Fuji Algebra” with only one type of basic / multi-valued logic circuit ★★
"Multi-value information processing-Post binary electronics-", p. 16-p. 17 “completeness, complete system, complete” description. Author: Tatsuo Higuchi, Michitaka Kameyama, Shokodo published in June 1989.

■■ Composition of multi-valued logic circuit shown in Fig. 19 and individual explanation ■■
As a precaution, the composition / individual logic circuit shown in FIG. 19 will be specifically described with reference to a “simplified f (x, y) truth table” shown in FIG. However, the problems of maximum fan-in, maximum fan-out, current capacity, and multi-value hazard are ignored.
◆ b) Each f (x, y) truth table of f (x, y) shown in Fig. 20 is usually marked with “each (specific integer value) f (x, y) = 0-9”. However, each multi-valued “OR (m) = m” circuit is prepared in which each specific integer value to be described is a specific integer m.
If there is a specific integer not described there, a multivalue “OR (m) = m” circuit of the specific integer not described, each multivalue “AND (m) = m”. The circuit and each multi-value “NOT (...) =...” Circuit connected to the previous stage of the “multi-value“ AND (m) = m ”circuit are unnecessary and can be omitted.
(B) In the truth table of f (x, y) shown in FIG. 20, when looking at an integer value of a certain cell, for example, a cell of f (x, y) = 0 set to an integer m = 0, Since there are two (since the illustration is simplified, there may be more cases in reality), the multi-value “OR (0 (0)) is set to a specific integer m = 0 in the multi-value“ OR (m) = m ”circuit. ) = 0 ”The number of input terminals of the circuit is set to two of the same number.
◆ C) Set the specific integer m = 0 in the multi-value “AND (m) = m” circuit by the same number as the number of input terminals of the multi-value “OR (0) = 0” circuit set to the specific integer m = 0. A multi-value “AND (0) = 0” circuit is prepared. Then, one multi-value “AND (0) = 0” circuit is connected to the preceding stage of the multi-value “OR (0) = 0” circuit one by one.
◆ D) At this time, the number of input terminals of each multi-value “AND (m) = m” circuit is 2 which is the same as the number 2 of logical variables x and y, but there are 3 logical variables x, y and z If the number of input terminals is 3, the number of input terminals is 4 if there are four logical variables w, x, y, and z, and the logical variables are 5 of u, w, x, y, and z. If there is one, the number of input terminals is five. All that remains is to connect a multi-value “NOT (m) = m” circuit to each input terminal one by one.
Each multi-value “AND (m) = m” circuit has two input terminals as described in the above section d).
◆ e) each multi-level "the AND (0) = 0" set to a specific integer m = 0 potential _{v 0} the output terminal of the circuit (this time m = 0 So _v m _{= v} 0.) Other potential _{v C0} ( At this time, since m = 0, it is pulled up or pulled down to v _Cm = v _C0 . v _C0 ≠ v ₀ (v _Cm ≠ v _m ).
The potential v _Cm is “a potential corresponding to an integer other than the specific integer m” or “an independent additional potential that does not correspond to any integer, and the multi-value“ OR (m) = m ”circuit is set to the specific integer m. Any potential that is not discriminated can be used.
F) Confirm each combination (5, 0), (8, 3) of the values of the logical variables x, y satisfying f (x, y) = 0 set to the integer m = 0 in FIG.
In general, each combination of the values of logical variables x and y satisfying f (x, y) = m is confirmed.

◆ G) For the first set (5, 0), between the input terminal Tx and the first input terminal of the first multi-value “AND (0) = 0” circuit (a specific integer m = 0 of AND) certain integer m = 5 multilevel "NOT (5) = 5" to (= logical variable value _{m x} of x) to connect the circuit, the multi-value "NOT (5) = 5" potential output terminal of the circuit to Pull “up or down” to v0 (v _m = v _{0 because} AND is a specific integer m = ₀ ).
On the other hand, in the case between the input terminal Ty and the second input terminal of the first multi-value “AND (0) = 0” circuit (where m = 0), the logical variable y value m _y = 0 and the AND Since the specific value m = 0 of the circuit is 0, the input terminal Ty is directly connected to the second input terminal of the first multi-value “AND (0) = 0” circuit as it is.
Of course, if the value m _y ≠ 0 of the logical variable y, as in the case of the input terminal Tx, between the input terminal Ty and its second input terminal, a multivalue “ NOT (...) =.
If there is a case where the value m _x = 0 of the logical variable x, the input terminal Tx remains as it is in the first multi-value “AND (0) = 0 as in the case where the value m _y = 0 of the logical variable y. Directly connected to the first input terminal of the circuit.
◆ H) For the second set (8, 3), specify between the input terminal Tx and the first input terminal of the second multi-value “AND (0) = 0” circuit (in this case, m = 0) integer m = 8 (= logical variable values of x _{m x)} to connect the multi-value "NOT (8) = 8" circuits, the multi-value "NOT (8) = 8" output terminal potential of the circuit _{v 0} Pull (up or down) to (v _m = v _{0 because} m = 0 at this time).
On the other hand, a specific integer m = 3 (= the value m _{y of the} logical variable _y ) between the input terminal Ty and the second input terminal of the second multi-value “AND (0) = 0” circuit (where m = 0). Multi-value “NOT (3) = 3” circuit is connected, and the output terminal of the multi-value “NOT (3) = 3” circuit is connected to potential v ₀ (since m = 0 at this time, v _m = v ₀ ). Pull to “up or down”.
Of course, if there is a case where the value m _x = 0 of the logical variable x or the value m _y = 0 of the logical variable y, the direct connection work is performed in the same manner as the connection work in the above item ( _g ).
◆ Re) If, f (x in the truth table of f (x, y) shown in FIG. 20, y) = 0 a satisfactory logical variables x and y values _m x, Yes in combination of _{m y} other If necessary, the connection work in the above item (vi) or item (v) is repeated for the number of combinations.
◆) Similarly, for the integer of “f (x, y) = 1 to 9” in the truth table of f (x, y) shown in FIG. Instead of m = 0, the specific integers m = 1 to 9 are set, respectively, and the connection work of “above ◆ b) to above ◆ re)” is repeated.
◆ Le) The above is the case of the decimal system, but in the case of the N-base system, the above “f (x, y) = 1 to 9” is replaced with “f (x, y) = 1 to (N− 1) "(ordinary N-value phenotype) or" f (x, y) =-(N-1) to -1, 1- (N-1) "(sign-symmetric phenotype), etc. .
The connection work is completed.

Then, in the synthesis / multi-value logic circuit of FIG. 19, each multi-value “OR (m) = m” circuit and each multi-value “AND (m) = m” circuit are simultaneously multi-value “NAND (m) = Multi-value equivalent circuits are possible, one by one replaced with the “m” circuit. Of course, each integer value of m is set to each integer value shown in FIG. 19, and each number of input terminals is also set to each number of input terminals shown in FIG.
Reasons, one an equivalent circuit of the multi-valued "OR (m) = m" circuit of FIG. 1 8 (a) each-multi-level "OR (m) = m" circuit in Figure 19 to become equivalent circuit Each of the series circuits of the “multi-value“ AND (m) = m ”circuit and the multi-value“ NOT (m) = m ”circuit connected to the subsequent stage” after the replacement is replaced with the multi-value “NAND (m This is because the above-described multi-value equivalent circuit is obtained by replacing one by one with the “) = m” circuit.
Further, as described above (paragraph number [0139]), each multi-value “NOT (m) = m” circuit in FIG. 19 is “multi-value in which all the input terminals are connected to one input terminal. If replaced with “NAND (m) = m” circuit ”one by one, the above multi-value equivalent circuit, that is, the composite / multi-value logic circuit of FIG. I understand.
Moreover, as described above (in paragraph No. [0140]), by changing each of the logical variables x and y and the logical variable range, it is possible to express N-ary, two logical variables, and multi-valued logical functions, and { The number of logical variables can be changed as in [0141] and [0146], or the number of digits of each logical variable x and y can be changed to 3 digits.
That's why the new multi-valued logic “Hooji Algebra” has a unique effect and feature of “completeness by one kind of multi-valued logic that is completely unaffected by the multi-valued number N, it is also [perfect]” There is.
◆ ↑ Only one type of basic / multi-valued logic circuit that is not affected by the multi-value number N at all ↑ ◆
◆ ↑ “Complete” of new multivalued logic “Hooji algebra” by ↑ ◆

◆◆◆ ＊＊＊＊＊ Multi-value wired OR circuit in “Fuji algebra” ********
***
19) Describe that a multi-value wired OR circuit holds in a multi-value logic circuit based on the new multi-value logic “Hooji algebra”.
First, FIG. 21 shows a synthesis / multi-value logic circuit (= complete circuit) in which a multi-value wired OR circuit is introduced into the synthesis / multi-value logic circuit (= complete circuit) of FIG. Of course, the latter circuit configuration is considerably simpler than the former circuit configuration, and the number of components is correspondingly reduced.
In the synthesis / multilevel logic circuit of FIG. 21, the pull-up resistor and the pull-down resistor are not connected to the output terminal Tf because the output switch unit of any AND circuit is always turned on and the output This is because the potential of the terminal Tf is pulled up or pulled down, so that the pull-up resistor and the pull-down resistor can be omitted.
→→ Power consumption of each pull resistor.
If there is at least one square in which no numerical value is entered in the truth table of FIG. 20, the output terminal Tf is opened at the x value and y value of the square, so that a pull-up resistor or pull-up resistor Attach one end of the down resistor at the output terminal Tf, required there to connect the other end to a predetermined power supply line V _Cm.
The composite / multi-valued logic circuit of FIG. 21 satisfies the truth table of FIG. 20 in the same manner as the composite / multi-valued logic circuit of FIG. y) If each integer value is applied to the synthesis / multi-value logic circuit of FIG. However, if simply considered, “each AND circuit of the synthesis / multi-value logic circuit of FIG. 19 outputs the output numerical value to the output terminal Tf via each OR circuit”, whereas “the synthesis / multiplication logic of FIG. The only difference is that each AND circuit of the multi-value logic circuit outputs its output value directly to the output terminal Tf.

Then, in addition to the problem of the circuit configuration and the number of parts, the composite / multi-value logic circuit of FIG. 19 has a “problem to be solved” that is “very inconvenient and impractical”, but “multi-value wired OR” The synthesis / multi-valued logic circuit of FIG. 21 using a circuit can solve the problem.
◆ Example 1: In the truth table of FIG. 20, there are a total of 80 cells whose integer value is 6, for example, and there are 2 or 3 cells each of integer values 0 to 5 and 7 to 9 other than 6. The total number of input terminals of the multi-value “OR (6) = 6” circuit is 80. The others are two or three.
◆ Example 2: In the truth table of FIG. 20, when the number of squares each having an integer value of m = 0 to 9 is uniformly about 10, each multi-value “OR (m) = m” circuit The total number of input terminals is about 10 uniformly.
***
In short, depending on the numerical pattern of the truth table of FIG. 20, that is, depending on how many squares of the same integer value, the total number of input terminals of each multi-value “OR (m) = m” circuit varies. In addition, if the integer value m to be written is shifted, the total number of input terminals of the specific multi-value “OR (m) = m” circuit is particularly increased.
As a result, it is very inconvenient and not practical when the multi-value logic function shown in the truth table of FIG. 20 is embodied and realized as a synthesis / multi-value logic circuit.
On the other hand, since the composite / multi-value logic circuit of FIG. 21 uses a multi-value wired OR circuit, “each multi-value“ OR (m) whose number of input terminals varies depending on the numerical pattern of the truth table of FIG. 20 ”. = M ”circuit itself” does not exist, and therefore the synthesis / multi-valued logic circuit of FIG. 21 can solve the above-mentioned “problem to be solved”. In addition, as described above, the synthesis / multi-value logic circuit of FIG. 21 has a simpler circuit configuration and a smaller number of parts than the synthesis / multi-value logic circuit of FIG. Convenient.
These are the relationship between “the synthesis / multi-valued logic circuit (multi-value number N = 3) in FIG. 22 and the truth table in FIG. 23” described later, and its development / derivation circuit (multi-value number N = 4). The same applies to the relationship of 5, 6,.

◆◆◆ ＊＊＊＊＊ “Complete” circuit (three-dimensional) IC / LSI, etc. *****＊＊ ◆◆◆◆
***
20) Explain that (complete) circuit (3D) programmable logic array, semi-order (3D) IC / LSI, etc. are possible.
The synthesis / multi-value logic circuit of FIG. 22 is “in the synthesis / multi-value logic circuit of FIG. 19, the multi-value number of both logical variables x and y is changed from 10 to 3, and three multi-value“ OR (m) ” = M ”A circuit configuration is simplified and standardized by using a multi-value wired OR circuit instead of the circuit (m = 0, 1, 2)”.
Note that since any one of the plurality of AND circuits is always on, connection of a pull-up resistor or a pull-down resistor can be omitted. That is, there is no need to connect it. →→ Power saving.
This facilitates implementation of (three-dimensional) programmable logic array and semi-order (three-dimensional) IC / LSI, which is convenient.
◆◆ Usefulness of multi-value wired OR circuit ◆◆
FIG. 23 is a truth table / diagram of the function f (x, y) = m _z in FIG. 22 and is rewritten as follows.
X = 0, 1, 2
◆ y = 0, 1, 2
◆ f (x, y) = m _z , (m _z = m0, m1,..., M7, m8)
f (0,0) = m0, f (0,1) = m1, f (0,2) = m2
f (1, 0) = m3, f (1,1) = m4, f (1,2) = m5
f (2,0) = m6, f (2,1) = m7, f (2,2) = m8
However, 2 ≧ m0, m1, m2, m3, m4, m5, m6, m7, m8 ≧ 0
***
Since each integer value of m0 to m8 is one of 0, 1, and 2, m0 has three values, m1 has three values,..., m8 has three values. “Types of multi-valued logical function f (x, y) that can be expressed in all of these” = (3 types) × (3 types) × (3 types) × (3 types) × (3 types) × (3 types) × There are (3 ways) × (3 ways) × (3 ways) = 3 to the 9th power and types = 19,683 types.
Then, in FIG. 22, one “simple conductor” is drawn next to each multi-value “NOT (m) = m” circuit, and each multi-value “AND (m _z ) = The “m _z ” circuit / input section is connected via each / multi-valued “NOT (m) = m” circuit and may be directly connected by “each connecting terminal and each dotted line”. Has been.
In FIG. 23, when the value m _x (any one of 0, 1, 2) of the logical variable x and the value m _{z of the} multi-valued logical function f (x, y) are the same (m _x = m _z ), The input terminal Tx is directly connected to “a first input terminal of a multi-value“ AND (m _z ) = m _z ”circuit whose m _z is a specific integer”.
On the other hand, when the value _{m z} of logical variables x values _{m x} and the multi-level logic function f (x, y) is different from _{(m x} ≠ _{m z),} the multi-level "NOT (m as the input terminal Tx 22 _x ) = m _x ”circuit is connected to“ a first input terminal of a multi-value “AND (m _z ) = m _z ” circuit whose m _z is a specific integer ”.
Similarly, the connection between the input terminal Ty and the second input terminal of each multi-value “AND (m _z ) = m _z ” circuit is also connected via the multi-value “NOT (m _y ) = m _y ” circuit. Or connected directly. However, _{m y} is the value of a logical variable y, of 0,1,2 is any one.

If the integer values of m0 to m8 are sequentially set to integers of 0 to 8, the synthesis / multi-value logic circuit of FIG. 22 becomes a ternary / 9-value code conversion circuit. Of course, y is the first digit of the ternary representation and x is the second digit of the ternary representation. In this case, the specific potential supply means of the “AND (0) = 0” circuit is, for example, the power supply line V ₀ , the specific potential supply means of the “AND (1) = 1” circuit is, for example, the power supply line V ₁ ,. The specific potential supply means of the “AND (9) = 9” circuit is, for example, the power supply line V ₉ .
In addition, the multi-value number of each of the three logical variables x and y and the three multi-value logic functions f (x, y) can be freely set. All / multi-value numbers may be set to the same value, or each / multi-value number may be set to a different value.
Further, when the three multi-value numbers N are the same and are 4, the “types of multi-valued logic function f (x, y) that can be expressed” are 4 16 · type≈4,294,968,000 types. . Moreover, such a large type of multi-valued logic function is “a multi-value [AND (...) =...] Circuit, two multi-value [NOT (...) =... The number of combinations of “and two conductors” is increased from 9 to 16 and the power supply and the power line are increased one by one as the multi-value increases by one ”.
Similarly, when the same multi-value number is 5, the “type of multi-valued logical function f (x, y) that can be expressed” is 5 to the 25th power and the kind≈2.980233 × (10 to the 17th power), In the synthesis / multi-valued logic circuit of FIG. 22, the above-mentioned combinations need only be increased from 16 sets to 25 sets.
Similarly, when the same multi-value number is 10, the “type of multi-value logic function f (x, y) that can be expressed” is 10 to the 100th power / type, and the above / combination in the composition / multi-value logic circuit of FIG. It is only necessary to increase the number from 25 to 100.
For this reason , the “number of types of multi-valued logic functions f (x, y) that can be expressed” increases super-explosively as the number N of the same multi-values increases for a small number of parts.
* Reference: Paragraph number [0031 to 0033] of JP-A-2007-035233.
In addition, as will be described later (paragraph number 0154), each of the multi-value numbers of the logic variable x, the logic variable y, and the multi-value logic function f (x, y) may be different. They do not have to be identical. → Flexibility.
Such super-explosive increase and the flexibility to cope with it are possible by combining each synthesis / multi-valued logic circuit of FIG. 21 and FIG. When it is put to practical use, it becomes an extremely powerful weapon and effect.

As specific multi-value circuits, for example, there are the following two examples.
◆ Example 1: FIG. 24 shows an example of an asynchronous multi-value “AND (m) = m” circuit, and FIGS. 25 and 26 show two examples of an asynchronous multi-value “NOT (m) = m” circuit. Indicates.
In the asynchronous multi-value NOT circuit of FIG. 25, the diode 125 indicates that “when the transistor 101 is off and the transistors 102 and 128 are on, the power line V _m goes through the resistor 123, the transistor 128, the resistor 120, and the transistor 102. _It is for preventing current from flowing to _m-1 . " When the transistors 101 and 128 cannot drive the transistor 124 off due to the forward voltage of the diode 125, the diode 126 and the resistor 127 are necessary. However, if the transistor 101 is off when the transistor 101 is off and the transistor 102 is on, the diodes 125 and 126 do not need to be inserted and connected, and the resistor 127 is also unnecessary.
* Reference: Each circuit of FIG. 10 and FIG. 9 of patent document 3 (Unexamined-Japanese-Patent No. 2005-236985).
The asynchronous / multi-value NOT circuit of FIG. 26 is changed to an asynchronous / multi-value NOT circuit by removing the D-type flip-flop 127 or the like in the embodiment 17 (= synchronous / multi-value NOT circuit) of FIG. It is a thing.
Example 2: Nine "invention / synchronous AND circuit in embodiment 14 shown in FIG. 14" and 18 "invention / invention / synchronous NOT circuit in embodiment 1 shown in FIG. 1" or "invention" In the “synchronous NOT circuit of the seventeenth embodiment shown in FIG. 17”, the combined / multi-valued logic circuits of FIGS. 21 and 22 are changed to the synchronous type, and the all-synchronous NOT circuit and the all-synchronous AND circuit thereof Thus, a synchronous synthesis / multi-valued logic circuit in which both latching timings are shifted is possible.
As a matter of course, this synchronous synthesis / multi-value logic circuit can eliminate multi-value hazards. In addition, if the connection of the gate terminal of the transistor 41 is changed from the Q terminal to the Q bar terminal in the first embodiment shown in FIG. 1 of the present invention, the first embodiment changes from a synchronous NOT circuit to a synchronous EVEN circuit (= synchronous EQUAL circuit). Therefore, the conductors shown next to each NOT circuit in each of FIGS. 21 and 22 are not necessary.
Also in this case, “increase in all multi-value numbers N” and “change to different multi-value numbers N” can be performed in the same manner as described above (paragraph number [0152]).

◆◆◆ ＊＊＊＊ Flexibility for logical variables with different multi-values ****** ◆◆◆
***
21) The new multi-valued logic “Hooji algebra” is called “flexible correspondence that can deal with multiple logical variables and multi-valued numbers N (≧ 2) of each logical function that are different from each other”. Features will be described below.
★ Reference: For multi-value number N = 2 → paragraph number [0135-0136].
Depending on the multi-value logic circuit system, there is a case where a plurality of pieces of information having different multi-value numbers N (≧ 2) are handled. For example, the multi-value number “3” for the three primary colors of light (blue-red-green), the multi-value number “2” for positive and negative images, and the multi-value number “multi-level of brightness”, “blue-red-green” It is a multi-value number such as “mixing ratio”.
In such a case, multi-value logic circuits having different multi-value numbers N (≧ 2) are mixed together, but “the multi-value logic having the larger multi-value number” is “the multi-value number of the multi-value number”. It is better to completely include the “smaller multi-valued logic” and the former is compatible with the latter.
In the case of the new multivalued logic “Hooji algebra”, the former is assembled based on the latter (multivalued number N ≧ 2) as described above (paragraph number [0137]). However, the former includes the latter and is compatible with the latter.
In the above-described synthesis / multi-value logic circuit of FIG. 19, the multi-value number N2 (≧ 2) of the logical variable x is always equal to the multi-value number N1 (≧ 2) of the multi-value AND circuit and multi-value OR circuit. It does not have to be the same, and the multi-value number N3 (≧ 2) of the logical variable y does not always have to be the same. There may be cases where N1 ≠ N2 or N1 ≠ N3. Furthermore, N2 and N3 need not always be the same. There may be cases where N1 ≠ N2 or N1 ≠ N3 or N2 ≠ N3.
Example 1: A ternary / nine-value code conversion circuit in paragraph number [0152].
Example 2: In the truth table of FIG. 20, when the variable range of the logical variable x is set to 0 to 7, for example, a multi-value “NOT (m) = m” circuit connected to the input terminal Tx in FIG. Among them, the multi-value “NOT (8) = 8” circuit where m = 8, 9 and the multi-value “NOT (9) = 9” circuit are removed, and the multi-value where the number of input terminals becomes one by the removal. If the “AND (m) = m” circuit is also removed, the change of the multi-value number can be handled.
In this case, if there is a multi-value AND circuit whose input is directly connected to the input terminal Tx among each multi-value “AND (8) = 8” circuit and each multi-value “AND (9) = 9” circuit. The multi-value AND circuit and the “multi-value NOT circuit connected to it” are unnecessary and can be removed.
This example 2 naturally applies to the logical variable y as well.
As a result, “[multiple logical variables and their functions] flexible correspondence that can be handled even if each multi-value number N (≧ 2) is different from each other” is a new multi-value logic “Hooji algebra” There is.
On the other hand, in the case of the multi-value logic circuit composed of the conventional “AND circuit, OR circuit, inverting circuit, literal circuit, and cycling circuit” described above (paragraph number [0135] latter half and paragraph number [0137] latter half). Since "inversion circuits, literal circuits, and cycling circuits" with different multi-value numbers are not included and incompatible, there is no flexible correspondence like the new multi-value logic "Fuji algebra".
* Reference: Non-Patent Document 3 p. 19-p. 20.
"Multi-valued information processing-post-binary electronics-", authors: Tatsuo Higuchi, Michitaka Kameyama, Shokodo in June 1989.

◆◆◆ ＊＊＊＊＊＊＊＊＊ Good connectivity with the binary circuit in the previous stage ********
***
● 22) About the unique effects and features of the new multi-valued logic “Hooji Algebra” that “when connecting a binary circuit in the previous stage, its connectivity is extremely good and no special interface is required between them” This will be described below.
In the case of each multi-value logic circuit based on the new multi-value logic “Fuji algebra”, the discrimination means that the discrimination means fundamentally is “a signal indicating whether each discrimination content is positive or negative, “Negative signal (binary choice signal)”, that is, “A signal indicating yes or no for each discrimination content, yes / no signal (binary choice signal), binary signal”, etc. In addition, the compatibility with the output signal of the preceding binary circuit is very good.
Therefore, all that remains is to match the output part of the preceding binary circuit and the input part of the multi-value logic circuit as follows.
◆ a) When the preceding binary circuit outputs two signals, H level and L level:
The output level range of one of the H level and L level of the binary circuit is completely within the input discriminating range in which the multilevel logic circuit determines “Yes”, and the multilevel logic circuit is It is only necessary to perform matching so that the other output level range completely falls within the input determination range for determining "."
◆ b) When the output part of the preceding binary circuit is open collector or open drain:
Pull-up resistor means or pull-down at the output terminals of the multi-value logic circuits as in each of the multi-value “NOT (...) =...” Circuits in the circuits of FIGS. 18, 19, 21, and 22. It is only necessary to connect a resistance means and match each of the output level range of the H level and L level output from the binary circuit in the same manner as in the above item a).
In both of the items ◆ a) and ◆ b), if both the power supply potentials corresponding to both the H and L levels are “two power supply potentials among the lowest potential to the highest potential of the multi-value circuit”. anything is fine. For example, in the decimal system, both the power supply potentials are “v ₀ and v ₁ ”, “v ₄ and v ₅ ”, “v ₈ and v ₉ ”, “v ₅ and v ₇ ”, “v ₃ and v _8”. ”,“ V ₀ and v ₉ ”,“ potential less than v ₀ and greater than v ₉ (both potentials do not correspond to numerical values) ”, and the like.
That's why the new multi-valued logic “Fuji Algebra” has a unique effect and feature that “when connecting a binary circuit in the previous stage, its connectivity is very good and no special interface is required between them” I understand.

◆◆◆ ＊＊＊＊＊＊＊＊＊ Good connectivity with the binary circuit at the latter stage ********
***
● 23) About the unique effect and feature of the new multi-valued logic “Hooji Algebra” that “when connecting a binary circuit in the latter stage, its connectivity is very good and no special interface is required between them” This will be described below.
There are the following two actual examples.
Example 1: “Each AND multi-value circuit” in the circuit of JP-A-2006-190239 and FIG.
Example 2: “Each multi-value NOT circuit shown in FIG. 11” and “Each binary NOR circuit shown in FIG. 12” in the circuit shown in FIGS.
***
On the other hand, in the case of the conventional Ukasevich-type multi-value logic circuit well known in the multi-value logic field, the connectivity with the binary circuit is poor both at the front and rear stages, and a special interface (binary / multi-value code) is used between them. Conversion means and multi-value / binary code conversion means) are required.
* Reference: Non-Patent Document 3 p. 13 of FIG.
"Multi-valued information processing-post-binary electronics-", authors: Tatsuo Higuchi, Michitaka Kameyama, Shokodo in June 1989.

◆◆◆ ＊＊＊＊＊ Various new and multi-valued logic that can express “ambiguity” ********
***
24) Eight new multi-value logics created by the present inventor, “multi-value OVER logic, multi-value NOVER logic, multi-value UNDER logic, multi-value NUNDER logic, Multi-value IN logic, multi-value NIN (nin) logic, multi-value OUT logic, multi-value NOUT (now) logic "By using multi-value logic circuit," ambiguousness "can be freely and flexibly and easily Can be defined and expressed.
By using each of these multi-valued logic circuits, for example, “ambiguity” can be easily and freely defined and expressed as follows.
◆ Example 1: When expressed in terms of logical numerical values, “approximately the numerical values in this area”. Among 0-9, “3-5”, “4-6”, “≦ 2”, “7 ≦”.
◆ Example 2: When neither Yes (→ numerical value 9) nor No (→ numerical value 0) is attached, the case where neither is attached is represented by the numerical value “4, 5”.
◆ Example 3: When expressing as “Nearly Yes”. “6-7” when it is defined that “numerical value 9 is Yes” and “numerical value 0 is No”.
◆ Example 4: When expressing as “Nearly No”. “2-3” when it is defined that “numerical value 9 is Yes” and “numerical value 0 is No”.
◆ Example 5: When expressing “Gray innocence (→ Numeric value 1) close to guilty (→ Numeric value 0)” by saying “Suspect is in the interest of the accused”. In other words, when the numerical value 0 means "complete guilt (black)" and the numerical value 9 means "complete innocence (white)", the numerical value 1 expresses "gray innocence that is almost guilty" If.
***
After that, "the person who uses these various new and multi-valued logic" can freely define and express the meaning of each numerical value as they like.

The number of corresponding input integers in each multi-value logic circuit of “multi-value OVER logic, multi-value UNDER logic, multi-value IN logic, multi-value OUT logic” is, for example, “the input specific integer value is 4”. When the number of integers 5, 6, and 7 corresponding to the multi-value IN logic of 8 is narrowed down from a plurality to one, the multi-value logic always becomes multi-value EVEN logic.
→→ paragraph number mentioned above [0058]
In other words, the refinement means focusing from “ambiguity” to “clarity” just like “focusing from“ blurring ”to“ matching ”in the focus of a photo”, so “OVER logic, NOVER ( (NOWBER) logic, UNDER logic, NUNDER logic, IN logic, NIN logic, OUT logic, NOUT logic, and "each of these multi-value logic and multi-value AND logic or multi-value OR logic The present inventor considers that expressing “ambiguity” by “combinatorial logic” is not true, is not out of focus, and is appropriate for reason.
For this reason, using these multi-value logic and “combination of these multi-value logic and multi-value AND logic and multi-value OR logic”, a new “fuzzy control technology (IMy [ai -Ai] -Control-Technology) "is considered by the present inventor. This is because in the conventional fuzzy control theory, “mathematical theory of probability and statistics” was introduced to Boolean algebra in order to express “ambiguity” in “numeric values 0 and 1 that clearly express YES and NO”. This is because it is generally quite complicated and difficult to understand.
It should be noted that, as soon as can be seen from the pronunciation, the English name, IMy [ai-mai] According to the present invention have from grounder (pun) alignment of the "ambiguity" of the Japanese name is named in the way.

◆◆◆ ** Possibility of using one-way switch in each circuit of Fig. 19, Fig. 21, Fig. 22
***
● 25) From the conclusion, it is possible to use a unidirectional output switch. In each of the composite / multi-valued logic circuits of FIGS. 19, 21 and 22 described above (paragraph numbers [0138 to 0153]), mainly “various basic / multiple circuits using bidirectional switching means for the output switch section” are mainly used. The "complete circuit" that can realize all multi-valued logic functions using "value logic circuit" has been described.
However, in each of the composite / multi-value logic circuits of FIGS. 19, 21, and 22, the output of each “basic / multi-value logic circuit having a pull-up resistor or a pull-down resistor connected to the output portion” is output. The switch part need not be any bidirectional switching means. Each of the "basic / multi-valued logic circuit with a pull-up resistor connected to its output section" is "the output switch section is a reverse blocking type or a type with no reverse blocking capability (eg, reverse conduction type, reverse conduction type, etc.) )) ”, Which is a pull-down switching means. The reverse conduction type includes, for example, a MOS • FET having a built-in diode, and the reverse conductivity type includes, for example, a bipolar transistor.
On the other hand, each of the "basic / multi-valued logic circuit with a pull-down resistor connected to its output part" is a pull-up switching means of "the output switch part is a reverse blocking type or a type without reverse blocking capability". It does not matter if it is a "basic / multi-valued logic circuit". Of course, “basic / multi-valued logic circuit that can connect either pull-up resistor or pull-down resistor to its output” depends on the pull direction of the resistor. “Basic or multi-value logic circuit that is“ pull-up switching means or pull-down switching means ”” of “type without type or reverse blocking capability”.
In these cases, in the synthesis / multi-value logic circuit of FIG. 19, “a multi-value NOT circuit and a multi-value AND circuit using a one-way pull output switch” and “a multi-value OR circuit using a bidirectional output switch” are used. At least three circuits form a complete system. In each of the composite / multi-value logic circuits of FIGS. 21 and 22, “multi-value NOT circuit using a one-way pull output switch” and “multi-output switch using a bidirectional output switch” are used. At least three circuits of “value AND circuit” and multi-value wired OR circuit form a complete system.

Further, with respect to each multi-value OR circuit in the synthesis / multi-value logic circuit of FIG. 19 and each multi-value AND circuit in the synthesis / multi-value logic circuit of FIG. If it doesn't have to be bidirectional and its pull output can be either pull-up or pull-down, all its basic / multi-valued logic circuits say "the output switch is a reverse blocking type pull "Basic / multi-valued logic circuit" that is "up-switching means or pull-down switching means" may be used. In this case, in the synthesis / multi-value logic circuit of FIG. 19, if the all-multi-value OR circuit uses reverse blocking pull-up switching means for the output switch section, the output terminal Tf is, for example, FIG. low power supply potential {example than the power supply potential v ₀ of synthesis and multivalued logic circuits: a power supply potential v ₀ than one potential lower supply potential v _-1. } Is output as a reference. On the other hand, if the all-multi-value OR circuit uses reverse blocking pull-down switching means for the output switch section, the output terminal Tf is, for example, the power supply potential v ₉ of the synthesis / multi-value logic circuit of FIG. higher supply potential {e.g. power supply potential _{v 9} than the potential one high power supply potential _{v 10.} } Is output as a reference. The same applies to each multi-value AND circuit in each composite multi-value logic circuit shown in FIGS.
In these cases, in the synthesis / multi-value logic circuit of FIG. 19, at least three circuits “a multi-value NOT circuit, multi-value AND circuit and multi-value OR circuit” using a one-way pull output switch ”form a complete system. 21 and 22, at least three circuits of “multi-value NOT circuit and multi-value AND circuit using a one-way pull output switch” and multi-value wired OR circuit are complete systems. Make it.

Then, each of the basics using “pull-up switching means or pull-down switching means” of “type without reverse blocking capability (eg reverse conduction type, reverse conduction type, etc.)” in the output switch section. The multi-level logic circuit can be used in the final stage of the circuit of FIG. For example, in the circuit of FIG. 21, the output terminals are all connected once for each “multi-value AND circuit whose output specific integer is the same value”, and for each connection / common terminal. A diode may be connected between the common terminal and the output terminal Tf. In this way, it is possible to prevent a power short circuit between the multi-value AND circuits.
Also in this case, the output switch section of the all-multi-value AND circuit performs either pull-up or pull-down operation when driving on, and there is no mixing of pull-up operation and pull-down operation. The output signal to be output is “power supply potential higher than power supply potential v ₉ {eg, power supply potential v ₁₀ higher by one than power supply potential v ₉ }” or “power supply potential lower than power supply potential v ₀ { Example: A power supply potential v ₋₁ lower than the power supply potential v ₀ by one.} ”.
Therefore, a diode is connected to the multi-value AND circuit group whose specific integer value for output is either 0 (when the reference power supply potential is v ₁₀ ) or 9 (when the reference power supply potential is v− ₁ ). 9 is not necessary, so the total number of output diodes required is nine.
In this case, in the synthesis / multi-value logic circuit of FIG. 21, in addition to at least three circuits of “multi-value NOT circuit and multi-value AND circuit using a one-way pull output switch” and multi-value wired OR circuit, its output Nine diodes form a complete system.
At first glance, the number of parts seems to have increased, but in the case of the composite / multilevel logic circuit of FIG. 21 using the reverse blocking pull switching means described above (one paragraph before), it is usually required. The total number of reverse blocking and output diodes is 100, and an additional 91 output diodes are required.

Alternatively, in the synthesis / multi-valued logic circuit of FIG. 19, for example, when the power supply potential increases in the order of v ₀ to v ₄ , vB, v _{5 to} v ₉ and there is an extra power supply potential vB, You can also do the following:
Each multi-value OR circuit in the synthesis / multi-value logic circuit of FIG. 19 outputs an output signal based on the power supply potential vB. Therefore, for each of the “multi-valued OR circuit whose specific integer value for output is any one of 0 to 4”, the output switch section is a reverse blocking pull-down switching means. On the other hand, for each “multi-value OR circuit whose specific integer value for output is any of 5 to 9”, the output switch section is reverse blocking pull-up switching means.
The power supply potential vB serving as a reference potential of the output signal is not necessarily there in between both the power supply potential v4 · v5, among the power supply potential v ₀ to v _9, the two power supply potential adjacent any two It may be in between. Of course, in this case, the voltage is pulled up higher than the power supply potential vB or pulled down below the power supply potential vB.
The same applies to the synthesis / multilevel logic circuit of FIG. 21, and each multilevel AND circuit outputs an output signal based on the power supply potential vB. What has been described above is applied to each multi-valued OR circuit in the composite / multi-valued logic circuit of FIG.
In these cases, there are cases where there are two pull directions, so in the synthesis / multi-value logic circuit of FIG. 19, “a multi-value NOT circuit, a multi-value AND circuit and a multi-value OR circuit using a one-way pull output switch”. At least 4 circuits form a complete system, and in the composite and multi-value logic circuit of FIG. At least four circuits form a complete system.

Alternatively, as described above (the content of the previous paragraph), each multi-value AND circuit in the synthesis / multi-value logic circuit of FIG. 21 outputs an output signal based on the power supply potential vB. This is a case where a reverse switching type or a reverse switching type pull switching means is used for the output switch section.
Regarding each of the “multi-value AND circuit whose specific integer value for output is any one of 0 to 4”, the output switch unit is a pull-down switching means such as a reverse conduction type or a reverse conduction type. It is devised in the same way as paragraph number [0161]. The output terminals are all connected once for each “multi-value AND circuit having the same specific integer for output”, and between the common terminal and the output terminal Tf for each connection / common terminal. Connect the diode in the pull-down direction.
On the other hand, regarding each of the “multi-value AND circuit whose specific integer value for output is any of 5 to 9”, the output switch unit is a pull-up switching means such as a reverse conduction type or a reverse conduction type. The same as the above (paragraph number [0161]). The output terminals are all connected once for each “AND circuit whose output specific integer is the same value”, and a diode is connected between the common terminal and the output terminal Tf for each connection / common terminal. Connect in the pull-up direction.
In this case, there are cases where there are two pull directions, so in the synthesis / multi-value logic circuit of FIG. 21, “multi-value NOT circuit and multi-value AND circuit” using a one-way pull output switch ”and multi-value wired In addition to at least four OR circuits, nine of its output diodes form a complete system.

The new multivalued logic (at the time of 2002) created by the present inventor is optimal for expressing “ambiguousness”.
◆◆◆ ＊＊＊＊＊ Various new and multi-valued logic that can express “ambiguity” ********
***
■■ a) As described above (paragraph numbers [0157 to 0158]), eight new multi-value logics created by the present inventor, “OVER logic, NOVER logic, UNDER logic, In addition to NUNDER logic, the use of multiple-valued logic circuits such as IN logic, NIN logic, OUT logic, NOUT logic, etc. allows for free and flexible “ambiguity”. Can be easily defined and expressed. Various other logics derived from these eight logics are described in the paragraph numbers [0088 to 0095, 0104 to 0108] described above.
The present inventor thinks that a new “fuzzy control technology (IMy [ai-mai] -Control-Technology”), which is different from the conventional fuzzy control technology, can be opened using these multi-value logic circuits. However, the technology of the present invention can be used for each of these multi-value logic circuits.

◆◆◆ ＊＊＊＊＊＊ New concept computer that doesn't use programs, etc. ＊＊＊＊＊ ◆◆◆
***
■■ b) The present inventor described “(previous) processing result storage type (alias: input) as“ a new concept computer that does not use program software, CPU, etc. ” Output pattern storage type or function storage type) "Decimal computer (= Decimal Computers) and the like are disclosed, and the technology of the present invention can be used for this.
→→ (Decimal) Computers of Pre-processing-Result-Memory-Type etc.
Note that the pre-processing includes the pre-collection before collecting information in advance, so of course, the previous (pre-) processing results include the previous (pre-) information collection results in addition to the previous (pre-) information processing results. Is also included. Its white before processing result, the white before the information collection results, white on the input pattern, white to the function, "one and both" one or more "input data or input information '" or "the output data or output information" multiple relationships ", since become the new software that represents the correlation, hear well recently" Big data "can be as it is to the new software. So, in other words, compatibility with the new concept computer and its "Big Data" is outstanding good.
'The Pre-processing' means 'Preprocessing data or information' or 'Precollecting data or information'.
In other words, 'Means 0f The Pre-processing' inclusion 'preprocessing data or information' and 'precollecting data or information'.
This patent's inventor thinks that 'Big Data to often become a topic of conversion recurrence' can direct become 'Present software'.
This inventor calls 'The Pre-processing Result Software''The Pres Software Software' for short.
In the new concept computer, it will be called “preprocessing result software {Present (or Presert) software (Present Software) for short. }] (Also known as I / O pattern software or function software) and multi-value logic circuits.
→→ ★ Presult-Memoriizing-Type Computers
Further, “Presalting (or Presalting) = Presulting” (also known as patterning or functioning) corresponds to programming, and “Presalter (or Presalter) = Presulter” (also known as patterner) corresponds to the programmer. Or a functioner).
'The Presulting' means 'producing the Presult Software', and 'The Presulters' mea n 'people producing the Presult Software'.

In the case of a conventional computer, since “information to be processed” is given and information processing is started and results are output, a long information processing time is required. On the other hand, in the case of this new concept computer, “all the contents to be processed” is known in advance or is completely inferred and grasped. Pre) Information processing result (Result) ”, that is,“ Presert (= Presult. Or Pres.) ”Has already been stored in the memory area. For each “content part that is input”, the “present corresponding to it” is simply read out. For this reason, as a matter of course, the information processing speed is overwhelmingly fast when viewed from the outside of the computer. Whether it looks or not, the information processing speed is actually overwhelmingly fast, so it is extremely advantageous for real-time processing.
In the future, the “Present storage computer of this new concept” and the “conventional program storage type (or built-in type) computer” will have the possibility that the former will be super-high-performance. The present inventor believes that there is a large or small amount of storage capacity that is permitted or required, “high priority of information processing speed”, “necessity of using multi-valued logic” ”,“ Improvement / advancement of 3D technology of IC and LSI ”,“ Improvement / advancement of each performance of MOS / FET ”,“ In terms of power saving ”,“ Requirement of cooling or suppression of heat generation ” The present inventor is convinced that “the fields of use of both can be distinguished” by “ease of software creation”, “bug occurrence”, “resistance to unauthorized intrusion operation”, and the like.
And the present inventor is convinced that “in the future, there is always a good arrangement of both methods, and both methods may be used in an organic combination”.

In the case of a conventional program storage type computer, a considerable number of instructions (instructions) are processed for “information processing on the input contents” each time, so a considerable amount of power is consumed. The CPU is in the heater state. On the other hand, in the case of a Preset memory type computer, since “information processing for the input contents” is performed only once each time, only one memory access is required, so that the power consumption is extremely small. That's why if you replace program storage computers around the world with Presto storage computers, you can save a tremendous amount of power. How much energy will it save for nuclear power plants? ?
Also, regarding resistance to unauthorized intrusion operations, in the case of a conventional program storage type computer, an unauthorized intruder would misuse "each command, each application software, etc. of the intrusion destination computer". If it is unprotected, the computer can be completely controlled by “a relatively small malicious program compared to the total amount of programs in the system”. On the other hand, in the case of a Presto memory type computer, if it is attempted to completely control the computer completely, it is necessary to rewrite the entire Pres software (= Present Software). It is almost impossible to completely improperly control.
Then, regarding the storage capacity of the program storage type computer, for example, in the automobile field, the program has reached tens of millions of lines, and the required storage capacity has become enormous. ) The use of a memory computer is overwhelmingly advantageous, so its full use will gradually come into view.
And the compatibility of the Presto storage computer and the cloud computer is considered good. The cloud computer absorbs and bears the amount of memory required.
Then, all the various functions, characteristic curves and calculations used in fuzzy control can be expressed in a truth table, so it is natural that fuzzy control can be performed using this new concept computer.

◆◆◆ ＊＊＊＊ Information processing means to make malicious programs harmless. ******** ◆◆◆
***
■■ c) The present inventor discloses “information processing means having a function of preventing unauthorized intrusion operation” in his invention “Japanese Patent Application Laid-Open No. 2006-190239 (subject to voluntary withdrawal)”. Technology can be utilized.
This prior application technology is based on the idea that “if an unauthorized intrusion occurs, if it is not illegally operated, that is fine”.
For example, in this information processing means, an “instruction (instruction), program or command expressed in a ternary expression (eg, at least one digit of the machine language is a numerical value 2) that can be clearly distinguished from the binary expression. , Etc., and when "external data or external information" expressed in binary representation that is completely unreliable is taken in, "filter means that passes only what is expressed in binary representation (eg: clamp diode) Incorporate it via "Hardware means etc.").
In other words, in this information processing means, only “instructions (instructions), programs or commands” expressed in ternary values are targets of execution, and internal or external “data or information” expressed in binary values is the information. The “external data or external information” that is the target of processing and is expressed in binary is included in the input target. And an external reliable “instruction (instruction), program or command”, etc., or data or information ”expressed in a ternary expression that can be clearly distinguished from the binary expression, Input / output from “input / output port”.
As a result, even if this information processing means can be illegally infiltrated, the illegally intruding “illegal program, illegal command”, etc. are not executed at all, so that the information processing means is illegally operated. Is completely absent.
The unauthorized program, unauthorized command, etc. are merely harmless and worthless trash “data or information” for the information processing means.
That's why, according to the recent “hands-on countermeasures against unauthorized intrusion operations” and “strong demands for the ultimate countermeasures and measures to end the illegal operations and countermeasures,” this prior-application technology is immediately available. The present inventor thinks that it is not strange to use. In addition, there is an “information processing means having an unauthorized intrusion operation prevention function” disclosed in Japanese Patent Application Laid-Open No. 2011-103124.
The compatibility between this intrusion prevention technology and cloud computers is outstanding. This is because the request contents of the client and the processing result contents can be expressed in binary.
Further, when the difference between the numerical values 1 and 0 is expressed by the difference in frequency, the communication line itself can be used as a frequency filter. In other words, it is not necessary to define and prepare the frequency corresponding to the numerical value 2 from the beginning.

Claims (2)

When a predetermined plural number of 3 or 3 is represented by N and a predetermined natural number is represented by S,
“N constant potentials that increase or decrease in numerical order from the first constant potential to the Nth constant potential” are supplied, and each constant potential and 0 to (N -1), the first constant potential supply means to the Nth constant potential supply means defined as one-to-one correspondence with the first constant potential in order from the integer 0, "
“First to Sth Inlet Means for Incoming S Input Potential Signals”,
“Exit means for exiting output potential signal”;
“When connected between the“ first constant potential supply means to one predetermined constant potential supply means for output among the first constant potential supply means to the Nth constant potential supply means ”and the outlet means, "Pull switching means that is turned off in one or both directions";
“ The S input potential signals are supplied from the first to S-th inlet means, “ when S = 1, an input integer corresponding to one of the input potential signals, and when S ≧ 2, [S All of the S input integers corresponding one-to-one with each of the input potential signals] or [at least one of the S input integers corresponding one-to-one with each of the S input potential signals. ]] [[Is equal to or not equal to one input specific integer predetermined in integer 0 to (N-1)], [predetermined in integer 0 to (N-2) Or larger than one input specific integer], [whether smaller than one predetermined input integer in integers 1 to (N−1)], [integer 0 to ( N-1), the difference determined in advance is at least 2. "Whether or not between two input specific integers"], it is determined whether it is affirmative or negative based on the "two or four threshold potentials below" applied to it, Numeric discrimination means for outputting the discrimination result as a discrimination result signal,
"Since" is directly or matching a hold signal the determination result signal based on the synchronizing signal supplied from outside "type, binary outputs a" positive output signal or the complement output signal "corresponding to the holding signal Synchronous flip-flop means "

“The pull switching means is driven on and off based on“ the positive output signal or the complementary output signal ”, but“ the determination result at the time of input indicated by the output signal based on that is positive. If it is negative, drive it off, or if it is negative, drive it off ”or“ If it is affirmative, drive it off, and if it is negative, drive it on ”on / off drive means”,
A multi-valued logic circuit having a synchronous latching function.
However, the meaning of “less than one input specific integer” does not include the one input specific integer, and the meaning of “greater than one input specific integer” means that one input. The specific integer for use is not included, and the meaning of “between two input specific integers” does not include the two input specific integers.
■■ Two or four threshold potentials ■■
(1) When these constant potentials increase in numerical order from the first constant potential to the Nth constant potential,
● a) “Equal or not”:
* In the case of “equal to”, “a positive threshold potential and a negative threshold potential determined in advance with reference to an input specific constant potential corresponding to the input specific integer”. However, when the specific integer for input is 0, only the positive threshold potential is obtained, and when the specific integer for input is (N-1), only the negative threshold potential is obtained.
* In the case of “not so”, “a negative threshold potential determined in advance with reference to a constant potential one of the first constant potential to the Nth constant potential that is one higher than the specific constant potential for input” “A positive threshold potential determined in advance with reference to a constant potential one lower than the specific constant potential for input among the first constant potential to the Nth constant potential”. However, when the specific integer for input is 0, only the negative threshold potential is obtained, and when the specific integer for input is (N-1), only the positive threshold potential is obtained.
● b) If “Large or not”:
* In the case of “larger”, “the predetermined constant of the first constant potential to the Nth constant potential is determined in advance with reference to a constant potential that is one higher than the“ specific constant potential for input corresponding to the specific integer for input ”. Negative threshold potential ”.
* In the case of “not so”, “a positive threshold potential determined in advance on the basis of the specific constant potential for input”.
● c) “Small or not”:
* “It is small” is “predetermined on the basis of a constant potential one lower than the“ specific constant potential for input corresponding to the specific integer for input ”among the first constant potential to the Nth constant potential”. “Positive side threshold potential”.
* "If not" is "a negative threshold potential determined in advance with reference to the input specific constant potential".
D) In the case of “whether or not between two specific integers for input”:
* “Is it between the two?” Means that “of the first constant potential to the Nth constant potential, the lower constant of the two input specific constant potentials corresponding to the two input specific integers. Among the first constant potential to the Nth constant potential, “of the two input specific constant potentials”. “Higher constant potential” is a positive threshold potential determined in advance based on a constant potential one level lower than “the higher constant potential”.
* In the case of “not”, “the positive threshold potential determined in advance with respect to the lower constant potential of the two input specific constant potentials” and “the two specific input constant potentials” The negative threshold potential determined in advance based on the higher constant potential.
(2) When these constant potentials decrease in numerical order from the first constant potential to the Nth constant potential,
● a) “Equal or not”:
* In the case of “equal to”, “a positive threshold potential and a negative threshold potential determined in advance with reference to an input specific constant potential corresponding to the input specific integer”. However, when the specific integer for input is 0, only the negative threshold potential is obtained, and when the specific integer for input is (N-1), only the positive threshold potential is obtained.
* In the case of “not so”, “a negative threshold potential determined in advance with reference to a constant potential one of the first constant potential to the Nth constant potential that is one higher than the specific constant potential for input” “A positive threshold potential determined in advance with reference to a constant potential one lower than the specific constant potential for input among the first constant potential to the Nth constant potential”. However, when the specific integer for input is 0, only the positive threshold potential is obtained, and when the specific integer for input is (N-1), only the negative threshold potential is obtained.
● b) If “Large or not”:
* In the case of “larger”, “it is determined in advance from the first constant potential to the Nth constant potential based on a constant potential that is one lower than the“ input specific constant potential corresponding to the input specific integer ”. Plus threshold potential.
* "If not" is "a negative threshold potential determined in advance with reference to the input specific constant potential".
● c) “Small or not”:
* In the case of “smaller”, “it is determined in advance from the first constant potential to the Nth constant potential, based on a constant potential one level higher than“ the specific constant potential for input corresponding to the specific integer for input ”. Negative threshold potential ”.
* In the case of “not so”, “a positive threshold potential determined in advance on the basis of the specific constant potential for input”.
D) In the case of “whether or not between two specific integers for input”:
* “Is it between the two?” Means that “of the first constant potential to the Nth constant potential, the lower constant of the two input specific constant potentials corresponding to the two input specific integers. Among the first constant potential to the Nth constant potential, “of the two input specific constant potentials”. “Higher constant potential” is a positive threshold potential determined in advance based on a constant potential one level lower than “the higher constant potential”.
* In the case of “not”, “the positive threshold potential determined in advance with respect to the lower constant potential of the two input specific constant potentials” and “the two specific input constant potentials” The negative threshold potential determined in advance based on the higher constant potential. A multi-value logic circuit having a synchronous latching function according to claim 1 ;
"Synchronization signal supply means for supplying the synchronization signal to the binary synchronization flip-flop means"
The S input potential signals are inputted to the first to S-th inlet means from the outside, and based on the synchronization signal, “a period in which no hazard appears in the discrimination result signal and the discrimination result signal is stable” multilevel hazard removing circuit wherein the binary synchronous flip-flop means, characterized in that the input "were allowed to directly or matching" the discrimination result signal as said hold signal to.