JP2014179977A - Multivalued not two-stage connection means based on hooji algebra, multivalued not even two-stage connection means based on hooji algebra, multivalued even two-stage connection means based on hooji algebra, and multivalued even not two-stage connection means based on hooji algebra - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide novel multivalued NOT two-stage connection means having a novel action and effect on the basis of a principle of the multivalued logic "Hooji algebra".SOLUTION: Asynchronous type or synchronous type multivalued NOT means of a specific integer m and asynchronous type or synchronous type multivalued NOT means of a specific integer Cm (≠m) are connected in two stages. "A first pull resistor pulling up/down an output potential of the front stage to a specific constant potential vCm (a potential of a power line VCm) of the rear stage" is connected, and "a second pull resistor pulling up/down an output potential of the rear stage to a specific constant potential vm (a potential of a power line Vm) of the front stage" is connected. Thereby, multivalued EVEN means of one stage can be changed to multivalued NOT two-stage connection means, and the specific integer can be changed from m to Cm. Therefore, it is convenient in a case where a multivalued circuit is modified equivalently (for example, from a multivalued complete circuit shown in Fig. 21 to that shown in Fig. 13). Unlike multivalued NOT two-stage connection means of the same specific integer m (Fig.2), it is convenient that options with respect to distribution or concentration of a load applied to a power supply can be increased.

Description

The first to fourth inventions are a combination of two “new-valued logic born in Japan, multi-value logic means (or multi-value logic circuit) in potential mode (or voltage mode) based on“ Hooji Algebra ”” ” The present invention relates to a multi-level logic two-stage connection means.
For example, the multi-value NOT two-stage connection means of the first invention is “using a complete system such as a multi-value AND circuit, all multi-value logic circuits (or multi-value logic means) regardless of the multi-value number N”. When applied to a multi-value complete circuit (eg, FIG. 21) that can be expressed / configured, a multi-value complete circuit using a complete system such as a multi-value NOR circuit, which is an equivalent modification of the multi-value complete circuit ( Example: FIG. 13) ”can be configured. This means that when configuring a multi-value complete circuit, the choices of basic / multi-value logic circuits (eg, multi-value AND circuit, multi-value OR circuit, etc.) to be used increase and become convenient. In this case, it means that a multi-value AND circuit or the like may be used, or a multi-value NOR circuit or the like may be used.
● “Multi-valued complete circuit” is a feature that “all types of multi-valued logic circuits can be expressed and configured with only one or several basic / multi-valued logic circuits (→ complete system)”, “completeness ( = Complementess) ”, and the present inventor uses the term“ multi-value complete circuit ”in that sense.
In addition, the principle of “Hooji Algebra” that has not yet been widely known, the technology of “various multi-valued logic circuits based on the Houji algebra”, and “synchronous latching of Patent Document 7” In order to be able to treat the technology of “multi-value logic means and multi-value hazard removal means having functions” ”in the description of the present invention in the same manner as the common technical knowledge, those principles and techniques are described in paragraph numbers [0049 to [0112] and paragraph numbers [0113 to 0237], the present inventor will respectively explain.
In particular, the present inventors will explain in detail in paragraph numbers [0083 to 0096] regarding “multi-valued complete circuit based on Fuji algebra”, which have already been disclosed in the following Patent Documents 6 to 7. However, the use of the name “Fuji algebra” is from Patent Document 6.
JP 2004-032702 (New multi-value logic circuit based on multi-value logic “Fuji algebra”) JP 2005-198226 (New multi-value logic circuit based on multi-value logic "Fuji algebra") JP 2005-236985 (Multi-valued logic circuit based on new multi-valued logic “Fuji algebra”) Patent No. 5363511 (Japanese Patent Laid-Open No. 2011-097637 greatly corrected, multi-value logic circuit based on new multi-value logic “Fuji algebra”), division of Patent Document 2. JP2011-229069 (multi-value hazard elimination circuit) Japanese Patent Application Laid-Open No. 2012-034345 (Multi-value Hazard Removal Circuit) →→ Each multi-value complete circuit of FIGS. 10 and 12 in Patent Document 6. JP 2012-077504 (multi-value logic means having a synchronous latching function and multi-value hazard removal circuit) →→ Each multi-value complete circuit of FIGS. 12 and 14 in Patent Document 7. “Digital Digital Circuits Understandable”, p. 9 line 14 to p. "Complete system" on the first line of 10. Author: Keitaro Sekine, published by OHM Co., Ltd. on July 25, 1997. “Introduction to Logic Circuits”, p. 31 “(8) Complete system”. Author: Ryuji Hamabe, published by Morikita Publishing Co., Ltd. on September 28, 2001. "Multi-value information processing-Post binary electronics-", p. 16-p. 17 “completeness, complete system, complete” description. Author: Tatsuo Higuchi, Michitaka Kameyama, Shokodo published in June 1989.

In the first invention (claim 1), two “multi-value NOT means having a specific value common to input and output whose input specific value and output specific value are the same” are arranged in the preceding stage and the subsequent stage (= next stage). There are two types of “multi-value NOT two-stage connection means based on the Fuji algebra” that are connected in two stages, for example, asynchronous type and synchronous type.
Here, it is important that the multi-level NOT means in the preceding stage and the multi-value NOT means in the subsequent stage have different “specific values common to input and output”. Moreover, the logical operation of the multi-level NOT two-stage connection means is equivalently the same as that of one stage of the multi-value EVEN means. Convenient because you can change that value to “to value”.
However, when the number of synchronous types differs between the multi-value one-stage means and the multi-value two-stage connection means with respect to the equivalent relationship between the two logic operations, the difference in the logic operation timing between the two is ignored. .
Also, this multi-value NOT two-stage connection means is convenient for “when the signal propagation time is positively delayed for time adjustment and operation timing adjustment”. In other words, the signal propagation time can be delayed by the amount increased from the multilevel one-stage means to the multilevel two-stage connection means.
◆ Further, the multi-level NOT two-stage connection means is equivalent to the multi-level EVEN means, but if both of the preceding and subsequent stages are synchronous, there are two timings for synchronous latching in the front and rear. Therefore, this multi-level NOT two-stage connection means is convenient when the timing of the entire synchronous latching is adjusted within a certain “multi-level circuit based on the Fuji algebra”.
◆ Then, the "specific value common to input and output" is different between the preceding stage means and the subsequent stage means that the DC power supply means for multi-values used by both means is also "a part or all". Means. As a result, a plurality of multi-value logic means (or multi-value logic circuits) serving as a load for each DC power supply means for multi-values are “distributed to each DC power supply means” or “specific DC power supply means”. You can freely choose how to get power, such as “collecting”.
For example, in a 10-value logic circuit, at least “9 DC power supplies (means) are connected in series in the same direction, and 10 power lines are taken out from each power terminal (or each common power terminal). It is “configuration”.

In the second invention (claim 2), two "multi-value NOT means and multi-value EVEN means" having a common input / output specific value whose input specific value and output specific value are the same are arranged in the preceding and subsequent stages ( = Multi-level NOT / EVEN two-stage connection means based on Fuji algebra "such as two-stage connection at the next stage), there are an asynchronous type and a synchronous type.
Here, it is important that the multi-level NOT means in the preceding stage and the multi-value EVEN means in the subsequent stage have different “specific values common to input and output”. Moreover, since the logical operation of the multi-level NOT / EVEN two-stage connection means is equivalently the same as that of one stage of the multi-level NOT means of the previous stage, This is convenient because you can change that value to "specific value".
However, when the number of synchronous types differs between the multi-value one-stage means and the multi-value two-stage connection means with respect to the equivalent relationship between the two logic operations, the difference in the logic operation timing between the two is ignored. .
The multi-level NOT / EVEN two-stage connection means is convenient for “when the signal propagation time is positively delayed for time adjustment and operation timing adjustment”. In other words, the signal propagation time can be delayed by the amount increased from the multilevel one-stage means to the multilevel two-stage connection means.
Furthermore, the multi-level NOT / EVEN two-stage connection means is equivalent to the multi-level NOT means one stage, but if both the preceding stage and the latter stage are synchronous, the timing of the synchronous latching is 2 Therefore, this multi-value NOT / EVEN two-stage connection means is convenient when the timing of the entire synchronous latching is adjusted within a certain “multi-value circuit based on the Fuji algebra”.
◆ Then, the "specific value common to input and output" is different between the preceding stage means and the subsequent stage means that the DC power supply means for multi-values used by both means is also "a part or all". Means. As a result, a plurality of multi-value logic circuits serving as loads of each DC power supply means for the multi-value can be distributed such as “distributed to each DC power supply means” or “collected in specific DC power supply means”. You can freely choose how to take.
For example, the 10-value logic circuit has at least “a power supply circuit configuration in which nine DC power supplies (means) are connected in series in the same direction and ten power supply lines are taken out from each power supply terminal”.

The third aspect of the present invention (invention 3) provides two "multi-value EVEN means having a specific value common to input and output whose input specific value and output specific value are the same" in the preceding stage and the subsequent stage (= next stage). There are two types of “multi-level EVEN two-stage connection means based on Fuji algebra”, such as two-stage connection, which are asynchronous and synchronous.
Here, it is important that the multi-value EVEN means in the preceding stage and the multi-value EVEN means in the subsequent stage have different “specific values common to input and output”. Moreover, since the logical operation of the multi-level EVEN two-stage connection means is equivalently the same as that of the first stage multi-value EVEN means, it is substantially the same as that of the previous stage I / O common / specific value to the subsequent stage I / O common / specific value. It is convenient because its value can be changed.
However, when the number of synchronous types differs between the multi-value one-stage means and the multi-value two-stage connection means with respect to the equivalent relationship between the two logic operations, the difference in the logic operation timing between the two is ignored. .
Also, this multi-value EVEN two-stage connection means is convenient for “when the signal propagation time is positively delayed for time adjustment and operation timing adjustment”. In other words, the signal propagation time can be delayed by the amount increased from the multilevel one-stage means to the multilevel two-stage connection means.
◆ Furthermore, the multi-level EVEN two-stage connection means is equivalent to the multi-level EVEN means one stage, but if both of the preceding and subsequent stages are synchronous, there are two timings for synchronous latching in the front and rear. Therefore, this multi-level EVEN two-stage connection means is convenient when the timing of the entire synchronous latching is adjusted within a certain “multi-level circuit based on the Fuji algebra”.
◆ Then, the "specific value common to input and output" is different between the preceding stage means and the subsequent stage means that the DC power supply means for multi-values used by both means is also "a part or all". Means. As a result, a plurality of multi-value logic circuits serving as loads of each DC power supply means for the multi-value can be distributed such as “distributed to each DC power supply means” or “collected in specific DC power supply means”. You can freely choose how to take.
For example, the 10-value logic circuit has at least “a power supply circuit configuration in which nine DC power supplies (means) are connected in series in the same direction and ten power supply lines are taken out from each power supply terminal”.

According to a fourth aspect of the present invention (invention 4), two "multi-value EVEN means and multi-value NOT means" having a common input / output specific value whose input specific value and output specific value are the same are provided in the preceding and subsequent stages ( = Multi-level EVEN / NOT two-stage connection means based on Fuji algebra "such as two-stage connection at the next stage), there are an asynchronous type and a synchronous type.
Here, it is important that the multi-value EVEN means in the preceding stage and the multi-value NOT means in the subsequent stage have different “specific values common to input and output”. In addition, the logical operation of the multi-level EVEN / NOT two-stage connection means is equivalent to “one-stage multi-value NOT means having the same specific value as the multi-level EVEN means in the previous stage”. It is convenient because the value can be changed from “common input / output / specific value to common / specific value for subsequent input / output”.
However, when the number of synchronous types differs between the multi-value one-stage means and the multi-value two-stage connection means with respect to the equivalent relationship between the two logic operations, the difference in the logic operation timing between the two is ignored. .
Also, this multi-value EVEN / NOT two-stage connection means is convenient for “when the signal propagation time is positively delayed for time adjustment and operation timing adjustment”. In other words, the signal propagation time can be delayed by the amount increased from the multilevel one-stage means to the multilevel two-stage connection means.
◆ Further, the multi-level EVEN / NOT two-stage connection means is equivalent to one stage of the multi-value NOT means, but if both of the preceding stage and the latter stage are synchronous, the timing of the synchronous latching is 2 before and after in time. Therefore, this multi-level EVEN / NOT two-stage connection means is convenient when the timing of the entire synchronous latching is adjusted within a certain “multi-level circuit based on the Fuji algebra”.
◆ Then, the "specific value common to input and output" is different between the preceding stage means and the subsequent stage means that the DC power supply means for multi-values used by both means is also "a part or all". Means. As a result, a plurality of multi-value logic circuits serving as loads of each DC power supply means for the multi-value can be distributed such as “distributed to each DC power supply means” or “collected in specific DC power supply means”. You can freely choose how to take.
For example, the 10-value logic circuit has at least “a power supply circuit configuration in which nine DC power supplies (means) are connected in series in the same direction and ten power supply lines are taken out from each power supply terminal”.

■■ Background art of the first to fourth inventions ■■
The present inventor has created a new multi-valued logic called “Hooji Algebra”, but it can be easily derived in accordance with the principle of multi-valued logic. 2. “NOT two-stage connection means”, “conventional multi-value NOT / EVEN two-stage connection means”, “conventional multi-value EVEN two-stage connection means” and “conventional multi-value EVEN / NOT two-stage connection means” are shown in FIG. FIG. 5, FIG. 8, and FIG.
Here, as a precaution, each and logical operation of the asynchronous “multi-value NOT means and multi-value EVEN means” based on the Fuji algebra will be described. When a certain logical (integer) value is input to the multi-value EVEN means, if the logical value is the same as the “specific (integer) value common to input and output” of the multi-value EVEN means, the multi-value EVEN means is The specific value is output, otherwise, the output of the multi-value EVEN means is released. On the other hand, when a certain logical value is input to the multi-value NOT means, if the logical value is the same as the “specific value common to input and output” of the multi-value NOT means, the output of the multi-value NOT means is released. Otherwise, the multi-value NOT means outputs the specific value. When they are synchronous, each “relationship between input and output” is temporally shifted by the synchronization period.
Unlike the conventional multi-valued logic, the Fuji algebra has a logic output “open output or open output”. The multi-value NOT means is a “multi-value NEVEN means that is negative of the multi-value EVEN means”. Since “NOT” has a smaller number of characters and is easier to use than “NEVEN”, the name “multi-value NOT means” is used in the present invention.
A specific circuit example of the asynchronous multi-value NOT means is shown in FIGS. 23 to 24, and a specific circuit example of the asynchronous multi-value EVEN means is shown in FIG. Further, specific circuit examples of the synchronous multi-value NOT means are shown in FIGS. 32 and 43, and specific circuit examples of the synchronous multi-value EVEN means are shown in FIGS.
In each of the conventional multi-level logic two-stage connection means, the value of the “specific value m common to input / output” of the front-stage means and the subsequent stage means is the same. Includes “one-stage each / multi-valued logic means logically equivalent as shown in FIGS. 2, 5, 8 and 11”.
For this reason, the signal propagation time is delayed by the amount that each of the multi-value logic means is logically increased from one stage to two stages. Therefore, these conventional multi-value logic two-stage connection means " This is convenient when the signal propagation time is positively delayed.
In addition, when both the previous stage and the subsequent stage of the conventional multi-level logic two-stage connection means are synchronous, there are two timings for synchronous latching in the front and rear. The multi-level logic two-stage connection means is convenient when the timing of the entire synchronous latching is adjusted within the "."

These conventional multi-valued logic two-stage connecting means are usually used as “multi-valued two-stage connecting means based on the Fuji algebra”, and it is thus far possible to directly derive the combination of the multi-value NOT means and the multi-value EVEN means.
However, after that, the present inventor discovered some new actions and effects that were not originally anticipated in the principle of multi-valued logic called “Fuji algebra”. These are the functions and effects of the first to fourth inventions described above (paragraph numbers [0002 to 0005]).
However, each “multi-valued logic two-stage connection means” of the first to fourth inventions is also present in each of the conventional multi-value logic two-stage connection means for each “time adjustment and synchronous latching / timing adjustment / effect”. With the advent of the connection means, the number of options of the multi-value logic two-stage connection means that can use these two actions and effects is increased and it becomes convenient.

Japanese Patent Application Laid-Open No. 2004-032702 (Multi-valued logic circuit based on new multi-valued logic "Fuji algebra", ◆ deemed withdrawal) Japanese Patent Laying-Open No. 2005-198226 (Multi-valued logic circuit based on new multi-valued logic “Fuji algebra”) →→ Patent No. 4,500,778. And divided into the following and Patent Document 4. Japanese Patent Laying-Open No. 2005-236985 (multi-value logic circuit based on new multi-value logic “Fuji algebra”) →→ Patent No. 4643297 JP 2011-097637 (New multi-value logic circuit based on multi-value logic “Fuji algebra”) →→ Registered after significant correction, Patent No. 5363511. The above-mentioned divisional application of Patent Document 2. JP2011-229069 (Multi-value hazard elimination circuit, ◆ Deemed withdrawal) JP 2012-034345 (multi-value hazard removal circuit) JP2012-077504 (Multi-valued logic means and multi-value hazard removal means having a synchronous latching function)

■■ Related / Patent Literature ■■
JP 2006-190239 ("Information processing means with illegal intrusion operation blocking function" applying multi-valued logic, ◆ Self-initiated. In recent years, cyber terrorism, cyber wars and other emergencies will be required, etc. Therefore, it was withdrawn voluntarily.) →→ ◎ Divided into the following patent document 13. JP-A-2006-228388 →→ Patent No. 4800642 (multi-value storage means and multi-stable circuit). In addition, ◆ Japanese Patent Laid-Open No. 2005-116168 of the same invention of the prior application is undertaken voluntarily. JP-A-2006-252742 →→ Patent No. 4800657 (multi-value storage means and multi-stable circuit) Japanese Patent Laid-Open No. 2006-345468-> Patent No. 4643376 (multi-value storage means, multi-value transfer gate means, multi-value synchronous latch means and multi-value synchronization signal generating means). Japanese Patent Laid-Open No. 2007-035233 →→ Patent No. 4,800,706 (multi-value decoding means, multi-value storage circuit, and multi-value information processing means) JP 2011-103124 ("Information processing means with illegal intrusion operation blocking function" applying multi-valued logic, ◆ Self-initiated. In recent years, cyber terrorism, cyber wars and other emergencies will be required, etc. Therefore, it was withdrawn voluntarily.) →→ The above-mentioned divisional application of Patent Document 8. JP 2011-172254 →→ Patent No. 5249379 (multi-value bidirectional switching means), divisional application of the above-mentioned Patent Document 10. Furthermore, it is divided into the following and patent document 16. Japanese Patent Application Laid-Open No. 2011-204349 (multi-state buffer means, multi-value multiplexer means and multi-value demultiplexer means, ◆ under voluntary withdrawal), divisional application of the above-mentioned Patent Document 12. JP 2012-069236 →→ Patent No. 5139568 (multi-value buffer means), divisional application of the above-mentioned Patent Document 14.

■■ Related / non-patent literature ■■
“Digital Digital Circuits Understandable”, p. 9 line 14 to p. "Complete system" on the first line of 10 and p. 76-p. 80 [[1] logic level to [2] noise margin]. Author: Keitaro Sekine, published by OHM Co., Ltd. on July 25, 1997. “Introduction to Logic Circuits”, p. 31 “(8) Complete system” and p. 126-p. 128 “6.4 IC characteristics (1) Signal voltage value and noise margin”. Author: Ryuji Hamabe, published by Morikita Publishing Co., Ltd. on September 28, 2001. "Multi-value information processing-Post binary electronics-", p. 16-p. 17 “completeness, complete system, complete” description. Author: Tatsuo Higuchi, Michitaka Kameyama, Shokodo published in June 1989. P. Of "Introduction to Illustrated Digital Circuit". 79-88 (binary pulse trigger method). Published 4th edition on April 25, 2008 by Nippon Riko Publishing Co., Ltd. Author: Tsuguo Nakamura. “Introduction to Transistor Circuit Lecture 5: Digital Circuits”, p. 46-p. 47 “4.6 Notes on using logic circuits [1] Logic voltage level and noise margin”. Supervision: Yoshifumi Amemiya and Nori Koshiba. Authors: Kensuke Shimizu and Masahiro Masakazu. Issued on May 20, 1981 by Ohm Co., Ltd. “Pulse Digital Circuit”, p. 125-p. 130 “5. Basic characteristics of circuit 5.1 Amplitude characteristics of pulse digital circuit ”. Author: Akira Kawamata. Published by Nikkan Kogyo Shimbun on February 15, 1995. “Pulse and digital circuit”, p. 128 “Threshold Level” and p. 129 “Logical Level”. Edit: Masao Yoneyama. Author: Shigeyuki Ohara, Sumio Yoshikawa, Toshio Shinozaki, Shiro Takahashi. Published by Tokai University Press on April 5, 2001. “Practical Introduction Series: How to Use CMOS Circuit [1]”, “Element Threshold Voltage” on page 44 and “Circuit Threshold Voltage” on page 50. Author: Yasoji Suzuki. Published on October 15, 1997 by the Industrial Research Committee. "High-tech classroom, multi-value logic circuit, IC density increases and binary and ternary do not go", published by Nikkei Sangyo Shimbun (Tokyo version) on November 22, 1985. Written by Ishizuka Yoshihiko. Mathematical Sciences February Issue (1980, No.200) Special Issue Multivalued Logic, published by Science Co., Ltd. on February 1, 1980. “Attic Resource Room Multi-valued Logic” on pages 374-375 of “Transistor Technology September 1997”. Published on September 1, 1997 by CQ Publishing Co., Ltd. Author: Hidekazu Inoue. “The Institute of Electrical Engineers of Electrical Technical Term No. 9 Power Electronics, Author: “The Electrotechnical Society, Electrical Terminology Standards Special Committee”, “The Institute of Electrical Engineers, Semiconductor Power Converter Terminology Subcommittee”, Editor: The Institute of Electrical Engineers of Japan, Corona Corp. Issued the first revised edition of Japan. "Bidirectional switch, bidirectional controllable switch, reverse conducting switch, reverse blocking switch". “Valve” has almost the same meaning as “switch”.

■■ Problems to be solved by the first invention ■■
In order to realize the “multi-value NOT two-stage connection means based on the Fuji algebra” having the above-described effects (paragraph number [0002]), the preceding multi-value NOT means and the subsequent multi-value NOT means It is an object to provide “multi-value NOT two-stage connection means based on the Fuji algebra” in which “specific values common to input and output” are different from each other.

■■ Problems to be solved by the second invention ■■
In order to realize the “multi-value NOT / EVEN two-stage connection means based on the Fuji algebra” having the above-described effects (paragraph number [0003]), the preceding multi-value NOT means and the subsequent multi-value EVEN means are provided. Then, it is a problem to provide “multi-value NOT / EVEN two-stage connection means based on the Fuji algebra” whose “specific values common to input and output” are different from each other.

■■ Problems to be solved by the third invention ■■
In order to realize the “multi-value EVEN two-stage connection means based on the Fuji algebra” having the above-mentioned effects (paragraph number [0004]), the preceding multi-value EVEN means and the subsequent multi-value EVEN means It is an object to provide a “multi-value EVEN two-stage connection means based on the Fuji algebra” having different “specific values common to input and output”.

■■ Problems to be solved by the fourth invention ■■
In order to realize the “multi-value EVEN / NOT two-stage connection means based on the Fuji algebra” having the above-mentioned effects (paragraph number [0005]), the preceding multi-value EVEN means and the subsequent multi-value NOT means Then, it is a problem to provide “multi-value EVEN / NOT two-stage connection means based on the Fuji algebra” whose “specific values common to input and output” are different from each other.

■■ Means for Solving the Problem of the First Invention ■■
"The following multi-value NOT means or the following multi-value synchronous NOT means" and "the following multi-value NOT means or the following multi-value synchronous NOT means" having a specific integer different from this are connected in two stages before and after,
"First potential pulling means for pulling up or pulling down the potential of the outlet means in the previous stage to the specified constant potential in the subsequent stage" and "Pulling the potential of the outlet means in the subsequent stage to the specified constant potential in the preceding stage “Multi-value NOT two-stage connection means based on the Fuji algebra” provided with “second potential pulling means for up or pulling down”.
◆ ◇ ◆ Multi-value NOT method ◆ ◇ ◆
When three or three or more predetermined plurals are represented by N,
“N constant potentials that increase or decrease in numerical order from the first constant potential to the Nth constant potential” are supplied, and each constant potential and 0 to (N -1), the first constant potential supply means to the Nth constant potential supply means defined as one-to-one correspondence with the first constant potential in order from the integer 0, "
“Inlet means to be the entrance of one input potential signal”;
“Exit means for exiting output potential signal”;
“One specific constant potential supply means determined in advance among the first constant potential supply means to the Nth constant potential supply means” and the outlet means are connected in one direction when driven off. Or pull-switching means that is bi-directionally off, "
“To“ whether or not the input integer corresponding to the input potential signal is equal to or not equal to the specific integer corresponding to the specific constant potential supply means ”is applied to“ the following two or four threshold potentials ” Numerical determination means for determining whether the determination is positive or negative and outputting the determination result as a determination result signal ",
"On / off drive means that operates based on the determination result signal and drives the pull switching means off if the determination result is affirmative, and on-drives it if negative,"
Is a multi-value NOT means.
◆ ◇ Two or four threshold potentials ◇ ◆
◆ “Is equal?” Means “a positive threshold potential and a negative threshold potential determined in advance with reference to a specific constant potential of the specific constant potential supply means”.
* However, when these constant potentials increase in numerical order from the first constant potential to the Nth constant potential, when the specific integer is 0, only the positive threshold potential may be used, or the specific potential When the integer is (N-1), only the negative threshold potential may be used. On the other hand, when these constant potentials decrease in numerical order from the first constant potential to the Nth constant potential, when the specific integer is 0, only the negative threshold potential may be used, or the specific integer When is (N-1), only the positive threshold potential may be used.
“In the case of not”, “a negative threshold potential determined in advance with reference to a constant potential one higher than the specific constant potential among the first constant potential to the Nth constant potential” and “ A positive threshold potential determined in advance with reference to a constant potential one lower than the specific constant potential among the first constant potential to the Nth constant potential ”.
* However, when these constant potentials increase in numerical order from the first constant potential to the Nth constant potential, when the specific integer is 0, only the negative threshold potential may be used, or the specific potential When the integer is (N−1), only the positive threshold potential may be used. On the other hand, when these constant potentials decrease in numerical order from the first constant potential to the Nth constant potential, when the specific integer is 0, only the positive side threshold potential may be used, or the specific integer When (N-1) is, only the negative threshold potential is sufficient.
◆ ◇ ◆ Multi-value synchronous NOT means ◆ ◇ ◆
In the multi-value NOT means,
The signal line connection between the numerical discriminating means and the on / off driving means is temporarily disconnected, and during that period, the discrimination result signal is input “as is or matched” as a holding signal based on the synchronization signal, and the holding is performed. A “binary synchronous flip-flop means for outputting a“ positive output signal or complementary output signal ”of the signal to the on / off driving means”,
"Synchronization signal supply means for supplying the synchronization signal to the binary synchronization flip-flop means" is provided,
The on / off driving means drives the pull switching means on / off based on “the positive output signal or the complementary output signal”, but “the output signal on the basis of the pull switching means indicates the input signal at the time of input”. If the “determination result” is affirmative, it is turned off, and if it is negative, it is multi-value synchronous NOT means for driving it on.

This is equivalent to the multi-value EVEN means (or multi-value EVEN circuit) based on the Fuji algebra, and is different from the “conventional multi-value NOT two-stage connection means using the same specific integer in the preceding stage and the subsequent stage”. “Multi-value NOT two-stage connection means using different specific integers in the preceding stage and the succeeding stage” can be configured.
1) For this reason, the multi-level NOT means at the preceding stage and the multi-level NOT means at the subsequent stage have different “specific values common to input and output”, and the logical operation of the multi-level NOT two-stage connection means. Is equivalent to one stage of the multi-value EVEN means, but the value can be substantially changed from “previous input / output common / specific value to subsequent input / output common / specific value”.
(Effect 1)
However, if the number of synchronization types differs between the multi-value logic one-stage means and the multi-value logic two-stage connection means with respect to the equivalence relationship between the two logic operations, the difference in the logic operation timing between the two is ignored. ing.
2) Since the number of stages can be increased from the multi-level logic one-stage means to the multi-value logic two-stage connection means, “the signal propagation time can be positively delayed for time adjustment and operation timing adjustment.
(Effect 2)
However, this effect is also present in the conventional multi-value NOT two-stage connection means, but it becomes convenient because the choices of multi-value NOT means that can be used increase. That is, it becomes possible to newly use a multi-value NOT means having different specific integers.
3) Furthermore, when both the preceding stage and the latter stage are synchronous, there are two timings for synchronous latching in the front and rear, so that the timing of the overall synchronous latching in a certain “multi-value circuit based on the Fuji algebra” It is convenient to use this multi-value NOT two-stage connection means when matching the two. (Effect 3)
However, this effect is also present in the conventional multi-value NOT two-stage connection means, but it is convenient because the choices of the multi-value NOT means that can be used increase. That is, it becomes possible to newly use a multi-value NOT means having different specific integers.
For example, in either multi-value NOT two-stage connection means, there are the following four patterns.
A) Both the former stage and the latter stage are asynchronous.
B) The preceding stage is a synchronous type and the subsequent stage is an asynchronous type.
C) The front and rear stages are both synchronous.
D) The preceding stage is an asynchronous type and the subsequent stage is a synchronous type.
When the preceding stage and the subsequent stage are both synchronous, the opportunity for synchronous latching and the timing are increased by one to become two. There are times when it becomes more advantageous than “,” which is convenient.
◆ 4) Then, the multi-level DC power supply means and power lines used by the multi-level NOT means in the preceding stage and the multi-level NOT means in the subsequent stage are different in “a part or all of them”. Each of the plurality of multi-value logic means (or multi-value logic circuits) serving as a load of each DC power supply means is "distributed to each DC power supply means" or "collected in a specific DC power supply means" It is possible to freely select how to power the multi-value logic means. (Effect 4)
In addition, in “each multi-valued logic circuit (or each multi-valued logic means) based on the Fuji algebra”, regardless of whether it is an asynchronous type or a synchronous type, when the specific integer is changed in the same type of multi-valued logic circuit, the circuit is connected There is an advantage that the specific integer can be changed only by changing the power source and the power line.
For example, in a 10-value logic circuit, “a power supply circuit configuration in which at least nine DC power supplies (means) are connected in series in the same direction and ten power supply lines and power supply plates are taken out from each power supply terminal or each common power supply terminal”. It has become. At that time, it is good if at least nine DC power supplies can be prepared easily, but normally, the “remaining DC power supplies” are configured using DC-DC converter circuits from Omoto DC power supplies. In many cases, it is possible to collect several loads on the large DC power supply. Alternatively, it may be possible to collect several loads separately in the several DC power supplies. That is, the load of the load can be applied to each DC power source.
Alternatively, if the at least nine DC power supplies can be easily and equally prepared, it is very convenient to distribute each load as evenly as possible to each DC power supply.

◆ 5) As an additional effect, the multi-value NOT two-stage connection means of the first invention is expressed as follows: “All multi-value logic circuits can be expressed and configured regardless of the multi-value number N, and multi-value AND "Multi-value complete circuit that uses a circuit etc. as a complete system" is equivalent to this multi-value complete circuit. "Multi-value complete circuit that uses a multi-value NOR circuit etc. as a complete system" Circuit "can be provided. That is, the number of options of the multi-value logic circuit to be used is increased, which is convenient.
(Additional effect)
“Digital Digital Circuits Understandable”, p. 9 line 14 to p. "Complete system" on the first line of 10. Author: Keitaro Sekine, published by OHM Co., Ltd. on July 25, 1997. “Introduction to Logic Circuits”, p. 31 “(8) Complete system”. Author: Ryuji Hamabe, published by Morikita Publishing Co., Ltd. on September 28, 2001. "Multi-value information processing-Post binary electronics-", p. 16-p. 17 “completeness, complete system, complete” description. Author: Tatsuo Higuchi, Michitaka Kameyama, Shokodo published in June 1989.

■■ Means for Solving the Problem of the Second Invention ■■
In the multi-value NOT two-stage connection means described in paragraph [0015],
When the subsequent stage is the multi-value NOT means, the multi-value NOT means is “a multi-value EVEN means whose on / off driving means is turned on / off in the opposite direction to the positive / negative of the determination result”. ,
When the subsequent stage is the multi-value synchronous NOT means, the multi-value synchronous NOT means “the on / off drive means drives on / off in the opposite direction to the positive / negative of the determination result at the time of input”. “Multi-value synchronous EVEN means” is “multi-value NOT / EVEN two-stage connection means based on Fujie algebra”.

As a result, it is equivalent to the multi-value NOT means (or multi-value NOT circuit) based on the Fuji algebra, and moreover, “conventional multi-value NOT / EVEN two-stage connection means using the same specific integer in the preceding stage and the subsequent stage” Unlike the above, "multi-value NOT / EVEN two-stage connection means using different specific integers in the former stage and the latter stage" can be configured.
1) For this reason, the multi-level NOT means in the preceding stage and the multi-value EVEN means in the subsequent stage have different “specific values common to input and output”, and the multi-level NOT / EVEN two-stage connection means The logical operation is equivalently the same as that of one stage of the multi-value NOT means, but the value can be substantially changed from “previous input / output common / specific value to subsequent input / output common / specific value”.
(Effect 1)
However, if the number of synchronization types differs between the multi-value logic one-stage means and the multi-value logic two-stage connection means with respect to the equivalence relationship between the two logic operations, the difference in the logic operation timing between the two is ignored. ing.
2) Since the number of stages can be increased from the multi-level logic one-stage means to the multi-value logic two-stage connection means, “the signal propagation time can be positively delayed for time adjustment and operation timing adjustment.
(Effect 2)
However, this effect is also present in the conventional multi-value NOT / EVEN two-stage connection means, but it becomes convenient because the choices of the multi-value EVEN means that can be used increase. That is, it becomes possible to newly use multi-value EVEN means whose specific integers are different.
3) Furthermore, when both the preceding stage and the latter stage are synchronous, there are two timings for synchronous latching in the front and rear, so that the timing of the overall synchronous latching in a certain “multi-value circuit based on the Fuji algebra” It is convenient to use this multi-value NOT / EVEN two-stage connection means when matching the two. (Effect 3)
However, this effect is also present in the conventional multi-value NOT / EVEN two-stage connection means, but it becomes convenient because the number of usable multi-value EVEN means increases. That is, it becomes possible to newly use multi-value EVEN means whose specific integers are different.
For example, in either of the multi-value NOT / EVEN two-stage connection means, there are the following four patterns.
A) Both the former stage and the latter stage are asynchronous.
B) The preceding stage is a synchronous type and the subsequent stage is an asynchronous type.
C) The front and rear stages are both synchronous.
D) The preceding stage is an asynchronous type and the subsequent stage is a synchronous type.
When the preceding stage and the subsequent stage are both synchronous, the opportunity for synchronous latching and the timing are increased by one to become two, so the synchronous type “multi-value NOT means or multi-value NOT means having only one opportunity and timing” There are times when it becomes more advantageous than “,” which is convenient.
◆ 4) Then, the multi-level DC power supply means and power lines used by the multi-level NOT means in the preceding stage and the multi-level EVEN means in the subsequent stage are different in “a part or all of them”. Each of the plurality of multi-value logic means (or multi-value logic circuits) serving as a load of each DC power supply means is "distributed to each DC power supply means" or "collected in a specific DC power supply means" It is possible to freely select how to power the multi-value logic means. (Effect 4)
In addition, in “each multi-valued logic circuit (or each multi-valued logic means) based on the Fuji algebra”, regardless of whether it is an asynchronous type or a synchronous type, when the specific integer is changed in the same type of multi-valued logic circuit, the circuit is connected There is an advantage that the specific integer can be changed only by changing the power source and the power line.
For example, in a 10-value logic circuit, “a power supply circuit configuration in which at least nine DC power supplies (means) are connected in series in the same direction and ten power supply lines and power supply plates are taken out from each power supply terminal or each common power supply terminal”. It has become. At that time, it is good if at least nine DC power supplies can be prepared easily, but normally, the “remaining DC power supplies” are configured using DC-DC converter circuits from Omoto DC power supplies. In many cases, it is possible to collect several loads on the large DC power supply. Alternatively, it may be possible to collect several loads separately in the several DC power supplies. That is, the load of the load can be applied to each DC power source.
Alternatively, if the at least nine DC power supplies can be easily and equally prepared, it is very convenient to distribute each load as evenly as possible to each DC power supply.

■■ Means for Solving the Problem of the Third Invention ■■
"The following multi-value EVEN means or the following multi-value synchronous EVEN means" and "the following multi-value EVEN means or the following multi-value synchronous EVEN means" having a specific integer different from this are connected in two stages before and after,
"First potential pulling means for pulling up or pulling down the potential of the outlet means in the preceding stage to the specified constant potential in the subsequent stage" and "Pulling the potential of the outlet means in the subsequent stage to the specified constant potential in the preceding stage “Multi-value EVEN two-stage connection means based on the Fuji algebra” provided with “second potential pulling means for up or pulling down”.
◆ ◇ ◆ Multi-value EVEN means ◆ ◇ ◆
When three or three or more predetermined plurals are represented by N,
“N constant potentials that increase or decrease in numerical order from the first constant potential to the Nth constant potential” are supplied, and each constant potential and 0 to (N -1), the first constant potential supply means to the Nth constant potential supply means defined as one-to-one correspondence with the first constant potential in order from the integer 0, "
“Inlet means to be the entrance of one input potential signal”;
“Exit means for exiting output potential signal”;
“One specific constant potential supply means determined in advance among the first constant potential supply means to the Nth constant potential supply means” and the outlet means are connected in one direction when driven off. Or pull-switching means that is bi-directionally off, "
“To“ whether or not the input integer corresponding to the input potential signal is equal to or not equal to the specific integer corresponding to the specific constant potential supply means ”is applied to“ the following two or four threshold potentials ” Numerical determination means for determining whether the determination is positive or negative and outputting the determination result as a determination result signal ",
"On / off drive means that operates based on the determination result signal and drives the pull switching means on if the determination result is affirmative;
Is a multi-value EVEN means.
◆ ◇ Two or four threshold potentials ◇ ◆
◆ “Is equal?” Means “a positive threshold potential and a negative threshold potential determined in advance with reference to a specific constant potential of the specific constant potential supply means”.
* However, when these constant potentials increase in numerical order from the first constant potential to the Nth constant potential, when the specific integer is 0, only the positive threshold potential may be used, or the specific potential When the integer is (N-1), only the negative threshold potential may be used. On the other hand, when these constant potentials decrease in numerical order from the first constant potential to the Nth constant potential, when the specific integer is 0, only the negative threshold potential may be used, or the specific integer When is (N-1), only the positive threshold potential may be used.
“In the case of not”, “a negative threshold potential determined in advance with reference to a constant potential one higher than the specific constant potential among the first constant potential to the Nth constant potential” and “ A positive threshold potential determined in advance with reference to a constant potential one lower than the specific constant potential among the first constant potential to the Nth constant potential ”.
* However, when these constant potentials increase in numerical order from the first constant potential to the Nth constant potential, when the specific integer is 0, only the negative threshold potential may be used, or the specific potential When the integer is (N−1), only the positive threshold potential may be used. On the other hand, when these constant potentials decrease in numerical order from the first constant potential to the Nth constant potential, when the specific integer is 0, only the positive side threshold potential may be used, or the specific integer When (N-1) is, only the negative threshold potential is sufficient.
◆ ◇ ◆ Multi-value synchronous EVEN means ◆ ◇ ◆
In the multi-value EVEN means,
The signal line connection between the numerical discriminating means and the on / off driving means is temporarily disconnected, and during that period, the discrimination result signal is input “as is or matched” as a holding signal based on the synchronization signal, and the holding is performed. A “binary synchronous flip-flop means for outputting a“ positive output signal or complementary output signal ”of the signal to the on / off driving means”,
"Synchronization signal supply means for supplying the synchronization signal to the binary synchronization flip-flop means" is provided,
The on / off driving means drives the pull switching means on / off based on “the positive output signal or the complementary output signal”, but “the output signal on the basis of the pull switching means indicates the input signal at the time of input”. If the “determination result” is affirmative, it is turned on, and if it is negative, it is multi-value synchronous EVEN means that drives it off.

This is equivalent to the multi-value EVEN means (or multi-value EVEN circuit) based on the Fuji algebra, and is different from the "conventional multi-value EVEN two-stage connection means using the same specific integer in the preceding stage and the subsequent stage". “Multi-value EVEN two-stage connection means using different specific integers in the preceding stage and the succeeding stage” can be configured.
1) For this reason, the multi-level EVEN means in the preceding stage and the multi-level EVEN means in the subsequent stage have different “specific values common to input and output”, and the logical operation of the multi-level EVEN two-stage connection means Is equivalent to one stage of the multi-value EVEN means, but the value can be substantially changed from “previous input / output common / specific value to subsequent input / output common / specific value”.
(Effect 1)
However, if the number of synchronization types differs between the multi-value logic one-stage means and the multi-value logic two-stage connection means with respect to the equivalence relationship between the two logic operations, the difference in the logic operation timing between the two is ignored. ing.
2) Since the number of stages can be increased from the multi-level logic one-stage means to the multi-value logic two-stage connection means, “the signal propagation time can be positively delayed for time adjustment and operation timing adjustment.
(Effect 2)
However, this effect also exists in the conventional multi-value EVEN two-stage connection means, but it becomes convenient because the choices of the multi-value EVEN means that can be used increase. That is, it becomes possible to newly use multi-value EVEN means whose specific integers are different.
3) Furthermore, when both the preceding stage and the latter stage are synchronous, there are two timings for synchronous latching in the front and rear, so that the timing of the overall synchronous latching in a certain “multi-value circuit based on the Fuji algebra” It is convenient to use this multi-value EVEN two-stage connection means when matching. (Effect 3)
However, this effect is also present in the conventional multi-value EVEN two-stage connection means, but it is convenient because the choices of the multi-value EVEN means that can be used increase. That is, it becomes possible to newly use multi-value EVEN means whose specific integers are different.
For example, in any of the multi-value EVEN two-stage connection means, there are the following four patterns.
A) Both the former stage and the latter stage are asynchronous.
B) The preceding stage is a synchronous type and the subsequent stage is an asynchronous type.
C) The front and rear stages are both synchronous.
D) The preceding stage is an asynchronous type and the subsequent stage is a synchronous type.
When the preceding stage and the subsequent stage are both synchronous, the opportunity for synchronous latching and the timing are increased by one to become two. There are times when it becomes more advantageous than “,” which is convenient.
◆ 4) Then, the multi-value DC power supply means and power lines used by the multi-value EVEN means in the preceding stage and the multi-value EVEN means in the subsequent stage are different in “a part or all of them”. Each of the plurality of multi-value logic means (or multi-value logic circuits) serving as a load of each DC power supply means is "distributed to each DC power supply means" or "collected in a specific DC power supply means" It is possible to freely select how to power the multi-value logic means. (Effect 4)
In addition, in “each multi-valued logic circuit (or each multi-valued logic means) based on the Fuji algebra”, regardless of whether it is an asynchronous type or a synchronous type, when the specific integer is changed in the same type of multi-valued logic circuit, the circuit is connected There is an advantage that the specific integer can be changed only by changing the power source and the power line.
For example, in a 10-value logic circuit, “a power supply circuit configuration in which at least nine DC power supplies (means) are connected in series in the same direction and ten power supply lines and power supply plates are taken out from each power supply terminal or each common power supply terminal”. It has become. At that time, it is good if at least nine DC power supplies can be prepared easily, but normally, the “remaining DC power supplies” are configured using DC-DC converter circuits from Omoto DC power supplies. In many cases, it is possible to collect several loads on the large DC power supply. Alternatively, it may be possible to collect several loads separately in the several DC power supplies. That is, the load of the load can be applied to each DC power source.
Alternatively, if the at least nine DC power supplies can be easily and equally prepared, it is very convenient to distribute each load as evenly as possible to each DC power supply.

■■ Means for Solving the Problem of the Fourth Invention ■■
In the multi-value EVEN two-stage connection means described in paragraph [0020],
When the subsequent stage is the multi-value EVEN means, the multi-value EVEN means is “a multi-value NOT means that the on / off driving means is turned on / off in the opposite direction to the positive / negative of the determination result”. ,
When the subsequent stage is the multi-value synchronous EVEN means, the multi-value synchronous EVEN means “the on / off drive means is turned on / off in the opposite direction to the positive / negative of the determination result at the time of input”. “Multi-value synchronous NOT means” is “multi-value EVEN / NOT two-stage connection means based on Fuji algebra”.

By this, it is equivalent to the multi-value NOT means (or multi-value NOT circuit) based on the Fuji algebra, and moreover, “conventional multi-value EVEN / NOT two-stage connection means using the same specific integer in the preceding stage and the subsequent stage” Unlike the above, "multi-value EVEN / NOT two-stage connection means using different specific integers in the preceding and succeeding stages" can be configured.
1) For this reason, the multi-level EVEN means in the preceding stage and the multi-level NOT means in the subsequent stage have different “specific values common to input and output”, and the multi-level EVEN / NOT two-stage connection means The logical operation is equivalently the same as that of one stage of the multi-value NOT means, but the value can be substantially changed from “previous input / output common / specific value to subsequent input / output common / specific value”.
(Effect 1)
However, if the number of synchronization types differs between the multi-value logic one-stage means and the multi-value logic two-stage connection means with respect to the equivalence relationship between the two logic operations, the difference in the logic operation timing between the two is ignored. ing.
2) Since the number of stages can be increased from the multi-level logic one-stage means to the multi-value logic two-stage connection means, “the signal propagation time can be positively delayed for time adjustment and operation timing adjustment.
(Effect 2)
However, this effect is also present in the conventional multi-value EVEN / NOT two-stage connection means, but it becomes convenient because the choices of the multi-value NOT means that can be used increase. That is, it becomes possible to newly use a multi-value NOT means having different specific integers.
3) Furthermore, when both the preceding stage and the latter stage are synchronous, there are two timings for synchronous latching in the front and rear, so that the timing of the overall synchronous latching in a certain “multi-value circuit based on the Fuji algebra” It is convenient to use this multi-value EVEN / NOT two-stage connection means when matching the two. (Effect 3)
However, this effect is also present in the conventional multi-value EVEN / NOT two-stage connection means, but it becomes convenient because the choices of the multi-value NOT means that can be used increase. That is, it becomes possible to newly use a multi-value NOT means having different specific integers.
For example, in either multi-value EVEN / NOT two-stage connection means, there are the following four patterns.
A) Both the former stage and the latter stage are asynchronous.
B) The preceding stage is a synchronous type and the subsequent stage is an asynchronous type.
C) The front and rear stages are both synchronous.
D) The preceding stage is an asynchronous type and the subsequent stage is a synchronous type.
When both the preceding stage and the subsequent stage are synchronous, the opportunity for synchronous latching and the timing are increased by one to become two, so the synchronous type "multi-value NOT means or multi-value NOT circuit having only one opportunity and timing" There are times when it becomes more advantageous than “,” which is convenient.
◆ 4) Then, the multi-value DC power supply means and power lines used by the multi-value EVEN means in the preceding stage and the multi-value NOT means in the subsequent stage are different in “a part or all of them”. Each of the plurality of multi-value logic means (or multi-value logic circuits) serving as a load of each DC power supply means is "distributed to each DC power supply means" or "collected in a specific DC power supply means" It is possible to freely select how to power the multi-value logic means. (Effect 4)
In addition, in “each multi-valued logic circuit (or each multi-valued logic means) based on the Fuji algebra”, regardless of whether it is an asynchronous type or a synchronous type, when the specific integer is changed in the same type of multi-valued logic circuit, the circuit is connected There is an advantage that the specific integer can be changed only by changing the power source and the power line.
For example, in a 10-value logic circuit, “a power supply circuit configuration in which at least nine DC power supplies (means) are connected in series in the same direction and ten power supply lines and power supply plates are taken out from each power supply terminal or each common power supply terminal”. It has become. At that time, it is good if at least nine DC power supplies can be prepared easily, but normally, the “remaining DC power supplies” are configured using DC-DC converter circuits from Omoto DC power supplies. In many cases, it is possible to collect several loads on the large DC power supply. Alternatively, it may be possible to collect several loads separately in the several DC power supplies. That is, the load of the load can be applied to each DC power source.
Alternatively, if the at least nine DC power supplies can be easily and equally prepared, it is very convenient to distribute each load as evenly as possible to each DC power supply.

The effects of the first to fourth inventions are summarized as follows.
■■ Effects of the first invention ■
1) The multi-level NOT means in the preceding stage and the multi-value NOT means in the subsequent stage have different “specific values common to input and output”, and the logical operation of the multi-level NOT two-stage connection means is equivalent. The multi-value EVEN means is the same as one stage, but the value can be changed substantially from “input / output common / specific value in the previous stage to input / output common / specific value in the subsequent stage”. (Effect 1)
However, when the number of synchronous types differs between the multi-value one-stage means and the multi-value two-stage connection means with respect to the equivalent relationship between the two logic operations, the difference in the logic operation timing between the two is ignored. .
2) Since the number of stages can be increased from the one-stage multi-value logic means to the multi-value logic means connected in two stages, “the signal propagation time can be positively delayed for time adjustment and operation timing adjustment.
(Effect 2)
However, this effect is also present in the conventional multi-value NOT two-stage connection means, but it is convenient because the number of options of the multi-value NOT means to be used increases. That is, it becomes possible to use multi-value NOT means having different specific integers.
◆ 3) When both the preceding and succeeding stages are synchronous, there are two timings of synchronous latching in the front and rear, so when matching the timing of the entire synchronous latching in a certain “multi-value circuit based on the Fuji algebra” It is convenient to use this two-stage multi-level logic means.
(Effect 3)
However, this effect is also present in the conventional multi-value NOT two-stage connection means, but it is convenient because the number of options of the multi-value NOT means to be used increases. That is, it becomes possible to use multi-value NOT means having different specific integers.
4) Since the multi-level DC power supply means used by the preceding stage means and the subsequent stage means differ in “a part or all of them”, a plurality of multi-values serving as loads on the multi-level DC power supply means It is possible to freely select the power supply method of each multi-value logic means, such as “distributing the logic means to each DC power supply means” or “collecting it to a specific DC power supply means”. (Effect 4)

◆ 5) As an additional effect, the multi-value NOT two-stage connection means of the first invention is “all multi-value logic circuits can be expressed and configured regardless of the multi-value number N, and a multi-value AND circuit, etc. "Multi-value complete circuit that uses a multi-value NOR circuit as a complete system" having the same circuit function and logic function equivalent to this multi-value complete circuit. Can be provided. That is, the number of options of the multi-value logic circuit to be used is increased, which is convenient.
(Additional effect)
“Digital Digital Circuits Understandable”, p. 9 line 14 to p. "Complete system" on the first line of 10. Author: Keitaro Sekine, published by OHM Co., Ltd. on July 25, 1997. “Introduction to Logic Circuits”, p. 31 “(8) Complete system”. Author: Ryuji Hamabe, published by Morikita Publishing Co., Ltd. on September 28, 2001. "Multi-value information processing-Post binary electronics-", p. 16-p. 17 “completeness, complete system, complete” description. Author: Tatsuo Higuchi, Michitaka Kameyama, Shokodo published in June 1989.

■■ Effects of the second invention ■
1) The multi-level NOT means in the preceding stage and the multi-value EVEN means in the subsequent stage have different “specific values common to input and output”, and the logical operation of the multi-level NOT / EVEN two-stage connection means is Equivalently, it is the same as one stage of the multi-level NOT means in the preceding stage, but the value can be changed substantially from “previous input / output common / specific value to subsequent input / output common / specific value”.
(Effect 1)
However, when the number of synchronous types differs between the multi-value one-stage means and the multi-value two-stage connection means with respect to the equivalent relationship between the two logic operations, the difference in the logic operation timing between the two is ignored. .
◆ 2) Since the number of stages can be increased from the one-stage multi-value logic means to the multi-value logic means connected in two stages, the signal propagation time can be actively delayed for time adjustment and operation timing adjustment.
(Effect 2)
However, this effect is also present in the conventional multi-value NOT / EVEN two-stage connection means, but it is convenient because the number of options of the multi-value EVEN means to be used increases. That is, it becomes possible to use multi-value EVEN means having different specific integers.
◆ 3) When both the preceding and succeeding stages are synchronous, there are two timings of synchronous latching in the front and rear, so when matching the timing of the entire synchronous latching in a certain “multi-value circuit based on the Fuji algebra” It is convenient to use this two-stage multi-level logic means.
(Effect 3)
However, this effect is also present in the conventional multi-value NOT / EVEN two-stage connection means, but it becomes convenient because the number of options of the multi-value EVEN means to be used increases. That is, it becomes possible to use multi-value EVEN means having different specific integers.
4) Since the multi-level DC power supply means used by the preceding stage means and the subsequent stage means differ in “a part or all of them”, a plurality of multi-values serving as loads on the multi-level DC power supply means It is possible to freely select the power supply method of each multi-value logic means, such as “distributing the logic means to each DC power supply means” or “collecting it to a specific DC power supply means”. (Effect 4)

■■ Effects of the third invention ■
1) The multi-level EVEN means in the preceding stage and the multi-level EVEN means in the subsequent stage have different “specific values common to input and output”, and the logical operation of the multi-level EVEN two-stage connection means is equivalent. However, it is possible to change the value substantially from “previous input / output common / specific value to subsequent input / output common / specific value”.
(Effect 1)
However, when the number of synchronous types differs between the multi-value one-stage means and the multi-value two-stage connection means with respect to the equivalent relationship between the two logic operations, the difference in the logic operation timing between the two is ignored. .
2) Since the number of stages can be increased from one-stage multi-value logic means to multi-value logic means connected in two stages, the signal propagation time can be positively delayed for time adjustment and operation timing adjustment.
(Effect 2)
However, this effect is also present in the conventional multi-value EVEN two-stage connection means, but it becomes convenient because the number of options of the multi-value EVEN means to be used increases. That is, it becomes possible to use multi-value EVEN means having different specific integers.
◆ 3) When both the preceding and succeeding stages are synchronous, there are two timings of synchronous latching in the front and rear, so when matching the timing of the entire synchronous latching in a certain “multi-value circuit based on the Fuji algebra” It is convenient to use this two-stage multi-level logic means.
(Effect 3)
However, this effect is also present in the conventional multi-value EVEN two-stage connection means, but it becomes convenient because the choices of the multi-value EVEN means to be used increase. That is, it becomes possible to use multi-value EVEN means having different specific integers.
4) Since the multi-level DC power supply means used by the preceding stage means and the subsequent stage means differ in “a part or all of them”, a plurality of multi-values serving as loads on the multi-level DC power supply means It is possible to freely select the power supply method of each multi-value logic means, such as “distributing the logic means to each DC power supply means” or “collecting it to a specific DC power supply means”. (Effect 4)

■■ Effects of the fourth invention ■
1) The multi-value EVEN means in the preceding stage and the multi-value NOT means in the subsequent stage have different “specific values common to input and output”, and the logical operation of the multi-value EVEN / NOT two-stage connection means is Equivalently, it is the same as “one-stage multi-value NOT means having the same specific value as the previous stage multi-value EVEN means”, but substantially “from the previous stage input / output common / specific value to the subsequent stage input / output common / specific value. You can change that value. (Effect 1)
However, when the number of synchronous types differs between the multi-value one-stage means and the multi-value two-stage connection means with respect to the equivalent relationship between the two logic operations, the difference in the logic operation timing between the two is ignored. .
◆ 2) Since the number of stages can be increased from the one-stage multi-value logic means to the multi-value logic means connected in two stages, the signal propagation time can be actively delayed for time adjustment and operation timing adjustment.
(Effect 2)
However, although this effect is also present in the conventional multi-value EVEN / NOT two-stage connection means, the number of options of the multi-value NOT means to be used is increased and it becomes convenient. That is, it becomes possible to use multi-value NOT means having different specific integers.
◆ 3) When both the preceding and succeeding stages are synchronous, there are two timings of synchronous latching in the front and rear, so when matching the timing of the entire synchronous latching in a certain “multi-value circuit based on the Fuji algebra” It is convenient to use this two-stage multi-level logic means.
(Effect 3)
However, this effect is also present in the conventional multi-value EVEN / NOT two-stage connection means, but it becomes convenient because the number of options of the multi-value NOT means to be used increases. That is, it becomes possible to use multi-value NOT means having different specific integers.
4) Since the multi-level DC power supply means used by the preceding stage means and the subsequent stage means differ in “a part or all of them”, a plurality of multi-values serving as loads on the multi-level DC power supply means It is possible to freely select the power supply method of each multi-value logic means, such as “distributing the logic means to each DC power supply means” or “collecting it to a specific DC power supply means”. (Effect 4)

It is a circuit diagram which shows one Example of the multi-value NOT two-stage connection means of 1st invention, and its equivalent circuit. It is a circuit diagram which shows the conventional multi-value NOT two-stage connection means and its equivalent circuit for the first invention. FIG. 5 is a circuit diagram showing “another multi-value NOT two-stage connection means and a circuit in which an equivalent relationship is not established” that supports the unique effect of the first invention. It is a circuit diagram which shows one Example of the multi-value NOT * EVEN two-stage connection means of 2nd invention, and its equivalent circuit. It is a circuit diagram which shows the conventional multi-value NOT / EVEN two-stage connection means and its equivalent circuit for the second invention. FIG. 5 is a circuit diagram showing “another multi-value NOT / EVEN two-stage connection means and a circuit in which an equivalent relationship is not established” that supports the unique effect of the second invention. It is a circuit diagram which shows one Example of the multi-value EVEN two-stage connection means of 3rd invention, and its equivalent circuit. It is a circuit diagram which shows the conventional multi-value EVEN two-stage connection means with respect to 3rd invention, and its equivalent circuit. FIG. 10 is a circuit diagram showing “another multi-value EVEN two-stage connection means and a circuit in which an equivalent relationship is not established” that supports the unique effect of the third invention. It is a circuit diagram which shows one Example of the multi-value EVEN * NOT two-stage connection means of 4th invention, and its equivalent circuit. It is a circuit diagram which shows the conventional multi-value EVEN / NOT two-stage connection means and its equivalent circuit for the fourth invention. It is a circuit diagram showing "another multi-value EVEN / NOT two-stage connection means and a circuit in which an equivalent relationship is not established" that supports the unique effect of the fourth invention. FIG. 7 is a circuit diagram showing a “multi-value complete circuit mainly using a multi-value NOR circuit or the like (fifth invention)” supporting the additional effect of the first invention. FIG. 5 is a circuit diagram for explaining an equivalent circuit and duality of “a (basic) multi-value logic circuit based on multi-value logic“ Hooji Algebra ””. FIG. 3 is a circuit diagram showing a synthesis / multi-value logic circuit (= first 10-value complete circuit) that supports “extremely flexible completeness (sexuality)” of “Fuji algebra” that is the basis of each invention. →→ Complete circuit means of multi-valued logic functions. FIG. 16 is a truth table / diagram showing a truth table simplified for explanation of the synthesis / multi-value logic circuit of FIG. 15. The composite / multi-valued logic circuit (= second 10-value complete circuit) is simplified by introducing a multi-value wired OR circuit into the composite / multi-value logic circuit (= first 10-value complete circuit) of FIG. FIG. →→ Complete circuit means of multi-valued logic functions. Similarly, it is a circuit diagram showing a “ternary complete circuit with a multi-value wired OR circuit” that supports “extremely flexible completeness” of “Fuji algebra”. →→ Complete circuit means of multi-valued logic functions. FIG. 19 is a truth table / diagram illustrating a truth table of the synthesis / multi-value logic circuit of FIG. 18. FIG. 16 is a circuit diagram showing a synthesis / multi-value logic circuit (= third 10-value perfect circuit) obtained by improving the synthesis / multi-value logic circuit (= first 10-value perfect circuit) of FIG. 15; →→ Complete circuit means of multi-valued logic functions. FIG. 18 is a circuit diagram showing a synthesis / multi-value logic circuit (= fourth 10-value perfect circuit) obtained by improving the synthesis / multi-value logic circuit (= second 10-value perfect circuit) of FIG. 17; →→ Complete circuit means of multi-valued logic functions. FIG. 10 is a circuit diagram showing a conventional example of an asynchronous multi-valued EVEN circuit based on “Fuji algebra”. FIG. 10 is a circuit diagram showing a first conventional example of an asynchronous multi-value NOT circuit based on “Fuji algebra”. FIG. 10 is a circuit diagram showing a second conventional example of an asynchronous multi-value NOT circuit based on “Fuji algebra”. FIG. 12 is a circuit diagram showing a first conventional example of an asynchronous multi-value AND circuit based on “Fuji algebra”. Second conventional example of asynchronous type multi-value AND circuit based on "Fuji algebra" (when H = G) and one conventional example of asynchronous type "multi-value AND / NOUT circuit or multi-value AND / IN circuit" It is a circuit diagram showing (when H> G). The first conventional example of an asynchronous multi-level NAND circuit based on “Fuji algebra” (when H = G) and the first example of an asynchronous “multi-level NAND / NOUT circuit or multi-level NAND / IN circuit” It is a circuit diagram which shows a prior art example (at the time of H> G). A third conventional example of an asynchronous multi-value AND circuit based on “Fuji algebra” (when H = G), and another conventional example of an asynchronous “multi-value AND / NOUT circuit or multi-value AND / IN circuit” It is a circuit diagram showing (when H> G). The second conventional example of an asynchronous multi-value NAND circuit based on “Fuji algebra” (when H = G) and the second example of an asynchronous “multi-value NAND / NOUT circuit or multi-value NAND / IN circuit” It is a circuit diagram which shows a prior art example (at the time of H> G). One conventional example of an asynchronous type multi-value OR circuit based on “Fuji algebra” (when H = G) and one conventional example of an asynchronous type “multi-value OR / NOUT circuit or multi-value OR / IN circuit” (H FIG. One conventional example of an asynchronous multi-value NOR circuit based on “Fuji algebra” (when H = G) and one conventional example of an asynchronous “multi-value NOR / NOUT circuit or multi-value NOR / IN circuit” (H FIG. It is a circuit diagram showing one embodiment common to the published prior application and the first and second inventions. ◆ When connected to Q terminal: Synchronous type, multi-value NOT means, ◆ When connected to Q bar terminal: Synchronous type, multi-value EVEN means. It is a circuit diagram showing one embodiment common to the published prior application and the first and second inventions. ◆ When connected to Q terminal: Synchronous “multi-value NIN means or multi-value OUT means”, ◆ When connected to Q-bar terminal: Synchronous “multi-value IN means or multi-value NOUT means”. It is a circuit diagram showing one embodiment common to the published prior application and the first and second inventions. ◆ When connected to Q terminal: Synchronous “multi-value NIN means or multi-value OUT means”, ◆ When connected to Q-bar terminal: Synchronous “multi-value IN means or multi-value NOUT means”. It is a circuit diagram showing one embodiment common to the published prior application and the first and second inventions. ◆ When connected to Q terminal: Synchronous type “multi-valued UNDER means or multi-valued OVER means”, ◆ Connected to Q bar terminal: Synchronous type “multi-valued UNDER means or multi-valued NOVER means”. It is a circuit diagram showing one embodiment common to the published prior application and the first and second inventions. ◆ When connected to Q terminal: Synchronous type “multi-value UNDER means or multi-value NOVER means”. ◆ When connected to the Q-bar terminal: Synchronous type “multi-value NUNDER means or multi-value OVER means”. It is a circuit diagram showing one embodiment common to the published prior application and the first and second inventions. ◆ When connected to the Q terminal: Pull-down output synchronous type multi-value NOT means, ◆ When connected to the Q bar terminal: Pull-down output synchronous type multi-value EVEN means. It is a circuit diagram showing one embodiment common to the published prior application and the first and second inventions. ◆ When connected to Q terminal: Pull-up output synchronous type, multi-value NOT means, ◆ When connected to Q bar terminal: Pull-up output synchronous type, multi-value EVEN means It is a circuit diagram showing one embodiment common to the published prior application and the first and second inventions. When connected to the Q terminal and H = G: Synchronous multi-value EVEN means, H> G: Synchronous “multi-value IN means or multi-value NOUT means”. When connected to the Q bar terminal and H = G: synchronous type / multi-value NOT means, and H> G: synchronous type “multi-value NIN means or multi-value OUT means”. FIG. 3 is a circuit diagram showing a first example of the “on / off drive means and pull switching means” portion common to the published prior application, first and second inventions. It is a circuit diagram showing one embodiment common to the published prior application and the first and second inventions. ◆ When connected to Q terminal: Synchronous type, multi-value EVEN means. ◆ When connected to Q bar terminal: Synchronous type, multi-value NOT means. FIG. 6 is a circuit diagram showing a second example of the “on / off drive means and pull switching means” portion common to the published prior application, first and second inventions. It is a circuit diagram showing one embodiment common to the published prior application and the first and second inventions. ◆ When connected to Q terminal: Synchronous type, multi-value NOT means, ◆ When connected to Q bar terminal: Synchronous type, multi-value EVEN means. FIG. 12 is a circuit diagram showing a third example of the “on / off drive means and pull switching means” portion common to the published prior application, first and second inventions. FIG. 12 is a circuit diagram showing a fourth example of the “on / off drive means and pull switching means” portion common to the published prior application, first and second inventions. It is a circuit diagram showing one embodiment common to the published prior application and the first and second inventions. When connected to the Q terminal, H = G + 2: synchronous multi-value NOT means, and H> G + 2: synchronous “multi-value IN means or multi-value NOUT means”. When connected to the Q bar terminal, H = G + 2: synchronous multi-value EVEN means, H> G + 2: synchronous “multi-value NIN means or multi-value OUT means”. Published prior application common to the first and second inventions, “◆ When H = G: AND discriminating means, ◆ When H> G: AND / IN discriminating means” and “Binary synchronous flip-flop means” It is a circuit diagram which shows the 1st example of a "synchronization signal supply means." FIG. 5 is a circuit diagram showing a second example of the “AND discriminating means, binary synchronous flip-flop means and synchronizing signal supply means” common to the published prior application and the first and second inventions. It is a circuit diagram showing one embodiment common to the published prior application and the first and second inventions. When connected to the Q terminal and H = G: synchronous type / multi-value NAND means, and H> G: synchronous type “multi-value NAND / IN means or multi-value NAND / NOUT means”. When connected to the Q bar terminal, when H = G: synchronous multi-value EVEN means, when H> G: synchronous “multi-value AND / IN means or multi-value AND / NOUT means”. FIG. 5 is a circuit diagram showing a first example of a portion of an “OR discriminating means, binary synchronous flip-flop means, and synchronizing signal supply means” common to the published prior application, first and second inventions. It is a circuit diagram showing one embodiment common to the published prior application and the first and second inventions. When connected to the Q terminal and H = G: synchronous type / multi-value NOR means, and H> G: synchronous type “multi-value NOR / IN means or multi-value NOR / NOUT means”. When connected to the Q bar terminal and H = G: synchronous type / multi-value OR means, and H> G: synchronous type “multi-value OR / IN means or multi-value OR / NOUT means”. It is a circuit diagram showing one embodiment common to the published prior application and the first and second inventions. ◆ When connected to Q terminal: Synchronous type, multi-value EVEN means. ◆ When connected to Q bar terminal: Synchronous type, multi-value NOT means.

In order to describe the first to fourth inventions in more detail, these will be described below with reference to the accompanying drawings. The following 8 points of caution are stated first.
◆ 1) There are “explanations from the viewpoint of electronic circuits” and “explanations from the viewpoint of logic mathematics”, and there are also descriptions that are a mixture of both.
2) Each embodiment will be described mainly in the case where these constant potentials “go higher” in numerical order from the first constant potential to the Nth constant potential. (→→ Positive logic)
On the other hand, each example in the case where these constant potentials “become lower” is “each power source potential (corresponding to each of these constant potentials)” Each controllable switching means is replaced one by one with “controllable switching means in complementary relationship (eg, P-channel MOS • FET with respect to N-channel MOS • FET)” one by one. This corresponds to “an embodiment having a symmetrical relationship with respect to the voltage direction or the voltage polarity with respect to the original embodiment” in which the direction of each component having a voltage polarity (eg, diode) is reversed. (→→ Negative logic)
However, in that case, the multi-value logic function may be the same as or different from the original circuit.
3) In each embodiment, n corresponds to the aforementioned N (predetermined plural = multi-value number).
◆ 4) The integer m corresponds to “a specific integer common to input and output in which the input specific integer and the output specific integer are the same”, and “the output specific constant potential supply means (for example, the power supply line V _m ) described above. It is an integer corresponding to “specific constant potential for output (eg, specific power supply potential v _m )”. The relationship is “n−1 ≧ m ≧ 0”.
(5) The integer Cm (≠ m) is an integer other than the integer m among the “integers 0 to (n−1) used when the multi-value number N = n”.
6) Each of “V _G , V _H , V _m , V _Cm , V ₋₁ , V ₀ , V _{1 to} V _n−1 , V _n ” expressed in capital letter V is a power line, and lowercase letter v “V _G , v _H , v _m , v _Cm , v ₋₁ , v ₀ , v _{1 to} v _n−1 , v _n ” and the like expressed in the order of the potentials (= constant potential) of these power supply lines. s to represent the power supply potential _v -1 to v _n their power supply potential in this order becomes higher from _{v -1} to _{v n.} Of course, the power supply line V ₀ or other power supply line is “the main body of the circuit” or “the main body of the circuit device” or “the body of an automobile, motorcycle, bicycle, etc.” or “the hull of a ship” or “ "Body of hovercraft, etc. for two-purpose use" or "Body of airplane, helicopter, etc." or "Main body of space navigation, space station, etc." The potential of the main body, the vehicle body, the hull, and the celestial body becomes a reference potential such as a ground potential.
However, although one DC power supply or DC power supply means for supplying DC voltage is connected between each of “two power supply lines adjacent to each other at the level of the power supply potential”, it is not shown.
7) For example, diodes 10, 12, 35, 36, “a Zener diode pair in which two Zener diodes are connected in series in opposite directions” and the like, “the circuit configuration means itself, or connection of the circuit configuration means” "Means that there are cases where the connection or insertion / connection is present and not."
◆ 8) “Two gate terminals or common gate terminals of the transistors 41, 47, and 48 are drawn, and each gate terminal is connected to the Q terminal (positive output terminal) of the D-type flip-flop 27. , “Is connected to the Q bar terminal (complementary output terminal)”.
Naturally, “change in connection from the Q terminal to the Q bar terminal” or “change in connection from the Q bar terminal to the Q terminal” means that the circuit after the connection change is different from the circuit before the connection change. It logically becomes the negation circuit.
As a precaution, “Q bar” means a character in which a line is drawn on the letter Q.

The first embodiment shown in the upper side of FIG. 1 is one embodiment of the “multi-value NOT two-stage connection means based on the Fuji algebra” of the first invention, and two “synchronous or synchronous multi-value NOT means” are two stages. In the lower part of FIG. 1, one stage of “asynchronous or synchronous type multi-value EVEN means equivalent to the multi-value logical (or circuit)” of the first embodiment is shown. Yes.
However, regarding the equivalent relationship of both multi-value logic operations, if the number of synchronization types differs between the multi-value logic one-stage means and the multi-value logic two-stage connection means, the difference in the logic operation timing between the two is related to each synchronization action. Ignoring.
In the first embodiment of FIG. 1, each component corresponds to each component described above (paragraph number [0015]), and “n ≧ 3”, “n−1 ≧ m ≧ 0”, “n−” 1 ≧ Cm ≧ 0 ”and“ Cm ≠ m ”.
A) “Multi-value NOT means or multi-value synchronous NOT means” as described above (paragraph number [0015]) is “asynchronous or synchronous multi-value NOT means indicated by NOT (m) = m”. (Corresponding).
B) The integer m becomes “a specific integer common to the previous input and output”.
C) “Asynchronous or synchronous multi-value NOT means indicated by NOT (Cm) = Cm” described above (paragraph number [0015].) “Multi-value NOT means or multi-value” in the subsequent stage (= next stage) "Synchronous NOT means".
◆ d) The integer Cm is set to “a specific integer common to the subsequent input and output”.
E) The power line V _Cm is used as the specific constant potential supply means in the latter stage.
◆ f) The specific power supply potential v _Cm is set to the specific constant potential in the latter stage described above.
◆ g) The power supply line V _m is used as the above-mentioned specific constant potential supply means.
◆ h) The specific power source potential v _m is the above-mentioned specific constant potential in the previous stage.
I) “The resistance connected between the outlet means (eg, output terminal) of the multi-level NOT means in the previous stage and the power supply line _VCm ” is the first potential pulling means described above.
◆ j): the second potential pull means "exit means in the subsequent stage of the multi-level NOT means (eg. The output terminal) and a resistor connected between the power supply line V _m" is described above.
Each of Tin and Tout is an input terminal and an output terminal of the multi-value NOT two-stage connection means.
Specific circuit examples of the asynchronous / multi-value NOT means are shown in FIGS. 23 to 24, and specific circuit examples of the synchronous / multi-value NOT means are shown in FIGS. 32, 37 to 38, and 39 (Q-bar terminal connection). 41) (when Q-bar terminal is connected), FIG. 43, FIG. 46, and FIG. 52 (when Q-bar terminal is connected).

When the input logical values m and Cm and “other input logical values CCm” are input to the first embodiment on the upper side of FIG. 1 and the “multi-valued EVEN means shown on the lower side of FIG. 1” respectively, It can be seen that the multi-level logical operation is exactly the same.
Note that “n−1 ≧ CCm ≧ 0”, “CCm ≠ m”, and “CCm ≠ Cm”.
・ Tin = m →→ Tout = m
・ Tin = Cm →→ Tout = Cm
・ Tin = CCm →→ Tout = Cm
In addition, input logic values m and Cm and “other input logic values CCm” are respectively set in “conventional multi-value NOT two-stage connection means shown in the upper side of FIG. 2” and “multi-value EVEN means shown in the lower side of FIG. 2”. Even if it inputs, it turns out that both operate | move exactly the same in multi-value logic.
・ Tin = m →→ Tout = m
・ Tin = Cm →→ Tout = (Open output)
・ Tin = CCm →→ Tout = (Open output)
However, input logic values m and Cm and “other input logic values CCm” are input to “multi-value NOT two-stage connection means shown on the upper side of FIG. 3” and “multi-value EVEN means shown on the lower side of FIG. 3”, respectively. It can be seen that the two do not perform the same operation in terms of multivalued logic and are not equivalent in multivalued logic. Equivalence holds for the input logical values m and Cm, but no equivalence holds for the input logical value CCm.
・ Tin = m →→ Tout = m
・ Tin = Cm →→ Tout = Cm
Tin = CCm →→ FIG. 3 upper circuit: Tout = Cm, FIG. 3 lower circuit: Tout = m, not established.
From these facts, it can be seen that there is a unique action / effect unique to the first embodiment of the multi-value NOT two-stage connection means shown in the upper side of FIG. This unique action / effect lies not only in the first embodiment of FIG. 1 but also in the multi-value NOT two-stage connection means of the first invention.
While sneaking in, it is determined whether “the input numerical value is CCm or not” in the subsequent stage of “multi-value NOT two-stage connection means shown on the upper side of FIG. 3” and “multi-value EVEN means shown on the lower side of FIG. 3”. When a multi-value circuit having a numerical value discriminating means (for example, a numerical value discriminating circuit, a multi-value EVEN circuit, a multi-value AND circuit, a multi-value OR circuit, etc.) is connected, both are logically equivalent to each other. However, it is limited when the function / effect is exhibited.

1) From the above, in the case of the first embodiment shown in the upper side of FIG. 1, the multi-value NOT means in the preceding stage and the multi-value NOT means in the subsequent stage have different “specific values common to input and output”. Moreover, the “circuit operation and logic operation” of the multi-value NOT two-stage connection means is equivalent to “one stage of the multi-value EVEN means” if “time ignorance or timing delay is ignored”. The value can be changed from “common output / specific value to common input / output value / specific value in later stage”
(Effect 1)
◆ 2) Since the number of stages can be increased from one-stage multi-value logic means to multi-value logic means connected in two stages, “the signal propagation time can be positively delayed for time adjustment and operation timing adjustment. Effect 2)
However, this effect is also present in the “conventional multi-value NOT two-stage connection means shown on the upper side of FIG. 2”, but it is convenient because the number of options of the multi-value NOT means to be used increases. That is, it becomes possible to newly use a multi-value NOT means having different specific integers.
3) Furthermore, when both the preceding stage and the latter stage are synchronous, there are two timings for synchronous latching in the front and rear, so that the timing of the overall synchronous latching in a certain “multi-value circuit based on the Fuji algebra” It is convenient to use this multi-value NOT two-stage connection means when matching the two.
(Effect 3)
However, this effect is also present in the “conventional multi-value NOT two-stage connection means shown in the upper side of FIG. 2”, but it is convenient because the number of options of the multi-value NOT means to be used increases. That is, it becomes possible to newly use a multi-value NOT means having different specific integers.
For example, in either multi-value NOT two-stage connection means, there are the following four patterns.
A) Both the former stage and the latter stage are asynchronous.
B) The preceding stage is a synchronous type and the subsequent stage is an asynchronous type.
C) The front and rear stages are both synchronous.
D) The preceding stage is an asynchronous type and the subsequent stage is a synchronous type.
When the preceding stage and the subsequent stage are both synchronous, the opportunity for synchronous latching and the timing are increased by one to become two. There are times when it becomes more advantageous than “,” which is convenient.
4) Then, each DC power source (or each DC power source means) and each power line used by the multi-level NOT means in the preceding stage and the multi-level NOT means in the subsequent stage are “part or all of them”. Are different from each other, so that a plurality of multi-value logic means (or multi-value logic circuits) serving as loads for each multi-value DC power source can be "distributed to each DC power source" or "specific DC power source etc." You can freely choose how to use the power supply. (Effect 4)
In addition, in “each multi-value logic circuit based on the Fuji algebra”, regardless of whether it is an asynchronous type or a synchronous type, when changing the specific integer in the same type of multi-value logic circuit, the power supply or power line connected to the circuit is changed. There is an advantage that the specific integer can be changed only by changing.
For example, in a 10-value logic circuit, “a power supply circuit configuration in which at least nine DC power supplies (means) are connected in series in the same direction and ten power supply lines and power supply plates are taken out from each power supply terminal or each common power supply terminal”. It has become. At that time, it is good if at least nine DC power supplies (means) can be easily prepared. Usually, a DC-DC converter circuit is used for the remaining DC power supplies. In other words, it is conceivable to collect several loads on the large DC power supply. Alternatively, it may be possible to collect several loads separately in the several DC power supplies. That is, the load of the load can be applied to each DC power source.
Alternatively, when the at least nine DC power sources (means) can be easily and equally prepared, it is very convenient to distribute each load as evenly as possible to each DC power source.
◆ 5) Then, as an additional effect (→ paragraph number [0043]) later, as will be described in detail in FIG. 13, the multi-value NOT two-stage connection means of the first invention is “all regardless of the multi-value number N. Multi-valued logic circuit can be expressed and configured, and when used in a multi-valued complete circuit that uses a multi-valued AND circuit or the like as a complete system (for example, FIG. 21 described later), It is possible to provide a “multi-value complete circuit using a multi-value NOR circuit or the like as a complete system (for example, FIG. 13 described later)” having the same circuit function and logic function equivalently. In other words, the number of usable multi-value logic circuits increases, which is convenient. (Additional effect)
“Digital Digital Circuits Understandable”, p. 9 line 14 to p. "Complete system" on the first line of 10. Author: Keitaro Sekine, published by OHM Co., Ltd. on July 25, 1997. “Introduction to Logic Circuits”, p. 31 “(8) Complete system”. Author: Ryuji Hamabe, published by Morikita Publishing Co., Ltd. on September 28, 2001. "Multi-value information processing-Post binary electronics-", p. 16-p. 17 “completeness, complete system, complete” description. Author: Tatsuo Higuchi, Michitaka Kameyama, Shokodo published in June 1989.

The second embodiment shown in the upper side of FIG. 4 is one embodiment of the “multi-value NOT / EVEN two-stage connection means based on the Fuji algebra” of the second invention. Alternatively, two of the synchronous multi-value EVEN means are connected in two stages, and the lower part of FIG. 4 shows “asynchronous or multi-value logical (or circuit) equivalent to the second embodiment”. One stage of "synchronous" multi-value NOT means "is shown.
However, regarding the equivalent relationship of both multi-value logic operations, if the number of synchronization types differs between the multi-value logic one-stage means and the multi-value logic two-stage connection means, the difference in the logic operation timing between the two is related to each synchronization action. Ignoring.
In Example 2 of FIG. 4, each component corresponds to each component described above (paragraph numbers [0015, 0018]), and “n ≧ 3”, “n−1 ≧ m ≧ 0”, “ n-1 ≧ Cm ≧ 0 ”and“ Cm ≠ m ”.
A) "Multi-value NOT means or asynchronous multi-value NOT means indicated by NOT (m) = m" is the previous stage of "Multi-value NOT means or multi-value synchronous NOT" (paragraph numbers [0015, 0018]). Means (corresponds).
B) The integer m becomes “a specific integer common to the previous input and output”.
C) “Even (Cm) = Asynchronous or synchronous multi-value EVEN means indicated by Cm” described above (paragraph number [0015, 0018]). "Multi-level synchronous EVEN means".
◆ d) The integer Cm is set to “a specific integer common to the subsequent input and output”.
E) The power line V _Cm is used as the specific constant potential supply means in the latter stage.
◆ f) The specific power supply potential v _Cm is set to the specific constant potential in the latter stage described above.
◆ g) The power supply line V _m is used as the above-mentioned specific constant potential supply means.
◆ h) The specific power source potential v _m is the above-mentioned specific constant potential in the previous stage.
I) “The resistance connected between the outlet means (eg, output terminal) of the multi-level NOT means in the previous stage and the power supply line _VCm ” is the first potential pulling means described above.
◆ j): the second potential pull means "exit means in the subsequent stage of the multi-level EVEN means (eg. The output terminal) and a resistor connected between the power supply line V _m" is described above.
Each of Tin and Tout is an input terminal and an output terminal of the multi-value NOT / EVEN two-stage connection means.
Specific circuit examples of the asynchronous / multi-value NOT means are shown in FIGS. 23 to 24, and specific circuit examples of the asynchronous / multi-value EVEN means are shown in FIG. Further, specific circuit examples of the synchronous multi-value NOT means are shown in FIGS. 32, 37 to 38, FIG. 39 (when the Q bar terminal is connected), FIG. 41 (when the Q bar terminal is connected), FIGS. 52 (when Q-bar terminal is connected), FIG. 32 (when Q-bar terminal is connected), FIG. 37 (when Q-bar terminal is connected) to FIG. 38 (when Q-bar terminal is connected) ), FIG. 39, FIG. 41, FIG. 43 (when Q-bar terminal is connected), FIG. 46 (when Q-bar terminal is connected), and FIG.

When the input logical values m and Cm and “other input logical values CCm” are input to the embodiment 2 on the upper side of FIG. 4 and the “multi-value NOT means shown on the lower side of FIG. 4” respectively, It can be seen that the multi-level logical operation is exactly the same.
Note that “n−1 ≧ CCm ≧ 0”, “CCm ≠ m”, and “CCm ≠ Cm”.
・ Tin = m →→ Tout = Cm
・ Tin = Cm →→ Tout = m
・ Tin = CCm →→ Tout = m
Also, “conventional multi-value NOT / EVEN two-stage connection means shown on the upper side of FIG. 5” and “multi-value NOT means shown on the lower side of FIG. 5” are respectively input logic numerical values m and Cm and “other input logical numerical values CCm”. "", It can be seen that both perform the same operation in terms of multi-valued logic.
・ Tin = m →→ Tout = (open output)
・ Tin = Cm →→ Tout = m
・ Tin = CCm →→ Tout = m
However, the input logical values m and Cm and “other input logical values CCm” are assigned to the “multi-value NOT / EVEN two-stage connection means shown on the upper side of FIG. 6” and the “multi-value NOT means shown on the lower side of FIG. When input, it can be seen that the two do not perform the same operation in terms of multi-valued logic and are not equivalent in multi-valued logic. Equivalence holds for the input logical values m and Cm, but no equivalence holds for the input logical value CCm.
・ Tin = m →→ Tout = Cm
・ Tin = Cm →→ Tout = m
Tin = CCm →→ FIG. 6 upper circuit: Tout = m, FIG. 6 lower circuit: Tout = Cm.
From these facts, it can be seen that there is a unique action / effect unique to the second embodiment of the multi-value NOT / EVEN two-stage connection means shown in the upper side of FIG. This unique action / effect lies not only in the second embodiment of FIG. 4 but also in the second invention.
While staggering, “the multi-value NOT / EVEN two-stage connection means shown on the upper side of FIG. 6” and the “multi-value NOT means shown on the lower side of FIG. 6” are followed by “whether the input numerical value is CCm or not. When a multi-value circuit (for example, a numeric discriminator circuit, a multi-value EVEN circuit, a multi-value AND circuit, a multi-value OR circuit, etc.) having a numeric discriminating means for discriminating is connected, the two are logically equivalent to each other. However, it is limited when its action and effect are exhibited.

1) From the above, in the case of the second embodiment shown in the upper side of FIG. 4, the multi-value NOT means in the preceding stage and the multi-value EVEN means in the subsequent stage have different “specific values common to input and output”. Moreover, the “circuit operation and logic operation” of the multi-level NOT / EVEN two-stage connection means is equivalently equivalent to “one stage of the multi-value NOT means” if “time delay or timing delay is ignored”. The value can be changed from “common input / output / specific value to common / specific value for subsequent input / output”.
(Effect 1)
◆ 2) Since the number of stages can be increased from one-stage multi-value logic means to multi-value logic means connected in two stages, “the signal propagation time can be positively delayed for time adjustment and operation timing adjustment. Effect 2)
However, this effect is also present in the “conventional multi-value NOT / EVEN two-stage connection means shown on the upper side of FIG. 5”, but it is convenient because the number of options of the multi-value EVEN means to be used increases. That is, it becomes possible to newly use multi-value EVEN means whose specific integers are different.
3) Furthermore, when both the preceding stage and the latter stage are synchronous, there are two timings for synchronous latching in the front and rear, so that the timing of the overall synchronous latching in a certain “multi-value circuit based on the Fuji algebra” It is convenient to use this multi-value NOT / EVEN two-stage connection means when matching the two. (Effect 3)
However, this effect is also present in the “conventional multi-value NOT / EVEN two-stage connection means shown on the upper side of FIG. 5”. However, the number of options of the multi-value EVEN means to be used is increased, which is convenient. That is, it becomes possible to newly use multi-value EVEN means whose specific integers are different.
For example, in either of the multi-value NOT / EVEN two-stage connection means, there are the following four patterns.
A) Both the former stage and the latter stage are asynchronous.
B) The preceding stage is a synchronous type and the subsequent stage is an asynchronous type.
C) The front and rear stages are both synchronous.
D) The preceding stage is an asynchronous type and the subsequent stage is a synchronous type.
When both the preceding stage and the subsequent stage are synchronous, the opportunity for synchronous latching and the timing are increased by one to become two, so the synchronous type "multi-value NOT means or multi-value NOT circuit having only one opportunity and timing" There are times when it becomes more advantageous than “,” which is convenient.
4) Then, each DC power source (or each DC power source means) and each power line used by the multi-level NOT means in the preceding stage and the multi-level EVEN means in the subsequent stage are “part or all of them”. Are different from each other, so that a plurality of multi-value logic means (or multi-value logic circuits) serving as loads for each multi-value DC power source can be "distributed to each DC power source" or "specific DC power source etc." You can freely choose how to use the power supply. (Effect 4)
In addition, in “each multi-value logic circuit based on the Fuji algebra”, regardless of whether it is an asynchronous type or a synchronous type, when changing the specific integer in the same type of multi-value logic circuit, the power supply or power line connected to the circuit is changed. There is an advantage that the specific integer can be changed only by changing.
For example, in a 10-value logic circuit, “a power supply circuit configuration in which at least nine DC power supplies (means) are connected in series in the same direction and ten power supply lines and power supply plates are taken out from each power supply terminal or each common power supply terminal”. It has become. At that time, it is good if at least nine DC power supplies (means) can be easily prepared. Usually, a DC-DC converter circuit is used for the remaining DC power supplies. In other words, it is conceivable to collect several loads on the large DC power supply. Alternatively, it may be possible to collect several loads separately in the several DC power supplies. That is, the load of the load can be applied to each DC power source.
Alternatively, when the at least nine DC power sources (means) can be easily and equally prepared, it is very convenient to distribute each load as evenly as possible to each DC power source.

The third embodiment shown in the upper side of FIG. 7 is one embodiment of the “multi-value EVEN two-stage connection means based on the Fuji algebra” of the third invention, and two “synchronous or synchronous multi-value EVEN means” are two stages. In the lower part of FIG. 7, one stage of “asynchronous or synchronous multi-value EVEN means that is logically (or circuit-wise) equivalent to the third embodiment” is shown. Yes.
However, regarding the equivalent relationship of both multi-value logic operations, if the number of synchronization types differs between the multi-value logic one-stage means and the multi-value logic two-stage connection means, the difference in the logic operation timing between the two is related to each synchronization action. Ignoring.
In Example 3 of FIG. 7, each component corresponds to each component described above (paragraph number [0020]), and “n ≧ 3”, “n−1 ≧ m ≧ 0”, “n−” 1 ≧ Cm ≧ 0 ”and“ Cm ≠ m ”.
A) “Multi-valued EVEN means or multi-valued synchronous EVEN means” as described above (paragraph number [0020]) in “Asynchronous or synchronous multivalued EVEN means indicated by EVEN (m) = m” (Corresponding).
B) The integer m becomes “a specific integer common to the previous input and output”.
C) “Asynchronous or synchronous multi-value EVEN means indicated by EVEN (Cm) = Cm” described above (paragraph number [0020]). "Synchronous EVEN means".
◆ d) The integer Cm is set to “a specific integer common to the subsequent input and output”.
E) The power line V _Cm is used as the specific constant potential supply means in the latter stage.
◆ f) The specific power supply potential v _Cm is set to the specific constant potential in the latter stage described above.
◆ g) The power supply line V _m is used as the above-mentioned specific constant potential supply means.
◆ h) The specific power source potential v _m is the above-mentioned specific constant potential in the previous stage.
I) “The resistance connected between the outlet means (eg, output terminal) of the multi-level EVEN means in the previous stage and the power supply line _VCm ” is the first potential pulling means described above.
◆ j): the second potential pull means "exit means in the subsequent stage of the multi-level EVEN means (eg. The output terminal) and a resistor connected between the power supply line V _m" is described above.
Note that Tin and Tout are respectively an input terminal and an output terminal of the multi-value EVEN two-stage connection means.
FIG. 22 shows a specific circuit example of the asynchronous type / multi-value EVEN means, and FIG. 32 (when Q bar terminal is connected) and FIG. 37 (when Q bar terminal is connected). 38 (when Q bar terminal is connected), FIG. 39, FIG. 41, FIG. 43 (when Q bar terminal is connected), FIG. 46 (when Q bar terminal is connected), and FIG.

When the input logical values m and Cm and “other input logical values CCm” are input to the third embodiment on the upper side of FIG. 7 and the “multi-valued EVEN means shown on the lower side of FIG. 7” respectively, It can be seen that the multi-level logical operation is exactly the same.
Note that “n−1 ≧ CCm ≧ 0”, “CCm ≠ m”, and “CCm ≠ Cm”.
・ Tin = m →→ Tout = m
・ Tin = Cm →→ Tout = Cm
・ Tin = CCm →→ Tout = Cm
In addition, input logic values m and Cm and “other input logic values CCm” are respectively set in “conventional multi-value EVEN two-stage connection means shown on the upper side of FIG. 8” and “multi-value EVEN means shown on the lower side of FIG. Even if it inputs, it turns out that both operate | move exactly the same in multi-value logic.
・ Tin = m →→ Tout = m
・ Tin = Cm →→ Tout = (Open output)
・ Tin = CCm →→ Tout = (Open output)
However, input logical values m and Cm and “other input logical values CCm” are input to “multi-value EVEN two-stage connection means shown on the upper side of FIG. 9” and “multi-value EVEN means shown on the lower side of FIG. 9”, respectively. It can be seen that the two do not perform the same operation in terms of multivalued logic and are not equivalent in multivalued logic. Equivalence holds for the input logical values m and Cm, but no equivalence holds for the input logical value CCm.
・ Tin = m →→ Tout = m
・ Tin = Cm →→ Tout = Cm
Tin = CCm →→ FIG. 9 upper circuit: Tout = Cm, FIG. 9 lower circuit: Tout = m, not established.
From these facts, it can be seen that there is a unique action / effect unique to the third embodiment of the multi-value EVEN two-stage connection means shown in the upper side of FIG. This unique action / effect lies not only in the third embodiment shown in FIG.
While being staggered, it is determined whether “the input numerical value is CCm or not” in the subsequent stage of “multi-value EVEN two-stage connection means shown in the upper part of FIG. 9” and “multi-value EVEN means shown in the lower part of FIG. 9”. When a multi-value circuit having a numerical value discriminating means (eg, a numerical value discriminating circuit, a multi-value EVEN circuit, a multi-value AND circuit, a multi-value OR circuit, etc.) is connected, the two values are logically equivalent. However, it is limited when the function / effect is exhibited.

1) From the above, in the case of Example 3 shown in the upper part of FIG. 7, the “specific value common to input and output” is different between the multi-value EVEN means in the preceding stage and the multi-value EVEN means in the subsequent stage. Moreover, the “circuit operation and logic operation” of the multi-level EVEN two-stage connection means is equivalent to “one stage of the multi-value EVEN means” if it is “ignoring time delay or timing delay”. The value can be changed from “common output / specific value to common input / output value / specific value in later stage”.
(Effect 1)
◆ 2) Since the number of stages can be increased from one-stage multi-value logic means to multi-value logic means connected in two stages, “the signal propagation time can be positively delayed for time adjustment and operation timing adjustment. Effect 2)
However, this effect is also present in the “conventional multi-value EVEN two-stage connection means shown in the upper part of FIG. 8”, but it is convenient because the number of options of the multi-value EVEN means to be used increases. That is, it becomes possible to newly use multi-value EVEN means whose specific integers are different.
3) Furthermore, when both the preceding stage and the latter stage are synchronous, there are two timings for synchronous latching in the front and rear, so that the timing of the overall synchronous latching in a certain “multi-value circuit based on the Fuji algebra” It is convenient to use this multi-value EVEN two-stage connection means when matching. (Effect 3)
However, this effect is also present in the “conventional multi-value EVEN two-stage connection means shown in the upper part of FIG. 8”, but it is convenient because the number of options of the multi-value EVEN means to be used increases. That is, it becomes possible to newly use multi-value EVEN means whose specific integers are different.
For example, in any of the multi-value EVEN two-stage connection means, there are the following four patterns.
A) Both the former stage and the latter stage are asynchronous.
B) The preceding stage is a synchronous type and the subsequent stage is an asynchronous type.
C) The front and rear stages are both synchronous.
D) The preceding stage is an asynchronous type and the subsequent stage is a synchronous type.
When the preceding stage and the subsequent stage are both synchronous, the opportunity for synchronous latching and the timing are increased by one to become two. There are times when it becomes more advantageous than “,” which is convenient.
◆ 4) Then, each multi-value DC power source (or each DC power source means) and each power line used by the multi-level EVEN means in the preceding stage and the multi-level EVEN means in the subsequent stage are “part or all of them”. Are different from each other, so that a plurality of multi-value logic means (or multi-value logic circuits) serving as loads for each multi-value DC power source can be "distributed to each DC power source" or "specific DC power source etc." You can freely choose how to use the power supply. (Effect 4)
In addition, in “each multi-value logic circuit based on the Fuji algebra”, regardless of whether it is an asynchronous type or a synchronous type, when changing the specific integer in the same type of multi-value logic circuit, the power supply or power line connected to the circuit is changed. There is an advantage that the specific integer can be changed only by changing.
For example, in a 10-value logic circuit, “a power supply circuit configuration in which at least nine DC power supplies (means) are connected in series in the same direction and ten power supply lines and power supply plates are taken out from each power supply terminal or each common power supply terminal”. It has become. At that time, it is good if at least nine DC power supplies (means) can be easily prepared. Usually, a DC-DC converter circuit is used for the remaining DC power supplies. In other words, it is conceivable to collect several loads on the large DC power supply. Alternatively, it may be possible to collect several loads separately in the several DC power supplies. That is, the load of the load can be applied to each DC power source.
Alternatively, when the at least nine DC power sources (means) can be easily and equally prepared, it is very convenient to distribute each load as evenly as possible to each DC power source.

The fourth embodiment shown in the upper side of FIG. 10 is one embodiment of the “multi-value EVEN / NOT two-stage connection means based on the Fuji algebra” of the fourth invention. Alternatively, two of the synchronous multi-value NOT means are connected in two stages, and the lower side of FIG. 10 shows “asynchronous or multi-value logical (or circuit) equivalent to the fourth embodiment”. One stage of "synchronous" multi-value NOT means "is shown.
However, if the number of synchronization types differs between the multi-level one-stage means and the multi-level two-stage connection means with respect to the equivalent relationship between both multi-value logic operations, the difference in the logic operation timing between the two is ignored. ing.
In Example 4 of FIG. 10, each component corresponds to each component described above (paragraph numbers [0020, 0022]), and “n ≧ 3”, “n−1 ≧ m ≧ 0”, “ n-1 ≧ Cm ≧ 0 ”and“ Cm ≠ m ”.
◆ a) “Asynchronous or synchronous multi-valued EVEN means indicated by EVEN (m) = m” as described above (paragraph numbers [0020, 0022]). Means (corresponds).
B) The integer m becomes “a specific integer common to the previous input and output”.
C) “Asynchronous or synchronous multi-value NOT means indicated by NOT (Cm) = Cm” described above (paragraph numbers [0020, 0022]). "Multi-level synchronous NOT means".
◆ d) The integer Cm is set to “a specific integer common to the subsequent input and output”.
E) The power line V _Cm is used as the specific constant potential supply means in the latter stage.
◆ f) The specific power supply potential v _Cm is set to the specific constant potential in the latter stage described above.
◆ g) The power supply line V _m is used as the above-mentioned specific constant potential supply means.
◆ h) The specific power source potential v _m is the above-mentioned specific constant potential in the previous stage.
I) “The resistance connected between the outlet means (eg, output terminal) of the multi-level EVEN means in the previous stage and the power supply line _VCm ” is the first potential pulling means described above.
◆ j): the second potential pull means "exit means in the subsequent stage of the multi-level NOT means (eg. The output terminal) and a resistor connected between the power supply line V _m" is described above.
Each of Tin and Tout is an input terminal and an output terminal of the multi-level EVEN / NOT two-stage connection means.
FIG. 22 shows a specific circuit example of the asynchronous / multi-valued EVEN means, and FIGS. 23 to 24 show specific circuit examples of the asynchronous / multi-valued NOT means. Further, specific circuit examples of the synchronous multi-value EVEN means are shown in FIG. 32 (when Q bar terminal is connected), FIG. 37 (when Q bar terminal is connected) to FIG. 38 (when Q bar terminal is connected), FIG. 43 (when Q-bar terminal is connected), FIG. 46 (when Q-bar terminal is connected), and FIG. 52, specific circuit examples of the synchronous / multi-value NOT means are shown in FIGS. 32, 37 to 38, and 39 (Q 41 (when Q bar terminal is connected), FIG. 41 (when Q bar terminal is connected), FIG. 43, FIG. 46, and FIG. 52 (when Q bar terminal is connected).

When the input logical values m and Cm and “other input logical values CCm” are input to the fourth embodiment on the upper side of FIG. 10 and the “multi-value NOT means shown on the lower side of FIG. 10” respectively, It can be seen that the multi-level logical operation is exactly the same.
Note that “n−1 ≧ CCm ≧ 0”, “CCm ≠ m”, and “CCm ≠ Cm”.
・ Tin = m →→ Tout = Cm
・ Tin = Cm →→ Tout = m
・ Tin = CCm →→ Tout = m
Further, “conventional multi-value EVEN / NOT two-stage connection means shown in the upper part of FIG. 11” and “multi-value NOT means shown in the lower part of FIG. 11” are respectively input logic numerical values m and Cm and “other input logical numerical values CCm”. "", It can be seen that both perform the same operation in terms of multi-valued logic.
・ Tin = m →→ Tout = (open output)
・ Tin = Cm →→ Tout = m
・ Tin = CCm →→ Tout = m
However, input logic values m and Cm and “other input logic values CCm” are assigned to “multi-value EVEN / NOT two-stage connection means shown on the upper side of FIG. 12” and “multi-value NOT means shown on the lower side of FIG. 12”, respectively. When input, it can be seen that the two do not perform the same operation in terms of multi-valued logic and are not equivalent in multi-valued logic. Equivalence holds for the input logical values m and Cm, but no equivalence holds for the input logical value CCm.
・ Tin = m →→ Tout = Cm
・ Tin = Cm →→ Tout = m
Tin = CCm →→ FIG. 10 upper circuit: Tout = m, FIG. 10 lower circuit: Tout = Cm, not established.
From these facts, it can be seen that there is a unique action / effect unique to “Embodiment 4 of the multi-value EVEN / NOT two-stage connection means shown in the upper side of FIG. 10”. This unique action / effect lies not only in the fourth embodiment of FIG.
While staggering, “the multi-value EVEN / NOT two-stage connection means shown on the upper side of FIG. 12” and “multi-value NOT means shown on the lower side of FIG. 12” are followed by “whether the input numerical value is CCm or not. When a multi-value circuit (for example, a numeric discriminator circuit, a multi-value EVEN circuit, a multi-value AND circuit, a multi-value OR circuit, etc.) having a numeric discriminating means for discriminating is connected, the two are logically equivalent to each other. However, it is limited when its action and effect are exhibited.

1) From the above, in the case of Example 4 shown in the upper part of FIG. 10, the “specific value common to input and output” is different between the multi-value EVEN means in the preceding stage and the multi-value NOT means in the subsequent stage. Moreover, the “circuit operation and logic operation” of the multi-level EVEN / NOT two-stage connecting means is equivalent to “one stage of the multi-level NOT means” if “time delay or timing delay is ignored”. The value can be changed from “common input / output / specific value to common / specific value for subsequent input / output”.
(Effect 1)
◆ 2) Since the number of stages can be increased from one-stage multi-value logic means to multi-value logic means connected in two stages, “the signal propagation time can be positively delayed for time adjustment and operation timing adjustment. Effect 2)
However, this effect is also present in the “conventional multi-value EVEN / NOT two-stage connection means shown on the upper side of FIG. That is, it becomes possible to newly use a multi-value NOT means having different specific integers.
3) Furthermore, when both the preceding stage and the latter stage are synchronous, there are two timings for synchronous latching in the front and rear, so that the timing of the overall synchronous latching in a certain “multi-value circuit based on the Fuji algebra” It is convenient to use this multi-value EVEN / NOT two-stage connection means when matching the two. (Effect 3)
However, this effect is also present in the “conventional multi-value EVEN / NOT two-stage connection means shown on the upper side of FIG. That is, it becomes possible to newly use a multi-value NOT means having different specific integers.
For example, in either multi-value EVEN / NOT two-stage connection means, there are the following four patterns.
A) Both the former stage and the latter stage are asynchronous.
B) The preceding stage is a synchronous type and the subsequent stage is an asynchronous type.
C) The front and rear stages are both synchronous.
D) The preceding stage is an asynchronous type and the subsequent stage is a synchronous type.
When both the preceding stage and the subsequent stage are synchronous, the opportunity for synchronous latching and the timing are increased by one to become two, so the synchronous type "multi-value NOT means or multi-value NOT circuit having only one opportunity and timing" There are times when it becomes more advantageous than “,” which is convenient.
◆ 4) Then, each multi-value DC power source (or each DC power source means) and each power line used by the multi-value EVEN means in the preceding stage and the multi-value NOT means in the subsequent stage are “part or all of them”. Are different from each other, so that a plurality of multi-value logic means (or multi-value logic circuits) serving as loads for each multi-value DC power source can be "distributed to each DC power source" or "specific DC power source etc." You can freely choose how to use the power supply. (Effect 4)
In addition, in “each multi-value logic circuit based on the Fuji algebra”, regardless of whether it is an asynchronous type or a synchronous type, when changing the specific integer in the same type of multi-value logic circuit, the power supply or power line connected to the circuit is changed. There is an advantage that the specific integer can be changed only by changing.
For example, in a 10-value logic circuit, “a power supply circuit configuration in which at least nine DC power supplies (means) are connected in series in the same direction and ten power supply lines and power supply plates are taken out from each power supply terminal or each common power supply terminal”. It has become. At that time, it is good if at least nine DC power supplies (means) can be easily prepared. Usually, a DC-DC converter circuit is used for the remaining DC power supplies. In other words, it is conceivable to collect several loads on the large DC power supply. Alternatively, it may be possible to collect several loads separately in the several DC power supplies. That is, the load of the load can be applied to each DC power source.
Alternatively, when the at least nine DC power sources (means) can be easily and equally prepared, it is very convenient to distribute each load as evenly as possible to each DC power source.

■■ Application 1 of the first invention (5th invention) and additional effects ■■
The multi-value complete circuit shown in FIG. 13 is “a multi-value complete circuit shown in FIG. 21 described later,“ an equivalent circuit of a multi-value AND circuit in FIG. 14B ”described later” and “an equivalent circuit of the first embodiment in FIG. 1”. 22 is a circuit that is modified by applying an equivalent circuit of the multi-value complete circuit of FIG.
“Multi-valued complete circuit” is a feature that “all types of multi-valued logic circuits can be expressed and configured with only one to several basic / multi-valued logic circuits (→ complete system)”, “completeness (= In this sense, the inventor uses the term “multi-value complete circuit”.
In particular, a multi-valued logic system / circuit based on “Fuji algebra” has the characteristic of “completeness”, that is, “completeness” that does not use a “logic constant input circuit” as in the past. Moreover, “complete” in “Fuji algebra” is not related to the magnitude of the multi-value number N, and any number of multi-value logic circuits having different multi-value numbers N may be mixed. Details are in paragraph numbers [0083-0096].
"Complete" ⇒⇒ Completeness of Completeness
The multi-value complete circuit of FIG. 21 is an equivalent circuit of each of the multi-value complete circuits of FIGS. 15 and 17, and these three multi-value complete circuits and their “completeness, complete” will be described in detail later. To do.
→→ Paragraph number [0083 to 0096].
From here, the equivalence of both the multi-valued complete circuit of FIGS. 13 and 21 will be described. First, in the multi-value complete circuit of FIG. 21, each multi-value AND circuit is replaced by “the equivalent circuit of the multi-value AND circuit of FIG. 14 (b)” one by one while considering the specific integer value. Secondly, each combination of the “multi-valued OR circuit and the subsequent multi-valued NOT circuit” after the replacement is replaced one by one with the multi-valued NOR circuit. Thirdly, a specific integer value is assigned to each of the multi-level NOT two-stage connection circuits on the input side of the multi-level NOR circuit after the replacement, one by one for the equivalent circuit of the first embodiment of FIG. Applying it in consideration, it transforms into a multi-level EVEN circuit. Then, fourthly, the "conventional equivalent circuit of FIG. 11" is applied to each of the multi-level EVEN and NOT two-stage connection circuits on the input side of the multi-level NOR circuit, taking into account the specific integer value. Thus, the multi-level NOT circuit is transformed into one stage. As a result, it can be seen that the multi-value complete circuit of FIG. 13 can be derived from the multi-value complete circuit of FIG.
When comparing the multi-value complete circuit of FIG. 21 and the multi-value complete circuit of FIG. 13, the former is composed of a complete system centered on a multi-value AND circuit, whereas the latter is centered on a multi-value NOR circuit. It consists of a complete system. For this reason, whichever multi-value complete circuit is employed, the number of types of basic / multi-value logic circuits that can be used is increased, which is convenient. This effect is an example of the additional effect of the first invention.
“Digital Digital Circuits Understandable”, p. 9 line 14 to p. "Complete system" on the first line of 10. Author: Keitaro Sekine, published by OHM Co., Ltd. on July 25, 1997. “Introduction to Logic Circuits”, p. 31 “(8) Complete system”. Author: Ryuji Hamabe, published by Morikita Publishing Co., Ltd. on September 28, 2001. "Multi-value information processing-Post binary electronics-", p. 16-p. 17 “completeness, complete system, complete” description. Author: Tatsuo Higuchi, Michitaka Kameyama, Shokodo published in June 1989.

◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆
◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆◆
*** *** *** *** *** *** *** ***
◆◆◆ ＊＊＊＊＊＊＊＊＊ Finally, we will supplement the following. ＊＊＊＊＊＊＊＊＊ ◆◆◆
*** *** *** *** *** *** *** ***
●● 1) For convenience of explanation, it is called an input terminal and an output terminal (corresponding to the inlet means and outlet means described in claims 1 to 4, respectively), but it does not actually exist as a terminal, but a simple lead or electrode. In many cases. This is similar to what is called a transistor base terminal, base electrode, base lead, or simply base, for example.
●● 2) In each embodiment or each derivative embodiment thereof, with respect to “each NMOS having its back gate and source connected”, its back gate is not “its source” but “the lowest constant potential supply means of the circuit {example: It may be connected to the power line V ₀ or V ₋₁ } ”. Alternatively, it may be connected to other constant potential supply means whose potential is lower than its source potential. (Derived Example)
Further, in each embodiment or each derivative embodiment thereof, the back gate is not “its source” but “the highest constant potential supply means of the circuit {example: power supply line” for “each PMOS having its back gate and source connected” V _n−1 or V _n } ”. Alternatively, it may be connected to other constant potential supply means having a higher potential than the source potential. (Derived Example)
3) Instead of resistors 15, 20, 21, 26, 28, 62-64, 67, etc. in each embodiment or its derivatives, “junction FET with its gate and source directly connected or normally on The “type MOS • FET” or “the normally-off type MOS • FET with its drain and gate connected” can be used one by one as the resistance means. (Derived Example)
Furthermore, if there is no hindrance to the circuit operation, in each embodiment or each of its derivatives, a constant current diode instead of each resistor, “two constant current diodes connected in series in reverse direction”, current mirror One circuit or two-terminal constant current means can be used as the resistance means one by one. However, when using a constant current diode, constant current means, etc., pay attention to the voltage division ratio. (Derived Example)

●● 4) In each embodiment or each derivative embodiment thereof, instead of each diode, “bipolar transistor with its collector and base directly connected”, “junction FET with its drain and source directly connected”, “its drain and Bipolar mode SIT or GTBT with direct gate connection, “Normally-off type MOS FET with its gate, back gate and source connected” or “Between its drain and back gate, between its source and back gate, respectively. The normally-off type MOS FET having its back gate potential maintained and its drain and gate connected can be used one by one. (Derived Example)
●● 5) In each embodiment or each derivative embodiment, the level of each power supply potential is reversed, and each controllable switching means is set to “controllable switching means in a complementary relationship with it (for example, for N-channel type MOS • FETs). “P-channel MOS · FET)” one by one, and the direction of each component (eg, diode) having a voltage direction or voltage polarity is reversed. “Symmetrical with respect to the voltage direction or voltage polarity with respect to the original embodiment” Naturally, an “embodiment having a general relationship” is also possible. Each embodiment having this symmetric relationship corresponds to “a case where these constant potentials decrease in numerical order from the first constant potential to the Nth constant potential” in claim 1. However, in that case, since it corresponds to negative logic relative to positive logic, the multi-value logic function may be the same as or different from the original circuit. (Derived Example)
●● 6) In each embodiment or each derivative embodiment thereof, the power line V ₀ or another power line is “the main body of the circuit” or “the main body of the circuit device” or “the body of an automobile, motorcycle, bicycle, etc.” "Or" hulls such as ships "or" main bodies of amphibious hovercrafts "or" main bodies of flying means such as airplanes and helicopters "or" main bodies of space navigation means such as spacecraft and space stations / space drifting means " ”Or“ celestial bodies such as the Earth, the Moon, and Mars ”, etc., and the potential of the main body, the vehicle body, the hull, and the celestial body often becomes a reference potential of a large book such as a ground potential. However, although one DC power supply for supplying DC voltage is connected between each of “two power supply lines adjacent to each other at the level of the power supply potential”, it is not shown.

●● 7) Although “Beyond the CMOS” has been proposed, various new devices such as quantum devices have been proposed, but ☆☆☆ CMOS will also evolve! ! ! ☆☆☆ CMOS evolves toward 3D IC, multi-value, new concept computer (→→ paragraph number [0240-0245] described later)! ! !
One example thereof is “bidirectional switch combining transistors 3 and 5” or “bidirectional switching means combining transistors 3, 5, 22 to 25 (and diode 36)” in FIG. →→ The following Patent Document 10 (Japanese Patent Laid-Open No. 2006-252742).
Another example is the multi-valued memory of FIG. 15 of the following Patent Document 12 (Japanese Patent Laid-Open No. 2007-035233).
Moreover, even if a certain circuit does not have a complete CMOS structure, there is no problem if the power consumption of the entire circuit is fundamentally low. For example, even in the case of using a pull-up resistor or a pull-down resistor, in the circuit, “such as a MOS FET that pulls the pull-up (or pull-down) resistor in the ON state during operation” This is the case of a circuit in which the total number is always small and “the total number of MOS / FETs that are turned on / off during the operation is always small”. This is expected to be the case with an input / output pattern storage type decimal computer which will be described later. →→ Paragraph number [0240-00245].
On the other hand, despite the fact that the current CPU is a block of CMOS circuits, the total number of “MOS / FETs that are switched on and off at a high switching frequency” is extremely large. The current situation is that the CPUs are like heaters due to the "total switching loss including power loss due to power" and "total power loss due to charging / discharging of each gate-source capacitance". .
JP-A-2006-252742 (bidirectional switching means, multi-value buffer means, multi-value storage means) JP 2007-035233 (multi-value decoding means, multi-value information processing means, etc.)

●● 8) For normally-off type MOS FETs used in the present invention, the withstand voltage between the drain and the source and the withstand voltage between the gate and the source are kept to a certain level (when possible), while being off. If the on / off threshold voltage can be made smaller and smaller while keeping the leakage drain current of the device small, a 100-value (or 100-decimal) computer, and a 1000-value (or 1000-decimal) computer (!?) Also comes into view.
●● 9) Data input part (example: D terminal input part) of binary synchronous flip-flop means which is one constituent means of the first and second inventions of the prior application first and second inventions described later (paragraph numbers [0113 to 0237]) )) “If the input integer satisfies the requirement of the numerical discriminating means for determining whether the input integer is“ larger or not larger ”or“ smaller or smaller ”than the one input specific integer, the binary synchronization type Of course, the flip-flop means may also serve as the numerical value discrimination means.

◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆
◆◆◆
In the description of the present invention, paragraph numbers [0049 to 0112] for the “Fuji algebra” etc. just in case, so that the “Fuji algebra” which is not widely known can be handled in the same way as the common general knowledge. Will be described in detail.
After that, in paragraph numbers [0113 to 0237], “multi-value logic means and multi-value hazard removal means having a synchronous latching function” and the like will be described in detail so that they can be handled in the same manner as common technical knowledge.

◆◆◆ ＊＊＊＊ Explanation of new and multi-valued logic “Hooji algebra” ＊＊＊＊ ◆◆◆
***
◆◆◆ ＊＊＊＊ Expansion of the new-multi-
value-logic, "Hooji algebra" ****** ◆◆◆
***
●● 10) The multi-value logic circuit of the potential mode (or voltage mode) that is the basis of the first invention to the fourth invention is “a completely new world-first multi-value that the inventor originally conceived at the time of 2002. It is the embodiment of "logic". However, it is inconvenient if there is no name in the new multi-valued logic, so in 2010, I decided to name it “Hooji Algebra”.
The multi-value-logic-circuits of who the 1st to 4th present inventory are on the base, are circuits 'embodied and rearmed' fronted.
The new-multi-value-logic present inventor tho out out by himsel in the year 2002. And present inventor called the logic “Hooji algebra” in the year 2010.
Reference: JP 2010-149141 (application number in Japan).
In addition, in the multi-value-logic-circuits it is defined thateach 'electrical-potential or voltage' is
Generally, the definition is called 'electric-potential mode' or 'voltage mode'.

The reason for the name is “Because the inventor is Japanese, it is named after Mt. Fuji, the symbol of Japan.” (Even if it is combined) "and" Ability including its ambiguous (ambiguous) expression ability, possibility, practicality, expandability, future, etc. ) Is very large, tremendously large, and huge.} The present inventor strongly judges that it is, so that the language is aligned with the English huge. (Reference: Patent documents 1 to 3 below)
When deciding the name in English, “H” in the “Huge” spare, “oo” in the “Boole” spare, and “ji” in the “Fuji” spaer are combined into “Hooji”. did.
The three reasons why present inventor called the logic so, the the following.
(1) named from Mt. Fuji who is a symbol of Japan, because present inventor is a Japan.
→→ the spelling of 'ji' from the spelling of 'Fuji'.
(2) named a little from 'Boole' of Boolean Algebra.
→→ the spelling of 'oo' from the spelling of 'Bool'.
(3) named from the word of 'huge'.
Because present inventor strong judge shat “Hooji algebra” has some heavy strong points.
For example, 'the huge capabilities to include an ability to express ambiguity', the huge possibilities, the huge practicability, .
→→ the spelling of 'H' from the spelling of 'Huge'.
To unite 'H', 'oo' and 'ji', The spelling becomes “Hooji”.
→→ ◆ ● ◇ 'H' + 'oo' + 'ji' ⇒⇒ “Hooji”

JP 2004-032702 (Multi-valued logic circuit based on “Fuji algebra”) [Application date: March 10, 2003, Priority date: March 11, 2002, also May 7], (Deemed under).・ Reference patent no. 1: JP 2004-032702A / Application date: March 10, 2003. First priority date: March 11, 2002. Second priority date: May 7, 2002. Japanese Patent Application Laid-Open No. 2005-198226 (patent document 1 patent re-enlarged application, patent registration), Reference patent no. 2: JP2005-198226A JP-A-2005-236985 (improvement of patent document 2 patent registration), Reference patent no. 3: JP2005-236985A

The reason for this determination is that the multi-value logic circuit based on the new multi-value logic “Fuji algebra” is as follows: ““ No matter how many multi-value numbers N ”, the conventional multi-value logic circuit This is because there are a number of advantageous and unique effects (⇒ the world's first in 2002). However, there was an effect that was not noticed in 2002.
Speaking of the reasons for present inventor to judge so, because there are 'many advantageous special effects not to exist in any multi-value-logic-circuits of until now' in the new-multi-value-logic-circuits on the basis of the new-multi-value-logic, "Hooji Algebra", even if it's multi-value-number 'N' is any number.
The advantageous special effects are asmented bellow.

◆ a) When a binary circuit is connected to the preceding stage, the connectivity is extremely good, and no special interface (eg, binary multi-value code conversion means) is required between them. [Paragraph number 0104]
To have extremly good connectivity, 2-connecting a 2-the-circut at the pre-stage of the new-multi-valent-logic-cir- For example, a circuit for converting 2-value-code to multi-value-code.
For example, a circuit for converting 2-value-code to multi-value-code.
→→ minutely explained at 'paragraph number 0104'.

B) When a binary circuit is connected to the subsequent stage, the connectivity is extremely good, and no special interface (eg, multi-value binary code conversion means) is required between them. [Paragraph number 0105]
To have extremly good connectivity, 2-connecting a specific number of stages, and the number of stages in the future. For example, a circuit for converting multi-value-code to 2-value-code.
For example, a circuit for converting multi-value-code to 2-value-code.
→→ minutely explained at 'paragraph number 0105'.

C) As will be described later (paragraph numbers [0113 to 237]), the connectivity with the binary circuit is extremely good even during signal transmission in the multi-value logic circuit, and a special interface is provided between them. Not necessary. [Paragraph numbers 0151 to 0152]
To have extremely good connectivity, when insert-connecting a 2-value-circuit into one of the fixed places on the process of signal communiucation in the new-multi-value-logic-circuit, and to need no special interface between both the circuits .
→→ minutely explained at 'paragraph number 0151-0152'.

◆ d) Therefore, unlike the conventional multi-value circuit, the multi-value hazard can be removed as in the present invention without needing to convert to binary. [Paragraph number 0155]
For this reason, to be able to elicitate multi-value-hazards like presents the full-in-a-thir-d
→→ minutely explained at 'paragraph number 0155'.

E) Binary and Boolean algebra (non-inverted logic) AND logic, OR logic, NOT logic, NAND logic, NOR logic, and basic logic circuits are included and compatible. [Paragraph numbers 0080-0081]
To have compatibility with the 2-value-basic-logic-circuits on the basis of Boolean algorithm.
Thatis, the logic-circuits on the basis of “Hooji Algebra” include some logic-circuits on the basis of Boolean algorithm.
For example, each circuit of (NON-REVERSE-logic), AND-logic, OR-logic, NOT-logic, NAND-logic, and NOR-logic on the basis of Boolean algorithm.
→→ minutely explained at 'paragraph number 0080-0081'.

◆ f) Depending on the multi-value number N, there may be a case where a plurality of “same kind of basic / multi-value logic circuits with different specific integers” are used. “Connected power lines” are just different from each other, their basic configuration is exactly the same and compatible. [Paragraph numbers 0078 to 0079]
To have both 'compatibility' and 'completely same basic structure'
But 'each of the power-lines which connect all the logic-circuits to their power-sources' is different from each other, in case each specific integer of the logic-circuits is different from each other according to each multi-value-number 'N'.
→→ minutely explained at 'paragraph number 0078-0079'.

◆ g) Therefore, it is possible to assemble a synthesis / multi-value logic circuit having a large multi-value number N using a synthesis / multi-value logic circuit having a small multi-value number N as it is. [Paragraph number 0082]
For this reason, to beable to construct 'the synthetic multi-value-logic-circuits with the large multi-value-number' N '' on the thee.
Of course, in the cases, the large are satisfied with the truth table of the small.
→→ minutely explained at 'paragraph number 0082'.

◆ h) The multi-value number N can be changed very easily. [Paragraph number 0082]
To be extreme easy to change the multi-value-number 'N'.
→→ minutely explained at 'paragraph number 0082'.

◆ i) Have duality that “the duality is true”. [Paragraph numbers 0075 to 0077]
To have duality in the multi-value-logic.
→→ minutely explained at 'paragraph number 0075-0077'.

J) Regardless of the multi-value number N, all multi-value logic functions can be expressed by one type of multi-value logic circuit (complete system). ⇒⇒ Completeness, also “complete”. [Paragraph numbers 0083 to 0096]
To be able to express all the multi-value-logic-functions by using a kind of the multi-value-logic-circut (→ Complete System)
⇒⇒ 'Completeness', further 'Completeness of Completeness'.
***
→→ minutely explained at 'paragraph number 0083-0096'.

◆ k) It is very easy to “unitize or modularize” the basic or composite / multi-valued logic circuit. [Paragraph numbers 0078 to 0079, 0082]
To be so easy to make 'each circuit-unit or etch circuit-module' of 'each basic multi-value-logic-cyclic-fluidic-fluticulitic-citifici
→→ minutely explained at 'paragraph number 0078-0079, 0082'.

◆ l) Each of the multi-value numbers N (≧ 2) of the plurality of logical variables “..., X, y, z,. However, it must be flexible enough to respond flexibly without any problems. [Paragraph number 0103]
To have flexible adaptability to beable to adapt the multi-value-logic-logic-to-both the full logic-variables' ..., x, y, z,. , ...) 'with no probe at all, even if multi-value-number'N (≧ 2, includes 2)' of '..., x, y, z, ..., f (..., x, y, z, ...) 'is complete differential different from other.
→→ minutely explained at 'paragraph number 0103'.

◆ m) Since a multi-value wired OR circuit is formed in the same manner as a binary wired OR circuit, it is very advantageous in simplifying the entire circuit configuration and reducing the total number of parts. [Paragraph numbers 0097 to 0098]
To be very advantageous both 'when simplifying the whole circuit structure' and 'when decreasing total articles of the parts', as it is possible to construct multi-value-wired-OR-circuits as well as 2-value-wired-OR- circuits.
→→ minutely explained at 'paragraph number 0097-0098'.

N) It is possible to make (complete) circuit (3D) programmable logic array, semi-order (3D) IC / LSI, etc. [Paragraph numbers 0099 to 0102]
To be possible to construct '(3-dimensional) programmable-logic-arrays', '(3-dimensional) semi-ordered-ICs &LSIs', etc. who 'embody and realize'"Completeness of Completeness" -curcuits.
→→ minutely explained at 'paragraph number 00099 to 0102'.

◆ o) Eight new multi-valued logics created by the present inventor: “OVER logic, NOVER logic, UNDER logic, NUNDER logic, IN logic, NIN logic, OUT logic, “Ambiguity” can be easily and freely defined and expressed by using each multi-valued logic circuit such as “NOUT logic”. [Paragraph numbers 0238 to 0239]
To be 'freely, flexible and easy' ble to 'define and express'"ambiguity" by using ea who present inventor further created out.
The logics of the circuits are OVER-logic, NOVER-logic, UNDER-logic, NUNDER-logic, IN-logic, NIN-logic, OUT-logic, NOUT-logic, & c. .
The names are named from the golf terms in order to be easy for everyone to re-member.
→→ minutely explained at 'paragraph number 0238-0239'.

None of these multi-valued logic systems / circuits before the advent of “Fuji Algebra” had any distinctive advantageous effects or features.
For that reason, “New multi-valued logic 'Fuji algebra” is' the most faithful and orthodox expansion and extension of Boolean algebra to date 'and so far.' The present inventor believes that it is huge in any case such as ability, possibility, practicality, expandability, and future potential.
There are no 'multi-value-logic-system and it's circuits' to have' the conspicuously advantageous effects and characteristics.
For this reason, present inventor is thinking that the new-multi-value-logic, "Hooji Algebra" is the logic to have expanded Boolean algebra into the direction of multi-value 'most faithfully and most orthodoxly until now'.
Furter present inventor is thinking that all the following characteristics area huge.
'The abilities to include an expiry to express ambiguity', the possibilities, the practicality, the expirability, thec. .

The first major reason why multi-level computers have not been developed and developed as widely as binary computers until now is the first major reason: “In the case of binary, it becomes the foundation that firmly supports the binary circuit, and it is in practical use. There was a binary logic system that could withstand "Boolean algebra", but in the case of multivalued, there was no multivalued logic system that would firmly support multivalued circuits and withstand practical use. " The inventor believes that this is a body.
Present inventor thinks of the reasons why multi-value-computers have ben 'neigher put into the newly developed.
● The first big reason:
As against that there was the 2-value-logic-system'Boolean algebra 'to be able both' to become the foundation which firmly supports all 2-value-logic-circuits' and 'to endure their practical application' in case of the 2-value-computers,
there was no multi-value-logic-system to be able both 'to become the foundation which firmly supports all multi-value-logic-circuits' and 'to endure their practical application' in case of the multi-value-computers.
In addition, three-dimensional IC technology and “low voltage drive (= absolute value of on / off threshold voltage is small) and high withstand voltage technology” are particularly important, such as energy saving and cooling technology. It is also important.
Besides, the following technologies are specially important for the multi-value-computers.
(1) 3 dimension IC (includes LSI) technologies.
(2) compatible technologies of transformers' low-voltage-driving (= the small absolute value of it on-off threshold voltage.
(3) technologies to save energy for the multi-value-computers to consume.
(4) technologies to cool the multi-value-computers, and so on.

In order to become the basis of such a multi-valued computer, it is “compatible with binary logic,“ Boolean algebra ”and completely includes it”, and “the same kind of basics with different multi-valued numbers N from each other”・ Multi-valued logic circuits are compatible with each other, and the larger one of the multi-valued number N completely includes the smaller one. Further, “regardless of binary or multi-valued,“ the logical function and [part 1 “One or more logical variables]” can be used freely and flexibly without any influence regardless of the number of multi-values N (≧ 2), even if they are completely different from each other. The inventor believes that this is necessary.
In order what the multi-value-logic-system becomes the founding of the multi-value-computers like the fever, and the present inventor th
● The 1st function:
The multi-value-logic-system is compatible with the 2-value-logic-system 'Boulean algebra' and the former perfecties the tetrater.
● The 2nd function:
as regards all of 'the same kind of the plural basic multi-value-logic-circuits to have the different multi-value-number "N" each other', they are compatible each other, and the large of 'N' perfectly includes the smallr of 'N'.
Of course, the large is satisfied with the truth table of the small.
● The 3rd function:
The multi-value-logic-system can-free-and-full-and-it-and-the-of-the-the-life-and-the-of-the-of-the-of-the-the-lever-to-the-the-of-the-of-the-the-number] “any number of number” “N (≧ 2)” of the logic function and it's logic “a variable or variables” “. No problem at all even number the number 'N (≧ 2)' is complete differential with another.

By the way, the larger the multi-value number N, the more “the number of types of multi-valued logic functions that can be expressed”, that is, “the number of types of information processing that can be expressed” increases as described below. Furthermore, if the number of digits is also used, it will become super -... excessively explosive, and can easily exceed the "program memory type (= built-in type) computer type of information processing by programming" !! Therefore, for example, a new concept computer system that does not use a program on a 10-value / decimal computer becomes possible.
Changing the peaking, the large multi-value-number 'N' is, the more of the number of the kins of the number of the quotients, and the number of the quotients. kinds of the information-processing to beable to express' increases-exploively as following the number of the kinds.
In addition to the increasing of the multi-value-number 'N', the more 'the number of the numbers-the numbers of the numbers-the numbers of the numbers-the numbers of the numbers-the numbers of the numbers. of the kind of the information-processing 'increases -ultra-ultra-ultra-exploively as following the number of the kinds.
As the result, 'the New-Concept-Computing-Method not to use programs in 10value-Decimal-Computers for example' becomes possible, because the 'the number of the kinds of the information-processing' can easily exceed 'the number of the kinds of the information-processing who “the Computing-Method of Program-Memory-Type-type” can express by the programming.

◆◆ Examples of the number of types such as 10-valued logic functions ◆◆
However, the number of each (multi-valued) logical variable is two.
◆◆ for examples, the number of the kind of the 10-value-logic-function etc. ◇◇
But two variables to each multi-value-logic.
Andeach Chinese character means in Japan as following.
◆ 'value' means 'a value' or 'values'.
◆ 'digits' means 'a figure', 'a digit', 'figures' or 'digits'.
◆ 'Logical variable' means 'a logic-variable' or 'logic-variables'.
◆ 'Type' means 'a kind' or 'kinds'.
***
* 2 values, 1 digit, 2 logical variables →→ 4 to the power of 2 = 16 types 2value-1 figure-2 logic-variables →→
2 ⁴ kind = 16 kind
* 3 value 1 digit 2 logical variable →→ 9 to the power of 3, 19 = 683 types (= kinds)
= 3 ⁹ kinds
* 4 values, 1 digit, 2 logical variables →→ 4 to the 16th power / type ≒ 4,294,968,000 types = 4 ¹⁶ kinds
* 5 value 1 digit 2 logical variable →→ 5 to the 25th power / kind = 5 ²⁵ kinds
* 6 values, 1 digit, 2 logical variables →→ 6 to the 36th power, type = 6 ³⁶ kinds
* 7 value 1 digit 2 logical variable →→ 7 to the 49th power / kind = 7 ⁴⁹ kinds
* 8 values, 1 digit, 2 logical variables →→ 8 to the 64th power, type = 8 ⁶⁴ kinds
* 9 value 1 digit 2 logical variable →→ 9 to the power of 81, type = 9 ⁸¹ kinds
* 10 value 1 digit 2 logical variable →→ 10 to the 100th power / kind = 10 ¹⁰⁰ kinds
* 10-value 2-digit 2-logical variable-> 10 to the 10th power / kind = 10 ^10,000 kinds
* 10-value 3-digit 2-logical variable →→ 10 millionth power / kind = 10 ^1,000,000 kinds
* 10-value 4-digit 2-logical variable-> 10 to the ¹⁰⁰ millionth power / type = 10 ^100,000, kinds
* 10-value 5-digit 2-logical variable →→ 10 to the 10 billionth power / type = 10 ^{10,000,000,000} kinds
* 10-value 6-digit 2-logical variable →→ 10 to the power of 1 trillion / type = 10 ^{1,000,000,000,000} kinds
* 10-value 7-digit 2-logical variable →→ 10 to the power of 100 trillion / kind = 10 ^{100,000,000,000,000} kinds
* 10-value 8-digit 2-logical variable →→ 10 raised to 1K (= 10,000 trillion) / type 10value-8figures-2logic-variables →→
→→ 10 ^{10,000,000,000,000,000} kinds
Paragraph No. [0029 to 0033] of JP2007-035233.

Speaking correctly, it is the opposite of the above-mentioned “can be lightly exceeded (!!!!)”, and the number of multi-values N (≧ 2) is “the number of types of information processing by programming”. Can never exceed "the number of types of logical functions that can be expressed using the number of digits".
Exactly speaking, 'the number of the kinds of the information-processing by the programing' can not absolutely exceed 'the number of the kinds of the logic-function to be able to express both' by increasing its multi-value-number "N (≧ 2) ”and and by utilities of the number of the figures ', even if the multi-value-number'N (≧ 2)' is any number.

The reason is as follows. Also in “information processing by program”, the function content as the information processing means can be determined only from the entry / exit of the “data or information” regardless of the process of the information processing. In addition, both the “each input“ data or information ”” and the “individual information processing result” must be a combination of numbers! In other words, since it can be expressed by a truth table, the information processing content can never exceed “the number of types of logical functions that can be expressed by the truth table”.
Moreover, the number of types of “information created by programming, useful to humans, and actually used” does not seem to be as many as 10 to the 100th power.

◆◆◆ ＊＊＊＊＊＊ “Hooji Algebra” Duality ＊＊＊＊＊＊ ◆◆◆
***
●● 11) The new multivalued logic “Fuji algebra” that “a duality is established regardless of the multivalued number N”, “duality”, etc. will be described below.
"Fuji algebra" is "a binary Boolean algebra that has been expanded and expanded to multi-value faithfully to the present inventor and the present invention", so of course, its multi-value (specific value) NOT logic, multi-value (specific value) “Dual” holds for AND logic and multi-value (specific value) OR logic.
“Duality in Boolean algebra” means “in the identity of an arbitrary logic function composed of NOT logic, AND logic, or OR logic, swapping“ 1 ”and“ 0 ”on both sides, and simultaneously AND logic and OR logic Even if they are replaced, the identity holds. "
FIG. 14 shows that “theorem corresponding to each of the double negation theorem, de Morgan's theorem and duality theorem in Boolean algebra” holds in “Fuji algebra”.
***
“Introduction to Transistor Circuit Lecture 5: Digital Circuits”, p. 27-p. 31 “3-3 Boolean Algebra [1] Axiom [2] Theorem [3] Duality”, Supervision: Yoshifumi Amemiya, Norii Koshiba, Author: Kensuke Shimizu, Masatoshi Kazuwa (Masahiro), issued by Ohm Co., Ltd. on May 20, 1986.

First, an equivalent circuit of each of an OR circuit and an AND circuit already known in the Boolean algebra will be described.
★★ Equivalent circuit of OR circuit:
* From the double negation theorem "OR logic of A and B" = A + B
= “Double negation of (A + B)”
* From the de Morgan theorem "Double negation of (A + B)" = "Negation of (Negation of A) and (Negation of B)"
= "Negation of AND logic of (Negation of A) and (Negation of B)"
* Therefore,
“OR logic of A and B” = “Negation of AND logic of (Negation of A) and (Negation of B)” ……
………………………………………… Formula (1)
★★ Equivalent circuit of AND circuit:
* From the double-negative theorem "AND logic of A and B" = A · B
= "Double negation of A and B"
* From the de Morgan theorem "Double negation of A and B" = "Negation of {(Negation of A) + (Negation of B)}"
= "Negation of OR logic between (Negation of A) and (Negation of B)"
* Therefore,
“AND logic of A and B” = “Negation of OR logic of (Negation of A) and (Negation of B)” ……
………………………………………… Equation (2)
★ ◆ ★ Duality in Boolean Algebra;
In the equations (1) and (2), if “1” and “0” on both sides of the self are exchanged, and AND logic and OR logic are exchanged at the same time, they become identities of each other and duality is established.

★ ◆ ★ New multivalued logic [duality in Hooji algebra:
Next, based on the multi-value logic circuit of FIG. 14, “the duality is established regardless of the multi-value number N in the new multi-value logic [Hooji algebra]” and the like will be described.
Where m = a specific integer for input = a specific integer for output, v _m is “a potential corresponding to the specific integer m”, and v _Cm (≠ v _m ) is “a potential corresponding to an integer other than the specific integer m” or “which “Independent additional potential that does not correspond to an integer”, that is, “any potential as long as the multi-value AND, OR, and NOT circuits cannot determine that the input numerical value is the specific integer m”. Note that represents the power line of the power supply potential _{v m} in _{V m,} represents the power line of the power supply potential _{v Cm} at _{V Cm.}
“NOT (m) = m” is abbreviated input specific integer = output specific integer = m multi-value NOT circuit, “AND (m) = m” is abbreviated input specific integer = output specific A multi-value AND circuit with integer = m, and “OR (m) = m” is abbreviated to mean a specific integer for input = specific integer for output = m.
To be sure, the definitions of multi-value {specific value (= specific integer)} NOT logic, multi-value (specific value) AND logic, and multi-value (specific value) OR logic are as follows.
Multi-value NOT logic: “Open the output” when the input numerical value is equal to the specific integer m, otherwise output the specific integer m.
Multi-value AND logic: When all the input numerical values are equal to the specific integer m, the specific integer m is output. Otherwise, the output is released.
Multi-valued OR logic: When the at least one input numerical value is equal to the specific integer m, the specific integer m is output. Otherwise, the output is released.
In the equivalent circuit of the multi-valued OR (m) circuit of FIG. 14A, “when at least one of the input logical variables x and y is an integer m, the logical function f (x, y) outputs a specific integer m, while If not, the output is released ". Moreover, the value of m is a free value from a negative integer to a positive integer.
On the other hand, in the equivalent circuit of the multi-value AND (m) circuit of FIG. 14B, “when the input logic variables x and y are all integers m, the logic function f (x, y) outputs a specific integer m, Otherwise, the output is released ". Again, the value of m is a free value from a negative integer to a positive integer.
Moreover, since the multi-valued number N can be changed very easily as described in the paragraph (14) to be described later (paragraph number 0082), “new multi-valued logic [Fuji algebra] is at least double negated regardless of the multi-valued number N. Theorem, De Morgan theorem, and duality theorem hold ”.

◆◆◆ ＊＊＊＊＊ Easiness to change specific integers not affected by multi-valued number N ＊＊＊＊＊ ◆◆◆
***
●● 12) Multi-valued logic circuit based on “Fuji algebra” has no influence on the multi-valued number N at all [Easily change specific integer value m] and [Easily unitized or modularized circuit ( The following is a description of the two features of unique effects)]].
◆ Each embodiment of the EQUAL (or determination) circuit, AND circuit, OR circuit, NOT circuit, NAND circuit, NOR circuit and its derivatives disclosed in the following patent publications of Patent Documents 1, 2, and 3 In this case, when the output switch unit is bidirectional, the specific integer m is (n−2) ≧ m ≧ 1, but even if “m = n−1” or “m = 0”, There is no problem in terms of operation and logic operation, and the value of the specific integer m can be freely set in the range of (n−1) ≧ m ≧ 0. However, it is only necessary to change the potential supply means (for example, a power supply line) to be connected.
However, in the case of m = n−1, the potential v (n−1) [in the present invention, expressed as v _n−1 . Denoted by _{v n} in the potential vn [present invention over. ] Denoted by _{V n} denotes a power line Vn [present invention supplies. ] Or the like, or there is an extra function or component such as “determination based on the threshold voltage on the plus side”.
In the case of m = 0, denoted by _{v 0} is the potential v0 [present invention. ] Is represented by a potential v (−1) [in the present invention, v ₋₁ . ] Power supply line V (-1) [in the present invention, expressed as V- ₁ . Is necessary, or there is an extra function or component such as “determining based on the minus threshold voltage”.
Moreover, the specific integer m may take any value from the integer 0 to a positive integer. In any case, the value of the specific integer m can be freely changed simply by changing the “potential supply means to be connected (eg, power supply line)”.
For this reason, it is not necessary to consider the difference of the specific integer m between the same multi-valued logics, and the same circuit configuration can be maintained, so that the circuit can be “unitized or modularized” for each type of multi-valued logic. Become. (Unique effect)
☆☆ Example of circuit:
Asynchronous type multi-value EVEN circuit of FIG. 22 Each of FIGS. 23 to 24 Asynchronous type multi-value NOT {or NEVEN (Neven or Neven)} circuit.
Each of FIG. 25 to FIG. 26, FIG. 28, Asynchronous type, Multi-value AND circuit, Asynchronous type of FIG. 27, FIG. 29, Multi-value NAND circuit, Asynchronous type of FIG. 30, Multi-value OR circuit・ Multi-value NOR circuit
JP 2004-032702 (New multi-value logic circuit based on multi-value logic “Fuji algebra”) JP 2005-198226 (same as above) JP 2005-236985 (same as above)

Also, “IN circuit, OUT circuit, NIN (nin) circuit”, “NOUT” circuit, “IN circuit, UNDER circuit, NOVER circuit, NUNDER circuit”, “IN circuit, OUT circuit, NIN circuit, NOUT”, which will be described later (paragraph numbers 0173 to 0177). Even in the case of “circuit”, the integer can be freely set within the limited setting range of “one or two specific integers for input”. However, the potential supply means to be connected (for example, a power supply line or the like) is simply changed in the same manner.
Here too, it is not necessary to consider the difference of each specific integer m between the same multi-valued logics, and the same circuit configuration can be used, so the circuit can be “unitized or modularized” for each type of multi-valued logic. become. (Unique effect)
In addition, in each case, as described later (paragraph number 0082), it has a feature that “change of the multi-value number N is very easy”, and therefore “changeability of a specific integer” is also “ Unitization or modularization] ”is not affected at all by the multi-valued number N.

◆◆◆ ＊＊＊＊＊＊＊＊ “Fuji Algebra” including Boolean Algebra ********
***
●● 13) The fact that the new multi-valued logic “Hooji algebra” includes Boolean algebra of binary logic and is compatible will be described below.
The new multi-valued logic "Fuji algebra" is a Boolean algebra faithfully expanded and expanded to multi-values in the manner of the present inventor, completely including Boolean algebra, and compatible with Boolean algebra. .
For example, each output of a multi-value specific value EQUAL {or EVEN (even) or non-inverted} circuit having a specific integer value of 1, an AND circuit, an OR circuit, a NOT {or NEVEN (neven)} circuit, a NAND circuit, or a NOR circuit If the terminal is pulled down to the potential v ₀ of the power supply line V ₀ with a resistor and each input numerical value is limited to “1” and “0”, these multi-value logic circuits can use a binary / positive logic buffer (or The non-inverting circuit, the AND circuit, the OR circuit, the NOT circuit, the NAND circuit, and the NOR circuit perform the same logical operation and are compatible.
Each output of the multi-value specific value EQUAL {or EVEN (even) or non-inverted} circuit having a specific integer value of 0, an AND circuit, an OR circuit, a NOT {or NEVEN (neven)} circuit, a NAND circuit, and a NOR circuit By pulling up the terminal to the potential v ₁ of the power supply line V ₁ with a resistor and limiting each input numerical value to “1” and “0”, these multi-valued logic circuits can use binary / negative logic buffers ( (Or non-inverted) circuit, AND circuit, OR circuit, NOT circuit, NAND circuit, and NOR circuit have the same logical operation and are compatible.
On the other hand, a Boolean algebra composed of “AND circuit (= Min circuit), OR circuit (= Max circuit), inversion (complement circuit), literal circuit and cycling circuit” is expanded to multi-value. In the case of the conventional multi-valued logic circuit (Ukashevich type) that has been expanded, any multi-value circuit is a Boolean algebra with respect to the “invert circuit, literal circuit, and cycling circuit” that expands and expands the binary NOT circuit to multi-value. The binary NOT circuit is not included, and there is no compatibility.
Therefore, it goes without saying that the conventional multi-level NAND circuit and multi-level NOR circuit do not include a Boolean algebraic binary NAND circuit and a binary NOR circuit, and are not compatible at all.
* Reference: Non-Patent Document 3 p. 18-p. 20.
"Multi-valued information processing-post-binary electronics-", authors: Tatsuo Higuchi, Michitaka Kameyama, Shokodo in June 1989.

In addition, for example, in the 10-value logic circuit based on “Fuji algebra”, when the specific integer value for each input / output is common, “the AND circuit of the specific integer value 8 corresponding to the power supply potential v ₈ ” is “the potential of the power supply line V ₀ . The specific integer value is 8 because v ₀ is defined as corresponding to the integer 0, etc. “If the potential v ₇ of the power line V ₇ is defined as corresponding to the integer 0, etc. ”, The specific integer value is 1. In this case, a “binary AND compatible circuit based on a Boolean algebra” is formed between the power supply lines V ₇ and V ₈ , and an AND circuit based on “Fuji algebra” is a “binary AND circuit based on a Boolean algebra ( In particular, open drain type and open collector type) ”.
Similarly, if the power supply potential to turn from the power supply line V ₆ to the power supply line V ₁ is redefined as such and the corresponding integer 0, integer value corresponding to the potential v ₈ of the power supply line V ₈ below It becomes like this.
・ Power supply line V ₆ potential v ₆ →→ integer value 2
・ Power supply line V ₅ potential v ₅ →→ integer value 3
・ Power supply line V ₄ potential v ₄ →→ integer value 4
・ Power supply line V ₃ potential v ₃ →→ integer value 5
And potential of the power supply line _{V 2 v 2} →→ integer value 6
・ Power supply line V ₁ potential v ₁ →→ integer value 7
During these redefinitions, the circuit configuration of the electronic circuit has not changed or changed at all, and is completely the same.
This is because, in the case of various / multi-valued logic circuits based on “Fuji algebra”, as described above (paragraph numbers 0078 to 0079), the change of the specific integer m is “one or more connected to the multi-value logic circuit”. This is because it is only necessary to change the plurality of power supply lines.

◆◆◆ ＊＊＊＊＊＊＊＊＊＊＊ Easiness to change multi-value number N ＊＊＊＊＊＊＊＊＊＊ ◆◆◆◆
***
●● 14) About the unique effects and features of the new multi-valued logic “Hooji algebra” that “the multi-valued number N is very easy to change”:
As described above (paragraph numbers 0078 to 0079, 0081), since the specific integer m can be changed very easily, the multi-value number N can be changed very easily.
For example, in each basic / multi-value logic circuit such as an AND circuit, an OR circuit, a NOT circuit, etc., the same kind of basic / multi-value logic circuit groups having different multi-value numbers N are compatible with each other, and the multi-value number N The larger one includes the smaller one. This is because the multi-value number N can be obtained by adding “basic / multi-value logic circuit having the same basic configuration even if the specific integers are different (= only the power supply lines to be connected are different from each other)” as necessary. This can be easily changed.
Further, for example, if a combination / multi-value logic circuit is assembled with four values using a basic / multi-value logic circuit such as an AND circuit, OR circuit, NOT circuit, etc., if it is desired to change to five values, a potential supply means (eg: "One power supply and power line.)" And added the specific integer for input or the specific integer for output to "5" (that is, the power line to be connected, etc.) The multi-value number N can be changed very easily by simply adding a multi-value logic circuit or multi-value logic circuit unit or multi-value logic circuit module and making the necessary connections.
That is, it is possible to configure a “composite / multi-valued logic circuit with a large multi-value number N” as it is based on “a composite / multi-valued logic circuit with a small multi-value number N”.
***
On the other hand, in the case of a multi-value logic circuit based on “multi-valued logic such as Ukasevich's cocoon that expands / expands Boolean algebra to multi-value” as a conventional technique, binary NOT as described above (two previous paragraphs). Regarding “inverting circuits, literal circuits, and cycling circuits”, which are expanded and expanded to multi-valued circuits, not all multi-valued logic circuits include binary NOT circuits and are not interchangeable at all, and the multi-valued number N The same kind of basic / multi-valued logic circuits of different types cannot be included, and there is no compatibility.
For example, “a ternary inverting circuit and a quaternary inverting circuit”, “a ternary literal circuit and a quaternary literal circuit”, and “a ternary cycling circuit and a quaternary cycling circuit”. The same applies to other multivalued numbers.
For this reason, it is impossible to construct a “basic / multi-valued logic circuit with a large multi-value number” based on the “basic / multi-valued logic circuit with a small multi-valued number” as it is for these basic / multi-valued logic circuits. Of course, the same can be said for a multi-value NAND circuit and a multi-value NOR circuit to which these basic and multi-value logic circuits are applied.
As a result, it is possible to construct a “composite / multi-value logic circuit having a larger multi-value number” based on “a composite / multi-value logic circuit using at least one of these basic / multi-value logic circuits”. Since it is not possible to change the multi-value number N, it is extremely difficult. It is necessary to reassemble from scratch.

◆◆◆ ＊＊＊＊＊＊＊＊ Completeness of “Fuji Algebra”
***
●● 15) New multi-valued logic “Hooji Algebra” has a unique effect and feature of “completeness with one kind of multi-valued logic circuit that is completely unaffected by multi-valued number N, it is also [perfect]” Is described below. →→ Realization of multi-valued complete circuit.
As described above (paragraph numbers [0075 to 0077]), “multi-valued NAND logic or multi-valued NOR logic, one kind of multi-values”, etc. The perfection that can realize all multi-valued logic functions regardless of the multi-valued number N by [single] or [by combining a plurality of logics], and the effect / feature of [perfect] Algebra ”.
“Digital Digital Circuits Understandable”, p. 9 line 14 to p. "Complete system" on the first line of 10. Author: Keitaro Sekine, published by OHM Co., Ltd. on July 25, 1997. “Introduction to Logic Circuits”, p. 31 “(8) Complete system”. Author: Ryuji Hamabe, published by Morikita Publishing Co., Ltd. on September 28, 2001. "Multi-value information processing-Post binary electronics-", p. 16-p. 17 “completeness, complete system, complete” description. Author: Tatsuo Higuchi, Michitaka Kameyama, Shokodo published in June 1989.

Based on the composite / multi-valued logic circuit of FIG.
◆ However, in multi-level number N = 10 (10 decimal), the-specific integer m (= input specific integer = output for a particular integer) each Power line potential _{(eg: v 0 ~v 9,} v _C0 ˜v _C9 , v _C0 ≠ v ₀ , v _C1 ≠ v ₁ ,..., V _C8 ≠ v ₈ , v _C9 ≠ v ₉ , each integer m (= 0, 1, 2, .., 8, 9) are written, but the definition of each basic / multilevel logic circuit is as described above (first half of paragraph number 0132). Note that represent each power line of the power supply potential _v 0 to v ₉ at _V 0 ~V _9, represent the respective power line of the power supply potential _v C0 _{to v C9} in _V C0 _{~V C9.}
Also, as in the case of the binary logic circuit, “all the input terminals of the multi-level NAND circuit are connected and combined into one input terminal” or “the other input is left with one input terminal of the multi-level NAND circuit. If all the input terminals are connected to the power supply line or the like of the input specific potential v _m of the NAND circuit (= the power supply potential corresponding to the input specific integer m), the multi-level NAND circuit is “multi-level NOT. Circuit ".
★ Asynchronous multi-value NAND circuit of FIGS. 27 and 29 ★ Reference: Japanese Patent Application Laid-Open No. 2005-236985 ・ Multi-value (specific value) NAND circuit (3-input) of FIG.
Furthermore, the output terminal of the multi-level NAND circuit is pulled up or down with a resistor or the like to a power supply potential v _Cm (≠ v _m ) other than the input specific potential (= output specific potential) v _m of the NAND circuit If the “multi-level NOT circuit” is connected to the subsequent stage of the output terminal, the multi-level NAND circuit becomes a multi-level AND circuit.

◆ Or, as in the case of the binary logic circuit, “all the input terminals of the multi-value NOR circuit are connected to one input terminal” or “one other input terminal of the multi-value NOR circuit is left. The multi-value NOR circuit is “a multi-value NOT circuit” by connecting all of the input terminals to a power line of a power supply potential v _Cm (≠ v _m ) other than the input specific potential v _{m of the} NOR circuit. become.
★ Asynchronous type multi-value NOR circuit of FIG. 31 ★ Reference: JP 2005-236985 A Multi-value (specific value) NOR circuit of FIG.
◆ Then, the output terminal of the multi-value NOR circuit is pulled up or down with a resistor to a power supply potential v _Cm (≠ v _m ) other than the input specific potential (= output specific potential) v _m of the NOR circuit. If the “multi-value NOT circuit” is connected to the subsequent stage of the output terminal, the multi-value NOR circuit becomes a multi-value OR circuit.
In addition, as described above (FIG. 14 and paragraph numbers [0075 to 0077]), a multi-valued OR circuit can be constructed from a multi-valued OR circuit due to the feature of “duality of new multivalued logic“ Fuji algebra ””. Or, conversely, a multi-value OR circuit or the like can be constructed from a multi-value AND circuit.
Therefore, a multi-value NOR circuit, a multi-value AND circuit, a multi-value NOT circuit, and a multi-value NAND circuit are constructed from one type of multi-value NOR circuit, or a multi-value OR circuit and a multi-value AND circuit are constructed from one type of multi-value NAND circuit. A multi-value NOT circuit and a multi-value NOR circuit can be configured.
As a result, the new multi-valued logic “Fuji algebra” has the characteristic of “ease of changing the specific integer m, which is not influenced by the multi-valued number N at all” as described above (paragraph numbers [0078 to 0079]). It can be seen that the composite / multi-valued logic circuit of FIG. 15 can be configured with only one type of basic / multi-valued logic circuit based on the above.

Then, the synthesis / multi-value logic circuit of FIG. 15 is capable of realizing and realizing “all the multi-value logic functions represented by the truth table of the multi-value logic function f (x, y) shown in FIG. 16”. It is a complete circuit. However, FIG. 16 is considerably omitted and simplified for easy understanding.
The truth table of f (x, y) shown in FIG. 16 is obtained by rewriting the numerical pattern, that is, by rewriting the numerical value of each 升 (mass), all decimal numbers and two logical variables x and y. A multi-valued logic function (10 to the 100th power / various in total) can be expressed.
Because there are 10 numbers of integers “0-9” that can be taken by one square, and the total number of squares is 100, so the numerical patterns that 100 squares can take are all. (10 ways) × (10 ways) × …… ≪ << Product of 100 (10 ways) >> ≫ ………… (10 ways) × (10 ways) = 10 to the 100th power Because it becomes.
In addition, in the truth table of f (x, y) shown in FIG. 16, the N-ary / two logical variables are changed by changing the “multi-value number N” and “each of the logical variables x and y / the logical variable range”. Can express all / multi-valued logic functions. For example, 6 ≧ x ≧ 0, 6 ≧ y ≧ 0 in N = 7 octal system. In this case, there are a total of 7 cells in the x horizontal direction and 7 cells in the y vertical direction in FIG. 16, so the total number of cells is 49.・ It becomes a kind.
Japanese Unexamined Patent Application Publication No. 2007-035233 paragraph number [0030-0031] explains the number of types of multi-valued logic functions.

By the way, the item {D> in paragraph number [0093] described later. } "As the combination of each value of the input logic variables x and y can be expressed by a 2-input multi-value AND circuit", the combination of each value of the input logic variables x, y and z is 3 inputs. "A combination of input logic variables w, x, y, and z can be expressed by a 4-input multi-value AND circuit" and " The combination of the values of the input logical variables u, w, x, y, and z can be expressed by a multi-input AND circuit with five inputs, etc., and so on, according to the number of the input logical variables. By increasing or decreasing the number of inputs of the circuit, it is possible to cope with the increase or decrease of the number.
However, according to the increase or decrease in the number of input logical variables (the way the truth table is written changes), the “total number of cells in the corresponding truth table” also increases or decreases. It corresponds to the total number / increase / decrease of the squares of the truth table according to "."
For example, in the case of 6 inputs of 10-digit 1-digit input logical variables u, w, x, y, z, and a, the place of x is replaced with uwx and the place of y is replaced with yza in the truth table of FIG. . For this reason, the uwx horizontal direction becomes 1,000 squares of “numerical value 000 to 999”, and the yza vertical direction also becomes 1,000 squares of “numeric value 000 to 999”. The numerical pattern is 10 millionth power / kind = 10 ^1,000,000 kinds in total. Of course, at this time, each of the input logical variables u, w, x, y, z, and a represents an integer of 10 values and 1 digit. By this representation, the number of input logical variables is 6 The truth table can be represented by a truth table (although it is quite difficult from the total number of cells), and can be expressed by a vertical, horizontal, or simple mechanism.

Here, furthermore, the uwx can be replaced with x ₂ x ₁ x ₀ , and the x ₂ x ₁ x ₀ can represent the three digits of x. At this time, it can be interpreted that the input logical variable x is expressed by 10 values and 3 digits, or can be interpreted as expressed by 1000 values and 1 digit.
It may sound strange to say "1000 values represented by one digit", but we already have 16 values "0, 1, 2, ..., 8, 9, A, B, C, D, E. , F "is represented by one digit of 16 characters. “Numerical value 10 corresponds to A, numerical value 11 corresponds to B,..., Numerical value 14 corresponds to E, and numerical value 15 corresponds to F”. Similarly, if each numerical value of 10 to 999 is replaced with one character at a time, it can be expressed with one digit of 1000 values. On the other hand, in the case of 10-value 3-digit expression, the three characters x ₂ x ₁ x ₀ represent independent numbers, so if x ₂ x ₁ x ₀ is represented by one character, it is 10-digit 3-digit・ The meaning of expression is lost. Further, at least 1000 power supply potentials are required for 1000 values, but at least 10 are required for 10 values.
The remaining yza side can also replace the yza with y ₂ y ₁ y ₀ and express the three digits of y with this y ₂ y ₁ y ₀ . At this time, similarly, the input logical variable y can be interpreted as being expressed by 10 values and 3 digits, or can be interpreted as being expressed by 1000 values and 1 digit.
For this reason, if the synthesis / multi-value logic circuit of FIG. 15 is expressed by the truth table of the logic function f (x, y) shown in FIG. If it can be proved that the "value logic function" can be realized and embodied, the "completeness" of the multi-valued logic "Hooji Algebra", or "perfect", regardless of the number or number of digits of the logical variable. It will be proved.

The synthesis / multi-value logic circuit of FIG. 15 is one configuration example of “a circuit that can realize all the multi-value logic functions of two logic variables”, and most of the configuration means are indicated by dotted lines. Although not shown, it is as follows.
However, “NOT (m) = m” is a specific integer for input = specific integer for output = m, and “AND (m) = m” is a specific integer for input = specific integer for output = m. A multi-value AND circuit, “OR (m) = m” means a multi-value OR circuit in which a specific integer for input = a specific integer for output = m, respectively. In FIG. m (= 0, 1, 2,..., 8, 9) is written.
In FIG. 15, between the multi-value “OR (0) = 0” circuit and the multi-value “OR (9) = 9” circuit, the multi-value “OR (1) = 1” circuit to the multi-value “OR (8) ) = 8 ”circuit, and there are multi-value“ AND (0) = 0 ”circuit group (= circuits represented by“ AND (0) = 0 ”) and multi-value“ AND (9) = ”. 9 ”circuit group (= circuits represented by“ AND (9) = 9 ”/ all) are usually multi-value“ AND (1) = 1 ”circuit group to multi-value“ AND (8) = 8 ”. There are 8 circuit groups of circuit groups. Each multi-value “AND (...) =...” Circuit group is connected with a necessary number of multi-value “NOT (...) =.
In addition, again, the operations of the multi-value “OR (m) = m” circuit, multi-value “AND (m) = m” circuit, and multi-value “NOT (m) = m” circuit are as follows. Street.
Multi-value “OR (m) = m” circuit: outputs a specific integer m when at least one of a plurality of input numerical values is a specific integer m, and releases the output otherwise.
→→ Asynchronous multi-value OR circuit of FIG.
Multi-value “AND (m) = m” circuit: outputs a specific integer m when all of a plurality of input numerical values are a specific integer m, and releases the output otherwise.
→→ Each of FIG. 25 to FIG. 26, FIG. 28, Asynchronous type, Multi-value AND circuit ◆ Multi-value “NOT (m) = m” circuit: While one input numerical value is a specific integer m, the output is released, Otherwise, a specific integer m is output.
→→ Asynchronous / multi-valued NOT {or NEVEN (Neven or Neven)} circuits shown in FIGS.

■■ Rough explanation of circuit and function ■■
In FIG. 15, a specific integer value m (= 0, 1, 2,..., 8, 9) is written in each specific integer m, and the function of each circuit is as follows.
The multi-value “OR (m) = m” circuit group (drawing / vertically extending group; 10 circuits in total) is each integer m described in the truth table of f (x, y) shown in FIG. = 0, 1, ..., 8, 9 are output.
Accordingly, the number of multi-valued “OR (m) = m” circuits and the “number of types of integers described in the truth table of f (x, y) shown in FIG. 16” are the same. For this reason, if only 9 types of integers are described, there are only 9 circuits corresponding to the remaining 9 integers, excluding the integers not described. If there are 8 types, there are only 8 circuits. The same applies to the following, but for the sake of clarity, the description will be made assuming that m = 0 to 9.
◆ Multi-valued “OR (m) = m” circuit and multi-valued “AND (m) = m” belonging to the same multi-valued OR-AND-NOT circuit group (drawing / horizontal direction group in total 10 groups) Each value (= 0-9) of both m of the circuit is the same. Naturally, the number of groups and the total number of multi-valued “OR (m) = m” circuits are the same.
Each multi-value “AND (m) = m” circuit group (drawing / vertically extending group, m = 0 to 9) is “as per the relationship shown in the truth table of FIG. 16” f (x , Y) and each value of x, y are linked.
For this reason, the number of the logical variables and the number of input terminals of each multi-value “AND (m) = m” circuit are the same.
The number of “AND (m) = m” circuits belonging to each multi-valued OR-AND-NOT circuit group is “integer specific to the circuit group” in the truth table of f (x, y) shown in FIG. Is the same as the total number of cells that have written the value m ”.
Each multi-value “NOT (m) = m” circuit group (drawing / longitudinal group; m = 0 to 9) discriminates each value of x and y.
The reason for this is that the m value of each multi-value “AND (m) = m” circuit may be different from the “specific integer value m that should be originally compared when discriminating”. For this reason, the m value of each AND circuit and the m value of the “NOT circuit connected thereto” are necessarily different.
If both m values match, the multi-value “NOT (m) = m” circuit is unnecessary, and the multi-value “AND (m) = m” circuit directly determines the value of x or y. The input terminal Tx or the input terminal Ty is directly connected to the input part of the multi-value “AND (m) = m” circuit.
That is, when the value of f (x, y) and the value of x are the same m value, the multi-value “AND (m) = m” circuit directly determines the value of x, and the value of f (x, y) If the values of y and y are the same m value, the multi-value “AND (m) = m” circuit directly determines the y value.
◆ Pull-up resistor or pull-down resistor connected between each multi-value “AND (m) = m” circuit and each multi-value “OR (m) = m” circuit is the former. In order to make each output signal each input signal of the latter, both signals are matched. Each power supply potential has a relationship of v _C0 ≠ v ₀ , v _C1 ≠ v ₁ , v _C2 ≠ v ₂ ,..., V _C9 ≠ v ₉ , but each power line of the power supply potentials v _{0 to} v _9. the expressed as _V 0 ~V _9, it represents the respective power line of the power supply potential _v C0 _{to v C9} in _V C0 _{~V C9.}
◆ Pull-up resistors or pull-down resistors connected between each multi-value “NOT (m) = m” circuit and each multi-value “AND (m) = m” circuit are also the former. In order to make each output signal each input signal of the latter, both signals are matched.

■■ Details of each function are as follows. ■■
1) In the multi-value OR-AND-NOT circuit group in which the specific integer m = 0 of the multi-value OR circuit, the input part of the multi-value “OR (0) = 0” circuit is f (x, In the truth table of y), all cases where f (x, y) = 0 are satisfied are covered. Therefore, “the total number of cells in which m = 0 is written” = the total number of input terminals of the multi-value “OR (0) = 0” circuit (= the total number of multi-value “AND (0) = 0” circuits). .
It should be noted that both m values of “OR (m) = m” and “AND (m) = m” belonging to the same multi-valued OR-AND-NOT circuit group are the same, but each “NOT (m ) = M ”is always different from the m value.
Also, if there are only two “total cells in which m = 0” is written in the truth table, the number of input terminals of the multi-value “OR (0) = 0” circuit is also two. If there are a total of 70 “cells in which m = 0” are written, the number of input terminals is also 70.
2) Each multi-value “AND (0) = 0” circuit set to a specific integer m = 0 “each value / combination of logical variables x and y satisfying f (x, y) = 0” Cover it. In other words, each multi-value “AND (0) = 0” circuit has a one-to-one correspondence with “each combination of x value and y value of a square in which m = 0 is written”.
In the truth table of FIG. 16, each combination of (5, 0) and (8, 3) is illustrated, and f (5, 0) = 0 and f (8, 3) = 0.
In this way, each multi-value “AND (m) = m” circuit covers (returns) “each combination of values of logical variables x and y satisfying f (x, y) = m”.
◆ 3) Each “NOT (m) = m” circuit connected to the input terminal Tx determines the logical variable x = m (= 0, 1, 2,..., 8, 9) and connects to the input terminal Ty. Each “NOT (m) = m” circuit thus determined determines the logical variable y = m (= 0, 1, 2,..., 8, 9).
However, when the value of the logical variable x to be determined is the same as the m value of the multi-value “AND (m) = m” circuit, the multi-value “AND (m) = The “m” circuit directly determines whether the logical variable x = m.
For example, if the value of the logical variable x satisfying f (x, y) = 0 is 0 (that is, when the f value = x value), the “NOT (0) = 0” circuit is not necessary, so the input terminal Tx The potential signal is input as it is to the multi-value “AND (0) = 0” circuit.
If the value of the logical variable y satisfying f (x, y) = 0 is 0 (that is, when the f value = y value), the “NOT (0) = 0” circuit is not necessary, so that the input terminal Ty Since the potential signal is input to the multi-value “AND (0) = 0” circuit as it is, both are directly connected by a conducting wire as shown in FIG.
→→ When f (5,0) = 0, the input terminal Ty is directly connected to the second input terminal of the lowest multi-value “AND (0) = 0” circuit.
→→ Similarly, when f (7,9) = 9, the input terminal Ty is directly connected to the second input terminal of the lowest multi-value “AND (9) = 9” circuit.
◆ 4) Pull-up or “up or down” connected one by one between the multi-value “OR (0) = 0” circuit set to a specific integer m = 0 and each multi-value “AND (0) = 0” circuit A “down” resistor provides input / output signal matching. Therefore, the potential v _C0 ≠ v ₀ .
5) Each combination of “multi-value“ NOT (...) =... Circuit ”and pull /“ up or down ”resistance in the same circuit group is each potential signal of the input terminals Tx and Ty and each multi-value“ AND ”. (0) = 0 ”Match the input part of the circuit.
6) Similarly, each of the multi-value circuit groups (= multi-value OR, AND, and NOT circuit groups) set to “specific integer m = 1 to 9” has the same function. Fulfill.

The above is the case of the decimal system. However, in the case of the N-base system, the cell value = 0 is as described above, and only the above-mentioned “similar integers m = 1 to 9” are also used. It is simply changed to “each of the specific integers m = 1 to (N−1)” in the same manner.
***
As described above, the synthesis / multi-value logic circuit of FIG. 15 can realize and implement “all the multi-value logic functions represented by the truth table of f (x, y) shown in FIG. 16”.・ The "completeness" of the multi-valued logic "Fuji algebra" is proved. Moreover, since all the multi-valued logic functions can be realized and embodied by using only one basic / multi-valued logic circuit as described above (paragraph numbers 0084 to 0085) without using a “logic constant input circuit”.・ "Complete" of multi-valued logic "Fuji algebra" is proved.
★★ “Complete” of “Fuji Algebra” with only one type of basic / multi-valued logic circuit ★★
“Digital Digital Circuits Understandable”, p. 9 line 14 to p. "Complete system" on the first line of 10. Author: Keitaro Sekine, published by OHM Co., Ltd. on July 25, 1997. “Introduction to Logic Circuits”, p. 31 “(8) Complete system”. Author: Ryuji Hamabe, published by Morikita Publishing Co., Ltd. on September 28, 2001. "Multi-value information processing-Post binary electronics-", p. 16-p. 17 “completeness, complete system, complete” description. Author: Tatsuo Higuchi, Michitaka Kameyama, Shokodo published in June 1989.

■■ Configuration of the synthesis / multi-valued logic circuit shown in FIG.
As a precaution, the composition / individual logic circuit shown in FIG. 15 will be specifically described using the “simplified f (x, y) truth table” shown in FIG. However, the problems of maximum fan-in, maximum fan-out, current capacity, and multi-value hazard are ignored.
◆ b) Each of the squares in the truth table of f (x, y) shown in Fig. 16 is usually described as “each (specific integer value) f (x, y) = 0-9”. However, each multi-valued “OR (m) = m” circuit is prepared in which each specific integer value to be described is a specific integer m.
If there is a specific integer not described there, a multivalue “OR (m) = m” circuit of the specific integer not described, each multivalue “AND (m) = m”. The circuit and each multi-value “NOT (...) =...” Circuit connected to the previous stage of the “multi-value“ AND (m) = m ”circuit are unnecessary and can be omitted.
(B) In the truth table of f (x, y) shown in FIG. 16, when looking at an integer value of one cell, for example, a cell with f (x, y) = 0 set to an integer m = 0, Since there are two (since the illustration is simplified, there may be more cases in reality), the multi-value “OR (0 (0)) is set to a specific integer m = 0 in the multi-value“ OR (m) = m ”circuit. ) = 0 ”The number of input terminals of the circuit is set to two of the same number.
◆ C) Set the specific integer m = 0 in the multi-value “AND (m) = m” circuit by the same number as the number of input terminals of the multi-value “OR (0) = 0” circuit set to the specific integer m = 0. A multi-value “AND (0) = 0” circuit is prepared. Then, one multi-value “AND (0) = 0” circuit is connected to the preceding stage of the multi-value “OR (0) = 0” circuit one by one.
◆ D) At this time, the number of input terminals of each multi-value “AND (m) = m” circuit is 2 which is the same as the number 2 of logical variables x and y, but there are 3 logical variables x, y and z. If the number of input terminals is 3, the number of input terminals is 4 if there are four logical variables w, x, y, and z, and the logical variables are 5 of u, w, x, y, and z. If there is one, the number of input terminals is five. All that remains is to connect a multi-value “NOT (m) = m” circuit to each input terminal one by one.
Each multi-value “AND (m) = m” circuit has two input terminals as described in the above section d).

◆ e) each multi-level "the AND (0) = 0" set to a specific integer m = 0 potential _{v 0} the output terminal of the circuit (this time m = 0 So _v m _{= v} 0.) Other potential _{v C0} ( At this time, since m = 0, it is pulled up or pulled down to v _Cm = v _C0 . v _C0 ≠ v ₀ (v _Cm ≠ v _m ).
The potential v _Cm is “a potential corresponding to an integer other than the specific integer m” or “an independent additional potential that does not correspond to any integer, and the multi-value“ OR (m) = m ”circuit is set to the specific integer m. Any potential that is not discriminated can be used.
(F) Confirm each combination (5, 0), (8, 3) of the values of the logical variables x and y satisfying f (x, y) = 0 set to the integer m = 0 in FIG.
In general, each combination of the values of logical variables x and y satisfying f (x, y) = m is confirmed.
◆ G) For the first set (5, 0), between the input terminal Tx and the first input terminal of the first multi-value “AND (0) = 0” circuit (a specific integer m = 0 of AND) certain integer m = 5 multilevel "NOT (5) = 5" to (= logical variable value _{m x} of x) to connect the circuit, the multi-value "NOT (5) = 5" potential output terminal of the circuit to Pull “up or down” to v0 (v _m = v _{0 because} AND is a specific integer m = ₀ ).
On the other hand, in the case between the input terminal Ty and the second input terminal of the first multi-value “AND (0) = 0” circuit (where m = 0), the logical variable y value m _y = 0 and the AND Since the specific value m = 0 of the circuit is 0, the input terminal Ty is directly connected to the second input terminal of the first multi-value “AND (0) = 0” circuit as it is.
Of course, if the value m _y ≠ 0 of the logical variable y, as in the case of the input terminal Tx, between the input terminal Ty and its second input terminal, a multivalue “ NOT (...) =.
If there is a case where the value m _x = 0 of the logical variable x, the input terminal Tx remains as it is in the first multi-value “AND (0) = 0 as in the case where the value m _y = 0 of the logical variable y. Directly connected to the first input terminal of the circuit.

◆ H) For the second set (8, 3), specify between the input terminal Tx and the first input terminal of the second multi-value “AND (0) = 0” circuit (in this case, m = 0) integer m = 8 (= logical variable values of x _{m x)} to connect the multi-value "NOT (8) = 8" circuits, the multi-value "NOT (8) = 8" output terminal potential of the circuit _{v 0} Pull (up or down) to (v _m = v _{0 because} m = 0 at this time).
On the other hand, a specific integer m = 3 (= the value m _{y of the} logical variable _y ) between the input terminal Ty and the second input terminal of the second multi-value “AND (0) = 0” circuit (where m = 0). Multi-value “NOT (3) = 3” circuit is connected, and the output terminal of the multi-value “NOT (3) = 3” circuit is connected to potential v ₀ (since m = 0 at this time, v _m = v ₀ . Pull to “up or down”.
Of course, if there is a case where the value m _x = 0 of the logical variable x or the value m _y = 0 of the logical variable y, the direct connection work is performed in the same manner as the connection work in the above item ( _g ).
◆ Re) If Yes to other combinations of the values _m x, _{m y} logical variables x and y which satisfies f (x, y) = 0 in the truth table of f (x, y) shown in FIG. 16 If necessary, the connection work in the above item (vi) or item (v) is repeated for the number of combinations.
◆ N) Similarly, for the integer of “f (x, y) = 1 to 9” in the truth table of f (x, y) shown in FIG. Instead of m = 0, the specific integers m = 1 to 9 are set, respectively, and the connection work of “above ◆ b) to above ◆ re)” is repeated.
◆ Le) The above is the case of the decimal system, but in the case of the N-base system, the above “f (x, y) = 1 to 9” is replaced with “f (x, y) = 1 to (N− 1) "etc.
The connection work is completed.

Then, in the synthesis / multi-value logic circuit of FIG. 15, each multi-value “OR (m) = m” circuit and each multi-value “AND (m) = m” circuit are simultaneously multi-value “NAND (m) = Multi-value equivalent circuits are possible, one by one replaced with the “m” circuit. Of course, each integer value of m is set to each integer value shown in FIG. 15, and each number of input terminals is also set to each number of input terminals shown in FIG.
The reason why it becomes an equivalent circuit is that each of the multi-value “OR (m) = m” circuits in FIG. 15 is one by one with the equivalent circuit of the multi-value “OR (m) = m” circuit in FIG. The multi-value “NAND (m)” is replaced with each of the “multi-value“ AND (m) = m ”circuit and the multi-value“ NOT (m) = m ”circuit connected to the subsequent stage” after the replacement. This is because the above-described multi-value equivalent circuit is obtained by replacing one by one with the “= m” circuit.
Further, as described above (paragraph numbers [0084 to 0085]), each multi-value “NOT (m) = m” circuit in FIG. 15 is “combined all input terminals and combined into one input terminal”. If one multi-value “NAND (m) = m” circuit ”is replaced one by one, the above multi-value equivalent circuit, that is, the synthesis / multi-value logic circuit of FIG. It can be seen that it can be configured. In this case, a “logic constant input circuit” is not necessary.
In addition, as described above (in paragraph number [0086]), by changing each of the logical variables x and y and the logical variable range, it is possible to express all N-ary, two logical variables and multi-valued logical functions, The number of logical variables can be changed as in [0087] and [0093], or the number of digits of each of the logical variables x and y can be changed to 3 digits.
That's why the new multi-valued logic “Hooji Algebra” has a unique effect and feature of “completeness of one kind of multi-valued logic that is completely unaffected by the multi-valued number N, it is also [perfect]” There is.
◆ ↑ Only one type of basic / multi-valued logic circuit that is not affected by the multi-value number N at all ↑ ◆
◆ ↑ “Complete” of new multivalued logic “Hooji algebra” by ↑ ◆
“Digital Digital Circuits Understandable”, p. 9 line 14 to p. "Complete system" on the first line of 10. Author: Keitaro Sekine, published by OHM Co., Ltd. on July 25, 1997. “Introduction to Logic Circuits”, p. 31 “(8) Complete system”. Author: Ryuji Hamabe, published by Morikita Publishing Co., Ltd. on September 28, 2001. "Multi-value information processing-Post binary electronics-", p. 16-p. 17 “completeness, complete system, complete” description. Author: Tatsuo Higuchi, Michitaka Kameyama, Shokodo published in June 1989.

◆◆◆ ＊＊＊＊＊ Multi-value wired OR circuit in “Fuji algebra” ********
***
●● 16) A description will be given of the fact that a multi-value wired OR circuit is realized in a multi-value logic circuit based on the new multi-value logic “Hooji algebra”.
First, FIG. 17 shows a synthesis / multi-value logic circuit (= complete circuit) in which a multi-value wired OR circuit is introduced into the synthesis / multi-value logic circuit (= complete circuit) of FIG. Of course, the latter circuit configuration is considerably simpler than the former circuit configuration, and the number of components is correspondingly reduced.
In the synthesis / multi-value logic circuit of FIG. 17, the pull-up resistor and the pull-down resistor are not connected to the output terminal Tf because the output switch part of one of the AND circuits is always turned on and output. This is because the potential of the terminal Tf is pulled up or pulled down, so that the pull-up resistor and the pull-down resistor can be omitted.
→→ Power consumption by each pull resistor.
In addition, if there is at least one cell in which no numerical value is entered in the truth table of FIG. 16, the output terminal Tf is opened at the x value and y value of the cell, so that a pull-up resistor or Attach one end of the pull-down resistor to the output terminal Tf, required there to connect the other end to a predetermined power supply line V _Cm.
The composite / multi-valued logic circuit of FIG. 17 satisfies the truth table of FIG. 16 in the same manner as the composite / multi-valued logic circuit of FIG. 15. Specifically, the x-value, y-value, f (x, y) If each integer value is applied to the synthesis / multi-value logic circuit of FIG. However, if simply considered, “each AND circuit of the synthesis / multi-value logic circuit of FIG. 15 outputs the output numerical value to the output terminal Tf via each OR circuit”, whereas “the synthesis / multiplication logic circuit of FIG. The only difference is that each AND circuit of the multi-value logic circuit outputs its output value directly to the output terminal Tf.

Then, in addition to the problem of the circuit configuration and the number of parts, the composite / multi-value logic circuit of FIG. 15 has a “problem to be solved” that is “very inconvenient and impractical”. The synthesis / multi-valued logic circuit of FIG. 17 using a circuit can solve the problem.
◆ Example 1: In the truth table of FIG. 16, there are a total of 80 squares whose integer value is 6, for example, and there are 2 or 3 squares of integer values 0 to 5 and 7 to 9 other than 6. The total number of input terminals of the multi-value “OR (6) = 6” circuit is 80. The others are two or three.
◆ Example 2: In the truth table of FIG. 16, when the number of squares each having an integer value of m = 0 to 9 is uniformly about 10, each multi-value “OR (m) = m” circuit The total number of input terminals is about 10 uniformly.
***
In short, depending on the numerical pattern of the truth table of FIG. 16, that is, depending on how many squares of the same integer value are present, the total number of input terminals of each multi-value “OR (m) = m” circuit varies. In addition, if the integer value m to be written is shifted, the total number of input terminals of the specific multi-value “OR (m) = m” circuit is particularly increased.
As a result, it is very inconvenient and not practical when the multi-value logic function shown in the truth table of FIG. 16 is embodied and realized as a synthesis / multi-value logic circuit.
On the other hand, since the composite / multi-value logic circuit of FIG. 17 uses a multi-value wired OR circuit, “each multi-value“ OR (m) whose number of input terminals varies depending on the numerical pattern of the truth table of FIG. = M ”circuit itself” does not exist, and therefore the synthesis / multi-valued logic circuit of FIG. In addition, as described above, the synthesis / multi-value logic circuit of FIG. 17 has a simpler circuit configuration and a smaller number of parts than the synthesis / multi-value logic circuit of FIG. Convenient.
These are the relationship between “the synthesis / multi-value logic circuit (multi-value number N = 3) in FIG. 18 and the truth table in FIG. 19” described later, and its development / derivation circuit (multi-value number N = 4). The same applies to the relationship of 5, 6,.

◆◆◆ ＊＊＊＊＊ “Complete” circuit (three-dimensional) IC / LSI, etc. *****＊＊ ◆◆◆◆
***
●● 17) Explain that “complete” circuits (three-dimensional) programmable logic arrays, semi-order (three-dimensional) ICs and LSIs, etc. are possible.
The composite / multi-valued logic circuit of FIG. 18 is “in the composite / multi-valued logic circuit of FIG. 15, the multi-value number of both logical variables x and y is changed from 10 to 3, and three multi-value“ OR (m) ” = M ”A circuit configuration is simplified and standardized by using a multi-value wired OR circuit instead of the circuit (m = 0, 1, 2)”.
Note that since any one of the plurality of AND circuits is always on, connection of a pull-up resistor or a pull-down resistor can be omitted. That is, there is no need to connect it. →→ Power saving.
This facilitates implementation of (three-dimensional) programmable logic array and semi-order (three-dimensional) IC / LSI, which is convenient.
◆◆ Usefulness of multi-value wired OR circuit ◆◆
FIG. 19 is a truth table / diagram of the function f (x, y) = m _z in FIG.
X = 0, 1, 2
◆ y = 0, 1, 2
◆ f (x, y) = m _z , (m _z = m0, m1,..., M7, m8)
f (0,0) = m0, f (0,1) = m1, f (0,2) = m2
f (1, 0) = m3, f (1,1) = m4, f (1,2) = m5
f (2,0) = m6, f (2,1) = m7, f (2,2) = m8
However, 2 ≧ m0, m1, m2, m3, m4, m5, m6, m7, m8 ≧ 0

Since each integer value of m0 to m8 is one of 0, 1, and 2, m0 has three values, m1 has three values,..., m8 has three values. “Types of multi-valued logical function f (x, y) that can be expressed in all of these” = (3 types) × (3 types) × (3 types) × (3 types) × (3 types) × (3 types) × There are (3 ways) × (3 ways) × (3 ways) = 3 to the 9th power and types = 19,683 types.
Then, in FIG. 18, one “simple conductor” is drawn next to each multi-value “NOT (m) = m” circuit, and each multi-value “AND (m _z ) = The “m _z ” circuit / input section is connected via each / multi-valued “NOT (m) = m” circuit and may be directly connected by “each connecting terminal and each dotted line”. Has been.
In FIG. 19, when the value m _x (any one of 0, 1, 2) of the logical variable x and the value m _{z of the} multi-valued logical function f (x, y) are the same (m _x = m _z ), The input terminal Tx is directly connected to “a first input terminal of a multi-value“ AND (m _z ) = m _z ”circuit whose m _z is a specific integer”.
On the other hand, when the value _{m z} of logical variables x values _{m x} and the multi-level logic function f (x, y) is different from _{(m x} ≠ _{m z),} the multi-level "NOT (m as the input terminal Tx 18 _x ) = m _x ”circuit is connected to“ a first input terminal of a multi-value “AND (m _z ) = m _z ” circuit whose m _z is a specific integer ”.
Similarly, the connection between the input terminal Ty and the second input terminal of each multi-value “AND (m _z ) = m _z ” circuit is also connected via the multi-value “NOT (m _y ) = m _y ” circuit. Or connected directly. However, _{m y} is the value of a logical variable y, of 0,1,2 is any one.

If the integer values m0 to m8 are sequentially set to integers 0 to 8, the synthesis / multi-value logic circuit of FIG. 18 becomes a ternary / 9-value code conversion circuit. Of course, y is the first digit of the ternary representation and x is the second digit of the ternary representation. In this case, the specific potential supply means of the “AND (0) = 0” circuit is, for example, the power supply line V ₀ , the specific potential supply means of the “AND (1) = 1” circuit is, for example, the power supply line V ₁ ,. The specific potential supply means of the “AND (9) = 9” circuit is, for example, the power supply line V ₉ .
In addition, the multi-value number of each of the three logical variables x and y and the three multi-value logic functions f (x, y) can be freely set. All / multi-value numbers may be set to the same value, or each / multi-value number may be set to a different value.
Further, when the three multi-value numbers N are the same and are 4, the “types of multi-valued logic function f (x, y) that can be expressed” are 4 16 · type≈4,294,968,000 types. . Moreover, such a large type of multi-value logic function is “a multi-value [AND (...) =...] Circuit, two multi-value [NOT (...) =. The number of combinations of “and two conductors” is increased from 9 to 16 and the power supply and the power line are increased one by one as the multi-value increases by one ”.
Similarly, when the same multi-value number is 5, the “type of multi-valued logical function f (x, y) that can be expressed” is 5 to the 25th power and the kind≈2.980233 × (10 to the 17th power), In the synthesis / multi-valued logic circuit of FIG. 18, the above-mentioned combinations need only be increased from 16 sets to 25 sets.
Similarly, when the same multi-value number is 10, the “type of multi-valued logic function f (x, y) that can be expressed” is 10 to the 100th power / type. It is only necessary to increase the number from 25 to 100.
For this reason, the “number of types of multi-valued logic functions f (x, y) that can be expressed” increases with an increase in the same multi-value number N for a small number of parts.
* Reference: Paragraph number [0031 to 0033] of JP-A-2007-035233.
In addition, as will be described later (paragraph number 0103), each of the multi-value numbers of the logic variable x, the logic variable y, and the multi-value logic function f (x, y) may be different. They do not have to be identical. → Flexibility.
This super-explosive increase and the flexibility to deal with it are possible to program each of the composite / multi-valued logic circuits of FIG. 17 and FIG. 18 with a programmable / three-dimensional logic array, semi-order / three-dimensional IC / LSI. When it is put to practical use, it becomes an extremely powerful weapon and effect.

Specific examples of the multi-value logic circuit include the following.
◆ Example 1: FIGS. 23 and 24 show two examples of asynchronous / multi-value “NOT (m) = m” circuits, and FIGS. 25 to 26 and FIG. 28 show asynchronous / multi-value “AND (m) = Three examples of the “m” circuit are shown, and FIG. 30 shows one example of the asynchronous multi-value “OR (m) = m” circuit.
In the asynchronous / multi-valued NOT circuit of FIG. 24, the diode 225 indicates that “when the transistor 201 is off and the transistors 202 and 228 are on, power is supplied from the power line V _m through the resistor 223, transistor 228, resistor 220, and transistor 202. For preventing the current from flowing to the line V _m−1 ”. When the series circuit of the transistors 201 and 228 cannot drive the transistor 224 off due to the forward voltage of the diode 225, the diode 226 and the resistor 227 are necessary. However, when the transistor 201 is off and the transistor 228 is off when the transistor 202 is on, the diodes 225 and 226 do not need to be inserted and connected, and the resistor 227 is also unnecessary.
* Reference: Each circuit of FIG. 10 and FIG. 9 of patent document 3 (Unexamined-Japanese-Patent No. 2005-236985).
The asynchronous type / multi-value NOT circuit shown in FIG. 23 is the same as that of the prior application / first and second inventions shown in FIG. 43. In FIG. 23 (= synchronous type / multi-value NOT circuit), It is changed to an asynchronous type / multi-valued NOT circuit by removing it.
Example 2: Nine "prior application shown in FIG. 47 / synchronous AND circuit in embodiment 14 common to first and second inventions" and 18 "prior application / first, second shown in FIG. 32" Synthetic NOT circuit of the first embodiment common to the invention "or" Synchronous NOT circuit of the seventeenth embodiment common to the first application and the first and second inventions shown in FIG. 42 ". A synchronous synthesis / multi-value logic circuit in which the logic circuit is changed to a synchronous type and the latching timings of both the all / synchronous NOT circuit and the all / synchronous AND circuit are shifted is possible.
As a matter of course, this synchronous synthesis / multi-value logic circuit can eliminate multi-value hazards. In addition, if the gate terminal of the transistor 41 is changed from the Q terminal to the Q bar terminal in the first embodiment common to the prior application, first and second inventions shown in FIG. 32, the first embodiment is changed from the synchronous NOT circuit to the synchronous type. Since the circuit changes to an EVEN circuit (= synchronous EQUAL circuit), the conductors shown next to the NOT circuits in FIGS. 17 and 18 are not necessary.
Also in this case, “increase in all multi-value numbers N” can be performed in the same manner as described above (paragraph number [0101]), and “change to different multi-value numbers N” can be performed as described in the next section. .

◆◆◆ ＊＊＊＊ Flexibility for logical variables with different multi-values ****** ◆◆◆
***
●● 18) “Multi-valued logic“ Hooji algebra ”” “Flexible correspondence that can cope with multiple logical variables and multi-valued numbers N (≧ 2) of each of those logical functions” The characteristics will be described below.
* Reference: For multi-value number N = 2 → paragraph number [0080-0081].
Depending on the multi-value logic circuit system, there are cases where a plurality of “data or information” having different multi-value numbers N (≧ 2) are handled. For example, the multi-value number “3” for the three primary colors of light (blue-red-green), the multi-value number “2” for positive and negative images, and the multi-value number “multi-level of brightness”, “blue-red-green” It is a multi-value number such as “mixing ratio”.
In such a case, multi-value logic circuits having different multi-value numbers N (≧ 2) are mixed together, but “the multi-value logic having the larger multi-value number” is “the multi-value number of the multi-value number”. It is better to completely include the “smaller multi-valued logic” and the former is compatible with the latter.
In the case of the new multi-valued logic “Hooji algebra”, the former is assembled based on the latter (multi-valued number N ≧ 2) as described above (paragraph number [0082]). However, the former includes the latter and is compatible with the latter.
In the above-described synthesis / multi-value logic circuit of FIG. 15, the multi-value number N2 (≧ 2) of the logical variable x is always equal to the multi-value number N1 (≧ 2) of the multi-value AND circuit and multi-value OR circuit. It does not have to be the same, and the multi-value number N3 (≧ 2) of the logical variable y does not always have to be the same. There may be cases where N1 ≠ N2 or N1 ≠ N3. Furthermore, N2 and N3 need not always be the same. There may be cases where N1 ≠ N2 or N1 ≠ N3 or N2 ≠ N3.
Example 1: A ternary / nine-value code conversion circuit in paragraph number [0101].
Example 2: In the truth table of FIG. 16, when the variable range of the logical variable x is set to 0 to 7, for example, a multi-value “NOT (m) = m” circuit connected to the input terminal Tx in FIG. Among them, the multi-value “NOT (8) = 8” circuit where m = 8, 9 and the multi-value “NOT (9) = 9” circuit are removed, and the multi-value where the number of input terminals becomes one by the removal. If the “AND (m) = m” circuit is also removed, the change of the multi-value number can be handled.
In this case, if there is a multi-value AND circuit whose input is directly connected to the input terminal Tx among each multi-value “AND (8) = 8” circuit and each multi-value “AND (9) = 9” circuit. The multi-value AND circuit and the “multi-value NOT circuit connected to it” are unnecessary and can be removed.
This example 2 naturally applies to the logical variable y as well.
As a result, “[multiple logical variables and their functions] flexible correspondence that can be handled even if each multi-value number N (≧ 2) is different from each other” is a new multi-value logic “Hooji algebra” There is.
On the other hand, in the case of the multi-valued logic circuit composed of the conventional “AND circuit, OR circuit, inverting circuit, literal circuit, and cycling circuit” described above (paragraph number [0080] latter half and paragraph number [0082] latter half). Since "inversion circuits, literal circuits, and cycling circuits" with different multi-value numbers are not included and incompatible, there is no flexible correspondence like the new multi-value logic "Fuji algebra".
* Reference: Non-Patent Document 3 p. 19-p. 20.
"Multi-valued information processing-post-binary electronics-", authors: Tatsuo Higuchi, Michitaka Kameyama, Shokodo in June 1989.

◆◆◆ ＊＊＊＊＊＊＊＊＊ Good connectivity with the binary circuit in the previous stage ********
***
●● 19) When connecting a binary circuit to the previous stage of the new multi-valued logic “Hooji Algebra”, its connectivity is extremely good, and a special interface (eg, binary / multi-value code conversion) A unique effect / characteristic that “means is not necessary” will be described below.
In the case of each multi-value logic circuit based on the new multi-value logic “Fuji algebra”, the discrimination means that the discrimination means fundamentally is “a signal indicating whether each discrimination content is positive or negative, “Negative signal (binary choice signal)”, that is, “A signal indicating yes or no for each discrimination content, yes / no signal (binary choice signal), binary signal”, etc. In addition, the compatibility with the output signal of the preceding binary circuit is very good.
Therefore, all that remains is to match the output part of the preceding binary circuit and the input part of the multi-value logic circuit as follows.
◆ a) When the preceding binary circuit outputs two signals, H level and L level:
The output level range of one of the H level and L level of the binary circuit is completely within the input discriminating range in which the multilevel logic circuit determines “Yes”, and the multilevel logic circuit is It is only necessary to perform matching so that the other output level range completely falls within the input determination range for determining "."
◆ b) When the output part of the preceding binary circuit is open collector or open drain:
Pull-up resistor means or pull-down at the output terminals of these multi-valued logic circuits as in the multi-value “NOT (...) =...” Circuit in each circuit of FIGS. 14, 15, 17, and 18. It is only necessary to connect a resistance means and match each of the output level range of the H level and L level output from the binary circuit in the same manner as in the above item a).
In both of the items ◆ a) and ◆ b), if both the power supply potentials corresponding to both the H and L levels are “two power supply potentials among the lowest potential to the highest potential of the multi-value circuit”. anything is fine. For example, in the decimal system, both the power supply potentials are “v ₀ and v ₁ ”, “v ₄ and v ₅ ”, “v ₈ and v ₉ ”, “v ₅ and v ₇ ”, “v ₃ and v _8”. ”,“ V ₀ and v ₉ ”,“ potential less than v ₀ and greater than v ₉ (both potentials do not correspond to numerical values) ”, and the like.
That's why the new multi-valued logic “Fuji Algebra” has a unique effect and feature that “when connecting a binary circuit in the previous stage, its connectivity is very good and no special interface is required between them” I understand.

◆◆◆ ＊＊＊＊＊＊＊＊＊ Good connectivity with the binary circuit at the latter stage ********
***
●● 20) New multi-valued logic “Hooji algebra” “When connecting a binary circuit in the latter stage, the connectivity is very good, and there is a special interface (eg, multi-value / binary code conversion) A unique effect / characteristic that “means is not necessary” will be described below.
There are the following two actual examples.
Example 1: “Each AND multi-value circuit” in the circuit of JP-A-2006-190239 and FIG.
Example 2: “Each multi-value NOT circuit shown in FIG. 11” and “Each binary NOR circuit shown in FIG. 12” in the circuit shown in FIGS.
***
On the other hand, in the case of a conventional Ukasevich type multi-value logic circuit well known in the multi-value logic field, the connectivity with the binary circuit is poor both at the front and rear stages, and a special interface (binary / multi A value code conversion means and a multi-value / binary code conversion means) are required.
* Reference: Non-Patent Document 3 p. 13 of FIG.
"Multi-valued information processing-post-binary electronics-", authors: Tatsuo Higuchi, Michitaka Kameyama, Shokodo in June 1989.

◆◆◆ ** Possibility of using one-way switch in each circuit of Fig.15, Fig.17, Fig.18 * ◆◆◆
***
●● 21) From the conclusion, it is possible to use a unidirectional output switch. In each of the synthesis / multi-value logic circuits (= multi-value complete circuit) of FIGS. 15, 17, and 18 described above (paragraph numbers [0083 to 0098]), the “bidirectional switching means is provided in the output switch section”. The "multi-value complete circuit" that can realize all multi-value logic functions using "various basic / multi-value logic circuits to be used" has been described.
However, in each of the composite / multi-value logic circuits of FIGS. 15, 17, and 18, the output of each “basic / multi-value logic circuit having a pull-up resistor or a pull-down resistor connected to the output portion” is output. The switch part need not be any bidirectional switching means. Each of the "basic / multi-valued logic circuit with a pull-up resistor connected to its output section" is "the output switch section is a reverse blocking type or a type with no reverse blocking capability (eg, reverse conduction type, reverse conduction type, etc.) )) ”, Which is a pull-down switching means. The reverse conduction type includes, for example, a MOS • FET having a built-in diode, and the reverse conductivity type includes, for example, a bipolar transistor.
On the other hand, each of the "basic / multi-valued logic circuit with a pull-down resistor connected to its output part" is a pull-up switching means of "the output switch part is a reverse blocking type or a type without reverse blocking capability". It does not matter if it is a "basic / multi-valued logic circuit". Of course, “basic / multi-valued logic circuit that can connect either pull-up resistor or pull-down resistor to its output” depends on the pull direction of the resistor. “Basic or multi-value logic circuit that is“ pull-up switching means or pull-down switching means ”” of “type without type or reverse blocking capability”.
In these cases, in the synthesis / multi-value logic circuit of FIG. 15, “a multi-value NOT circuit and a multi-value AND circuit using a one-way pull output switch” and “a multi-value OR circuit using a bidirectional output switch” are used. At least three circuits form a complete system. In each of the composite / multi-value logic circuits of FIGS. 17 and 18, “multi-value NOT circuit using a one-way pull output switch” and “multi-use output switch using multi-directional output switches” are provided. At least three circuits of “value AND circuit” and multi-value wired OR circuit form a complete system.

Further, with respect to each multi-value OR circuit in the synthesis / multi-value logic circuit of FIG. 15 and each multi-value AND circuit in the synthesis / multi-value logic circuit of FIG. 17, the pull output of the output terminal Tf of each circuit is If it doesn't have to be bidirectional and its pull output can be either pull-up or pull-down, all its basic / multi-valued logic circuits say "the output switch is a reverse blocking type pull "Basic / multi-valued logic circuit" that is "up-switching means or pull-down switching means" may be used. In this case, in the synthesis / multilevel logic circuit of FIG. 15, if the all / multilevel OR circuit uses reverse blocking pull-up / switching means for the output switch section, the output terminal Tf is, for example, FIG. The power supply potential lower than the power supply potential v ₀ of the synthesis / multi-valued logic circuit {eg, the power supply potential v ₋₁ one lower than the power supply potential v ₀ . } Is output as a reference. On the other hand, if the all-multi-value OR circuit uses reverse blocking pull-down switching means for the output switch section, the output terminal Tf is, for example, the power supply potential v ₉ of the synthesis / multi-value logic circuit of FIG. higher supply potential {e.g. power supply potential _{v 9} than the potential one high power supply potential _{v 10.} } Is output as a reference. The same applies to each of the multi-value AND circuits in the synthesis / multi-value logic circuit of FIGS.
In these cases, in the synthesis / multi-value logic circuit of FIG. 15, at least three circuits of “a multi-value NOT circuit, a multi-value AND circuit, and a multi-value OR circuit using a one-way pull output switch” form a complete system. 17 and 18, at least three circuits of “multi-value NOT circuit and multi-value AND circuit using a one-way pull output switch” and multi-value wired OR circuit are complete systems. Make it.

Then, each of the basics using “pull-up switching means or pull-down switching means” of “type without reverse blocking capability (eg reverse conduction type, reverse conduction type, etc.)” in the output switch section. The multi-level logic circuit can also be used in the final stage of the circuit shown in FIG. For example, in the circuit of FIG. 17, the output terminals are all connected once for each “multi-value AND circuit whose output specific integer is the same value”, and the connection / common terminal / for each. A diode may be connected between the common terminal and the output terminal Tf. In this way, it is possible to prevent a power short circuit between the multi-value AND circuits.
Also in this case, the output switch section of the all-multi-value AND circuit performs either pull-up or pull-down operation when driving on, and there is no mixing of pull-up operation and pull-down operation. The output signal to be output is “power supply potential higher than power supply potential v ₉ {eg, power supply potential v ₁₀ higher by one than power supply potential v ₉ }” or “power supply potential lower than power supply potential v ₀ { Example: A power supply potential v ₋₁ lower than the power supply potential v ₀ by one.} ”.
Therefore, a diode is connected to the multi-value AND circuit group whose specific integer value for output is either 0 (when the reference power supply potential is v ₁₀ ) or 9 (when the reference power supply potential is v− ₁ ). 9 is not necessary, so the total number of output diodes required is nine.
In this case, in the synthesis / multi-value logic circuit of FIG. 17, in addition to at least three circuits of “multi-value NOT circuit and multi-value AND circuit using a one-way pull output switch” and multi-value wired OR circuit, its output Nine diodes form a complete system.
At first glance, it seems that the number of parts has increased, but in the case of the composite / multi-valued logic circuit of FIG. 17 that uses the reverse blocking pull switching means described above (the previous paragraph), it is usually required. The total number of reverse blocking and output diodes is 100, and an additional 91 output diodes are required.

Alternatively, in the synthesis / multi-valued logic circuit of FIG. 15, for example, when the power supply potential increases in the order of v ₀ to v ₄ , vB, and v _{5 to} v ₉ , and there is an extra power supply potential vB, You can also do the following:
Each multi-level OR circuit in the synthesis / multi-level logic circuit of FIG. 15 outputs an output signal based on the power supply potential vB. Therefore, for each of the “multi-valued OR circuit whose specific integer value for output is any one of 0 to 4”, the output switch section is a reverse blocking pull-down switching means. On the other hand, for each “multi-value OR circuit whose specific integer value for output is any of 5 to 9”, the output switch section is reverse blocking pull-up switching means.
The power supply potential vB serving as a reference potential of the output signal is not necessarily there in between both the power supply potential v4 · v5, among the power supply potential v ₀ to v _9, the two power supply potential adjacent any two It may be in between. Of course, in this case, the voltage is pulled up higher than the power supply potential vB or pulled down below the power supply potential vB.
The same applies to the synthesis / multilevel logic circuit of FIG. 17, and each multilevel AND circuit outputs an output signal based on the power supply potential vB. What has been described above is applied to each multi-valued OR circuit in the composite / multi-valued logic circuit of FIG.
In these cases, there are cases where there are two pull directions, so in the synthesis / multi-value logic circuit of FIG. 15, “a multi-value NOT circuit, a multi-value AND circuit and a multi-value OR circuit using a one-way pull output switch”. At least 4 circuits form a complete system. In the composite / multi-value logic circuit of FIG. 17, “a multi-value NOT circuit and multi-value AND circuit” using a one-way pull output switch ”and a multi-value wired OR circuit are used. At least four circuits form a complete system.

Alternatively, as described above (the content of the previous paragraph), each multi-value AND circuit in the synthesis / multi-value logic circuit of FIG. 17 outputs an output signal based on the power supply potential vB. This is a case where a reverse switching type or a reverse switching type pull switching means is used for the output switch section.
Regarding each of the “multi-value AND circuit whose specific integer value for output is any one of 0 to 4”, the output switch unit is a pull-down switching means such as a reverse conduction type or a reverse conduction type. It is devised like paragraph number [0106]. The output terminals are all connected once for each “multi-value AND circuit having the same specific integer for output”, and between the common terminal and the output terminal Tf for each connection / common terminal. Connect the diode in the pull-down direction.
On the other hand, regarding each of the “multi-value AND circuit whose specific integer value for output is any of 5 to 9”, the output switch unit is a pull-up switching means such as a reverse conduction type or a reverse conduction type. Just like the above (paragraph number [0106]). The output terminals are all connected once for each “AND circuit whose output specific integer is the same value”, and a diode is connected between the common terminal and the output terminal Tf for each connection / common terminal. Connect in the pull-up direction.
In this case, there are cases where there are two pull directions, so in the composition / multi-value logic circuit of FIG. In addition to at least four OR circuits, nine of its output diodes form a complete system.

◆◆◆ ＊＊＊＊＊＊＊＊ Complete circuit means of the third 10-valued logic function *****＊＊＊＊ ◆◆◆
***
22) A complete circuit means (= composite / multi-value logic circuit) of the third 10-value logic function is shown in FIG. The multi-value complete circuit means of FIG. 20 is an improvement of the multi-value complete circuit means of FIG. 15, and “multi-value EVEN circuit” and “multi-value EVEN circuit” are connected to the input terminal Ty and the input part of each multi-value AND circuit. "Pull-up resistor or pull-down resistor""is inserted and connected one by one.
Thus, when various multi-level synchronous logic means are used for the multi-value complete circuit means of FIG. 20, each synchronization timing and each signal propagation time can be made uniform. For example, the synchronization timing of “all / synchronous NOT unit and all / synchronous EVEN unit” is matched, the synchronization timing of all / synchronous AND unit is matched, and the synchronization timing of all / synchronous OR unit is matched. it can.
In this case, for example, the three synchronization timings may be different from each other, and the synchronization timing of “all / synchronous NOT means and all / synchronous EVEN means” is the same as that of all / synchronous OR means. In some cases, only the synchronization timing of all / synchronous AND means is different.
In both the complete circuit means of FIG. 20 and the complete circuit means of FIG. 15, the multi-value AND means and the multi-value OR means are replaced by multi-value NAND means by using the OR equivalent circuit of FIG. It can be replaced one by one. This is because “the multi-level NOT unit connected to the subsequent stage of the multi-level AND unit” is equivalently equivalent to the multi-level NAND unit.
Of course, the specific integer value of each multi-value NAND means is set to “specific integer value of each multi-value logic means to be replaced”.

◆◆◆ ＊＊＊＊＊＊＊＊ Complete circuit means of the fourth 10-valued logic function ********
***
23) A complete circuit means (= composite / multi-value logic circuit) of the fourth 10-value logic function is shown in FIG. The multi-value complete circuit means of FIG. 21 is an improvement of the multi-value complete circuit means of FIG. 17, and “multi-value EVEN circuit” and “multi-value EVEN circuit” are connected to the input terminal Ty and the input part of each multi-value AND circuit. "Pull-up resistor or pull-down resistor""is inserted and connected one by one.
Thus, when various multi-level synchronous logic means are used for the multi-value complete circuit means of FIG. 21, each synchronization timing and each signal propagation time can be made uniform. For example, the synchronization timings of “all-synchronous NOT means and all-synchronous EVEN means” can be matched, and the synchronization timings of all-synchronous AND means can be matched. However, as a matter of course, both synchronization timings are completely different and are usually shifted.

◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆
◆◆◆
◆◆◆ ＊＊＊＊＊ Disclosure contents of JP 2012-077504 A, etc. ********
***
●● 24) “Various multi-value logic circuits based on the Fuji algebra” and “Multi-value logic means and multi-value hazard removal means having synchronous latching function” disclosed in Japanese Patent Application Laid-Open No. 2012-075084 (Patent Document 7). As a precaution, the present inventor will now describe those techniques in paragraphs [0114 to 0237] so that they can be treated in the same manner as common technical knowledge.

◇◇◇ Technology field ◇◇◇
The first invention of the prior application is a "multi-value logic means having a synchronous latching function" in which a multi-value logic circuit in a potential mode (or voltage mode) based on the following "Fuji algebra (= multi-value logic)" has a synchronous latching function. ".
Rather than using multi-value synchronous latching means with "all-value latching function that can latch any numerical value used in multi-valued logic", the above-mentioned "synchronous latching function" Latching in units of "multi-valued logic means" has the following effects and features.
1) Since a binary synchronous flip-flop means is built in, each trigger method (eg, edge trigger, level trigger, pulse trigger) can be used as it is.
★ Reference materials on “each trigger method”: Non-Patent Document 4, pages 79-88.
● 2) “Output open or signal state corresponding to open output” can be latched.
* Note: The “Fuji algebra” below has a unique output method of “releasing output”.
● 3) There is no latching function for "signal state corresponding to each integer other than the output specific integer among all multi-values". That is, there is no extra / useless latching function.
→→ Since there are no useless parts and useless configurations, parts and circuits can be used efficiently and power consumption can be saved.
→→ Multi-value circuit to be used {Example: Multi-value logic circuit, multi-value arithmetic circuit (or multi-ary arithmetic circuit), multi-value storage means, multi-value memory means, multi-value digital circuit, etc. }, The number of options of the multi-level synchronous latching means to be connected to the subsequent stage is increased according to the configuration of {}.
Conventionally, for example, it has been considered to provide a multilevel synchronous latching means between a multilevel circuit and a multilevel circuit.
P. Of "Introduction to Illustrated Digital Circuit". 79-88 (binary pulse trigger method). Published 4th edition on April 25, 2008 by Nippon Riko Publishing Co., Ltd. Author: Tsuguo Nakamura.

● Because the flip-flop originally has only two states, the term “multi-value flip-flop” does not match, so the term “multi-value latching means” has been unified.
● Also, the multi-value logic circuit that constitutes each invention is a materialization and realization of “multi-value logic created by the inventor”. Since it is inconvenient if there is no name, I decided to name it “★ Houji Algebra” (details are in paragraph numbers [0049-0112]).
The reason for this is “Since the present inventor is Japanese, it is related to the symbol of Japan, Mt. Fuji,” and “Bool” of Boolean Algebra. ”And“ the ability, possibility, practicality, expandability, future potential, etc., anyway, huge {= very large, tremendously large, huge.} Since the present inventor strongly judges that it is, the language is aligned with the English huge. (Reference: The following patent documents 1-3)
JP 2004-032702 (Multi-valued logic circuit based on Fuji algebra) JP 2005-198226 (same as above) JP 2005-236985 (same as above)

● In addition, in the field of logic mathematics, “the concept of“ open output ”or“ open output (eg open collector, open drain) ””, which is well known as a basic technology in electronic circuits, It was not before "Fuji Algebra". However, with the advent of this “Fuji algebra,” the concept had to be adopted. This is because “Fuji algebra” has several “advantageous and unique effects” that are not found in conventional multi-valued logic. →→ paragraph number [0049-0068].
On the other hand, in the field of electronic circuits, “all one or several types of basic / multi-valued logic circuits” or “a combination or combination thereof” can be used regardless of the multi-value number N (N of N values). `` Function that can realize and embody multi-valued logic functions '', that is, `` completeness '', it is also `` perfect '', and it is built independently without relying on the multivalued logic system published in the field of logical mathematics There was no multi-valued logic system / circuit before the above-mentioned Patent Documents 1-3. The “completeness” of the above “★ Fuji algebra” was proved in paragraph numbers [0083 to 0096].
★ Reference materials on "complete system, completeness, completeness": Non-patent documents 1 to 3 below.
In the present invention, each integer of N value and each constant potential supply means (eg, power supply line, power supply plate, etc.) correspond to each other one by one in order, but as the integer increases, From the 1st constant potential to the Nth constant potential, these constant potentials correspond to the positive logic when they become higher, and the case where they become lower correspond to the negative logic.
“Digital Digital Circuits Understandable”, p. 9 line 14 to p. "Complete system" on the first line of 10. Author: Keitaro Sekine, published by OHM Co., Ltd. on July 25, 1997. "Introduction to Logic Circuits", authors: Ryuji Hamabe, published by Morikita Publishing Co., Ltd. on September 28, 2001. “Chapter 2 Logic Functions” → “2.1 Basic Logic Operations” → “2.1.4 Basic Logic Operations and Logic Symbols” → “(8) Complete System” (p.31 to p.32). "Multi-valued information processing-post-binary electronics-", authors: Tatsuo Higuchi, Michitaka Kameyama, Shokodo in June 1989. p. 16-p. 17.

The second invention of the prior application relates to a multi-value hazard removing means utilizing the “multi-value logic means having a synchronous latching function” of the first application of the first application, and the multi-value number N (= N of N values). Regardless, it is possible to remove the multi-value hazard that occurred before or during the input of the multi-value hazard removing means.
In the multi-value circuit (eg, multi-value logic circuit, multi-value arithmetic circuit (or multi-ary arithmetic circuit), multi-value storage means, multi-value memory means, multi-value digital circuit, etc.), “same as binary hazard” In addition to “multi-value hazards that occur due to various mechanisms”, there are three or more “logical values, logic levels and potentials (or voltages) that correspond one-to-one with each other”, so “multi-value specific hazards” Occur.

◇◇◇ Background technology ◇◇◇
■■■ Background art of the first invention of the prior application ■■■
As a conventional multi-level synchronous latching means, a level-trigger type multi-level synchronous latching means is disclosed in Example 10 (paragraph 0035) of Japanese Patent Laid-Open No. 2006-345468, and Japanese Patent Laid-Open No. 2007-35233. FIG. 18 and FIG. 15 of this publication disclose a multi-level synchronous latching means of a pulse trigger system (= master / slave system).
However, the "multi-level synchronous latching means of the method corresponding to each of the binary flip flop means of the positive edge trigger method and the negative edge trigger method" has not yet been realized and put into practical use. Naturally, the positive and negative edge trigger methods cannot be used.
If the synchronous multi-value circuit can be triggered at the rising edge or falling edge of the synchronization signal, the choices of trigger timing and trigger method are increased, which is very convenient. For example, if each of the edge trigger methods can be used, the stepwise multi-level synchronization signal (reference: the following, Patent Document 11) considered by the present inventor can be used more effectively. There are more trigger timing options in one cycle, which is very convenient.
Therefore, the conventional technique has a problem that “positive and negative edge trigger methods cannot be used”. (First problem to be solved by the first invention of the prior application)
Japanese Patent Laid-Open No. 2006-345468 (multi-level synchronization signal generating means, etc.). In the step-like multi-level synchronization signal waveform of FIG. 4, there are a plurality of rising or falling portions in one cycle. For example, one of the “plurality of rising or falling points” can be selected depending on which two power supply lines of the entire multi-level circuit are provided with one synchronous binary flip-flop means. it can. It is also possible to provide one synchronous binary flip-flop means at each of the plurality of locations.

  In addition, in the case of the multi-value logic circuit in the potential mode (or voltage mode) based on the “Fuji algebra” described above, there is an important output method of “output open or open output”. There is also a problem that the type latching means cannot latch the signal state corresponding to [output open or open output]. (Second problem to be solved by the first invention of the prior application)

Furthermore, there is a problem that “the latching function corresponding to [output numerical value] is not provided, and waste is generated”. (Third problem to be solved by the first invention of the prior application)
For example, both of the multi-level synchronous latching means have an “all-number latching function used in multi-level logic and capable of latching any numerical value”. If the (input / output) numerical value is over all numerical values, the use efficiency of the latching function is good. In the case of limitation), the use efficiency of the latching function deteriorates both in terms of effective use of components and circuits and in terms of power use efficiency.
In other words, because “the latching function part corresponding to the numerical value that is not output” is not used, the circuit of the function part is wasted, and “when all the transistors etc. are switched on / off due to the rewriting of the latching contents” "Total switching loss" increases by the amount of "switching loss of the unused latching function portion that is not used".
In other words, the number of parts is increased by the “latching function part for the numerical value that is not output”, and the circuit configuration becomes complicated. Therefore, the effective utilization rate of the part / circuit deteriorates, and the extra latching function. Extra power is consumed by the switching loss of the part on / off switching.
Moreover, if all of the transistors are voltage-driven, such as MOS / FET or insulated gate type transistors, there is charge / discharge energy loss due to the capacitance between the gate and source, etc. More power is consumed by the amount of energy loss.
As a result, the latching function / usage efficiency deteriorates both in terms of effective use of the parts / circuits and in terms of power use efficiency. If the effective utilization rate of the parts / circuits is poor, the occupied area of the multi-level synchronous latching means in the two-dimensional IC or two-dimensional LSI is naturally large if the three-dimensional IC or LSI is occupied. This increases costs.
As described above, the reason why the latching function / use efficiency is poor is that “there is an extra latching function for each numerical value other than the output numerical value”.
Therefore, there is a problem that “the latching function corresponding to [output numerical value] is not provided and waste occurs”. (Third problem to be solved by the first invention of the prior application)

Then, if the multi-value circuit to be used {eg multi-value digital circuit etc. }, It will be convenient if a multi-level synchronous latching means to be connected to the subsequent stage can be selected in accordance with the configuration of {}.
Specifically, if the multi-value logic means has a synchronous latching function, the multi-value logic means / unit can be synchronized and latched. More choices will be useful.
→→ In the case of each multi-value logic circuit based on “Fuji algebra”, the “numerical value” to be latched can be easily changed by changing the connection of the constant potential supply means (eg, power line, power plate, etc.) to which this circuit is connected. In addition, a use circuit can be selected from the various multi-value logic circuits. In other words, since there are many choices for the multi-value logic circuit from the beginning, if each multi-value logic circuit can be provided with a synchronous latching function, the number of “selectable multi-value synchronization latching means” is increased, which is convenient.
Therefore, the multi-value circuit to be used {eg, multi-value logic circuit, multi-value arithmetic circuit (or multi-value arithmetic circuit), multi-value memory, multi-value storage means, multi-value digital circuit, etc. }, It is desirable that there are many options of the multi-level synchronous latching means connected to the subsequent stage in accordance with the configuration of {}. When there are many choices, flexibility occurs in the configuration of the entire multi-value circuit. (Fourth problem to be solved by the first invention of the prior application)
→→ For example, the present inventor has described “(multi-value) AND circuit, (multi-value) OR circuit, (multi-value) NOT circuit, (multi-value) NAND circuit”, (multi-value) NOR circuit, etc. Circuit, OVER circuit, NOVER circuit, EVEN circuit, UNDER circuit, NUNDER circuit, IN circuit, NIN circuit, OUT circuit, NOUT circuit There are logic circuits and their combination multi-value logic circuits (eg, multi-value AND / OVER circuit, multi-value OR / OUT circuit, etc.).

Conventionally, a multi-value synchronous latching means must be provided between the multi-value circuit and the multi-value circuit, and the latching location is fixed. If there are many choices of the latching location, the configuration of the entire circuit becomes flexible.
Therefore, it is desirable that there are many choices of the latching location “where to latch in the entire circuit”. (Fifth problem to be solved by the first invention of the prior application)

■■■ Background Art of the Second Invention of the Prior Application ■■■
First, "multi-valued logic levels", "each threshold potential (or each threshold voltage) at each logic level" and "continuity of potential (or voltage) change" will be described as preliminary knowledge.
■■ Multi-level logic levels ■■
In the case of a binary circuit (eg, binary logic circuit, binary arithmetic circuit, binary memory, binary storage means, binary digital system, etc.), for example, “0” and “1” are used as the two logical values. Therefore, the term “L level and H level” can be used to express each logic level regardless of positive logic or negative logic. In the positive logic, the L level substantially means “logical level of logical value 0”, and the H level means “logical level of logical value 1”, whereas in negative logic, the L level is substantially “logical value 1”. "Logic level" means H and "H level" means "logic level of logical value 0".
In the case of a ternary circuit, since the three logical values include, for example, “0”, “1”, and “2”, the expression of each logical level can be expressed, for example, “L level, M” regardless of positive logic or negative logic. The terms “level, H level” can be used.
Further, in the case of a quaternary circuit, the four logical values include, for example, “0”, “1”, “2”, “3”. The terms “L level, M0 level, M1 level, H level” can be used.
Similarly, in the case of a quinary circuit, the five logical values include, for example, “0”, “1”, “2”, “3”, “4”. For example, the terms “L level, M0 level, M1 level, M2 level, H level” can be used.
However, in the case of a “composite multi-value digital circuit in which a plurality of multi-value circuits having different multi-value numbers (= N of N values) are mixed” or “multi-value logic functions having different multi-value numbers” And the term “anomalous multi-value digital circuit that includes a plurality of logic variables” or “one or more logic variables thereof” (explained in paragraph number [0154] described later)). .
For example, the H level of the ternary circuit corresponds to the M1 level of the quaternary circuit, and the H level of the quaternary circuit corresponds to the M2 level of the quinary circuit.
If that is the case, then “the largest multi-value number N (= N of N values) to be used” is used as a reference for the entire circuit, and “logic level name and logic value” corresponding to each power line. Is fixed and unified to “the logical level name and logical value of the largest multi-level number N to be used”, for example, “logical level of logical value 2” corresponding to the power supply line V2 is abbreviated to “logical It is called “2 level”, and the abbreviated “L2 level” is somewhat clearer.
Therefore, in the case of a 10-value circuit, for example, “logic levels 0 to 9” that correspond one-to-one with “power supply line V0 to power supply line V9” are called “L0 level to L9 level”. Each “constant potential or constant voltage” corresponding to 1 to 1 increases from the L0 level toward the L9 level, increasing in the positive logic state and decreasing in the negative logic state.
For this reason, when configuring a binary circuit in the 10-value circuit, for example, the “required two power supply lines” are selected from the “power supply lines V0 to V9” and used. In the entire circuit of 10 values, not only the numerical values “0 and 1” but also numerical values “4 and 5”, numerical values “8 and 9”, numerical values “3 and 7”, numerical values “5 and This means selection of various combinations of numerical values such as “9” and numerical values “0 and 9” and the magnitude of the power supply voltage for the binary circuit.
However, since there are only L level and H level in the binary circuit after all, if only in the binary circuit, the L level can be considered as a numerical value 0 and the H level can be considered as a numerical value 1. The entire circuit including the 10-value circuit is considered as “L0 level to L9 level”.
In short, there is no confusion if these things are considered with purely electronic circuits, but there is only a difference in the magnitude of the power supply voltage and the height of the power supply potential. In consideration of the correspondence relationship, it becomes easy to be confused because elements such as “the difference in each multi-value number” and “which power line corresponds to the reference value 0” are included.
Hereinafter, the logical levels of the multi-valued numerical values will be referred to as “L0 level, L1 level, L2 level...” For the time being.
★★★ Name of each logical level corresponding to each logical value one-to-one (provisional)

“Introduction to Transistor Circuit Lecture 5: Digital Circuits”, p. 46-p. 47 “4.6 Notes on using logic circuits [1] Logic voltage level and noise margin”. Supervision: Yoshifumi Amemiya and Nori Koshiba. Authors: Kensuke Shimizu and Masahiro Masakazu. Issued on May 20, 1981 by Ohm Co., Ltd. “Digital Digital Circuits Understandable”, p. 76-p. 80 [[1] logic level to [2] noise margin]. Author: Keitaro Sekine, published by OHM Co., Ltd. on July 25, 1997. “Introduction to Logic Circuits”, p. 126-p. 128 “6.4 IC characteristics (1) Signal voltage value and noise margin”. Author: Ryuji Hamabe, published by Morikita Publishing Co., Ltd. on September 28, 2001. “Pulse Digital Circuit”, p. 125-p. 130 “5. Basic characteristics of circuit 5.1 Amplitude characteristics of pulse digital circuit ”. Author: Akira Kawamata. Published by Nikkan Kogyo Shimbun on February 15, 1995. “Pulse and digital circuit”, p. 128 “Threshold Level” and p. 129 “Logical Level”. Edit: Masao Yoneyama. Author: Shigeyuki Ohara, Sumio Yoshikawa, Toshio Shinozaki, Shiro Takahashi. Published by Tokai University Press on April 5, 2001. “Practical Introduction Series: How to Use CMOS Circuit [1]”, “Element Threshold Voltage” on page 44 and “Circuit Threshold Voltage” on page 50. Author: Yasoji Suzuki. Published on October 15, 1997 by the Industrial Research Committee.

■■ Numeric discrimination and each threshold potential (or each threshold voltage) ■■
A positive logic numerical discrimination method will be described. In a binary circuit, “L-level input voltage (or input potential)” is essentially a plus based on the power supply voltage zero (or power supply potential zero) determined in advance by international standards, international standard specifications, etc. Side threshold voltage (or positive side threshold potential) ”and“ H-level input voltage (or input potential) ”is substantially determined in advance by its international standard, international standard specification, etc. The negative threshold voltage (or the negative threshold potential) with reference to the positive power supply voltage + V (or the positive power supply potential + V) ”.
In the binary circuit, what is usually called “threshold voltage (or threshold potential)” is, for example, in the case of CMOS “a boundary where the operating state of PMOS and NMOS is inverted”, ie, “circuit threshold voltage (or Threshold potential) ”. There is an on / off threshold voltage of the semiconductor element. These threshold values are uniquely determined by the magnitude of the power supply voltage and the characteristics of each semiconductor element. (Reference: Above / Non-Patent Document 8)
Therefore, the method for determining whether the multi-value input numerical value is “a numerical value defined as corresponding to the lowest logic level” is that the signal potential corresponding to the input numerical value is “a constant potential corresponding to the lowest logical level”. If the value is lower than the “predetermined positive side threshold potential”, the input value is determined to be “the value of the lowest logic level”.
However, since the multi-value “plus-side threshold potential” has not yet been determined in advance by international standards, international standard specifications, etc. (?), It is natural that the multi-value circuit. Each researcher / designer in the field will determine their own “plus-side threshold potential” in advance. If the “multi-value circuit in potential mode (or voltage mode)” will be used for general purposes in the future, the “positive side threshold potential” will be determined in advance according to international standards and specifications. Will be. This is also true for the following “each threshold potential”.
In addition, the method of determining whether a multi-value input value is a “number defined as corresponding to the highest logic level” is that the signal potential corresponding to the input value is “a constant potential corresponding to the highest logic level”. If it is higher than “a negative threshold potential determined in advance with reference to”, the input numerical value is determined to be “the numerical value of the highest logic level”.
Further, a method for determining whether a multi-valued input numerical value is “each numerical value defined to correspond one-to-one with each intermediate logical level other than the lowest and highest logical levels”. One of the potentials between “a positive threshold potential and a negative threshold potential” determined in advance with reference to each of the constant potentials corresponding to the one or more intermediate logic levels. , It is determined that the input numerical value is “the numerical value of the corresponding one intermediate logic level”.
Specifically, in the case of a 10-value circuit with numerical values 0 to 9, if positive logic, it is as follows.
* The L0 level region is a region lower than “the positive side threshold potential based on the first constant potential of the lowest potential (eg, power supply potential zero, etc.)”.
The regions of each level of L1 to L8 are regions between “plus side threshold potential and minus side threshold potential with reference to each of the second constant potential to the ninth constant potential” in order.
★ L9 level region is higher than “minus threshold potential with reference to 10th constant potential of maximum potential”.
In general, it is usually set as follows in “International Standards / International Standard Specifications”, etc., but there are exceptions that are not so (for example, when using bipolar transistors etc. like TTL, it becomes vertically asymmetric) .) Is also available. The negative threshold potentials of the L1 level to the L9 level are “constant potential of the logic level”, “constant potential of the logic level, and“ constant potential of the logic level one level lower than the constant potential of the logic level ”. Each of the positive side threshold potentials of the L0 level to L8 level is “a constant potential of a logic level one higher than the constant potential of the logic level” and its logic. One is set between “the middle potential of the constant potential of the level” and “the constant potential of the logic level”.

By the way, “threshold potential (or threshold voltage) when discriminating“… ”is a numerical value” ”and“ threshold potential when discriminating “not that numeric value” and “clearly” (Or threshold voltage) "is not the same and does not match. The reason for this is to eliminate a potential region (or a voltage region without any), since it is not necessary to have either a numerical value 0 or 1 at the time of digitization.
Although binary circuit is commonplace, if positive logic, "" Number 0 is ", the threshold voltage at the time of determination (or threshold voltage)" is L-level input potential (or input voltage) while becomes "" not a number 0 "and" clear "threshold potential (or threshold voltage) at the time of determination" is the threshold voltage at the time of determination as "" is a numerical value 1 "( Or threshold voltage) ”, that is, the same as the H level input potential (or input voltage), the two threshold potentials do not match.
For this reason, for example, in order to determine “clearly” that the input numerical value of the 10-value circuit is not the numerical value “0”, the input numerical value is determined to be any one of the numerical values “1 to 9”. Therefore, it must be determined that the signal potential of the input numerical value is always higher than the negative threshold potential of the L1 level.
In this case, “potential region without numerical value 1, 2”, “potential region without numerical value 2, 3”,..., “Potential region without numerical value 7, 8” and “numerical value 8”. , “None of the potential regions” is included in the “potential region for determining that it is any one of the numerical values“ 1 to 9 ””, but there is no problem at all. This is because any “potential region without any” is “a potential region that is not a numerical value 0”.
That is, although "the threshold voltage for the input number is to be numerical value" 0 "," clearly "determination" is the L0-level positive threshold potential, "the input value is the value" 0 The threshold potential for “clearly discriminating” is not “” is the negative threshold potential of the L1 level, and the two threshold potentials do not match.
Similarly, in order to determine “clearly” that the input value of the 10-value circuit is not the numerical value “9”, the input numerical value is determined to be any one of the numerical values “0 to 8”. Since it is necessary, it must be determined that the signal potential of the input numerical value is always lower than the positive threshold potential of the L8 level.
In other words, "the input numerical value and is a number" 9 "," clearly "threshold potential for the determination" is a L9 level of negative threshold potential, "the input value is the value" 9 The threshold potential for “clearly discriminating” that is not “” is the L8 level positive threshold potential, and the two threshold potentials do not match.
● Similarly, in order to determine “clearly” that the input value of the 10-value circuit is not the numerical value “1”, the input numerical value is any one of the numerical values “0, 2 to 9”. Since the signal potential of the input numerical value is always determined to be lower than the positive threshold potential of the L0 level or higher than the negative threshold potential of the L2 level. I have to do it.
In other words, "the input value" clearly and is a number "1", "threshold potential two for the determination" is L1 level plus, is a threshold potential of the negative sides, "the input “Two threshold potentials for“ clearly ”discrimination when the numerical value is not “ 1 ”” is “L0 level positive threshold potential” and “L2 level negative threshold potential”. Both “two threshold potentials” do not match.
In exactly the same way, both of the “threshold potentials” that are “clearly” determined for each of the numerical values “2 to 8” do not match.
→→→ “Two threshold potentials of ● a) to ● d) as described in claim 1 of the prior application”

■■ Continuity of potential (or voltage) change ■■
“Logical mathematics” does not have the concept of “continuity” or is not constrained by “continuity”, and there is no need to consider it at all, but its logical action (= logical thinking activity) is a physical action (= Example: electronic circuit operation etc.)), the replacement logical operation is always restricted by its physical properties. For example, a continuity of the capacitor voltage V _C (when the electrostatic capacitance C is constant.) And continuity of the coil current I _L (when the inductance L is constant.).
Both continuities are attributed to the “Energy Conservation Law” and “Energy conversion and movement takes time”. Energy or discontinuously generated and extinction by the energy saving law, because it will not be increased or decreased discontinuously, stored energy E _{C =} C-V C ^_2/2 by If C is a constant capacitor voltage V _C of the capacitor or also discontinuous generation and extinction, to never be increased or decreased discontinuously, the coil current I _L if L by magnetic energy (= exciting energy) E L _{= L} · I L ^_2/2 coils is constant Will not discontinuously occur or disappear, nor will it increase or decrease discontinuously.
Even if C is continuously (slightly) changed, since constant left-hand side of the stored energy type, also the capacitor voltage V _c only varies continuously (somewhat), the change is not a discontinuous. Since this is the same in the magnetic energy equation, even if L changes continuously (somewhat), the coil current _IL also changes only continuously (somewhat), and the change does not become discontinuous. This also applies to the case where the sum of the stored energy E _C and the magnetic energy E _L is constant.
Also, since there are always floating “capacitance, inductance, resistance” in the circuit and “internal capacitance, internal inductance, internal resistance” in each circuit component, “capacitor stored energy E _C ” and “ It takes time to convert the coil's magnetic energy E _L "to another energy or to move it to another location via the conductors and other circuit components in the circuit. For example, electromagnetic conversion due to resonance operation in the circuit, Joule heat generation due to resistance in the circuit, time delay due to each time constant, and the like. Therefore, it takes time to change both the coil current I _L capacitor voltage V _C. Neither changes at “time zero” or “discontinuously”.
This is why, with the exception of the following, the capacitor voltage V _C becomes always continuously when changing also the coil current I _L, it is not take a discontinuous discrete values.

However, when the primary side current of the transformer is interrupted by a flyback type power conversion circuit or a current interrupt type ignition circuit and the current starts to flow on the secondary side, in general, (inductance) ２ (2 turns) Since the change from the primary inductance value to the secondary inductance value becomes discontinuous unless the turns ratio is 1, the natural current conservation law naturally changes the primary current value to the secondary side. The change to the current value also becomes discontinuous.
If there are cases in addition to that positively discontinuously change the dielectric constant of permeability and capacitor C of the coil L is also the capacitor voltage V _C and the coil current I _L is also changed discontinuously. However, such circuit operations are not performed in a logic circuit or the like.

Of course, the (paragraphs [00127].) Because continuity of the capacitor voltage V _C is directly connected to the voltage continuity, such as the gate-source capacitance of the voltage-driven transistors such MOS-FET, its The “gate potential or gate voltage” or the like always changes continuously and does not take a discontinuous value.
→→ Digital circuit in potential mode (or voltage mode) (= 2-value to multi-value circuit)
On the other hand, lead in continuity and electronic circuitry of the coil current I _L, since directly linked to the continuity of the stray inductance current such as wiring, bipolar transistor or the like as long as the continuity of the current escape (the can) and are not The base current of the current driven transistor always changes continuously and does not take a discontinuous value.
→→ Digital circuit in current mode (= 2-value to multi-value circuit)
As a result, when the “logic level indicated by a certain multi-level signal” changes from “L0 level to L3 level”, for example, the logic level always passes “L1 level” and “L2 level” on the way.
If this is expressed in a logical numerical value, when the “logical numerical value indicated by the multi-level signal” changes from “0” to “3”, for example, the physical restriction described above, that is, “each continuity described above” The logical value always takes each value of “1” and “2” in the middle (passes these values).

■■■ Now, the main subject (background art of the second invention of the prior application) starts here. In general, “hazard” is equivalent to false “ghost signal, ghost data, or ghost information” as “signal noise” in both conventional binary circuit and multi-value circuit, and transmits true “signal, data, or information” To make it difficult to understand where and where, or from where to where is the real “signal, data or information”. The “hazard” adversely affects other circuit operations (malfunctions, useless circuit operations, etc.).
In addition, the five problems of the conventional multilevel logic circuit are summarized as follows. Detailed description thereof will be described later.
◆ 1) In addition to the hazard problem that occurs in the same mechanism as the conventional binary hazard, there are three or more logical values and logic levels, so “when the logic level of a multilevel signal changes, A multi-level inherent circuit failure and a multi-level hazard that “transient hazards occur by passing through the logic level” are particularly significant issues.
(First problem to be solved by the second invention of the prior application)
★ Reference: 13th to 10th lines from the back of the bottom of Non-Patent Document 9 below. Multi-valued inherent hazard.
◆ 2) “Similarly, when the logic level of a certain multi-level signal changes, it is too much shaken by overshooting or undershooting, passes the logic level that should be headed, reaches the next logic level, and then the logic that heads. A multi-valued inherent circuit failure and multi-valued hazard that “transient hazards occur by returning to the level” are particularly serious problems. (Second problem to be solved by the second invention of the prior application)
◆ 3) The problem with multi-level circuits is that “multi-level hazards lead to amplification and increase of power loss”. (Third problem to be solved by the second invention of the prior application)
(4) The larger the multi-value number, the greater the adverse effect of each of the first to third problems. Therefore, “the larger the multi-value logic circuit, the greater the adverse effect of the multi-value hazard”.
(Fourth problem to be solved by the second invention of the prior application)
◆ 5) Even if a possible conventional multi-value hazard removal circuit is used, the effect of the multi-value hazard is unavoidable in the previous stage of the circuit before removing the multi-value hazard. Want to be as small as possible.
Therefore, there is a problem that “if possible, I would like to narrow the range in the circuit affected by the generated multi-value hazard as much as possible”. (Fifth problem to be solved by the second invention of the prior application)
"High-tech classroom, multi-value logic circuit, IC density increases and binary and ternary do not go", published by Nikkei Sangyo Shimbun (Tokyo version) on November 22, 1985. Written by Ishizuka Yoshihiko.

■■ Detailed explanation of the first and third problems to be solved by the second invention of the prior application ■■
From here, “Generation of multi-value specific hazard due to first factor” will be described as an easy-to-understand example. For example, when the multi-value number N = 4 and the input value of the first multi-value circuit changes from the minimum value “0” to the maximum value “3”, it always passes the intermediate values “1 and 2”. The output side of the circuit changes from “output numerical value corresponding to input numerical value 0” to “output numerical value corresponding to input numerical value 1” and “output numerical value corresponding to input numerical value 2” to “output numerical value corresponding to input numerical value 3”. Become. At this time, depending on the value of each output numerical value, a multi-value hazard occurs as follows.
If the “output numerical value corresponding to the input numerical values 1 and 3” is “3” and the “output numerical value corresponding to the input numerical values 0 and 2” is “0”, the input numerical value is changed from “0” to “ Since the output value changes unnecessarily three times as “0” → “3” → “0” → “3” while changing to “3” once, the number of changes on the input side is amplified by three times. The first extra pulse appears on the output side.
(Generation of the first multi-value hazard →→ ● First issue to be solved by the second invention of the prior application)
And if the same thing happens in the second multi-value circuit in the subsequent stage that inputs the output numerical value, not only “while the input numerical value changes once from“ 0 ”to“ 3 ”” The same thing happens when the input numerical value changes once from “3” to “0”.
That is, while the input value changes once from “3” to “0” in the second multi-value circuit, the output value is “3” → “0” → “3” → “0”. Since the number of times of change changes, the number of changes on the input side is amplified by a factor of 3, and one second extra pulse appears on the output side.
(Generation of second multi-value hazard →→ ● First problem to be solved by the second invention of the prior application)
As a result, for each change of the input value of the second multi-value circuit, that is, three changes of “0 → 3”, “3 → 0” and “0 → 3”, the change of the input value for each time Since (every) the output side has a three-time value change and one extra pulse appearance, after all, the one-time change in the input numerical value of the first multi-value circuit is the second multi-value circuit. On the output side, there are nine numerical changes and three extra pulses. No, there are a total of four extra pulses. Actually, if you draw the 9 numerical changes on paper, you can see it.
In this way, if the same thing happens in the second multi-level circuit in the subsequent stage, the “number of wasteful changes” and the “number of extra pulses” are the number of connected stages of the multi-level circuit. The more you add, the more you add. As a result, the circuit operation becomes extremely complicated / abnormal as the circuit becomes a subsequent stage, and further adversely affects other circuit operations. It will no longer be useful for the end.
Examples of the adverse effects are “appearance of signal noise”, that is, “making it difficult to understand where and where or from where to where the true“ signal, data or information ””, “malfunction due to hazard noise”, For example, “useless circuit operation”.
(Amplification / increase of the number of occurrences of multi-value hazards and expansion of adverse effects)
→→ (● First problem to be solved by the second invention of the prior application)
Moreover, even if one hazard pulse is generated, it will naturally be ignored if the hazard pulses in the multi-valued circuit are summed up because “the dust accumulates,” but in addition, “ “Amplification / Increase”, that is, “Amplification / Increase in the number of multi-value hazard occurrences within an almost fixed period (= High-frequency multi-value hazard / Pulse generation frequency)” -In the case of FET, it means that the power loss due to charging / discharging such as capacitance between gate and source is further amplified and increased.
(Further increase in power loss →→ ● Third problem to be solved by the second invention of the prior application)

■■ Detailed explanation of the second and third problems to be solved by the second invention of the prior application ■■
Next, “Generation of multi-value specific hazard due to second factor” will be described as an easy-to-understand example. If the multi-value number N = 4 and the output numerical value of the first multi-value circuit changes from the minimum value “0” to the numerical value “2”, the input part of the second multi-value circuit in the subsequent stage “if positive logic “Overshooting, undershooting if negative logic” occurs. On the other hand, when the output numerical value changes from the maximum value “3” to the numerical value “1”, “under-shooting for positive logic and over-shooting for negative logic” occurs in the opposite direction.
Although these damped oscillations are the second cause of multi-value hazards, the output resistance of the first multi-value circuit is usually small, and the input impedance of the second multi-value circuit is capacitive (for example, MOS · FET The capacitance of the signal line between the two circuits is relatively inductive with a low internal resistance (eg, stray inductance). Shooting is likely to occur. In other words, if an attempt is made to transmit a signal from the preceding stage to the subsequent stage with high energy efficiency, these damping vibrations are likely to occur.
If the input signal overshoots or undershoots too much and the input signal passes the "logical level that should be headed" and reaches the next logical level, then the "logical level that the head should go" Returning to the step, transient hazard pulses are generated. Such a hazard pulse often occurs even in a ternary circuit.
(Generation of multi-value hazard due to overshooting etc.)
→→ (Second issue to be solved by the second invention of the prior application)

Here, a mechanism that causes overshooting and undershooting will be briefly described. Consider the operation of a circuit in which a series resonant circuit is connected to both ends of a DC power source via a bidirectional switch. Stored energy in the series resonant circuit as an initial condition is zero, turning on its bidirectional switch as energy loss zero at the resonant operation, the voltage of the resonance capacitor voltage zero around the power source voltage V _E And 2V _E oscillate endlessly. If the direction of the power supply voltage is opposite, the voltage of the resonance capacitor oscillates between zero voltage and negative 2V _E around the power supply voltage minus V _E.
In short, if there is no energy loss in the resonance operation, the voltage of the resonance capacitor will easily reach twice the power supply voltage (= twice the power supply potential difference).
In a general digital circuit, for example, the resonant capacitor is the capacitance between the gate and the source of the MOS / FET, the resonant coil is the floating inductance of the signal line / wiring between the preceding circuit and the succeeding circuit, and the preceding circuit The output resistance of is relatively small.
Similarly, when the input signal potential changes from the lowest power supply potential to the intermediate power supply potential in the ternary circuit, the input signal potential easily reaches the maximum power supply potential if there is no power loss in the resonance operation. (Over shooting). Even when the input signal potential changes from the highest power supply potential to the intermediate power supply potential, the input signal potential can easily reach the lowest power supply potential if there is no power loss in the resonance operation (under shooting). .
However, since the resonance operation actually has power loss, the resonance operation becomes a damped oscillation, so that the input signal potential reaches only “before the maximum power supply potential” or “before the minimum power supply potential”. There are many cases where this is not possible. However, for example, if the ternary circuit of numerical values 0, 1, and 2 is positive logic, the threshold potential of the logical level of numerical value 2 is “a negative threshold potential based on the highest power supply potential”. On the other hand, since the threshold potential of the logic level of the numerical value 0 is “a positive threshold potential with respect to the lowest power supply potential”, the input signal potential becomes the logical level of the numerical value 2 by the overshooting. It is often the case that the logic level of 0 is reached due to the undershooting or even the ternary circuit.
(Generation of multi-value hazard due to overshooting etc.)
→→ (Second issue to be solved by the second invention of the prior application)
For example, if this is a quaternary circuit of numerical values 0 to 3, the “potential difference corresponding to the numerical value 0 and the numerical value 2” is usually twice the “potential difference corresponding to the numerical value 2 and the numerical value 3”.・ "Potential difference corresponding to numerical value 3" is usually three times "potential difference corresponding to numerical value 3 and numerical value 4", so when the numerical value changes, the input signal potential is very easily " The next logical level can be reached past the "logical level of the numerical value that should be headed". As the number of overshooting or undershooting vibrations increases, the number of times that the adjacent logic level is reached also increases, and the number of generated hazard pulses increases.
(Generation of multi-value hazard due to overshooting etc.)
→→ (Second issue to be solved by the second invention of the prior application)
Moreover, even if one hazard pulse is generated, it will naturally be ignored if the hazard pulses in the multi-valued circuit are summed up because “the dust accumulates”, but the increase in the number of generated hazard pulses is “on”. "Increase in switching (power) loss when switching off" and "In the case of MOS / FET, increase in power loss due to charge / discharge of gate-source capacitance".
(Further increase in power loss)
→→ (● The third problem to be solved by the second invention of the prior application)

In the case of a binary circuit, there are only two values, 0 and 1, that is, there are only two types of maximum power supply potential and minimum power supply potential. By over-shooting or under-shooting the input portion by diode-clamping one diode in each direction, there is no problem of over-shooting or under-shooting as described above.
However, in the case of a multi-value circuit, since there is at least one intermediate power supply potential, the technique of “clamping the input signal potential to the intermediate power supply potential” cannot be used. This is because if the input signal potential of the subsequent circuit is diode-clamped in one direction even to one of its intermediate power supply potentials, the output circuit of the preceding circuit will have a voltage other than the intermediate power supply potential so that the forward voltage of the diode is obtained. This is because when the power supply potential is output, the output section and the clamp diode cause a power supply short circuit.

■■ Detailed explanation of the fourth problem to be solved by the second invention of the prior application ■■
First, the larger the multi-value number, the more “the number of logic levels that are in the middle of passing when the logic level of the multi-value signal changes”, and the greater the number of multi-value hazards. As the number of stages of the multi-value circuit is increased, the effect of amplifying / increasing the number of occurrences becomes stronger, and the adverse effects of the first and third problems also increase.
***
Secondly, the larger the multi-value number, the greater the change in the potential difference corresponding to the change in the numerical value, such as “change from a small numerical value to a large numerical value, or change from a large numerical value to a small numerical value. When the amplitude of the overshooting or undershooting becomes larger, the logical level that should be headed after reaching the next logical level next to the adjacent logical level due to the excessive swing. Returning to “more transient hazards” will occur.
In addition, since the adjacent logic level is often on both the high-potential side and the low-potential side of the logic level to which it is to go, further “more transient hazards” often occur. Therefore, the adverse effects of the second and third problems are also increased.
Of course, the greater the “number of oscillations of the overshooting or undershooting until convergence”, the greater the number of times that the adjacent logic level is reached, and the number of generated hazard pulses increases. The adverse effect spreads depending on the number of connection stages of the multi-value circuit.
***
Therefore, in terms of both the “magnitude and number of vibrations”, “the larger the multi-value number, the greater the problems and adverse effects of multi-value hazards”. (Fourth problem to be solved by the second invention of the prior application)

■■ Detailed explanation of the fifth problem to be solved by the second invention of the prior application ■■
Then, another multilevel hazard removal method is disclosed in the above-mentioned “Example 10 (paragraph number 0035) of Japanese Patent Laid-Open No. 2006-345468 or both FIGS. 18 and 15 of Japanese Patent Laid-Open No. 2007-35233”. One conventional multi-level synchronous latching means is provided between each of the "multi-level logic circuit based on a new multi-level logic [Fuji algebra]" connected in multiple stages before and after, and removed in the same manner. However, in addition to the “problem to be solved by the first invention of the prior application” which will be described later (paragraph number [0138]), “a range within the circuit affected by the generated multi-value hazard is slightly I want to make it narrower ”.
First, since the generation source of the multi-valued hazard (explained in paragraph numbers [0131 to 0134]) is the numerical value determination means of the multi-value logic circuit, the multi-value hazard generated by the numerical value determination means is the first. The value hazard is transmitted to the output switch section through the on / off driving means in the circuit and the subsequent stage, and the propagation is blocked by the multi-value synchronous latching means outside and behind the circuit.
Further, if the numerical value judging means starts to generate the multi-value hazard, it is a time when the output of the multi-value synchronous latching means outside the circuit and in the previous stage changes.
Therefore, the multi-level logic circuit between the two stages of the multi-level logic circuit, that is, the multi-level synchronous type latching means, that is, the multi-level logic circuit and the middle (the tenth) shows the effect of the multi-level hazard as However, it will be received as described above (the previous paragraph). This applies similarly to all of the “multi-value logic circuit sandwiched between two multi-value synchronous latching means connected to the preceding stage and the latter stage”.
For this reason, there is a problem that “if possible, I would like to narrow the range in the circuit affected by the generated multi-value hazard as much as possible”. (Fifth problem to be solved by the second invention of the prior application)

◇◇◇ Summary of prior application ◇◇◇
◇◇ ◆ Problems to be solved by the invention of the prior application ◆ ◇◇

■■■ Problems to be solved by the first invention of the prior application ■■■
For that reason (paragraph numbers 0118 to 0122), the conventional multi-level synchronous latching means has the following five problems.
◆ 1) Positive and negative edge trigger methods cannot be used.
→→ For example, if each edge trigger method can be used, in particular, the stepwise multilevel synchronization signal considered by the present inventor (the waveform shown in FIG. 4 of the following Patent Document 11). This makes it very convenient to increase the number of trigger timing options during one synchronization period.
◆ 2) “Output open or signal status corresponding to open output” cannot be latched.
* Note: The "Fuji algebra" mentioned above has a unique output method of "releasing output".
◆ 3) It does not have a latching function according to the “output numerical value”, resulting in waste.
→→ When only a part of the all-number latching function is used, waste is generated both in terms of effective use of the parts / circuits and power loss.
4) Multi-value circuit to be used {Example: Multi-value logic circuit, multi-value arithmetic circuit (or multi-ary arithmetic circuit), multi-value memory circuit, multi-value digital circuit, etc. }, It is desirable that there are many options of the multi-level synchronous latching means connected to the subsequent stage in accordance with the configuration of {}. When there are many choices, flexibility occurs in the configuration of the entire multi-value circuit.
◆ 5) It is desirable that there are many choices of the latching location “where to latch in the entire circuit”.
→→ Conventionally, a multi-value synchronous latching means must be provided between the multi-value circuit and the multi-value circuit, and the latching location is fixed. If there are many choices of the latching location, the configuration of the entire circuit becomes flexible.
JP-A-2006-345468 (multi-value storage means, multi-value transfer gate means, multi-value synchronous latch means, and multi-value synchronization signal generating means).

■■ Purpose of the first invention of the prior application ■■
Accordingly, the first invention of the prior application aims to provide a “multi-valued logic means having a synchronous latching function” having the following five effects.
◆ 1) Each trigger method (eg, edge trigger, level trigger, pulse trigger) of binary synchronous flip-flop means can be used.
(First effect of the first invention of the prior application)
◆ 2) “Output open or signal state corresponding to open output” can be latched.
(Second effect of the first invention of the prior application)
◆ 3) Since there is no latching function for “Each numerical value other than the output numerical value (= specific integer for output)”, a latching function corresponding to the “output numerical value” is provided, and no waste occurs.
(Third effect of the first invention of the prior application)
→→ Since there are no useless parts and useless configurations, parts and circuits can be used efficiently and power consumption can be saved.
4) Multi-value circuit to be used {Example: multi-value logic circuit, multi-value arithmetic circuit (or multi-ary arithmetic circuit), multi-value storage means, multi-value digital circuit, etc. }, The number of options of the multi-level synchronous latching means to be connected to the subsequent stage is increased according to the configuration of {}. Flexibility occurs in the configuration of the entire multi-value circuit. (Fourth effect of the first invention of the prior application)
→→ In the case of each multi-value logic circuit based on “Fuji algebra”, the “numerical value” latched by the constant potential supply means (eg, power line, power plate, etc.) connected to this circuit can be easily changed. The circuit to be used can be selected from the various multi-value logic circuits. In the first invention of the prior application, each multi-level logic circuit is provided with a synchronous latching function, so that the number of options for the multi-level synchronous latching means is increased.
→→ For example, the various invented multi-value logic circuits are called “(multi-value) AND circuit, (multi-value) OR circuit, OVER circuit, EVEN circuit, UNDER circuit, IN circuit, OUT circuit, etc.” There is a circuit.
◆ 5) The number of options for the latching location “where to latch in the entire circuit” increases, which is convenient. Flexibility occurs in the configuration of the entire circuit. (Fifth effect of the first invention of the prior application)
→→ The multi-value logic means of the first invention of the prior application itself has a synchronization latching function, so that the option of "no need to provide multi-value synchronous latching means between multi-value circuits and multi-value circuits" Is added.

■■■ Problems to be solved by the second invention of the prior application ■■■
As described above (paragraph numbers [0130 to 0136]), “hazard” generally becomes a “ghost signal, ghost data or ghost information” as “signal noise” in both conventional binary circuits and multi-value circuits. Correspondingly, it prevents the transmission of the real “signal, data or information” and “where” and “where” or “where” to “where” is the real “signal, data or information”. Make it difficult to understand. The “hazard” adversely affects other circuit operations (malfunctions, useless circuit operations, etc.).
In addition, the five problems of the conventional multilevel logic circuit are summarized as follows.
◆ 1) In addition to the hazard problem that occurs in the same mechanism as the conventional binary hazard, there are three or more logical values and logic levels, so “when the logic level of a multilevel signal changes, A multi-level inherent circuit failure and a multi-level hazard that “transient hazards occur by passing through the logic level” are particularly significant issues.
(First solution of the second invention of the prior application)
★ Reference: 13th to 10th lines from the back of the bottom of Non-Patent Document 9 below. Multi-valued inherent hazard.
◆ 2) “Similarly, when the logic level of a certain multi-level signal changes, it is too much shaken by overshooting or undershooting, passes the logic level that should be headed, reaches the next logic level, and then the logic that heads. A multi-valued inherent circuit failure and multi-valued hazard that “transient hazards occur by returning to the level” are particularly serious problems. (Second solution of the second invention of the prior application)
◆ 3) The problem with multi-level circuits is that “multi-level hazards lead to amplification and increase of power loss”. (Third solution to the second invention of the prior application)
(4) The larger the multi-value number, the greater the adverse effect of each of the first to third problems. Therefore, “the larger the multi-value logic circuit, the greater the adverse effect of the multi-value hazard”.
(Fourth solution to the second invention of the prior application)
◆ 5) Even if a possible conventional multi-value hazard removal circuit is used, the effect of the multi-value hazard is unavoidable in the previous stage of the circuit before removing the multi-value hazard. Want to be as small as possible.
Therefore, there is a problem that “if possible, I would like to narrow the range in the circuit affected by the generated multi-value hazard as much as possible”. (First solution of the second invention of the prior application)

■■ Purpose of the second invention of the prior application ■■
Accordingly, the second invention of the prior application is that “in addition to multi-value hazards generated by the same mechanism as binary hazards, multi-value hazards peculiar to multi-values can be removed” The purpose of the present invention is to provide a multi-value hazard removal means that can narrow the range in the circuit affected by the value hazard as much as possible.

◇◇ ◆ Means to solve the problem ◆ ◇◇
■■■ “Means for solving the problems” of the first invention of the prior application ■■■
That is, the first invention of the prior application is
When a predetermined plural number of 3 or 3 is represented by N and a predetermined natural number is represented by S,
“N constant potentials that increase or decrease in numerical order from the first constant potential to the Nth constant potential” are supplied, and each constant potential and 0 to (N -1), the first constant potential supply means to the Nth constant potential supply means defined as one-to-one correspondence with the first constant potential in order from the integer 0, "
“First to Sth Inlet Means for Incoming S Input Potential Signals”,
“Exit means for exiting output potential signal”;
“When connected between the“ first constant potential supply means to one predetermined constant potential supply means for output among the first constant potential supply means to the Nth constant potential supply means ”and the outlet means, "Pull switching means that is turned off in one or both directions";
““ When S = 1, an input integer corresponding to one of the input potential signals, and when S ≧ 2, [all of the S input integers corresponding one-to-one with each of the S input potential signals. ] Or [At least one of S input integers corresponding one-to-one with each of the S input potential signals] ”is determined in advance in [integer 0 to (N−1)]. It is equal to or not equal to one input specific integer], [is greater than one input specific integer predetermined in integer 0 to (N−2)], or [integer 1 to (N -1) smaller than or not one input specific integer predetermined in advance], [two predetermined in integer 0 to (N-1), the difference of which is at least 2 Any one of the input integers or not] Is determined as affirmative or negative based on “two or four threshold potentials in the following (= paragraph numbers [0143 to 0144]”) applied thereto, and the determination result is output as a determination result signal. Numeric discrimination means "
“Binary synchronous flip-flop means for inputting the determination result signal“ as is or matched ”as a holding signal based on the synchronizing signal and outputting a“ positive output signal or complementary output signal ”of the holding signal; ,
“Synchronizing signal supply means for supplying the synchronizing signal to the binary synchronous flip-flop means”;
“The pull switching means is driven on and off based on“ the positive output signal or the complementary output signal ”, but“ the determination result at the time of input indicated by the output signal based on that is positive. If it is negative, drive it off, or if it is negative, drive it off ”or“ If it is affirmative, drive it off, and if it is negative, drive it on ”on / off drive means”,
Is a multi-value logic means having a synchronous latching function.
However, the meaning of “less than one input specific integer” does not include the one input specific integer, and the meaning of “greater than one input specific integer” means that one input. The specific integer for use is not included, and the meaning of “between two input specific integers” does not include the two input specific integers.

■■ Two or four threshold potentials ■■
(1) When these constant potentials increase in numerical order from the first constant potential to the Nth constant potential,
● a) “Equal or not”:
* In the case of “equal to”, “a positive threshold potential and a negative threshold potential determined in advance with reference to an input specific constant potential corresponding to the input specific integer”. However, when the specific integer for input is 0, only the positive threshold potential is obtained, and when the specific integer for input is (N-1), only the negative threshold potential is obtained.
* In the case of “not so”, “a negative threshold potential determined in advance with reference to a constant potential one of the first constant potential to the Nth constant potential that is one higher than the specific constant potential for input” “A positive threshold potential determined in advance with reference to a constant potential one lower than the specific constant potential for input among the first constant potential to the Nth constant potential”. However, when the specific integer for input is 0, only the negative threshold potential is obtained, and when the specific integer for input is (N-1), only the positive threshold potential is obtained.
● b) If “Large or not”:
* In the case of “larger”, “the predetermined constant of the first constant potential to the Nth constant potential is determined in advance with reference to a constant potential that is one higher than the“ specific constant potential for input corresponding to the specific integer for input ”. Negative threshold potential ”.
* In the case of “not so”, “a positive threshold potential determined in advance on the basis of the specific constant potential for input”.
● c) “Small or not”:
* “It is small” is “predetermined on the basis of a constant potential one lower than the“ specific constant potential for input corresponding to the specific integer for input ”among the first constant potential to the Nth constant potential”. “Positive side threshold potential”.
* "If not" is "a negative threshold potential determined in advance with reference to the input specific constant potential".
D) In the case of “whether or not between two specific integers for input”:
* “Is it between the two?” Means that “of the first constant potential to the Nth constant potential, the lower constant of the two input specific constant potentials corresponding to the two input specific integers. Among the first constant potential to the Nth constant potential, “of the two input specific constant potentials”. “Higher constant potential” is a positive threshold potential determined in advance based on a constant potential one level lower than “the higher constant potential”.
* In the case of “not”, “the positive threshold potential determined in advance with respect to the lower constant potential of the two input specific constant potentials” and “the two specific input constant potentials” The negative threshold potential determined in advance based on the higher constant potential.

(2) When these constant potentials decrease in numerical order from the first constant potential to the Nth constant potential,
● a) “Equal or not”:
* In the case of “equal to”, “a positive threshold potential and a negative threshold potential determined in advance with reference to an input specific constant potential corresponding to the input specific integer”. However, when the specific integer for input is 0, only the negative threshold potential is obtained, and when the specific integer for input is (N-1), only the positive threshold potential is obtained.
* In the case of “not so”, “a negative threshold potential determined in advance with reference to a constant potential one of the first constant potential to the Nth constant potential that is one higher than the specific constant potential for input” “A positive threshold potential determined in advance with reference to a constant potential one lower than the specific constant potential for input among the first constant potential to the Nth constant potential”. However, when the specific integer for input is 0, only the positive threshold potential is obtained, and when the specific integer for input is (N-1), only the negative threshold potential is obtained.
● b) If “Large or not”:
* In the case of “larger”, “it is determined in advance from the first constant potential to the Nth constant potential based on a constant potential that is one lower than the“ input specific constant potential corresponding to the input specific integer ”. Plus threshold potential.
* "If not" is "a negative threshold potential determined in advance with reference to the input specific constant potential".
● c) “Small or not”:
* In the case of “smaller”, “it is determined in advance from the first constant potential to the Nth constant potential, based on a constant potential one level higher than“ the specific constant potential for input corresponding to the specific integer for input ”. Negative threshold potential ”.
* In the case of “not so”, “a positive threshold potential determined in advance on the basis of the specific constant potential for input”.
D) In the case of “whether or not between two specific integers for input”:
* “Is it between the two?” Means that “of the first constant potential to the Nth constant potential, the lower constant of the two input specific constant potentials corresponding to the two input specific integers. Among the first constant potential to the Nth constant potential, “of the two input specific constant potentials”. “Higher constant potential” is a positive threshold potential determined in advance based on a constant potential one level lower than “the higher constant potential”.
* In the case of “not”, “the positive threshold potential determined in advance with respect to the lower constant potential of the two input specific constant potentials” and “the two specific input constant potentials” The negative threshold potential determined in advance based on the higher constant potential.

Thus, the “means for solving the problems” of the first invention of the prior application is the conventional “multi-level logic circuit based on“ Fuji algebra ”” and the binary synchronous flip-flop means and the supply of the synchronization signal. It becomes a “multi-valued logic means having a synchronous latching function” by incorporating means.
The conventional multi-value logic circuit includes the “first constant potential supply means to Nth constant potential supply means”, the “first inlet means to Sth inlet means”, the “exit means”, the “pull Switching means "," numerical value discrimination means "and" on / off drive means ". In this conventional multi-value logic circuit, the on / off drive means is the pull switching means based on the discrimination result signal. Is driven on and off.
In this way, the binary circuit can be incorporated into the multi-value circuit as described later (paragraph numbers 0151 to 0152) “in the middle of the multi-value signal transmission (eg: the numerical value discriminating means and the on / off driving means Even if a binary circuit is inserted and connected in between), the connectivity between this binary circuit and its pre-stage and post-stage is extremely good, and [between its pre-stage and binary circuit] is also [ This is because “a multi-valued logic circuit based on the Fuji algebra” has a unique effect that “a special interface is not necessary between and the latter stage”.
However, there are cases where both can be connected as they are, but there are also cases where they are connected by matching.
Also, the end of the later paragraph (paragraph number [0157] ◇ 1). In some cases, the binary synchronous flip-flop means also serves as the on / off driving means.
Further, “determining whether or not the S input integers (= S integers corresponding to each of the S input potential signals on a one-to-one basis) is equal to or not equal to the one input specific integer. Is the same as “determining whether or not the S input integers are between“ two integers on both sides of the one input specific integer ”” and “the S input integers” "Determining whether the input integer of is equal to or not equal to 0" is the same as "determining whether the S input integers are less than or not 1" and " “Determining whether an input integer is equal to or not equal to (N−1)” is the same as “determining whether the S input integers are greater than (N−2)” or not. Numerous discrimination is difficult, and these discriminations are redundant. There.

As a result, since the binary synchronous flip-flop means can be built in between the numerical value discriminating means and the on / off driving means, each binary trigger method (eg, plus, minus edge)・ Triggers, level triggers, and pulse triggers can be used as they are. (First effect of the first invention of the prior application)
In particular, the stepwise multi-level synchronization signal (the waveform of FIG. 4 of Patent Document 11 considered by the present inventor. There are a plurality of rising portions, falling portions, or horizontal portions) can be used more effectively. Since this is possible, the number of trigger timing options increases during one period of the synchronization signal, which is very convenient.
This is because, depending on which of the two constant potential supply means (for example, two power supply lines) the binary synchronous flip-flop means is connected, a plurality of “rising points or falling points or horizontal portions” are used. This is because one can be selected.
If the binary synchronous flip-flop means satisfies the requirements of the on / off drive means, such as the output current capacity of the binary synchronous flip-flop means is large, the binary synchronous flip-flop Of course, the flop means may also serve as the on / off driving means.
In addition, the binary synchronous flip-flop means only latches either “signal state corresponding to a specific integer for output of the multi-value logic means” or “signal state corresponding to output open or open output”. Of course, the “signal state corresponding to the output open or open output” can be latched. (Second effect of the first invention of the prior application)
◆ Furthermore, since there is no latching function for “each numerical value other than the output numerical value (= specific integer for output)”, a latching function corresponding to “output numerical value” is provided, so that no waste occurs. (Third effect of the first invention of the prior application)
→→ Since there are no useless parts and useless configurations, parts and circuits can be used efficiently and power consumption can be saved.
◆ Then, the multi-value circuit to be used {example: multi-value logic circuit, multi-value arithmetic circuit (or multi-ary arithmetic circuit), multi-value digital circuit, etc. }, The number of options of the multi-level synchronous latching means to be connected to the subsequent stage is increased according to the configuration of {}. Flexibility occurs in the overall circuit configuration.
(Fourth effect of the first invention of the prior application)
→→ In the case of a multi-valued logic circuit based on “Fuji algebra”, its numerical identification means, pull-switching means, constant potential supply means (for example, power supply line, power supply plate, etc.) connected to each input specific integer, Both the output specific integers can be easily changed, and the circuit to be used can be selected from the various multi-value logic circuits. In the first invention of the prior application, each multi-level logic circuit is provided with a synchronous latching function, so that the number of options for the multi-level synchronous latching means is increased.
→→ For example, the various invented multi-value logic circuits are called “(multi-value) AND circuit, (multi-value) OR circuit, OVER circuit, EVEN circuit, UNDER circuit, IN circuit, OUT circuit, etc.” There is a circuit.
◆ And the number of options for the latching part “where to latch in the entire circuit” increases, which is convenient. Flexibility occurs in the overall circuit configuration. (Fifth effect of the first invention of the prior application)
→→ The multi-value logic means of the first invention of the prior application itself has a synchronization latching function, so that the option of "no need to provide multi-value synchronous latching means between multi-value circuits and multi-value circuits" Is added.

Note that N (≧ 3) indicates a multi-value number N of N values, and the integer used is 0 to (N−1). The first constant potential is an integer 0, the second constant potential is an integer 1, the third constant potential is an integer 2, and so on. The Nth constant potential is defined as corresponding to an integer (N-1).
→→ [Potential mode (or voltage mode)]
Therefore, it is defined as follows in relation to the logic level on the input side. However, since the expression “H level, L level” in a binary circuit cannot be used in a multi-value circuit, for example, “numerical level… logical level” or “specific integer level… logical level” is specifically output. I have to express it. As a matter of course, the logical level areas do not overlap each other, and one margin area between the two areas is set between each of the “two logical level areas adjacent to each other”.
◆ When these constant potentials “go higher” in numerical order from the first constant potential to the Nth constant potential:
The “first constant potential region lower than the positive side threshold potential with reference to the first constant potential” is the logic level region of the integer 0, and “the negative side threshold potential with reference to the second constant potential. The second constant potential region between the positive-side threshold potential and the logic level region of integer 1. In the same manner, “the third constant potential between the negative threshold potential and the positive threshold potential with reference to each constant potential from the third constant potential to the (N−1) th constant potential in order. The (N-1) th constant potential region from the potential region is sequentially “the logic level region of integer 2 to the logic level region of integer (N−2)”. The “Nth constant potential region higher than the negative threshold potential with reference to the Nth constant potential” is an integer (N−1) logic level region.
◆ When these constant potentials “go down” in numerical order from the first constant potential to the Nth constant potential:
The “first constant potential region that is higher than the negative threshold potential with reference to the first constant potential” is the logic level region with an integer 0, and “the positive threshold potential with reference to the second constant potential. The second constant potential region between the negative-side threshold potential and the logic level region of integer 1. Hereinafter, in the same manner, “a third constant potential between a positive threshold potential and a negative threshold potential with reference to each constant potential from the third constant potential to the (N−1) th constant potential in order. The (N-1) th constant potential region from the potential region is sequentially “the logic level region of integer 2 to the logic level region of integer (N−2)”. The “Nth constant potential region lower than the positive threshold potential with respect to the Nth constant potential” is an integer (N−1) logic level region.
As a result, if the input potential signal is in the first constant potential region in either case of “increase” or “increase”, “the corresponding input integer” is 0. If the input potential signal is within the second constant potential region, it is determined that “the corresponding input integer” is 1. Similarly, if the input potential signal is in order from the third constant potential region to the Nth constant potential region, the “corresponding input integer” is sequentially reduced from 2 to (N−1). It is determined that

However, the above-mentioned determination content of “how is it with respect to one or two predetermined input specific values” (e.g., whether it is equal or not, larger or not, smaller or not, There are only two or four of these threshold potentials to be applied every time. However, “the one specific integer for input can take any one integer value of“ integer 0 to integer (N−1) ””, that is, “when taking integer 0, when taking integer 1, integer 2” ..., And when taking an integer (N−1), each case is assumed. After all, “the relationship between each integer, each logic level, and each threshold potential” described above. Is derived.
The two input specific integers can also be any one of integer 0 to integer (N-3), while the smaller input specific integer can have the value of the larger input specific integer " Since any one of integers 2 to (N-1) can be taken according to the “specific integer for input”, the above-described “relationship between each integer, each logic level, and each threshold potential” is the same as above. Is derived.
By the way, when it is determined whether or not the S input integers (= S integers corresponding to each of the S input potential signals on a one-to-one basis) are between 2 and 5. For example, even if the S input integers are between 3 and 4, for example, and “do not get any”, it can be clearly determined that they are “between 2 and 5.” Similarly, when it is determined whether the S input integers are greater than 5 or not, even if the S input integers are between 7 and 8, for example, “Neither”, of course, “5 Greater than ". Similarly, when it is determined whether or not the S input integers are smaller than 6 or not, even if the S input integers are between 2 and 3, for example, and “do not get stuck”, “6 It is possible to determine that it is “smaller”.

Now, a specific integer for output is represented by m, and the logic level on the output side will be described. In the case of the multi-value logic means of the first invention of the prior application, the output is either one of the output specific integer m or the output release. Since the output specific constant potential supply means is selected from the first constant potential supply means to the Nth constant potential supply means, the output specific integer m is an integer 0 to (N−1). ) Can be any one integer value. Whichever integer value the output specific integer m takes, the logic level region of the output specific integer m always includes a margin and is included in the “input-side logic level region of integer m” in the subsequent circuit. It is set to be One or two margin areas are “noise margin against noise (or noise margin)”. This can be easily understood by considering the extension of the binary circuit.
Here, considering the (international) standardization and standardization of the standard and specification of each threshold potential, “what can be said about each input side logic level region of the subsequent circuit” is each of the multi-value logic means. Since it can also be said about the input side logic level area, the explanation of the output side and the logic level is, as a result, the multi-valued logic means. The “logic level area of the specific integer m for output” and “each input side logic level area” "Will be explained. Then, as the output specific integer m may take any integer value of “integer 0 to integer (N−1)”, the output side also sets each integer of 0 to (N−1). It is necessary to determine the corresponding logical level area.
Therefore, when these constant potentials “go higher” in numerical order from the first constant potential to the Nth constant potential, the negative thresholds of the input side logic levels of the integers 1 to (N−1) respectively. The “negative threshold potential of the output logic level” is higher than the potential by the noise margin on the minus side, and the positive threshold of the input logic level of each of the integer 0 to integer (N−2). The “positive side threshold potential of the output side logic level” is lower than the value potential by the noise margin on the positive side. Note that each threshold potential is as described above (paragraph numbers [0143 to 0144]).
On the other hand, when these constant potentials are “decreasing” in numerical order from the first constant potential to the Nth constant potential, the positive side threshold values of the input side logic levels of the integers 1 to (N−1). The positive threshold potential of the output logic level is lower than the potential by the noise margin on the plus side, and the negative threshold of the input logic level of each of integer 0 to integer (N-2). The “negative threshold potential of the output logic level” is higher than the value potential by the noise margin on the negative side. Note that each threshold potential is as described above (paragraph numbers [0143 to 0144]).
These things are the relationship between the “H level input potential (or input voltage), the H level output potential (or output voltage), and the H level noise margin” of the binary circuit and the “L level input potential (or It is easy to understand by considering “the relationship between the input voltage), the L level output potential (or output voltage), and the L level noise margin”. In the positive logic of the binary circuit, “the lower limit values of the H level input potential and the output potential are the negative side threshold potentials of the input side logic level and the output side logic level of the numerical value 1”, “The upper limit values of the L-level input potential and output potential are the positive-side threshold potentials of the input-side logic level and output-side logic level of numerical value 0”.
In spite of this, what is commonly referred to as “threshold potential (or voltage)” in a binary circuit is, for example, in the case of a CMOS inverter circuit, “a boundary where the operating state of PMOS and NMOS is reversed”, ie “circuit threshold potential (or Voltage) ”. There is an on / off threshold voltage of the semiconductor element.

“Introduction to Transistor Circuit 5: Digital Circuit Concept”, “4.6 Notes on Using Logic Circuits [1] Logic Voltage Level and Noise Margin” on pages 46-47. Supervision: Yoshifumi Amemiya and Nori Koshiba. Authors: Kensuke Shimizu and Masahiro Masakazu. Issued on May 20, 1981 by Ohm Co., Ltd. “A well understood digital electronic circuit”, “[1] Logic level to [2] Noise margin” on pages 76-80. Author: Keitaro Sekine, published by OHM Co., Ltd. on July 25, 1997. “Introduction to Logic Circuits”, “(1) Signal Voltage Value and Noise Margin” on pages 126-128. Author: Ryuji Hamabe, published by Morikita Publishing Co., Ltd. on September 28, 2001. “Pulse digital circuit”, “5-1. Amplitude characteristics of pulse digital circuit” on pages 125-130. Author: Akira Kawamata. Published by Nikkan Kogyo Shimbun on February 15, 1995. “Pulse and digital circuits”, “Threshold level” on page 128 and “Logic level” on page 129. Edit: Masao Yoneyama. Author: Shigeyuki Ohara, Sumio Yoshikawa, Toshio Shinozaki, Shiro Takahashi. Published by Tokai University Press on April 5, 2001. “Practical Introduction Series: How to Use CMOS Circuit [1]”, “Element Threshold Voltage” on page 44 and “Circuit Threshold Voltage” on page 50. Author: Yasoji Suzuki. Published on October 15, 1997 by the Industrial Research Committee.

Then, the “multi-value logic circuit on which the first invention of the first application was based” is a realization and implementation of a new multi-value logic “Fuji algebra”. In the three stages of the circuit part in the middle of signal transmission (for example, the numerical value determining means, the on / off driving means, and the pull switching means) [means on the previous stage side (for example, the numerical value determining means or the on / off state) [Connectivity between the output side of the off drive means.) And the binary circuit] and [Input side of the means at the subsequent stage (eg, the on / off drive means or the pull switching means) and the binary value. The connectivity between the circuits] is very good, and there is no special interface between them (ex. Binary / multi-value code conversion means, multi-value / binary code conversion means) ” There are features. (Unique effects and features of the multilevel logic circuit on which the first invention of the prior application was based)
The reason is as follows. The signal in the middle of transmission in the circuit is “at each output side of the numerical discriminating means and the on / off driving means“ affirmative or negative [the discrimination result signal and its on / off driving signal] ”, that is, a binary signal. “High / Low signal”, and “on each input side of the on / off drive means and the pull switching means,“ output a specific integer for that output (on drive) and open output (off) [The on / off signal and the on / off drive signal] corresponding to (at the time of driving) ”, that is, a binary signal, such as a High / Low signal”, the signal transmission middle part in the multi-value logic circuit is Excellent compatibility with binary circuits.

However, “the determination result signal and the on / off drive signal (both are like a binary signal, a high / low signal)” are “when they are the same as the“ H level and L level ”of a normal binary signal”. There are “provisional binary signals“ like H level and L level ”, which are different from the normal binary signals“ H level and L level ””. The “binary” and “provisional” binary signals are different from each other only in “potential level height” or “amplitude magnitude at level change”.
For example, even in a binary circuit, if the magnitude of each power supply voltage is different as in TTL and CMOS, the “height of the H level potential (or voltage)” and the “magnitude of the amplitude when the level changes” are different. In the positive logic, even if the potential level is different, the H level remains at the H level, and the numerical value 1 also remains at the numerical value 1.
On the other hand, when handling the H level and L level of a “normal or provisional” binary signal in a multi-value circuit, “three or more constant potentials corresponding to each integer one to one” or “ It is selected which of the two constant potentials to use from the added constant potential {example: power supply potential v _-1 of the power supply line V _{-1 in} FIG. 46} not included in these, According to the entire multi-value circuit, “the constant potential corresponding to the H level and L level” and “the level change” depending on “which constant potential is selected to be the power source for the binary circuit”. “Magnitude of time” is different.
If the constant potentials corresponding to the H level and L level are different from each other, the corresponding numerical values in the multi-value circuit are also different. The “2 numerical values corresponding to the H level and L level” are, for example, “9 and 0”, “8 and 5”, and “3 and 1”, which are not normally “1 and 0” of the binary circuit. There are many cases. This is because the multi-value circuit is considered as the center / reference, and each constant potential and each of the constant potential and each of the first means of the “means for solving the problems” (→ paragraph [0142]) of the first invention of the prior application This is because an integer relation is defined. Alternatively, in the case of “a completely different added constant potential”, the corresponding integer itself is not defined.
However, in general, a binary circuit of positive logic is originally considered based on itself as the center and reference. “While an input potential signal higher than the lower limit value of its own H level is determined as H level, It has a function of “determining an input potential signal lower than the upper limit value as an L level”. The first invention of the prior application effectively utilizes this discrimination function in the multi-value circuit. For this reason, the binary synchronous flip-flop means has a (voltage) matching function (eg, a voltage dividing function by a voltage dividing resistor connected to the input unit) if necessary in addition to the discrimination function. The provisional binary signal can be converted into a normal binary signal. The necessity of the matching depends on the withstand voltage of the input part of the binary synchronous flip-flop means.
Alternatively, the potential (or voltage) clamping means (for example, two clamping diodes) at the input part of the binary synchronous flip-flop means sets the temporary upper limit of the binary signal. While clamping to the positive constant potential of the binary circuit power supply, the lower limit of the temporary binary signal is clamped to the negative constant potential of the binary circuit power supply, and the temporary binary signal is normally Can be converted into a binary signal. In the first invention of the prior application, this conversion function is also effectively utilized in the multi-value circuit. In this case, if necessary, by having a kind of (impedance / matching) matching function (for example, insertion connection of a power supply short-circuit prevention resistor, resistor 28 in FIG. 1) Prevent short circuit.
The same applies to the case of a general negative logic binary circuit.

As mentioned above, taking into account the correspondence with the logical values, it is complicated to grasp the binary circuit and the multi-value circuit, but the above story is a matter of course if only a pure electronic circuit is considered. It is easy to grasp.
As for the synchronization signal of the binary synchronization flip-flop means, the synchronization signal supply means supplies "a synchronization signal that can be used by the binary synchronization flip-flop means". The signal supply means has the above-described matching functions, or uses the above-described binary circuit discrimination function or “conversion function by clamping”.
If the binary synchronous flip-flop means satisfies the requirements of the on / off driving means, such as the output current capacity of the binary synchronous flip-flop means is sufficiently large, the binary synchronous type Of course, the flip-flop means may also serve as the on / off driving means.

■■ “Means for solving the problems” of the second invention of the prior application ■■
In the “means for solving the problems” of the first invention of the prior application described above (paragraph numbers 0142 to 0144), that is, “multilevel logic means having a synchronous latching function”,
Based on the synchronization signal, during the “period in which no hazard appears in the discrimination result signal and the discrimination result signal is stable”, the binary synchronous flip-flop means uses the discrimination result signal as a holding signal “as is or matches. This is a multi-value hazard removing means for inputting.

As a result, the conventional binary hazard removal technique can be used for the “binary multi-value hazard appearing in the discrimination result signal”, so that the multi-value hazard can be removed. (effect)
The reason is as follows. Even if a multi-value signal is input to the multi-value logic circuit, it can be handled like a binary signal as described above (paragraph numbers 0151 to 0152) during signal transmission in the circuit. Even if a multi-value hazard occurs before or at the time of input, the multi-value signal can be handled like a binary signal including a binary hazard during the signal transmission. The binary hazard removal circuit and method can be utilized during the signal transmission.
In addition, since the period in which the multi-value hazard appears can be grasped in advance at the circuit design stage or the operation check stage, the timing of the multi-value hazard appearance and the timing of the synchronization signal (or clock pulse signal, etc.) is rubbed. Can be matched. For this reason, during the “period in which the binary hazard appears in the discrimination result signal”, the binary synchronous flip-flop means ignores the discrimination result signal based on the synchronization signal and holds the previous holding signal (or (Retained data) is retained.
On the other hand, the “binary synchronous flip-flop means incorporates the discrimination result signal based on the synchronization signal during a period when the binary hazard does not appear in the discrimination result signal and the discrimination result signal is stable”. Is held as a new / holding signal (or new / holding data), and the on / off driving is performed with the “positive output signal or complementary output signal” based on the new / holding signal (or holding data) as the on / off signal. Output to the means.
Similarly, the binary-synchronous flip-flop means rewrites the holding signal (or holding data) based on the synchronizing signal and reads “a positive output signal or a complementary output based on the holding signal (or holding data). Since the binary synchronous flip-flop means outputs a "binary signal obtained by removing a binary hazard from the binary signal being transmitted", the subsequent on / off driving means. Can be supplied to. As described above, the multi-value hazard removing means (= multi-value logic means having a multi-value hazard removing function) of the second invention of the prior application changes the multi-value hazard into a binary hazard during the signal transmission, It can be removed by applying a conventional binary hazard removal method. As a result, only the true “signal, data or information” portion can be extracted from the “multilevel signal including multilevel hazard”.
By the way, in the case of most conventional multi-value logic circuits, the multi-value hazard removal method in which a binary circuit (eg, flip-flop, etc.) is provided in the middle of signal transmission in this way cannot be applied. This is because in most cases, the signal in the middle of signal transmission is also a complete multi-value signal.

Then, since the binary-synchronous flip-flop means is immediately behind the “numerical value discrimination means that is one source of multi-valued hazards”, the binary-synchronous flip-flop means Since the multi-value hazard generated by the numerical discrimination means is immediately cut off, the multi-value hazard does not propagate to the on / off drive means and the pull switching means in the latter stage of the multi-value logic means. .
As a result, since “the range in the multi-value logic means affected by the generated multi-value hazard” is limited only to the numerical value determination means, “in the multi-value logic means affected by the generated multi-value hazard” The range can be narrowed even a little.

◇◇◇ Effect of prior application ◇◇◇
■■ Effects of the first invention of the prior application ■■
The effects of the first invention of the prior application are summarized as follows.
1) Since the binary synchronous flip-flop means can be built in between the numerical value discriminating means and the on / off driving means, each binary trigger method (eg, positive and negative edges)・ Triggers, level triggers, and pulse triggers can be used as they are. (First effect)
In particular, the step-like multilevel synchronization signal (the waveform shown in FIG. 4 of Japanese Patent Application Laid-Open No. 2006-345468, which has a plurality of rising points, falling points, or horizontal portions) considered by the present inventor is used more effectively. Therefore, the trigger timing options increase during one period of the synchronization signal, which is very convenient. This is because, depending on which of the two constant potential supply means (for example, two power supply lines) the binary synchronous flip-flop means is connected, a plurality of “rising points or falling points or horizontal portions” are used. This is because one can be selected.
If the binary synchronous flip-flop means satisfies the requirements of the on / off drive means, such as the output current capacity of the binary synchronous flip-flop means is large, the binary synchronous flip-flop Of course, the flop means may also serve as the on / off driving means.
2) Since the binary synchronous flip-flop means only latches either “signal state corresponding to the specific integer for output of the multi-value logic means” or “signal state corresponding to output open or open output”. Of course, the "signal state corresponding to the output open or open output" can be latched. (Second effect)
◆ 3) Since there is no latching function for each numerical value (= each integer) other than “output numerical value (= specific integer for output)”, a latching function corresponding to “output numerical value” is provided. There is no waste. (Third effect)
→→ Since there are no useless parts and useless configurations, parts and circuits can be used efficiently and power consumption can be saved.
4) Multi-value circuit to be used {Example: Multi-value logic circuit, multi-value arithmetic circuit (or multi-ary arithmetic circuit), multi-value digital circuit, etc. }, The number of options of the multi-level synchronous latching means to be connected to the subsequent stage is increased according to the configuration of {}. Flexibility occurs in the overall circuit configuration.
(4th effect)
→→ In the case of a multi-valued logic circuit based on “Fuji algebra”, its numerical identification means, pull-switching means, constant potential supply means (for example, power supply line, power supply plate, etc.) connected to each input specific integer, Both output specific integers can be easily changed, and a circuit to be used can be selected from various multi-value logic circuits (eg, AND circuit, OR circuit, OVER circuit, UNDER circuit, etc.). In the first invention of the prior application, each multi-level logic circuit is provided with a synchronous latching function, so that the number of options for the multi-level synchronous latching means is increased.
→→ For example, the various invented multi-value logic circuits are called “(multi-value) AND circuit, (multi-value) OR circuit, OVER circuit, EVEN circuit, UNDER circuit, IN circuit, OUT circuit, etc.” There is a circuit.
◆ 5) The number of options for the latching part “where to latch in the entire circuit” increases and becomes convenient. Flexibility occurs in the overall circuit configuration. (Fifth effect)
→→ The multi-value logic means of the first invention of the prior application itself has a synchronization latching function, so that the option of "no need to provide multi-value synchronous latching means between multi-value circuits and multi-value circuits" Is added.

■■ Effects of the second invention of the prior application ■■
The effects of the second invention of the prior application are summarized as follows.
In addition to multi-value hazards generated by the same mechanism as binary hazards, multi-value hazards inherent to multi-values can also be removed. (First effect)
→→ Only the true “signal, data or information” part can be extracted from the “multilevel signal including multilevel hazard”.
In addition, the range in the circuit affected by the generated multi-value hazard can be narrowed even a little. (Second effect)
These effects lead to reduction of multi-value hazard noise and power loss.
◇◇◇ Form for carrying out the invention of the prior application ◇◇◇
In order to explain the first and second inventions in more detail, these will be described with reference to the accompanying drawings. The following seven points of caution are stated first.
◆ 1) There are “explanations from the viewpoint of electronic circuits” and “explanations from the viewpoint of logic mathematics”, and there are also descriptions that are a mixture of both.
2) Each embodiment will be described mainly in the case where these constant potentials “go higher” in numerical order from the first constant potential to the Nth constant potential.
On the other hand, each example in the case where these constant potentials “become lower” is “each power source potential (corresponding to each of these constant potentials)” Each controllable switching means is replaced one by one with “controllable switching means in complementary relationship (eg, P-channel MOS • FET with respect to N-channel MOS • FET)” one by one. This corresponds to “an embodiment having a symmetrical relationship with respect to the voltage direction or the voltage polarity with respect to the original embodiment” in which the direction of each component having a voltage polarity (eg, diode) is reversed. However, in that case, the multi-value logic function may be the same as or different from the original circuit.
3) In each embodiment, n corresponds to the aforementioned N (predetermined plural).
◆ 4) The integer m corresponds to a specific integer for output, and corresponds to the above-mentioned specific constant potential for output of the output specific constant potential supply means (eg, power supply line V _m ) (eg, specific power supply potential v _m ). Is an integer. The relationship is “n−1 ≧ m ≧ 0”.
◆ 5) expressed in capital letters V _{"V G, V H, V m} , V -1, V 0, V 1~ V n-1, V n " in the power supply line, respectively, such as, represented by a lower case v etc. “V _G , v _H , v _m , v ₋₁ , v ₀ , v _{1 to} v _n−1 , v _n ” and the like represent the potentials (= constant potential) of these power supply lines in order, and the power supply potential The power supply potentials of v _{−1 to} v _n increase in this order. Of course, the power supply line V ₀ or other power supply line is “the main body of the circuit” or “the main body of the circuit device” or “the body of an automobile, motorcycle, bicycle, etc.” or “the hull of a ship” or “ "Body of hovercraft, etc. for two-purpose use" or "Body of airplane, helicopter, etc." or "Main body of space navigation, space station, etc." The potential of the main body, the vehicle body, the hull, and the celestial body becomes a reference potential such as a ground potential.
However, although one DC power supply for supplying DC voltage is connected between each of “two power supply lines adjacent to each other at the level of the power supply potential”, it is not shown.
◆ 6) For example, diodes 10, 12, 35, 36, “a pair of Zener diodes in which two Zener diodes are connected in series in the opposite direction”, etc. In the case of showing, it means that there are cases where the connection or insertion / connection is present and not.
7) “Two gate terminals or common gate terminals of the transistors 41, 47, and 48 are drawn, and each gate terminal is connected to the Q terminal (positive output terminal) of the D-type flip-flop 27. , “Is connected to the Q bar terminal (complementary output terminal)”.
Naturally, “change in connection from the Q terminal to the Q bar terminal” or “change in connection from the Q bar terminal to the Q terminal” means that the circuit after the connection change is different from the circuit before the connection change. It means that it becomes a negative circuit.
As a precaution, “Q bar” means a character in which a line is drawn on the letter Q.

◇ ◆ Prior application, Example 1 in Fig. 32 ◆ ◇
In the prior application / embodiment 1 of FIG. 32 (multi-value logic means having a synchronous latching function and multi-value hazard removing means), the respective constituent elements described above (paragraph numbers [0142 to 0144]) are as described above. S = 1, and “n ≧ 3” and “n−1 ≧ m ≧ 0”. Since the one output specific integer m also serves as the one input specific integer m, the output specific power supply potential v _m also serves as the input specific constant potential (→ paragraph number [0143]).
However, as described above (the last nine lines of paragraph number [0145]), “determining whether the one input integer is equal to or not the one input specific integer m” means “the one input integer. Is the same between the two input specific integers (m−1) and (m + 1) ”. Further, the power supply line V _n, etc. When n> m + 1 will be not shown.
A) The power supply potential v ₀ to the power supply potential v _n−1 are changed from the first constant potential to the Nth constant potential as described above (paragraph numbers [0142 to 0144]).
B) The power supply line V ₀ to the power supply line V _n−1 are the first constant potential supply means to the Nth constant potential supply means described above.
However, further or there is a power supply line _{V -1} supply potential _{v -1} under the power potential _{v 0,} or there is a further power supply line _{V n} of the power supply potential _{v n} on the power potential _{v n-1} Sometimes, there are cases. FIG. 32 shows only a part of the power supply lines.
C) The input terminal T _in serves as the first (S = 1) inlet means described above.
◆ d) The output terminal T _out is the outlet means described above.
E) The power supply line V _m serves as the above-mentioned output specific constant potential supply means (= input specific constant potential supply means).
◆ f) to a specific power supply voltage v _m is "specific input described above constant potential" and "specific constant potential output supplies its output a specific constant potential supply unit".
G) The series circuit of the transistors 3 and 4 is the aforementioned (bidirectional) pull switching means. ☆ Reference: JP 2005-236985 (Patent Document 3)
◆ h) “The circuit portion formed by the transistors 1, 2, 17, the diode 35 and the resistors 20, 21” is the numerical value discrimination means described above.
I) “Circuit part formed of transistors 41 and 37, diode 39 and resistor 15” is the on / off driving means described above.
J) The D-type flip-flop 27 is the binary synchronous flip-flop means described above.
◆ k) “Synchronous signal generating means 60, transistor 61, and circuit portion constituted by resistors 26 and 28” are the above-described synchronizing signal supply means.

If “D-type flip-flop 27, synchronization signal generating means 60, transistor 61 and resistors 26, 28” are removed and the gate of transistor 41 is directly connected to the anode of diode 35, “{power supply line V ₋₁ ,} Power supply line V ₀ to power supply line V _n−1 {, power supply line V _n }, transistors 1, 2, 3, 4, 17, 37, 41, diodes 35, 39, resistors 15, 20, 21 and the like (DC "Multi-valued logic circuit configured by a power supply not shown") is an asynchronous multi-valued logic circuit based on the aforementioned "Fuji algebra".
Further, the gate of the transistor 41 is connected to the Q terminal (positive output terminal) of the D-type flip-flop 27, but of course, it may be connected to the Q bar terminal (complementary output terminal).
Further, the transistor is changed by “changing the connection of each portion of the power supply lines V _{m−1 to} V _{m + 1} to which the transistors 1, 2, 17, 41 and the D-type flip-flop 27 are connected to the same high potential at the same time”. If the source of 41 is changed to the power line V _{m + 2} or “any power line having a higher potential”, a resistor or “two zener diodes are connected in series in reverse direction for voltage drop instead of the diode 39” Things can be used. In this case, the transistor 37 may be normally on (depletion mode).
Then, D-type sync signal input of the flip-flop 27 "identify the lower limit of the potential of the CP terminal power supply potential v clamping diode for clamping the _m (not shown.)" It is connected and the particular power supply potential v _{When m} is higher than the power supply potential v ₀ , the resistor 28 prevents the clamp diode and the transistor 61 from short-circuiting between both power supply lines V _m · V ₀ . When the specific power supply potential v _m = power supply potential v ₀ , the resistance value of the resistor 28 may be zero.
Of course, one DC power supply means (not shown) is connected between each “two power supply lines adjacent to each other at the level of the power supply potential”.

As described above, the output specific integer (= integer corresponding to the output specific constant potential) m also serves as the input specific integer (value), and the power supply line V _m is the input specific constant potential supply means and the output specific constant potential supply. also serves as a means, certain power potential v _m doubles as a certain constant potential output with a particular input constant potential.
"Input voltage v _{in (=} the potential of the input terminal T _in)", the relationship "the logic level of the threshold potential of the input specific integer m" and "input numerical value N _in corresponding to the input voltage v _in" following Street.
◆ 1) When specific integer m = 0:
If lower than the input potential v _in is the power supply potential v ₀ to the reference positive threshold potential, input numerical value N _in is determined that the integer 0, the input voltage v _in the one above "supply potential v ₀ of If it is higher than the negative threshold potential with reference to the power supply potential v ₁ ”, it is determined that the input numerical value N _in is not an integer 0.
◆ 2) When the specific integer m is “n−2 ≧ m ≧ 1”:
If there input potential v _in is a "between the positive side threshold potential and the negative side threshold potential relative to the specific power supply potential v _m", the input numeric N _in is determined that the integer m, the input potential v _in the "" specific power supply potential v power supply potential on the one than _m v _{m + 1} "higher than the negative threshold voltage relative to the" or "" specific power supply potential v below one than _m power supply potential v _{m- In the} case of “lower than the plus-side threshold potential with reference to ₁ ” ”, it is determined that the input numerical value N _in is not an integer m.
◆ 3) When a specific integer m = (n−1):
Is higher than the minus side threshold potential input potential _{v in} is the power supply potential _{v n-1} to the reference, the input numerical value _{N in} is determined that the integer (n-1), the input potential _{v in} the "power supply potential _{v n} If it is lower than the plus-side threshold potential with reference to the power supply potential v _n-2 that is one lower than _−1, it is determined that the input numerical value is not an integer (n−1).
Incidentally, normally taking into account the respective-noise margin (degrees), the negative side threshold potential of the input side logical level of a particular integer m certain supply potential v _m and a "specific supply potential v _m and a" specific power supply potential v while being set between the middle potential "of one power supply potential v _m-1 of below" _m, the plus side threshold potential of the input side logical level of a particular integer m is from "" specific power supply potential v _m 1 One power supply potential v _{m + 1} "on the middle potential" of a particular power supply potential v _m is set during a particular power supply potential v _m.
Of course, each noise margin (degree) is taken into consideration, but such a setting may be used instead of such a setting as “each threshold potential of binary TTL having no vertical symmetry”.

■ First, the operation of the original asynchronous / multi-valued logic circuit ■
“In the prior application of FIG. 32, the D-type flip-flop 27 is not inserted or connected in the first embodiment, and the gate of the transistor 41 is directly connected to the anode of the diode 35. The logic operation of the value logic circuit (reference: first in paragraph number 0161) is as follows.
Input numerical value _{N in} the input terminal _{T in} the transistor 1,2,17,37 is turned on when a particular integral m, since the transistor 41,3,4 is turned off, the output from the output terminal _{T out} is opened . On the other hand, "On the other hand either 1, 2," when the transistor input numerical value _{N in} the other than the specific integer m, 17,37 is turned off, in order to transistor 41,3,4 is turned on, the potential of the output terminal _{T out} becomes the specific supply potential v _m, the specific integer m is output. For this reason, the present inventor calls this asynchronous / multi-value logic circuit “(asynchronous /) multi-value (specific value) NOT (= knot) circuit”.
Accordingly, when the gate of the transistor 41 is connected to the Q terminal of the D-type flip-flop 27 in the prior application / embodiment 1 of FIG. 32, the present inventor determines that the prior application / embodiment 1 of FIG. Called “multi-value (specific value) NOT circuit”.
However, in the asynchronous multi-valued logic circuit, the drain signal of the transistor 17 is inverted by using a “binary NOT circuit (not shown) that takes its power supply from both power supply lines V _{m + 1} · V _m ”. 41, since the on / off operations of the transistors 41, 3 and 4 are opposite to each other, in this case, the present inventor designates the asynchronous type / multilevel logic circuit as "(asynchronous type) multilevel". (Specific value) EQUAL (= equal) circuit ”. Alternatively, there are “each circuit that the inventor has already called an asynchronous (multi-value specific value) OVER (= over) circuit or an asynchronous type (multi-value specific value) UNDER (= under) circuit”. The present inventors refer to the term “asynchronous (multi-value specific value) EVEN (= even) circuit” in golf terms. In this case, this negative circuit may be called an “asynchronous (multi-value specific value) NEVEN (= neven) circuit” instead of the “(asynchronous type) multi-value (specific value) NOT (= knot) circuit”.
Accordingly, when the gate of the transistor 41 is connected to the Q bar terminal of the D-type flip-flop 27 in the prior application / embodiment 1 of FIG. 32, the prior application / embodiment 1 of FIG. This is called a “synchronous EVEN circuit”.
Incidentally, the specific power supply potential v _m that satisfies "n-1 ≧ m ≧ 0" corresponds to a specific output integer m, the pull-open output of the output terminal T _out in which the power supply potential, for example, "the output terminal T _out up or pull-down or "or" is either "or the like for connecting the output terminal T _out and the output terminal T _out of another similar multivalued logic circuit, the output terminal Tout in any case the" multi-level Corresponding constant potential "can be output.

■ To synchronous type / multi-value logic circuit
The functions of the prior application / embodiment 1 of FIG. 32 are as follows. The “drain output signal of the transistor 17” and the “gate input signal of the transistor 41” are substantially signals like a binary circuit using the voltage between the power supply lines V _{m + 1} and V _m as a power source.
For this reason, as described above (paragraph numbers 0151 to 0152), the multi-value logic circuit based on the “Fuji algebra” “has extremely good connectivity with a binary circuit in the middle of signal transmission in the circuit, and specially in between. A unique interface (e.g., binary / multi-value code conversion means, multi-value / binary code conversion means) is not necessary ”.
(Unique effects of multi-valued logic circuits based on the "Fuji algebra")
The combination of the resistors 26 and 28 and “a means such as a binary / numerical value discriminating means or two clamp diodes in the CP input section of the D-type flip-flop 27” originally has a “deemed or converted” function. Yes. The “deemed or converted” function is to swing a “High / Low signal like a binary signal swinging between the power supply potential v ₀ and the power supply potential v _{m + 1”} between “the specific power supply potential v _m and the power supply potential v _{m + 1”.} This is a function that can be easily regarded as “normal binary signal” or can be easily converted into the normal binary signal.
However, a High / Low signal such as the binary signal can be regarded as a multi-level signal depending on numerical interpretation. →→ Paragraph number [0152] First half.
The “deemed or converted” function is “a numerical discriminating unit of a general binary circuit always outputs all“ (multi-value) potential signals or (multi-value) voltage signals ”higher than the lower limit value of the H level” to “H Binary circuit with unique operating characteristics that distinguishes all “(multi-valued) potential signals or (multi-valued) voltage signals” that are lower than the upper limit value of the L level ”and always distinguishes them from“ L level ”. Due to Alternatively, this is due to a binary circuit and a specific operation characteristic of “determining whether the rise from the L level to the H level or the fall from the H level to the L level”.

Alternatively, the “deemed or converted” function means that “the two clamp diodes in the input part of a general binary circuit have an upper limit of“ (multi-value) potential signal or (multi-value) voltage signal ””. while clamped to positive constant potential (or positive power supply voltage) v m _{+ 1,} the lower limit on the operating characteristics of the negative constant potential (or minus side power supply voltage) v is clamped to _m "of the binary circuit of the binary Is attributed.
In the case of the prior application / embodiment 1 shown in FIG. 32, the CP terminal / input section of the D-type flip-flop 27 is used as the “numerical value discrimination section or input section of the binary circuit”. The same applies to the 27 D terminals / input units. In other words, regarding the first and second inventions of the first and second inventions, the data input section (eg, the input section of the D terminal) of the binary synchronous flip-flop means which is one of the constituent means is “the input integer is for the one input. If the requirement of the numerical discriminating means for discriminating whether it is "larger or not larger" or "smaller or smaller" than a specific integer is satisfied, even if the binary synchronous flip-flop means also serves as the numerical discriminating means Of course.
For prior application, the first embodiment of FIG. 32, both the power supply line as the power is supplied from the power supply line V _{m + 1} and the power source line V _m of the binary circuit (= D-type flip-flop 27) is selected ing.

Further, the multi-value logic circuit based on the new multi-value logic “Hooji algebra” has extremely unique effects and features. This means that “connectivity with the binary circuit in the previous stage”, “connectivity with the binary circuit in the middle of signal transmission in the multi-level logic circuit”, and “connectivity with the binary circuit in the subsequent stage” are extremely good. Regardless of the multi-value number N, all multi-value logic functions can be expressed by a single basic multi-value logic circuit or a combination of them (complete system). ⇒ Completeness is also “complete”.
* Reference: Non-Patent Document 3, “Multi-valued information processing—Post-binary electronics”).
The proof of “perfect” in “Hooji algebra” has already been explained in paragraphs [0083-0096].
For this reason, a certain multi-value signal is input to the one type of multi-value logic circuit and is handled as a binary (target) signal as described above (paragraph number [0151 to 0152]) in the middle of signal transmission in the circuit. be able to. Even if a multi-value hazard occurs before or at the time of input, it can be treated as a binary (target) signal including a binary (target) hazard during the signal transmission. The hazard removal circuit and method can be utilized during the signal transmission.
Then, the period in which the multi-value hazard appears can be predicted or grasped in advance in the circuit design stage or the operation check stage, so that the appearance timing of the multi-value hazard and the “synchronization signal (or clock pulse signal etc.) input to the transistor 61” Can be rubbed together.
For example, during the “period in which the binary hazard appears in the drain output signal of the transistor 17”, the input synchronization signal of the transistor 61 is set to a low level or a high level. Ignore the output signal and continue to hold the previous hold signal (or hold data).
On the other hand, the D-type flip-flop is set so that the input synchronization signal of the transistor 61 falls during “a period in which the binary hazard does not appear in the drain output signal of the transistor 17 and the drain output signal is stable”. 27 takes in the drain output signal, holds it as a new holding signal (or holding data), and outputs it to the transistor 41 as it is.
Similarly, the D-type flip-flop 27 is configured to “rewrite its holding signal (or holding data)” and “hold / hold the new / holding signal (or new / holding data) based on the output synchronization signal of the transistor 61. Since the “output” is performed, the D-type flip-flop 27 outputs the “binary signal in which the binary hazard is removed from the binary signal being transmitted” to the subsequent on / off driving means. (Transistors 41, 37, etc.).
As described above, the prior application / embodiment 1 in FIG. 32 can treat a multi-value hazard as a binary hazard in the middle of signal transmission, so that the conventional binary hazard removal circuit and method are applied. Can be removed.

■ Explanation of operation of synchronous type multi-value logic circuit ■
When the gate of the transistor 41 is connected to the Q terminal of the D-type flip-flop 27 in the prior application / embodiment 1 of FIG. "Neven) circuit" or "synchronous NOT circuit". The circuit operation is as follows.
The “synchronizing signal generating means 60, the transistor 61, and the synchronizing signal supplying means constituted by the resistors 26 and 28” supply the synchronizing signal to the Q terminal of the D-type flip-flop 27. Based on this synchronizing signal, the D-type flip The flop 27 takes in the determination result signal from the transistor 17.
If shows a positive output signal of the intake discrimination result signal, that Q terminals may "input terminal T _in the input integer N _in the is an integer equal to the integer m", "on the transistor 41,37, etc. to form Since the “off driving means” drives the transistors 3 and 4 off, the output from the output terminal T _out is released.
However, if the positive output signal indicates that it is not, the on / off driving means drives the transistors 3 and 4 on, so that the specific power supply potential v _m is output from the output terminal T _{out in} terms of circuit. In terms of logical values, the output specific integer m is output.
Thereafter, the output state continues until the D-type flip-flop 27 takes in the next discrimination result signal from the transistor 17 based on the synchronization signal. Thereafter, similarly, the next determination result signal is taken in, and the same thing is repeated.

On the other hand, when the gate of the transistor 41 is connected to the Q bar terminal of the D-type flip-flop 27 in the prior application / embodiment 1 of FIG. "EVEN circuit" or "synchronous EQUAL circuit".
Since this circuit operation is a negative operation of the “synchronous NEVEN circuit”, the output from the output terminal T _out is just the opposite.

● Instead of the D-type flip-flop 27, a combination of “binary 3-state buffer improved to be conductive / non-conductive by edge trigger” and “binary memory means at the subsequent stage” or “ “Two stages connected to the preceding stage and the subsequent stage” (→→ substantially binary flip-flop means) may be used. (Derived Example)
● Also, there are three types of trigger methods in which the binary synchronous flip-flop means and binary three-state buffer means operate based on the synchronous signal (or clock pulse signal, etc.). It is also possible to change to another trigger method. (Derived Example)
B) Level trigger method b) Plus / minus edge trigger method c) Pulse trigger method (= master / slave method)
Furthermore, by reconnecting the drain of the transistor 3 from the power line V _m to any _one of the other power lines V _{0 to} V _m−1 , the specific integer for output is changed from m to 0 to (m−1). It can be changed to any one of these.
These things (the above combination, the above trigger methods, and the above-described connection change of the power supply line) are the same for the other embodiments.
P. Of "Introduction to Illustrated Digital Circuit". 79-p. 88. The 4th edition was published on April 25, 2008 by Nippon Riko Publishing Co., Ltd. Author: Tsuguo Nakamura. Reference: Each trigger method.

◇ ◆ Prior application, Example 2 ◆ ◇
The prior application / embodiment 2 shown in FIG. 33 is derived from the prior application / embodiment 1 of FIG. 32 or its derivative embodiments. As described above (paragraph number [0160], lines 6 to 10), “determining whether or not the one input integer N _in is equal to the one input specific integer m” means “the one It is the same as “determining whether or not the input integer N _in is between the two input specific integers (m−1) and (m + 1)”.
32 is the case where the number of integers between the two specific integers for input is one, the prior application / example 2 of FIG. 33 has two pieces. Is the case. For this reason, “whether the one input integer N _in is one of the integers between the two input specific integers (= is equal to either) or neither (= equal to either) In other words, the prior application / Example 2 of FIG.
The prior application / embodiment 2 in FIG. 33 is “the connection between the source and back gate of the transistor 1 and the back gate of the transistor 17” and the power line V _{m + 1} in the prior application / embodiment 1 of FIG. once disconnected, its source and those obtained reconnect to the "power line V _{m + 2 ~} power supply line V _n-1 of any one power line V _{H '".} That is, m + 2 ≦ H ≦ n−1.
However, if there is a “built-in clamp diode whose one end is connected to the power supply line V _{m + 1} ” at the D terminal, a power supply short-circuit prevention resistor is provided between the drain of the transistor 17 and the “connection point between the resistor 21 and the D terminal”. Need to be inserted and connected. (A kind of matching)
As a result, in the case of the following NIN circuit or IN circuit, two specific integers for input in the prior application / embodiment 2 are an integer (m−1) and “the number of the reconnected power line, that is,“ integer ( m + 2) to (n−1) ”is one integer H” corresponding to the power line. Details will be described later (paragraph numbers [0173 to 0177]).
Note that by reconnecting the drain of the transistor 3 from the power line V _m to any _one of the other power lines V _{0 to} V _m−1 , the output specific integer is changed from m to 0 to (m−1). It can be changed to any one.

When the gate of the transistor 41 is connected to the Q terminal of the D-type flip-flop 27 in the prior application / embodiment 2 of FIG. ) NOBETWEEN (= No Between. Negation of BETWEEN) "or" Synchronized (multi-value specific value) NIN (= Nin.IN negation) circuit "or" Synchronous (multi Value specific value) OUT (= out) circuit ”. Of course, if the D-type flip-flop 27 and the like are removed in these circuits and the gate of the transistor 41 is directly connected to the anode of the diode 35, these circuits become asynchronous.
However, in this case, the two specific integers of the IN circuit and the NIN circuit are (m−1) and H, but the two specific integers of the OUT circuit are m and (H−1). These will be described in detail later.
The circuit operation is as follows. The “synchronizing signal generating means 60, the transistor 61 and the synchronizing signal supplying means constituted by the resistors 26 and 28” supply the synchronizing signal to the CP terminal of the D-type flip-flop 27. Based on this synchronizing signal, the D-type flip The flop 27 takes in the determination result signal from the transistor 17.
Long as the positive output signal of the intake discrimination result signal, i.e. Q terminal indicates that the "input integer N _in the input terminal T _in is an integer there between the integer H integer (m-1)", " Since the on / off driving means formed by the transistors 41 and 37 etc. drives the transistors 3 and 4 off, the output from the output terminal T _out is released.
However, if the positive output signal indicates that it is not, the on / off driving means drives the transistors 3 and 4 on, so that the specific power supply potential v _m is output from the output terminal T _{out in} terms of circuit. In terms of logical values, the output specific integer m is output.
Thereafter, the output state continues until the D-type flip-flop 27 takes in the next discrimination result signal from the transistor 17 based on the synchronization signal. Thereafter, similarly, the next determination result signal is taken in, and the same thing is repeated.

On the other hand, when the gate of the transistor 41 is connected to the Q-bar terminal of the D-type flip-flop 27 in the prior application / embodiment 2, the present inventor states that the prior application / embodiment 2 is “synchronous (multi-value specific value)”. ) BETWEEN (= Between) circuit ”or“ synchronized (multi-value specific value) IN circuit ”or“ synchronous (multi-value specific value) NOUT (= Now. OUT negation) circuit ” "
Since this circuit operation is a negative operation of the “synchronous NIN circuit”, the way of output from the output terminal T _out is just opposite.

Of course, in these synchronous type “IN, NOUT” circuits, the D-type flip-flop 27 and the like are removed, and the power supply from both power supply lines V _{m + 1} and V _m is taken between the gate of the transistor 41 and the anode of the diode 35. If the “value inverter circuit” is connected and the drain signal of the transistor 17 is inverted, these circuits become asynchronous “IN, NOUT” circuits.
However, in the case of the synchronous OUT circuit and the synchronous NOUT circuit, the two specific integers for input are the integer m and ““ the number of the power line reconnected, that is, [of integers (m + 2) to (n−1). , An integer (H−1) ”obtained by subtracting 1 from one integer H]” corresponding to the power supply line. This is true even for asynchronous types. Details of this will be described later (paragraph numbers [0175 to 0176]).

The reason why the IN circuit and the NIN circuit are referred to based on the IN logic and the NIN logic is that “a specific integer a, b (where N−1 ≧ b ≧ a + 2 ≧ 2) If two are specified, the integer string is “an inner integer part consisting of [one or more integers] sandwiched between the two specified integers”, ie, each of the two specified integers. Of the three integers separated by the two specific integers, the inner integer part consisting of [one or more integers] inside it and the inner part not included in the inner integer part This is because it can be divided into “negative integer parts (including integers a and b)”.
Therefore, the present inventor uses the inner integer part of the former as a numerical discriminant criterion, “multi-value BETWEEN logic (Between) logic or multi-value IN (in) logic”, abbreviated “BETWEEN logic or IN logic”. On the other hand, the inner negative integer part of the latter is used as a numerical discriminant criterion, “multi-valued NOBETWEEN logic or multi-valued NIN logic”, abbreviated “NOBETWEEN logic or NIN logic”. I decided to call it.
Note that “IN” has a smaller number of characters, and since it begins with a vowel, the negation is convenient because it is sufficient to add “N” in front of it to “NIN”. In addition, the present inventor already has a multi-value specific value OVER logic (abbreviated OVER logic), a multi-value specific value UNDER (under) logic (abbreviated UNDER logic), and a multi-value specific value EVEN (abbreviated) logic (abbreviated). EVEN logic) is used, so it is convenient to unify the golf terms so that it is easy to remember.
Incidentally, there is the following way of dealing with multi-valued IN logic. Recalling the cross-section of a golf “hole or cup” and considering the walls on both sides as “two specific integers a, b” in the integer row, like the above-mentioned saddle, “hole in or cup” The inventor thinks that the term “multi-valued IN logic” is easy to remember from the association of “in”.

Here, the relationship between each of the IN logic and the NIN logic and the numerical value discrimination criteria and each of the logic outputs is summarized as follows.
● IN logic (also known as BETWEEN logic):
It is determined whether the one input integer N _in is one of its inner integer parts. That is, it is determined whether or not the one input integer N _in is an integer between the specific integers a and b. However, N is a multi-value number (N of N values), and N−1 ≧ b ≧ a + 2 ≧ 2.
Therefore,
If b> N _in > a, output a predetermined output specific integer,
If N _in ≧ b or a ≧ N _in , the output is released.
NIN logic (also known as NOBETWEEN logic):
Since it is negative of IN logic, it is determined whether or not that one input integer N _in is one of its inner negative integer parts. That is, the output method is opposite to the IN logic.
Therefore,
If b> N _in > a, release the output,
If N _in ≧ b or a ≧ N _in , a predetermined specific integer for output is output.

There is another way of calling, thinking. Specific integers a and b (where N-1> b ≧ a + 2> 2 in an integer sequence in which integers 0 to (N−1) are arranged in order. Note: This inequality is different from the case of IN logic.) If two are specified, the integer string is expressed as follows: “If each of the two specific integers is considered to be a 塀, the outer part consisting of a plurality of integers outside the three parts separated by the two specific integers. It can be divided into “integer part” and “outer negative integer part not included in the outer integer part (including two specific integers)”.
Therefore, the present inventor uses the former outer integer part as a numerical discrimination criterion and calls it “multi-valued OUT (out) logic, abbreviated as OUT logic”, while the latter outer negative integer part is used as a numerical discrimination criterion. We decided to call it "multi-valued NOUT logic".
***
★★ Difference between OUT logic and NIN logic ★★
The difference between OUT logic and NIN logic is that the two specific integers are not included in OUT and NIN is included.
★★ Difference between IN logic and NOUT logic ★★
The difference between IN logic and NOUT logic is that the two specific integers are not included in IN but NOUT.
***
Therefore, OUT (a, b) = NIN (a−1, b + 1), IN (a, b) = NOUT (a + 1, b−1), that is, NOUT (a, b) = IN (a−1, b + 1). It holds. However, two integer values in each parenthesis (parentheses) represent two specific integers for input. Of course, these things are true for both the asynchronous type and the synchronous type. However, the synchronous condition and the latching condition are the same for the synchronous type.

Here, the relationship between each (numerical value) discrimination criterion of OUT logic and NOUT logic and each logic output is summarized as follows.
● OUT logic:
It is determined whether the one input integer N _in is one of its outer integer parts. However, N is a multi-value number (N of N values), and N-1> b ≧ a + 2> 2 (* Note: this inequality is different from the case of IN logic).
Therefore,
If N _in > b or a> N _in , output a predetermined integer for output,
・ If b ≧ N _in ≧ a, the output is released.
● NOUT logic:
Since the OUT logic is negated, it is determined whether or not the one input integer is one of the outer negative integer parts. That is, the output method is the opposite of OUT logic.
Therefore,
If N _in > b or a> N _in , release the output,
If b ≧ N _in ≧ a, a predetermined specific integer for output is output.

The synchronous multi-value logic circuit described so far is of course included in the “multi-value logic means having a synchronous latching function” of the first invention of the prior application. These are summarized below.
☆ Synchronous EVEN circuit (also known as synchronous EQUAL circuit)
☆ Synchronous NEVEN circuit (also known as synchronous NOT circuit)
☆ Synchronous IN circuit (also known as synchronous BETWEEN circuit)
☆ Synchronous NIN circuit (also known as synchronous NOBETWEEN circuit)
☆ Synchronous OUT circuit ☆ Synchronous NOUT circuit

◇ ◆ Prior application, Example 3 ◆ ◇
The prior application / embodiment 3 shown in FIG. 34 is also derived from the prior application / embodiment 1 of FIG. 32 or its derivative embodiments. As described above (paragraph number [0160], lines 6 to 10), “determining whether or not the one input integer N _in is equal to the one input specific integer m” means “the one It is the same as “determining whether or not the input integer N _in is between the two input specific integers (m−1) and (m + 1)”.
The prior application / embodiment 1 in FIG. 32 is a case where the number of integers between the two specific integers for input is one, whereas the prior application / embodiment 3 is a case where the number is two. . For this reason, “whether the one input integer N _in is one of the integers between the two input specific integers (= is equal to) or neither (= is equal to either) In other words, the prior application / Example 3 is discriminated.
Prior application, the embodiment of FIG. 34 3 disconnects "the transistor 2 of the source and the back gate" to connect the power supply line V _m-1 once the prior application, Example 1 or each derived embodiments thereof "Figure 32, the source such as a those reconnect to "any one power line V _G of the power supply lines V _{0 ~} power supply line V _{m-2 '".} That is, 0 ≦ G ≦ m−2.

In the prior application / embodiment 3, when the gate of the transistor 41 is connected to the Q terminal of the D-type flip-flop 27, the inventor described the prior application / embodiment 3 as “synchronous NIN circuit” or “synchronous NOBETWEEN”. Circuit "or" Synchronous OUT circuit ".
The circuit operation is as follows. The “synchronizing signal generating means 60, the transistor 61 and the synchronizing signal supplying means constituted by the resistors 26 and 28” supply the synchronizing signal to the CP terminal of the D-type flip-flop 27. Based on this synchronizing signal, the D-type flip The flop 27 takes in the determination result signal from the transistor 17.
Long as the positive output signal of the intake discrimination result signal, i.e. Q terminal indicates that "an integer there between the input integer N _in an integer G and an integer input terminal T _in (m + 1)", "the transistor 41 , 37, etc. "drives the transistors 3 and 4 off, so that the output from the output terminal _Tout is released.
However, if the positive output signal indicates that it is not, the on / off driving means drives the transistors 3 and 4 on, so that the specific power supply potential v _m is output from the output terminal T _{out in} terms of circuit. In terms of logical values, the output specific integer m is output.
Thereafter, the output state continues until the D-type flip-flop 27 takes in the next discrimination result signal from the transistor 17 based on the synchronization signal. Thereafter, similarly, the next determination result signal is taken in, and the same thing is repeated.

On the other hand, when the gate of the transistor 41 is connected to the Q-bar terminal of the D-type flip-flop 27 in the prior application / embodiment 3 of FIG. Or “synchronous IN circuit” or “synchronous NOUT circuit”.
Since this circuit operation is a negative operation of the “synchronous NIN circuit”, the way of output from the output terminal T _out is just opposite.

In the case of the IN circuit or the NIN circuit, the two specified integers for input are an integer (m + 1) and “the number of the reconnected power line, that is,“ integer 0 to (m−2) ”. One integer G "corresponding to the line. On the other hand, in the case of the OUT circuit and the NOUT circuit, the two specific integers for input are the integer m and ““ the number of the reconnected power line, that is, among the integers 0 to (m−2), Integer (G + 1) ”obtained by adding 1 to the corresponding one integer G]”.
Further, by reconnecting the drain of the transistor 3 from the power line V _m to any _one of the other power lines V _{0 to} V _m−1 , the output specific integer is changed from m to 0 to (m−1). It can be changed to any one.

◇ ◆ Prior application, Example 4 ◆ ◇
The prior application / embodiment 4 shown in FIG. 35 is also derived from the prior application / embodiment 1 of FIG. 32 or its derivative embodiments. "Part one input integer N _in is possible to determine or not equal and its one input for a specific integer m", "" one of its inputs the integer N _in is for the first input before the description It is the same as “determining whether it is larger than the specific integer (m−1) and smaller than the second input specific integer (m + 1)” or not.
Then, “determining whether the one input integer N _in is between the two input specific integers a and b (≧ a + 2) or two integers” is “the one input integer. It is the same as “determining whether N _in is larger than the first input specific integer a and smaller than the second input specific integer b” or not.
For this reason, a part of the discrimination function of “the prior application / embodiment 1 of FIG. 32 or its derivative embodiments”, that is, “the one input integer N _in is not larger or larger than the first input specific integer a. The prior application / Embodiment 4 in which the “determination function” is eliminated can be a synchronous UNDER (under) circuit or a synchronous NUNDER circuit (= negative of the synchronous UNDER circuit).
Therefore, the prior application / embodiment 4 in FIG. 35 is “removing the transistors 2, 17, the diode 35, and the resistor 20 in the prior application / embodiment 1 of FIG. The “connection point of the D terminal of the flop 27” is reconnected to the drain of the transistor 1 ”.

When the gate of the transistor 41 is connected to the Q terminal of the D-type flip-flop 27 in the prior application / embodiment 4 of FIG. It is called a “synchronous OVER circuit”. Of course, both and input specific integers are different.
The circuit operation is as follows. The “synchronizing signal generating means 60, the transistor 61 and the synchronizing signal supplying means constituted by the resistors 26 and 28” supply the synchronizing signal to the CP terminal of the D-type flip-flop 27. Based on this synchronizing signal, the D-type flip The flop 27 takes in the determination result signal from the transistor 1.
If positive output signal of the intake discrimination result signal, i.e. Q terminal indicates that the "input integer N _in the input terminal T _in is an integer (m + 1) is smaller than the integer", the transistor 41,37, etc. to form Since the “on / off driving means” drives the transistors 3 and 4 off, the output from the output terminal T _out is released.
However, if a positive output signal is "otherwise" or "input integer N _in the input terminal T _in is an integer (m + 1) is greater than or equal to an integer" indicates the its on-off driving means transistor Since the circuits 3 and 4 are turned on, the specific power supply potential v _m is output from the output terminal T _{out in} terms of a circuit, and the output specific integer m is output in terms of a logical value.
Thereafter, the output state continues until the D-type flip-flop 27 takes in the next discrimination result signal from the transistor 1 based on the synchronization signal. Thereafter, similarly, the next determination result signal is taken in, and the same thing is repeated.

On the other hand, when the gate of the transistor 41 is connected to the Q-bar terminal of the D-type flip-flop 27 in the prior application / embodiment 4 of FIG. 35, the present inventor described the prior application / embodiment 4 as “synchronous UNDER circuit”. Or “synchronous NOVER circuit (= negation of synchronous OVER circuit)”. Of course, both and input specific integers are different.
Since this circuit operation is a negative operation of the “synchronous NUNDER circuit” or “synchronous OVER circuit”, the output method from the output terminal T _out is just opposite.

The difference between UNDER logic and NOVER logic is that UNDER does not include one specific integer for its own use, and NOVER includes one specific integer for its own use. The difference between the OVER logic and the NUNDER logic is “OVER does not include one specific integer for its own use, and NUNDER includes one specific integer for its own use”. Therefore, UNDER (m + 1) = NOVER (m) and NUNDER (m + 1) = OVER (m) hold. However, one integer value in each parenthesis represents one specific integer for input.
In addition, these things are valid for both the asynchronous type and the synchronous type, but naturally, the synchronous condition and the latching condition are the same in the synchronous type.
Furthermore, by reconnecting the “source and back gate of transistor 1” from the power supply line V _{m + 1} to any _one of the other power supply lines V _{m + 2 to} V _n−1 , each of the UNDER circuit and the NUNDER circuit is specified for each input. The integer can be changed from (m + 1) to “any one of (m + 2) to (n−1)”. However, when a “built-in clamp diode having one end connected to the power supply line V _{m + 1} ” is connected to the D terminal of the D-type flip-flop 27, the power supply short-circuit prevention resistor is connected to the drain of the transistor 1 It is necessary to connect between the “connection point of the D terminal and the resistor 21”.
Then, by reconnecting the drain of the transistor 3 from the power line V _m to any _one of the other power lines V _{0 to} V _m−1 , the output specific integer is changed from m to 0 to (m−1). It can be changed to any one.

◇ ◆ Prior application, Example 5 ◆ ◇
The prior application / embodiment 5 shown in FIG. 36 is also derived from the prior application / embodiment 1 of FIG. 32 or its derivative embodiments. "Part one input integer N _in is possible to determine or not equal and its one input for a specific integer m", "" one of its inputs the integer N _in is for the first input before the description It is the same as “determining whether it is larger than the specific integer (m−1) and smaller than the second input specific integer (m + 1)” or not.
Then, “determining whether the one input integer N _in is between the two input specific integers a and b (≧ a + 2) or two integers” is “the one input integer. It is the same as “determining whether N _in is larger than the first input specific integer a and smaller than the second input specific integer b” or not.
For this reason, a part of the discrimination function of “the prior application / Example 1 of FIG. 32 or its derivative examples”, that is, “the one input integer is discriminated whether it is smaller or smaller than the second input specific integer b”. The prior application / Embodiment 5 in which the “function to perform” is eliminated can be a synchronous OVER circuit or a synchronous NOVER circuit (= negative of the synchronous OVER circuit).
Therefore, the prior application / embodiment 5 of FIG. 36 is “the transistor 1 is removed in the prior application / embodiment 1 of FIG. 32 or its derivative embodiments, and the“ connection point between the source of the transistor 17 and the resistor 20 ” directly connected to _{m + 1} ".

When the gate of the transistor 41 is connected to the Q terminal of the D-type flip-flop 27 in the prior application / embodiment 5 of FIG. Negation of type OVER circuit) ”or“ synchronous UNDER circuit ”. Of course, both and input specific integers are different.
The circuit operation is as follows. The “synchronizing signal generating means 60, the transistor 61 and the synchronizing signal supplying means constituted by the resistors 26 and 28” supply the synchronizing signal to the CP terminal of the D-type flip-flop 27. Based on this synchronizing signal, the D-type flip The flop 27 takes in the determination result signal from the transistor 17.
If positive output signal of the intake discrimination result signal, i.e. Q terminal indicates that the "input integer N _in the input terminal T _in is an integer (m-1) integer greater than", transistors 41,37 etc. Since the “on / off driving means to be formed” drives the transistors 3 and 4 off, the output from the output terminal T _out is released.
However, if a positive output signal is "otherwise" or "input integer N _in the input terminal T _in is an integer (m-1) is less than or equal to the integer" indicates the its on-off driving means Since the transistors 3 and 4 are turned on, the specific power supply potential v _m is output from the output terminal T _{out in} terms of a circuit, and the output specific integer m is output in terms of a logical value.
Thereafter, the output state continues until the D-type flip-flop 27 takes in the next discrimination result signal from the transistor 17 based on the synchronization signal. Thereafter, similarly, the next determination result signal is taken in, and the same thing is repeated.

On the other hand, when the gate of the transistor 41 is connected to the Q-bar terminal of the D-type flip-flop 27 in the prior application / embodiment 5 of FIG. Or “synchronous NUNDER circuit”. Of course, both and input specific integers are different.
Since this circuit operation is a negative operation of the “synchronous NOVER circuit” or the “synchronous UNDER circuit”, the output method from the output terminal T _out is just opposite.

The difference between UNDER logic and NOVER logic is that UNDER does not include one specific integer for its own use, and NOVER includes one specific integer for its own use. The difference between the OVER logic and the NUNDER logic is “OVER does not include one specific integer for its own use, and NUNDER includes one specific integer for its own use”. Therefore, OVER (m−1) = NUNDER (m) and NOVER (m−1) = UNDER (m) hold. However, one integer value in each parenthesis represents one specific integer for input.
In addition, these things are valid for both the asynchronous type and the synchronous type, but naturally, the synchronous condition and the latching condition are the same in the synchronous type.
Furthermore, by reconnecting the source of the transistor 2 from the power supply line V _m-1 to any _one of the other power supply lines V _{0 to} V _m-2 , specific integers for input and input of each of the OVER circuit and the NOVER circuit ( m-1) can be changed to “any one of 0 to (m-2)”.
Then, by reconnecting the drain of the transistor 3 from the power line V _m to any _one of the other power lines V _{0 to} V _m−1 , the output specific integer is changed from m to 0 to (m−1). It can be changed to any one.

The synchronous multi-value logic circuit described so far is of course included in the “multi-value logic means having a synchronous latching function” of the first invention of the prior application. These are summarized below.
☆ Synchronous OVER circuit ☆ Synchronous EVEN circuit = Synchronous EQUAL circuit ☆ Synchronous UNDER (under) circuit ☆ Synchronous NOVER circuit ☆ Synchronous NEVEN circuit = Synchronous Type NOT circuit ☆ Synchronous NUNDER circuit

◇ ◆ Prior application / Example 6 ◆ ◇
32 can be derived from the prior application / Example 1 shown in FIG. 37 may be connected to the case where the reverse blocking diode 10 shown in FIG. 37 is not connected or connected.
“Prior application / embodiment 6 of FIG. 37 when the diode 10 is not connected” is obtained by removing “the transistor 3 in the prior application / embodiment 1 of FIG. 32,“ the source of the transistor 4, the drain of the transistor 37, and the resistor 15 Is connected directly to the power line V _m , and the pull switching means described above (in paragraph [0142]) is changed from the bidirectional controllable pull switching means to the reverse conduction type pull down switching means. Modified embodiment ".
(Derived Example of FIG. 32 Prior Application / Example 1)
“Furthermore, a reverse blocking diode is inserted and connected between the drain of the transistor 4 and the output terminal T _out , and the above-described pull switching means is switched from the bidirectional controllable pull switching means to the reverse blocking pull down switching. “Embodiment changed to means” is “prior application / embodiment 6 in FIG. 37 when the diode 10 is connected”. (Derived Example of FIG. 32 Prior Application / Example 1)
Like these circuit configuration changes, “reverse conduction type pull” similar to “prior application / embodiment 2, 3, 4 or 5 or embodiment 8 to be described later, or their respective derivatives” It can be derived from each of the derived embodiments having either a down switching means or a reverse blocking type pull down switching means.
In each embodiment and each of its derivation embodiment of the prior application, Embodiment 6 of FIG. 37, either the connection of the pull switching means from the power supply line V _m "of the power supply lines V _{0 ~} power supply line V _m-1 In this case, new and different embodiments are possible in which the input specific integer (value) and the output specific integer (value) are different from each other. (New and derived examples)
“The Institute of Electrical Engineers of Electrical Technical Term No. 9 Power Electronics, Author: “The Electrotechnical Society, Electrical Terminology Standards Special Committee”, “The Institute of Electrical Engineers, Semiconductor Power Converter Terminology Subcommittee”, Editor: The Institute of Electrical Engineers of Japan, Corona Corp. Issued the first revised edition of Japan. "Bidirectional switch, bidirectional controllable switch, reverse conducting switch, reverse blocking switch". “Valve” has almost the same meaning as “switch”.

◇ ◆ Prior application, Example 7 ◆ ◇
32 can be derived from the prior application / Example 1 of FIG. 32 to the prior application / Example 7 of FIG. The prior application / Embodiment 7 of FIG. 38 has a case where the reverse blocking diode 12 in FIG. 38 is not connected and a case where it is connected.
“Prior application / embodiment 7 of FIG. 38 when reverse blocking diode 12 is not connected” is obtained by removing “transistor 4 in prior application / embodiment 1 of FIG. An embodiment in which a reverse conduction type pull-up switching means is configured by connecting the output terminal T _out to the connection point of the drain and one end of the resistor 15 ”.
(Derived Example of FIG. 32 Prior Application / Example 1)
On the other hand, the “prior application / embodiment 7 of FIG. 38 in which the diode 12 is connected” is the same as the “prior application / embodiment 1 of FIG. This cathode terminal is used as the output terminal _Tout, and the reverse blocking type pull-up switching means is constituted by a series circuit of the diode 12 and the transistor 3.
(Derived Example of FIG. 32 Prior Application / Example 1)
Like these circuit configuration changes, “reverse conduction type pull” similar to “prior application / embodiment 2, 3, 4 or 5 or embodiment 8 to be described later, or their respective derivatives” It can be derived from each of the derived embodiments having either a down switching means or a reverse blocking type pull down switching means.
In each embodiment of the prior application / embodiment 7 of FIG. 38 and each of its derivatives, the connection of the pull switching means is changed from the power line V _m to any of the power line V ₀ to the power line V _m−1 . In this case, new and different embodiments are possible in which the input specific integer (value) and the output specific integer (value) are different from each other. (New and derived examples)

◇ ◆ Prior application / Example 8 ◆ ◇
The prior application / Embodiment 8 shown in FIG. 39 is different from the prior application / Embodiment 1 of FIG. 32 in that the numerical value discriminating means is replaced with another type of numerical value discriminating means. Value hazard removal means ”. “The circuit portion of the transistors 31 to 33, the diode 34, and the resistors 20 to 21, 62, and 67” is the new and numerical value discriminating means replaced.
However, when S = 1, the relationship of “n−1> H ≧ G ≧ m + 1” and “m ≧ 0 (zero)”, that is, “n-2> H−1 ≧ G-1 ≧ m ≧ 0 (zero)”. There is a relationship.

In the case of H = G, the determination content of the prior application / Embodiment 8 of FIG. For the sake of clarity, the logical operation in which the D input signal and the Q output signal of the D-type flip-flop 27 coincide with each other while ignoring the time delay associated with the synchronous operation is as follows.
Its input numerical value _{N in} becomes the transistor 31～33,37 is off when the H, the transistor 41,3,4 is turned on, the output terminal _{T out} outputs the specific power supply potential _{v m.} On the other hand, when the input numerical value N _in is other than H, the transistors “31, 33” or 32 ”, 37 are turned on and the transistors 41, 3, 4 are turned off, so that the output from the output terminal T _out is released. The After that, the normal operation of the D-type flip-flop 27 is added.
For this reason, the present inventor calls this “multi-value logic means having a synchronous latching function” as a “synchronous EQUAL circuit” or “synchronous EVEN circuit”.
However, simply disconnecting and connecting the gate terminal of the transistor 41 from the Q terminal to the terminal Q, for both the on-off operation of the transistors 3 and 4 is opposite, "specific potential v _m outputs an open output of the output terminal T _out "Is also the opposite, the present inventor calls this" multi-valued logic means having a synchronous latching function "as a" synchronous NOT (knot) circuit "or" synchronous NEVEN (neven) circuit ".

In the case of “H ≠ G, that is, H> G”, the determination contents of the prior application / Embodiment 8 in FIG. 39 are “two specific integers for input (H + 1), (G−1 ) Or not ”. For the sake of clarity, the logical operation in which the D input signal and the Q output signal of the D-type flip-flop 27 coincide with each other while ignoring the time delay associated with the synchronous operation is as follows.
When “H + 1> (input numerical value N _in )> G−1”, that is, when “H ≧ (input numerical value N _in ) ≧ G”, the output terminal T _out outputs the specific power supply potential v _m , while “( Output when “input numerical value N _in ) ≧ H + 1 or G−1 ≧ (input numerical value N _in )”, ie, “(input numerical value N _in )> H or G> (input numerical value N _in )”. The output from the terminal _Tout is opened. After that, the normal operation of the D-type flip-flop 27 is added.
For this reason, the present inventor refers to this “multi-valued logic means having a synchronous latching function” as “a synchronous BETWEEN circuit or a synchronous IN circuit whose two input specific integers are (H + 1) and (G−1)”. , “Synchronous NOUT circuit in which two input specific integers are H and G (= negation of synchronous OUT circuit)”.
However, simply disconnecting and connecting the gate terminal of the transistor 41 from the Q terminal to the terminal Q, for both the on-off operation of the transistors 3 and 4 is opposite, the "specific power supply potential v _m output of the output terminal T _out opening The output is also the opposite. For this reason, the present inventor refers to this “multi-valued logic means having a synchronous latching function” as “a synchronous NOBETWEEN circuit or a synchronous NIN circuit whose two input specific integers are (H + 1) and (G−1)”. , “Synchronous OUT circuit in which two input specific integers are H and G”.

Incidentally, the difference between the “synchronous IN circuit and the synchronous NOUT circuit” in which the two input specific integers of the prior application / Embodiment 8 in FIG. 39 are H and G does not include the two input specific integers. The latter is to include. Therefore, in order for the synchronous IN circuit to include H and G, the two specific integers for input are (H + 1) and (G-1).
Similarly, the difference between the synchronous OUT circuit and the synchronous NIN circuit whose two input specific integers are (H + 1) and (G-1) is that the former does not include the input specific integer two, and the latter includes it. That is. Therefore, in order for the synchronous OUT circuit to include (H + 1) and (G-1), the two specific integers for input are H and G.

39, in the case of H = G and “H ≠ G, that is, H> G”, the subsequent “pull-up resistor 26 or“ 26, 28 ”and the D-type flip-flop are used. Each operation of “Flop 27” is the same as in the case of the prior application / Example 1 of FIG. 32 (paragraph numbers [0166 to 0167]).
Further, what is described in the paragraph numbers [0168, 0182 to 0192] can be similarly applied to the prior application and Example 8. The same applies to each of the other embodiments using the numerical value discriminating means of the prior application / Embodiment 8. However, “how to take the values of (m + 1) and (m−1) in the prior application / Example 1 etc. of FIG. 32” and “the values of H and G in the prior application / Example 8 etc. of FIG. 39”. Further, by reconnecting the drain of the transistor 3 from the power line V _m to any _one of the other power lines V _{0 to} V _m−1 , the output specific integer is changed from m to 0 to (m -1) can be changed to any one of them.

In spite of this, the description and paragraph number [0033] of Japanese Patent Application Laid-Open No. 2005-236985 includes the asynchronous “AND”, “NAND”, “OR”, and “NOR” groups and the asynchronous “BETWEEN” and “NOBETWEEN”. ] Is described.
Similarly, a group of asynchronous “AND”, “NAND”, “OR”, “NOR” and asynchronous “IN”, “NIN”, “OUT”, “NOUT” (Naut) ”group combinations are considered as follows.
However, basically, AND means “all of the plurality of input integers are ...”, and OR means “at least one of the plurality of input integers is ...”.
In addition, when the present inventor first proposed these classifications / classification names, some of these multi-valued logic functions are given because each function has been made redundant. Although overlapping, if the Houji Algebra is widely used, these circuit names and functions will be converged for ease of use.

■■ Regarding various IN circuits and various NIN circuits ■■
● AND / IN circuit (also known as AND / BETWEEN circuit)
If all of the plurality of input integers are “integers between the two input specific integers a and b”, the output specific integer is output; otherwise, the output is released.
In other words, if at least one input integer among the plurality of input integers is “an integer less than or equal to a (≦ a), or an integer greater than or equal to b (≧ b)”, the output is If not, output a specific integer for output.
In this case, since b ≧ a + 2, there is of course no integer with “≧ b” and “a ≧”.

☆☆☆☆☆☆☆
In the set theory, the set “is A or B” becomes the union of the set “is only A”, the set “is only B”, and the set “is A and is B (common part)”.
Therefore, if the set “A and B” is empty, the set “A or B” becomes the union of the set “only A” and the set “only B”.

NAND / IN circuit (also known as NAND / BETWEEN circuit)
Since this circuit is the negation of the AND / IN circuit, the output method is opposite. Therefore, if all of the plurality of input integers are “integers between the two / input specific integers a and b”, the output is released; otherwise, the output specific integer is output. .
In other words, if at least one of the plurality of input integers is “an integer smaller than or equal to a (≦ a) or an integer larger than or equal to b (≧ b)”, the output integer Output a specific integer, otherwise release the output.
● AND / NIN circuit (also known as AND / NOBETWEEN circuit)
If all of the plurality of input integers are “an integer less than or equal to a (≦ a) or an integer greater than or equal to b (≧ b)”, that is, each of the plurality of input integers is “a If the integer is smaller than or equal to (≦ a) or “integer greater than or equal to b (≧ b)”, the output specific integer is output, otherwise the output is released.
In other words, if at least one input integer among the plurality of input integers is “an integer between the input specific integers a and b”, the output is released. The output specific integer is output.
NAND / NIN circuit (also known as NAND / NOBETWEEN circuit)
Since this circuit is a negative of the AND / NIN circuit, the output method is the opposite. Therefore, if all of the plurality of input integers are “an integer less than or equal to a (≦ a), or an integer greater than or equal to b (≧ b)”, that is, each of the plurality of input integers is If “integer less than or equal to a (≦ a)” or “integer greater than or equal to b (≧ b)”, the output is released, otherwise the output specific integer is output To do.
In other words, if at least one input integer among the plurality of input integers is “an integer between the two input specific integers a and b”, the output specific integer is output. If not, the output is released.

● OR / IN circuit (also known as OR / BETWEEN circuit)
If at least one of the plurality of input integers is “an integer between the two input specific integers a and b”, the output specific integer is output; otherwise, the output is output. Open.
In other words, if all of the plurality of input integers are “an integer less than or equal to a (≦ a), or an integer greater than or equal to b (≧ b)”, that is, each of the plurality of input integers. Is either “an integer less than or equal to a (≦ a)” or “an integer greater than or equal to b (≧ b)”, the output is released; otherwise, the output specific integer is Output.
● NOR / IN circuit (also known as NOR / BETWEEN circuit)
Since this circuit is the negation of the OR / IN circuit, the output method is opposite. Therefore, if at least one of the plurality of input integers is “an integer between the two input specific integers a and b”, the output is released. Otherwise, the output specific is set. Output an integer.
In other words, if all of the plurality of input integers are “an integer less than or equal to a (≦ a), or an integer greater than or equal to b (≧ b)”, that is, each of the plurality of input integers. Is an integer less than or equal to a (≦ a) or “an integer greater than or equal to b (≧ b)”, it outputs a specific integer for its output; otherwise, its output is Open.
● OR / NIN circuit (also known as OR / NOBETWEEN circuit)
If at least one of the plurality of input integers is “an integer less than or equal to a (≦ a), or an integer greater than or equal to b (≧ b)”, the output specific integer is output, Otherwise, the output is released.
In other words, if all of the plurality of input integers are “integers between the two input specific integers a and b”, the output is released; otherwise, the output specific integer is output. To do.
NOR / NIN circuit (also known as NOR / NOBETWEEN circuit)
Since this circuit is the negation of the OR / NIN circuit, the output method is opposite. Therefore, if at least one of the plurality of input integers is “an integer less than or equal to a (≦ a), or an integer greater than or equal to b (≧ b)”, the output is released, and so on. Otherwise, the output specific integer is output.
In other words, if all of the plurality of input integers are “an integer between the input specific integers a and b”, the output specific integer is output, otherwise the output is released. .

■■ Regarding various OUT circuits and various NOUT circuits ■■
When both the input specific integers are a and b, they are as follows.
AND / OUT circuit If all the plurality of input integers are “integer less than a (<a) or integer greater than b (> b)”, that is, each of the plurality of input integers is “ If either an integer less than or equal to a (≦ a) or an integer greater than or equal to b (≧ b), a specific integer for output is output, otherwise the output is released. .
In other words, if at least one of the plurality of input integers is “an integer equal to a or b, or an integer between a and b”, the output is released; Output a specific integer for output.
NAND / OUT circuit This circuit is the negation of the AND / OUT circuit, so the output method is the opposite. Therefore, if all of the plurality of input integers are “an integer smaller than a (<a) or an integer larger than b (> b)”, that is, each of the plurality of input integers is smaller than “a”. If it is either “equal integer (≦ a)” or “integer greater than or equal to b (≧ b)”, the output is released, otherwise the output specific integer is output.
In other words, if at least one of the plurality of input integers is “an integer equal to a or b, or an integer between a and b”, the specific integer for output is output. The output is released.
AND / NOUT circuit If all of the multiple input integers are "an integer equal to a or b, or an integer between a and b", a specific integer for output is output; otherwise, Release the output.
In other words, if at least one of the input integers is "an integer smaller than a (<a) or an integer larger than b (>b)", the output is released, otherwise , Output a specific integer for output.
NAND / NOUT circuit Since this circuit is the negation of the AND / NOUT circuit, the output method is the opposite. Therefore, if all of the plurality of input integers are "an integer equal to a or b, or an integer between a and b", the output is released, and if not, the output specific integer is output. To do.
In other words, if at least one of the plurality of input integers is “an integer smaller than a (<a) or an integer larger than b (> b)”, the specific integer for output is output, and so on. Otherwise, the output is released.

OR / OUT circuit If at least one of the multiple input integers is "an integer less than a (<a) or an integer greater than b (>b)", a specific integer for output is output. Otherwise, open its output.
In other words, if all of the plurality of input integers are "an integer equal to a or b, or an integer between a and b", the output is released; otherwise, the output specific integer Is output.
NOR / OUT circuit Since this circuit is the negation of the OR / OUT circuit, the output method is the opposite. Therefore, if at least one of the plurality of input integers is "an integer smaller than a (<a) or an integer larger than b (>b)", the output is released, otherwise, The output specific integer is output.
In other words, if all of the plurality of input integers are “an integer equal to a or b, or an integer between a and b”, the output specific integer is output; otherwise, the output is output. Is released.
OR / NOUT circuit If at least one of the input integers is “an integer equal to a or b, or an integer between a and b”, a specific integer for output is output. Otherwise, the output is released.
In other words, if all of the plurality of input integers are “an integer smaller than a (<a) or an integer larger than b (> b)”, that is, each of the plurality of input integers is “from a. If it is either a smaller or equal integer (≦ a) or “an integer greater than or equal to b (≧ b)”, the output is released, and if not, the output specific integer is output.
NOR / NOUT circuit Since this circuit is the negation of the OR / NOUT circuit, the output method is the opposite. Therefore, if at least one of the plurality of input integers is “an integer equal to a or b, or an integer between a and b”, the output is released; otherwise, the output is output. Output a specific integer.
In other words, if all of the plurality of input integers are “an integer smaller than a (<a) or an integer larger than b (> b)”, that is, each of the plurality of input integers is “from a. If either a smaller or equal integer (≦ a) or “an integer greater than or equal to b (≧ b)”, the output specific integer is output, and if not, the output is released.

The identities that hold for these multi-valued logic circuits are summarized as follows. As a matter of course, “each of a plurality of logical variables, each of two specific integers for input, each of specific integers for output” and the like of each circuit are the same. Furthermore, if each circuit is synchronous, the synchronization conditions such as the synchronization frequency and the latching conditions are the same.
However, in the “IN circuit, NIN circuit” and “OUT circuit, NOUT circuit” that are the basis of each circuit, as described above, these two specific integers for input are shifted by one each.
* A) AND / IN circuit = NOR / NIN circuit * b) NAND / IN circuit = OR / NIN circuit * c) AND / NIN circuit = NOR / IN circuit * d) NAND / NIN circuit = OR / IN circuit * e ) AND / OUT circuit = NOR / NOUT circuit * f) NAND / OUT circuit = OR / NOUT circuit * g) AND / NOUT circuit = NOR / OUT circuit * h) NAND / NOUT circuit = OR / OUT circuit

These identities also mean "synchronous, mutual, synchronous, or just call the same multi-valued logic circuit with two names". Has an important meaning.
For example, because NAND · IN logic is the negation of AND · IN logic, AND · IN logic and NAND · IN logic are complementary to each other, and NAND · IN logic and OR · NIN logic are the same. NIN logic is also complementary to each other. Similarly, NAND · IN logic and NOR · NIN logic are complementary to each other.
In this case, the “complementary relationship” is “when a predetermined number of logic variables are simultaneously given to the two logics, one of the logics always becomes the value of the specific integer for output, and the other logic is It means that the output is the opposite, that is, an open output ”.
Incidentally, for example, from the above item * a), AND / IN logic means “the combination of OR / NIN logic and NOT logic”, so that the synchronous AND / IN circuit is placed “after the synchronous OR / NIN circuit”. An asynchronous NOT circuit is connected, and a matching pull-up resistor or pull-down resistor is connected between both circuits "or" Synchronous NOT circuit is connected to the subsequent stage of the asynchronous OR / NIN circuit " However, it can be alternatively configured with a matching pull-up resistor or pull-down resistor connected between both circuits. However, “time delay, power loss, and multi-value hazard” However, it is also conceivable to use it for “time adjustment, timing adjustment, or matching of two logic signals”. In this case, both circuits can be considered to be synchronous.

◇ ◆ Prior application shown in Fig. 40, Example 9 ◆ ◇
FIG. 40 shows the “on / off driving means” and “bidirectional pull switching means” of the prior application / Embodiment 9. As the pre-stage circuit portion including the D-type flip-flop 27, the "prior application / examples 1 to 5 shown in FIGS. 32 to 36" or the "prior application / example 8 shown in FIG. 39" or The pre-stage circuit portion in “Embodiment 16 shown in FIG. 47 described later” or “Prior application / Embodiment 17 shown in FIG. 48 described later” is connected. “The circuit portion of the transistors 41, 22 to 25 (and the diode 36) and the resistor 15” is the on / off driving means, and the series circuit of the transistors 3 and 5 is the bidirectional pull switching means.
However, there is a case where there is no diode 36 indicated by a dotted line. In the case where there is no diode 36, when the potential of the output terminal T _out is higher than the power supply potential v _{m + 1} when the transistor 5 is driven off, the charging current of the gate-source capacitance of the transistor 5 Flows from the output terminal T _out to the power supply line V _{m + 1} through the transistor 5 built-in diode and the transistor 22.

Incidentally, remove the transistor 22～25,3,5 and the resistor 15 may be an output terminal _{T out} of the drain terminal of the transistor 41. In this case, the transistor 41 may be used as reverse conduction type pull-up switching means by forming the built-in diode, or a reverse blocking diode is connected in series with the transistor 41 as reverse blocking type pull-up switching means. Sometimes used. (Another example)
Alternatively, as in the prior application / embodiment 6 of FIG. 37, “reverse blocking pull-down switching means is configured with transistor 3 using reverse blocking diode 10 instead of transistor 5” or “transistor 5 It is also possible to configure the reverse conducting pull-down switching means by removing the transistor 3 and using the drain terminal of the transistor 3 as the output terminal _Tout . "
(Derived Example)
Or, as in the seventh embodiment of FIG. 38, “removing the transistor 3 and directly connecting the source of the transistor 5 to the power supply line V _m to form a reverse conduction type pull-up switching means” or “removing the transistor 3; directly the source of the transistor 5 to the power supply line V _m, and inserting and connecting the reverse blocking diode between the drain and the output terminal T _out of the transistor 5, reverse blocking pull a series circuit of the diode and the transistor 5 It is also possible to constitute an up-switching means. (Derived Example)
The same applies to the “prior application / Example 11 shown in FIG. 42” described later.

◇ ◆ Prior application shown in Fig. 41, Example 10 ◆ ◇
The prior application / Example 10 shown in FIG. 41 is a modification of the prior application / Example 9 shown in FIG. This prior application / Embodiment 10 is a “multi-value logic circuit called the multi-value logic circuit that the inventor calls a synchronous multi-value EVEN circuit or a non-inversion buffer circuit”, but the connection of both gates of the transistors 22 and 23. Is changed from the Q terminal to the Q bar terminal, the prior application / Embodiment 10 becomes "the inventor is a synchronous multi-value NOT circuit or multi-value NEVEN circuit".
Since the D-type flip-flop 127 in FIG. 41 operates at twice the power supply voltage of the D-type flip-flop 27 (in FIG. 40), power is supplied from both power supply lines V _m−1 and V _{m + 1} . For this reason, since the D-type flip-flop 127 directly drives the transistors 22 to 25 on and off, the transistor 41 and the resistor 15 in FIG. 40 are not necessary.
Further, the output part of the D-type flip-flop 127 (= the circuit part of the Q terminal and the Q bar terminal) has the same configuration as the “on / off driving means constituted by the transistors 22 to 25 (and the diode 36)”. If the output current capacity of each of the Q terminal and the Q bar terminal is sufficiently large, the D-type flip-flop 127 can directly drive the transistors 3 and 5 on and off.
That is, of the transistors 3 and 5, one gate is connected to the Q terminal and the other gate is connected to the Q bar terminal. In this case, the D-type flip-flop 127 also serves as the on / off driving means described above (paragraph number [0142]).

◇ ◆ Prior application shown in Fig. 42, Example 11 ◆ ◇
FIG. 42 shows the “on / off drive means” and “bidirectional pull switching means” of the prior application / Embodiment 11. As the pre-stage circuit portion including the D-type flip-flop 27, the “prior application / examples 1 to 5 shown in FIGS. 32 to 36” or the “prior application / example 8 shown in FIG. 39” or “ A pre-stage circuit portion in “prior application / embodiment 16 shown in FIG. 47” or “prior application / embodiment 17 shown in FIG. 48” described later is connected.
40 differs from the prior application / Embodiment 9 in “the connection order of transistors 3 and 5”, “how to connect the gates of transistors 3 and 5” and “on / off operation of transistors 3 and 5”. Therefore, the logic is the negative of the prior application / Embodiment 9 ”.
However, in both the prior application / Example 9 of FIG. 40 and the prior application / Example 11 of FIG. 42, the gate of the output terminal _Tout side transistor is accelerated in order to speed up the off-drive of the output terminal _Tout side transistor first. It is connected.

◇ ◆ Prior application shown in Fig. 43, Example 12 ◆ ◇
The prior application / embodiment 12 shown in FIG. 43 is a modification of the prior application / embodiment 11 shown in FIG. This prior application / embodiment 12 is a "multi-value logic circuit that the present inventor calls a synchronous multi-value NOT circuit or multi-value NEVEN circuit". If it is changed to a terminal, this prior application / embodiment 12 becomes "a multi-value logic circuit that the present inventor calls a synchronous multi-value EVEN circuit or a non-inverting buffer circuit".
The D-type flip-flop 127 in FIG. 43 operates at twice the power supply voltage of the D-type flip-flop 27 (in FIG. 42), and thus is supplied with power from both power supply lines V _m−1 and V _{m + 1} . For this reason, since the D-type flip-flop 127 directly drives the transistors 22 to 25 on and off, the transistor 41 and the resistor 15 in FIG. 42 are not necessary.
Further, the output part of the D-type flip-flop 127 (= the circuit part of the Q terminal and the Q bar terminal) has the same configuration as the “on / off driving means constituted by the transistors 22 to 25 (and the diode 36)”. If the output current capacity of each of the Q terminal and the Q bar terminal is sufficiently large, the D-type flip-flop 127 can directly drive the transistors 3 and 5 on and off.
That is, of the transistors 3 and 5, one gate is connected to the Q terminal and the other gate is connected to the Q bar terminal. In this case, the D-type flip-flop 127 also serves as the on / off driving means described above (paragraph number [0142]).

◇ ◆ Prior application shown in Fig. 44, Example 13 ◆ ◇
FIG. 44 shows the “on / off drive means” and the “bidirectional pull switching means” of the prior application / Embodiment 13. As the pre-stage circuit portion including the D-type flip-flop 27, the “prior application / examples 1 to 5 shown in FIGS. 32 to 36” or the “prior application / example 8 shown in FIG. 39” or “ A pre-stage circuit portion in “prior application / embodiment 16 shown in FIG. 47” or “prior application / embodiment 17 shown in FIG. 48” described later is connected.
Each gate can be reverse-biased in order to increase the off speed of the “bidirectional pull switching means formed by the transistors 3 to 6 and the diodes 9 to 12”.
If the transistors 3 and 6 and the diodes 9 and 12 are removed, the bidirectional switching means becomes reverse blocking pull-down switching means. On the other hand, if the transistors 4 and 5 and the diodes 10 and 11 are removed, the bidirectional switching means becomes reverse blocking pull-up switching means.
44, the transistor 41 and the resistor 15 are removed in the prior application / embodiment 13, and a pre-stage circuit unit including the D-type flip-flop 127 is shown as “the prior applications / embodiments 10 and 12 shown in the drawings of FIGS. 41 and 43”. The previous circuit portion in each of the embodiments may be connected.
In this case, the output section of the D-type flip-flop 127 (= the circuit portion of the Q terminal and the Q bar terminal) has the same configuration as the “on / off driving means formed by the transistors 22 to 25 (and the diode 36)”. If each output current capacity of the Q terminal and Q bar terminal is sufficiently large, the D-type flip-flop 127 can directly drive the transistors 3 to 6 on and off. That is, of the transistors 3 and 4 and the transistors 5 and 6, one common gate is connected to the Q terminal, and the other common gate is connected to the Q bar terminal. In this case, the D-type flip-flop 127 also serves as the on / off driving means described above (paragraph number [0142]).
Japanese Patent No. 3423780 (bidirectional switching means and unidirectional switching means)

◇ ◆ Prior application / Example 14 shown in Fig. 45 ◆ ◇
FIG. 45 shows the “on / off drive means” and “bidirectional pull switching means” of the prior application / Embodiment 14. As the pre-stage circuit portion including the D-type flip-flop 27, the “prior application / examples 1 to 5 shown in FIGS. 32 to 36” or the “prior application / example 8 shown in FIG. 39” or “ A pre-stage circuit portion in “prior application / embodiment 16 shown in FIG. 47” or “prior application / embodiment 17 shown in FIG. 48” described later is connected. However, the power line V _m and the power line IV _m may be the same or completely different.
In the prior application / Embodiment 14, the “fully insulated bidirectional switching means” is used as the “pull switching means described above (paragraph [0142])”, so that “the power supply to which one of the switch terminals is connected”. The line IV _m ”may be any of the power supply line V ₀ to the power supply line V _n−1 . In short, the power supply potential iv _m of the power supply line IV _m can be set freely.
The reason is as follows. When the transistors 41, 23, 24, 47 are on, the transistors 24, 47 and the diodes 49-50, 65-66 simultaneously gate reverse-bias “transistors 3-6 forming their bidirectional switching means” respectively. The forward bias capacitor 45 is charged. At this time, since the transistors 3 to 6 are turned off, the power supply line IV _m and the output terminal T _out are bidirectionally blocked from the gate-source portion, so that the power supply line V _{m + 1} and the power supply line V Both _m-1 are blocked in both directions.
On the other hand, when the transistors 41 and 23 are off and the transistor 22 is on, the “transistors 24 and 47 and the diodes 49 to 50 and 65 to 66” are off in both directions. due to being blocked in the power supply line V _{m + 1} and the power supply line V _m-1 two-way, completely trouble no it is in a conductive state a gate-source unit and the power supply line IV _m and the output terminal T _out. At this time, the capacitor 45 for gate forward bias simultaneously turns on all the “transistors 3 to 6 forming the bidirectional switching means”.
Patent No. 3423780 (fully insulated bidirectional switching means)

◇ ◆ Prior application shown in Fig. 46, Example 15 ◆ ◇
In the prior application / embodiment 15 shown in FIG. 46, “conditionally insulated bidirectional switching means” is used as “bidirectional pull switching means”. Potential of "subsequent circuit input and load the like connected to the output terminal T _out" certain power potential v _m and the power supply line V _m are both power supply potential v ₀ higher required there. Specific supply potential v _m as long as this potential condition is satisfied, it is possible to freely set the height of the particular power supply potential v _m.
Accordingly, the value of the output specific integer m is not constrained by the values of the input specific integers “H and G”, and the output specific integer m is set to a free value between n−1 ≧ m ≧ 1. be able to.
The reason is as follows. When the transistors 47 and 48 are on, together with the diodes 49 and 50, the “bidirectional pull switching means formed by the transistors 3 and 4” is reverse-biased to drive off, and at the same time, the gate forward bias capacitor 45 is charged. . At this time, as long as the specific power source potential v _m and the potential of the output terminal T _out are higher than the power source potential v ₀ , the gate-source portion of the transistors 3 and 4 is disconnected from the power source line V _m and the output terminal T _out .
On the other hand, when the transistors 47 and 48 are off, the capacitor 45 is turned on by turning on the bidirectional pull switching means, that is, the transistors 3 and 4, so that the reverse voltage is _dioded from the power line V _m through the transistor 3. 49 and 50, both diodes are turned off. For this reason, since the gate-source portion is cut off from both power supply lines V ₀ and V ₋₁ , there is no problem even if the gate-source portion is electrically connected to the power supply line V _m and the output terminal T _out .
Japanese Patent No. 3321203 (conditional insulation type switching means)

◇ ◆ Prior application shown in Fig. 47, Example 16 ◆ ◇
The prior application / embodiment 16 shown in FIG. 47 is an application of the “prior application / embodiment 8 shown in FIG. 39”. Although not shown in the prior application / embodiment 16 of FIG. 47, “transistors 41 and 37, diode 39 and resistor 15 in the prior application / embodiment 8 shown in FIG. 39” follow the D-type flip-flop 27. Are connected to "on / off drive means formed by" and "bidirectional pull switching means in which transistors 3 and 4 are connected in series".
Alternatively, the “on / off” shown in any one of “prior application / embodiment 9 shown in FIG. 40” to “prior application / embodiment 14 shown in FIG. 45” follows the D-type flip-flop 27. The driving means and the bidirectional pull switching means "are connected. However, when using the “on / off drive means and bidirectional pull switching means” shown in the prior application / embodiments 10 and 12 of FIGS. 41 and 43, a power source is used instead of the D-type flip-flop 27. A double D-type flip-flop 127 is used.
47, “Prior application / Example 8 shown in FIG. 39” or “Prior application / Example 9 shown in FIG. 40” or “Prior application / Example 13 shown in FIG. Consider the following four cases when the on / off driving means and the bidirectional pull switching means are connected.
◆ ◇ ◆ 1) When H = G:
For the sake of clarity, “the logic in each case where the D input signal of the D-type flip-flop 27 and the“ Q output signal, Q bar output signal ”match each other, ignoring the time delay associated with the synchronization operation. The “operation”, that is, “non-inversion / logic operation of the original asynchronous type / multi-valued logic circuit and its inversion / logic operation” is as follows.
◆ a) Non-inversion / logical operation;
Therefore one input for a specific integer is H, the input integer _{N in1, N in2} certain integer m output from the output terminal _{T out} if integer both H at the input terminal _{T in1, T in2} is output, if not The output from the output terminal _Tout is opened. For this reason, the present inventor further calls the “multi-valued logic means having a synchronous latching function” of the prior application / embodiment 16 of FIG. 47 as a synchronous (multi-valued) AND circuit.
◆ b) Inversion / logical operation;
If the input integers N _in1 and N _in2 are both integers H, the output from the output terminal T _out is released, otherwise the output specific integer m is output from the output terminal T _out . Therefore, when the gate terminal of the transistor 41 (in FIG. 39, FIG. 40, and FIG. 44) is reconnected from the Q terminal to the Q bar terminal in the prior application / embodiment 16 of FIG. The “multi-valued logic means having a synchronous latching function” is “a circuit called by the present inventor a“ synchronous (multi-valued) NAND circuit whose input specific integer is H ””.

◆ ◇ ◆ 2) If H> G:
For the sake of clarity, “the logic in each case where the D input signal of the D-type flip-flop 27 and the“ Q output signal, Q bar output signal ”match each other, ignoring the time delay associated with the synchronization operation. The “operation”, that is, “non-inversion / logic operation of the original asynchronous type / multi-valued logic circuit and its inversion / logic operation” is as follows.
◆ a) Non-inversion / logical operation;
Input integer _{N in1, N in2} are both _{"H ≧ N in1, N in2 ≧} G " of the input terminal _{T in1, T in2} if certain integer m output from the output terminal _{T out} is output, the output terminal _{T out} if not The output from is released. For this reason, the present inventor described the prior application / embodiment 16 shown in FIG. 47 as “synchronous AND / NOUT circuit (or synchronous NOR / OUT circuit) having two input specific integers (values) H and G”. Call it.
◆ b) Inversion / logical operation;
If both the input integers N _in1 and N _in2 are “H ≧ N _in1 and N _in2 ≧ G”, the output terminal T _out is opened, and if not, the output specific integer m is output from the output terminal T _out . Therefore, when the gate terminal of the transistor 41 (in FIG. 39, FIG. 40, and FIG. 44) is reconnected from the Q terminal to the Q bar terminal in the prior application / embodiment 16 of FIG. Is “a circuit called by the present inventor“ synchronous (multi-value) NAND / NOUT circuit (or synchronous OR / OUT circuit) in which two input specific integers (values) are H and G ””.

◆ ◇ ◆ 3) When transistors 32a and 32b, diode 34, and resistor 67 are removed:
For the sake of clarity, “the logic in each case where the D input signal of the D-type flip-flop 27 and the“ Q output signal, Q bar output signal ”match each other, ignoring the time delay associated with the synchronization operation. The “operation”, that is, “non-inversion / logic operation of the original asynchronous type / multi-valued logic circuit and its inversion / logic operation” is as follows.
◆ a) Non-inversion / logical operation;
Input integer _{N in1, N in2} certain integer m output from the output terminal _{T out} if both integers H less than or equal to the input terminal _{T in1, T in2} is outputted, the output from the output terminal _{T out} if not open Is done. Therefore, the present inventor calls the prior application / embodiment 16 shown in FIG. 47 as “synchronous AND / NOVER circuit (or synchronous NOR / OVER circuit) having one input specific integer H”.
◆ b) Inversion / logical operation;
If at least one of the input integers N _in1 and N _in2 is greater than the integer H, the output specific integer m is output, otherwise, if the input integers N _in1 and N _in2 are both less than or equal to the integer H, the output terminal the output from the T _out is opened. Therefore, when the gate terminal of the transistor 41 (in FIG. 39, FIG. 40, and FIG. 44) in FIG. Is a circuit that the present inventor calls “a synchronous NAND / NOVER circuit (or a synchronous OR / OVER circuit) in which one input specific integer is H”.

◆ ◇ ◆ 4) When transistors 31a, 31b, 33a, 33b, diodes 35a, 35b and resistors 20a, 20b, 62 are removed:
For the sake of clarity, “the logic in each case where the D input signal of the D-type flip-flop 27 and the“ Q output signal, Q bar output signal ”match each other, ignoring the time delay associated with the synchronization operation. The “operation”, that is, “non-inversion / logic operation of the original asynchronous type / multi-valued logic circuit and its inversion / logic operation” is as follows.
◆ a) Non-inversion / logical operation;
Input integer _{N in1, N in2} certain integer m output from the output terminal _{T out} if both greater than or equal to an integer G input terminal _{T in1, T in2} is outputted, the output from the output terminal _{T out} if not open Is done. Therefore, the present inventor calls the prior application / embodiment 16 shown in FIG. 47 as “synchronous AND / NUNDER circuit (or synchronous NOR / UNDER circuit) having one input specific integer G”.
◆ b) Inversion / logical operation;
If at least one of the input integers N _in1 and N _in2 is smaller than the integer G, the output specific integer m is output. If not, that is, if the input integers N _in1 and N _in2 are both greater than or equal to the integer G, the output terminal the output from the T _out is opened. Therefore, when the gate terminal of the transistor 41 (in FIG. 39, FIG. 40, and FIG. 44) is reconnected from the Q terminal to the Q bar terminal in the prior application / embodiment 16 of FIG. Is "a circuit called by the present inventor" synchronous NAND / NUNDER circuit (or synchronous OR / UNDER circuit) whose one specific input integer is G "".

The identities that hold for these multi-valued logic circuits are summarized as follows. As a matter of course, “each of a plurality of logical variables, input specific integers, mutual output specific integers” and the like of each circuit are the same. Furthermore, if each circuit is synchronous, the synchronization conditions such as the synchronization frequency and the latching conditions are the same.
However, in the “OVER circuit, NOVER circuit” and “UNDER circuit, NUNDER circuit” that are the basis of each circuit, as described above, these input specific integers are shifted by one.
* A) AND / NUNDER circuit = NOR / UNDER circuit * b) NAND / NUNDER circuit = OR / UNDER circuit * c) OR / UNDER circuit = NAND / UNDER circuit * d) NOR / NUNDER circuit = AND / UNDER circuit * e ) AND / NOVER circuit = NOR / OVER circuit * f) NAND / NOVER circuit = OR / OVER circuit * g) OR / NOVER circuit = NAND / OVER circuit * h) NOR / NOVER circuit = AND / OVER circuit

These identities also mean "synchronous, mutual, synchronous, or just call the same multi-valued logic circuit with two names". Has an important meaning.
For example, since NAND / NUNDER logic is the negation of AND / NUNDER logic, AND / NUNDER logic and NAND / NUNDER logic are complementary to each other, and NAND / NUNDER logic and OR / UNDER logic are the same. The UNDER logic is also complementary to each other. Similarly, the NAND · NUNDER logic and the NOR · UNDER logic are also complementary to each other.
In this case, the “complementary relationship” is “when a predetermined number of logic variables are simultaneously given to the two logics, one of the logics always becomes the value of the specific integer for output, and the other logic is It means that the output is the opposite, that is, the open output.
Incidentally, for example, from the above item * b), the OR / UNDER logic means “the combination of AND / NUNDER logic and NOT logic”, so that the synchronous OR / UNDER circuit is replaced with “the subsequent stage of the synchronous AND / NUNDER circuit”. A non-synchronous NOT circuit is connected to this circuit, and a matching pull-up resistor or pull-down resistor is connected between the two circuits "or" synchronous NOT circuit after the asynchronous AND NUNDER circuit. It can be alternatively configured with "Connecting and connecting pull-up or pull-down resistor for matching between both circuits", but "time delay, power loss and multi-value This is disadvantageous in terms of hazards.No (No), but it can be used in reverse to make use of “time adjustment, timing adjustment, or matching of two logic signals”. It is also conceivable to. In this case, both circuits can be considered to be synchronous.
Exactly in the same manner, for example, from the above item * a), AND / NUNDER logic means “the combination of OR / UNDER logic and NOT logic”. Therefore, the synchronous AND / NUNDER circuit is changed to “the synchronous OR / UNDER circuit”. An asynchronous NOT circuit is connected to the subsequent stage, and a matching pull-up resistor or pull-down resistor is connected between the two circuits "or" synchronous NOT circuit to the subsequent stage of the asynchronous OR / UNDER circuit Can be configured alternatively by connecting a pull-up resistor or a pull-down resistor for matching (matching) between both circuits. It is disadvantageous from the aspect. No (no), conversely, it may be used for “time adjustment, timing adjustment, or matching of two logic signals”. In this case, both circuits can be considered to be synchronous.

Then, “on / off drive means and bidirectional pull-switching means” such as the above-mentioned “prior application / Example 8 shown in FIG. 39” as a stage subsequent to the D-type flip-flop 27 in the prior application / Example 16 of FIG. When the “on / off drive means and bidirectional pull switching means” of “prior application / embodiment 11 shown in FIG. 42” or “prior application / embodiment 14 shown in FIG. 45” are connected instead of “ It becomes as follows.
“Contents when the gate terminal of the transistor 41 is connected to the Q terminal (= non-inverted logic) in ◇◇◇ 1) to ◇◇◇ 4) in the above (paragraph numbers [0215 to 0218].” When the gate terminal is connected to the Q bar terminal (= inverted logic), and when the gate terminal of the transistor 41 is connected to the Q bar terminal in the above-mentioned ◇◇◇ 1) to ◇◇◇ 4) The contents of (= inverted logic) ”only become“ here the contents when the gate terminal is connected to the Q terminal (= non-inverted logic) ”.
In each of the prior applications / embodiments 8 to 14 shown in FIGS. 39 to 45, the output specific integers have been described. However, the prior application / embodiment 16 shown in FIG. Since the “on / off drive means and bidirectional pull switching means” of the embodiment are used, the output specific integer can be changed in the prior application / embodiment 16 as a matter of course.
47, the reverse series circuit of the transistors 3 and 4 is used as the bidirectional pull switching means. However, the pull switching means is used instead of the bidirectional pull switching means. As in the sixth embodiment in FIG. 37 and the seventh embodiment in FIG. 38, an embodiment using a “reverse blocking type or reverse conducting type” “pull up switching means or pull down switching means” is also possible. is there.

◇ ◆ Prior application shown in Fig. 48, Example 17 ◆ ◇
The prior application / embodiment 17 shown in FIG. 48 is a combination of the transistors 33a, 33b and the like in the prior application / embodiment 16 shown in FIG. For this reason, the “on / off driving means and bidirectional pull switching means” and the like are exactly the same as in the case of the prior application / embodiment 16 of FIG.
48, the reverse series circuit of the transistors 3 and 4 is used as the bidirectional pull-switching means, but the pull-switching means is used instead of the bidirectional pull-switching means. As in the sixth embodiment in FIG. 37 and the seventh embodiment in FIG. 38, an embodiment using a “reverse blocking type or reverse conducting type” “pull up switching means or pull down switching means” is also possible. is there.

◇ ◆ Prior application shown in Fig. 49, Example 18 ◆ ◇
The prior application / Example 18 shown in FIG. 49 is derived from the asynchronous multi-value AND circuit shown in FIG. Reference: FIG. 11 of JP-A-2005-236985.
◆ ◇ ◆ 1) When H = G + 2, the specific integer for input is (H + G) / 2. And this prior application / Embodiment 18 is a “multi-value logic circuit that the inventor calls a synchronous multi-value NAND circuit”, but if the connection of the gate of the transistor 41 is changed from the Q terminal to the Q bar terminal, This prior application / Embodiment 18 becomes "a multi-value logic circuit which the inventor calls a synchronous multi-value AND circuit".
For the sake of clarity, “the logic in each case where the D input signal of the D-type flip-flop 27 and the“ Q output signal, Q bar output signal ”match each other, ignoring the time delay associated with the synchronization operation. The “operation”, that is, “inversion / logical operation and non-inversion / logical operation of the original asynchronous type / multilevel logic circuit” is as follows.
◆ a) Inversion / logical operation;
_If the input integers N _in1 , N _in2 , and N _{in3 of the} input terminals T _in1 , T _in2 , and T _in3 are all integers (H + G) / 2, the output from the output terminal T _out is released; otherwise, the output from the output terminal T _out Specific integer m is output. For this reason, the “multi-valued logic means having a synchronous latching function” of the prior application / Embodiment 18 of FIG. 49 is “the synchronous type (multi-valued) NAND in which the present inventor“ has a specific integer for input (H + G) / 2 ”. The circuit is called “circuit”.
◆ b) Non-inversion / logical operation;
Further, when the gate terminal of the transistor 41 is reconnected from the Q terminal to the Q bar terminal, if all three input integers N _in1 , N _in2 , and N _in3 are integers (H + G) / 2, the output terminal T _{out is} used for output. A specific integer m is output, otherwise the output from the output terminal _Tout is opened. For this reason, the “multi-valued logic means having a synchronous latching function” of the prior application / Embodiment 18 of FIG. 49 is “the synchronous type (multi-valued) in which the present inventor“ has a specific integer for input (H + G) / 2 ”. The circuit is called “AND circuit”.

◆ ◇ ◆ 2) When H> G + 2, the two specific integers for input are H and G. And this prior application / Embodiment 18 states that “the present inventor“ synchronous (multi-value) NAND circuit / NOUT circuit (or synchronous OR / OUT circuit) having two input specific integers (values) H and G ”. However, if the connection of the gate of the transistor 41 is changed from the Q terminal to the Q bar terminal, the prior application / Embodiment 18 states that “the present inventor has given“ two specific integers (values) for input ”. A circuit called “synchronous AND / NOUT circuit (or synchronous NOR / OUT circuit)”.
For the sake of clarity, “the logic in each case where the D input signal of the D-type flip-flop 27 and the“ Q output signal, Q bar output signal ”match each other, ignoring the time delay associated with the synchronization operation. The “operation”, that is, “inversion / logical operation and non-inversion / logical operation of the original asynchronous type / multilevel logic circuit” is as follows.
◆ a) Inversion / logical operation;
If all of the three input integers N _in1 , N _in2 , and N _in3 are “H> N _in1 , N _in2 , N _in3 > G”, the output terminal T _out is opened. Otherwise, the output specific integer is output from the output terminal T _out. m is output. For this reason, the prior application / Embodiment 18 states that “the present inventor“ synchronous (multi-value) NAND IN circuit (or synchronous OR NIN circuit) having two input specific integers (values) H and G ”. Is a circuit called "".
◆ b) Non-inversion / logical operation;
Further, when the gate terminal of the transistor 41 is reconnected from the Q terminal to the Q bar terminal, all of the three input integers N _in1 , N _in2 , N _in3 are “H> N _in1 , N _in2 , N _in3 > G”. Nara output terminal T _out certain integer m output from is output and the output from the output terminal T _out if not opened. For this reason, the prior application / Embodiment 18 states, “Furthermore, the present inventor“ synchronous (multi-value) AND / IN circuit (or synchronous NOR / NIN circuit) having two input specific integers (values) H and G ”. ) ”.

◆ ◇ ◆ 3) When the transistors 2a to 2c, 17 and the resistor 20 are removed and the open end of the resistor 62 is connected to the drain of the transistor 1c:
For the sake of clarity, “the logic in each case where the D input signal of the D-type flip-flop 27 and the“ Q output signal, Q bar output signal ”match each other, ignoring the time delay associated with the synchronization operation. The “operation”, that is, “inversion / logical operation and non-inversion / logical operation of the original asynchronous type / multilevel logic circuit” is as follows.
◆ a) Inversion / logical operation;
If all of the three input integers N _in1 , N _in2 , and N _in3 are smaller than the integer H, the output from the output terminal T _out is released, and if not, the output specific integer m is output. In other words, if at least one of the three input integers N _in1 , N _in2 , and N _in3 is greater than or equal to the integer H, the output specific integer m is output, otherwise the output from the output terminal T _out is released. Is done.
For this reason, the prior application / Embodiment 18 in FIG. 49 is “a circuit called by the present inventor“ a synchronous NAND / UNDER circuit (or synchronous OR / NUNDER circuit) having one input specific integer H ””. It is.
◆ b) Non-inversion / logical operation;
Further, when the gate terminal of the transistor 41 is connected from the Q terminal to the Q bar terminal in the prior application / Example 18 of FIG. 49, if all three input integers N _in1 , N _in2 , and N _in3 are smaller than the integer H, the output is used. A specific integer m is output, otherwise the output from the output terminal _Tout is opened. In other words, if at least one of the three input integers N _in1 , N _in2 , and N _in3 is greater than or equal to the integer H, the output from the output terminal T _out is released, otherwise the output from the output terminal T _{out is} for output. The specific integer m is output.
For this reason, the prior application / Embodiment 18 in FIG. 49 is “a circuit called by the present inventor“ a synchronous AND UNDER circuit (or a synchronous NOR / NUNDER circuit having one specific input integer H ”)”. become.

◆ ◇ ◆ 4) Remove the transistor 1 a to 1 c, when re-connecting the source of the transistor 17 to the power supply line _{V H:}
For the sake of clarity, “the logic in each case where the D input signal of the D-type flip-flop 27 and the“ Q output signal, Q bar output signal ”match each other, ignoring the time delay associated with the synchronization operation. The “operation”, that is, “inversion / logical operation and non-inversion / logical operation of the original asynchronous type / multilevel logic circuit” is as follows.
◆ a) Inversion / logical operation;
If all of the three input integers N _in1 , N _in2 , and N _in3 are larger than the integer G, the output from the output terminal T _out is released. Otherwise, the output specific integer m is output from the output terminal T _out . In other words, the output specific integer m is output if at least one of the three input integers N _in1 , N _in2 , N _in3 is smaller than or equal to the integer G, otherwise the output from the output terminal T _out is opened. Is done.
For this reason, the prior application / Eighteenth embodiment of FIG. 49 is a circuit referred to as “a synchronous NAND / OVER circuit (or a synchronous OR / NOVER circuit) having one input specific integer G”. is there.
◆ b) Non-inversion / logical operation;
Further, when the gate terminal of the transistor 41 is connected from the Q terminal to the Q bar terminal in the prior application / Example 18 of FIG. 49, if all of the three input integers N _in1 , N _in2 , and N _in3 are larger than the integer G, the output is used. A specific integer m is output, otherwise the output from the output terminal _Tout is opened. In other words, if at least one of the three input integers N _in1 , N _in2 , N _in3 is less than or equal to the integer G, the output from the output terminal T _out is released, otherwise, the output from the output terminal T _{out is} used. For this reason, the prior application / Embodiment 18 in FIG. 49 states, “Furthermore, the present inventor“ synchronized AND / OVER circuit (or synchronous NOR. NOVER circuit) ”.
49, the reverse series circuit of the transistors 3 and 4 is used as the bidirectional pull switching means in the prior application / Embodiment 18, but the pull switching means is used instead of the bidirectional pull switching means. As in the sixth embodiment in FIG. 37 and the seventh embodiment in FIG. 38, an embodiment using a “reverse blocking type or reverse conducting type” “pull up switching means or pull down switching means” is also possible. is there.

◇ ◆ Prior application shown in Fig. 50, Example 19 ◆ ◇
The prior application / example 19 shown in FIG. 50 is an application of the “prior application / example 8 shown in FIG. 39” in the same manner as the prior application / example 16 shown in FIG.
Although not shown in the prior application / embodiment 19 of FIG. 50, “transistors 41 and 37, diode 39 and resistor 15 in the prior application / embodiment 8 shown in FIG. 39” follow the D-type flip-flop 27. Are connected to "on / off drive means formed by" and "bidirectional pull switching means in which transistors 3 and 4 are connected in series".
Alternatively, the “on / off” shown in any one of “prior application / embodiment 9 shown in FIG. 40” to “prior application / embodiment 14 shown in FIG. 45” follows the D-type flip-flop 27. The driving means and the bidirectional pull switching means "are connected. However, when using the “on / off drive means and bidirectional pull switching means” shown in the prior application / embodiments 10 and 12 of FIGS. 41 and 43, a power source is used instead of the D-type flip-flop 27. A double D-type flip-flop 127 is used.

From here, the prior application / embodiment 19 shown in FIG. 50 corresponds to “the prior application / embodiment 8 shown in FIG. 39” or “the prior application / embodiment 9 shown in FIG. 40” or “preceding application / embodiment 13 shown in FIG. 44”. When the “on / off driving means and bidirectional pull switching means” are connected, the following four cases will be considered.
◆ ◇ ◆ 1) When H = G:
For the sake of clarity now, “each of the logic operations that the D input signal of the D-type flip-flop 27 and the“ Q output signal, Q bar output signal ”match each other, ignoring the time delay associated with the synchronous operation, "In other words," non-inversion / logic operation of the original asynchronous type / multi-value logic circuit and its inversion / logic operation "is as follows.
◆ a) Non-inversion / logical operation;
Since the one input specific integer is H, if at least one of the input integers N _in1 and N _in2 of the input terminals T _in1 and T _in2 is an integer H, the output specific integer m is output from the output terminal T _out. Otherwise, the output from the output terminal _Tout is opened. Therefore, the inventor further calls the “multi-valued logic means having a synchronous latching function” of the prior application / Embodiment 19 in FIG. 50 as a synchronous (multi-valued) OR circuit.
◆ b) Inversion / logical operation;
50, when the gate terminal of the transistor 41 (in FIG. 39, FIG. 40, and FIG. 44) is connected from the Q terminal to the Q bar terminal, the input integers N _in1 and N _in2 If at least one of them is an integer H, the output from the output terminal _Tout is released, and if not, the output specific integer m is output from the output terminal _Tout . Therefore, the “multi-valued logic means having a synchronous latching function” of the prior application / Embodiment 19 in FIG. 50 is “the synchronous type (multi-valued NOR circuit having a specific integer for input H”). It becomes a "calling circuit".

◆ ◇ ◆ 2) If H> G:
For the sake of clarity now, “each of the logic operations that the D input signal of the D-type flip-flop 27 and the“ Q output signal, Q bar output signal ”match each other, ignoring the time delay associated with the synchronous operation, "In other words," non-inversion / logic operation of the original asynchronous type / multi-value logic circuit and its inversion / logic operation "is as follows.
◆ a) Non-inversion / logical operation;
If at least one of the input integers N _in1 and N _in2 of the input terminals T _in1 and T _in2 is “equal to H or G, or an integer between H and G”, the output specific integer m from the output terminal T _out Is output, otherwise the output from the output terminal _Tout is opened. For this reason, the present inventor described the prior application / embodiment 19 shown in FIG. 50 as “synchronous OR / NOUT circuit (or synchronous NAND / OUT circuit) having two input specific integers (values) H and G”. Call it.
◆ b) Inversion / logical operation;
50, when the gate terminal of the transistor 41 (in FIG. 39, FIG. 40, and FIG. 44) is connected from the Q terminal to the Q bar terminal, the input integers N _in1 and N _in2 If at least one of them is “equal to H or G, or an integer between H and G”, the output terminal T _out is opened, and if not, the output specific integer m is output from the output terminal T _out . For this reason, the prior application / Embodiment 19 in FIG. 50 stated that “In addition, the present inventor“ synchronous (multi-value) NOR / NOUT circuit (or synchronous AND AND) having two input specific integers (values) H and G ”. -Circuit called "OUT circuit)".

◆ ◇ ◆ 3) When transistors 32a and 32b, diode 34, and resistor 67 are removed:
For the sake of clarity, “the logic in each case where the D input signal of the D-type flip-flop 27 and the“ Q output signal, Q bar output signal ”match each other, ignoring the time delay associated with the synchronization operation. The “operation”, that is, “non-inversion / logic operation of the original asynchronous type / multi-valued logic circuit and its inversion / logic operation” is as follows.
◆ a) Non-inversion / logical operation;
Of the input integer _{N in1, N in2} input terminal _{T in1, T in2,} at least one output is specified integer m output from the output terminal _{T out} if or equal to an integer smaller than H, from the output terminal _{T out} if not The output of is released.
In other words, if both of the input integers N _in1 and N _in2 are larger than the integer H, the output from the output terminal T _out is released, and if not, the output specific integer m is output.
Therefore, the present inventor calls the prior application / Embodiment 19 shown in FIG. 50 as “synchronous OR / NOVER circuit (or synchronous NAND / OVER circuit) having one input specific integer H”.
◆ b) Inversion / logical operation;
50, when the gate terminal of the transistor 41 (in FIG. 39, FIG. 40, and FIG. 44) is connected from the Q terminal to the Q bar terminal, the input integers N _in1 and N _in2 If at least one of them is less than or equal to the integer H, the output from the output terminal _Tout is released, and if not, the output specific integer m is output from the output terminal _Tout .
In other words, if both of the input integers N _in1 and N _in2 are larger than the integer H, the output specific integer m is output, and if not, the output from the output terminal T _out is released.
Therefore, the prior application / Embodiment 19 in FIG. 50 is a circuit further referred to as “a synchronous NOR / NOVER circuit (or a synchronous AND / OVER circuit) in which the specific integer for input is H”. become.

◆ ◇ ◆ 4) When transistors 31a, 31b, 33a, 33b, diodes 35, 68a, 68b and resistors 20a, 20b, 62 are removed:
For the sake of clarity, “the logic in each case where the D input signal of the D-type flip-flop 27 and the“ Q output signal, Q bar output signal ”match each other, ignoring the time delay associated with the synchronization operation. The “operation”, that is, “non-inversion / logic operation of the original asynchronous type / multi-valued logic circuit and its inversion / logic operation” is as follows.
◆ a) Non-inversion / logical operation;
Of the input integer _{N in1, N in2} input terminal _{T in1, T in2,} at least one output is specified integer m output from the output terminal _{T out} if greater than or equal to integer G, from the output terminal _{T out} if not The output of is released.
In other words, if both of the input integers N _in1 and N _in2 are smaller than the integer G, the output from the output terminal T _out is released, and if not, the output specific integer m is output.
Therefore, the present inventor calls the prior application / Embodiment 19 shown in FIG. 50 as “synchronous OR / NUNDER circuit (or synchronous NAND / UNDER circuit) having one input specific integer G”.
◆ b) Inversion / logical operation;
50, when the gate terminal of the transistor 41 (in FIG. 39, FIG. 40, and FIG. 44) is connected from the Q terminal to the Q bar terminal, the input integers N _in1 and N _in2 If at least one of them is greater than or equal to the integer G, the output from the output terminal T _out is released, and if not, the output specific integer m is output. In other words, both the input integer _{N in1, N in2} certain integer m output from the output terminal _{T out} if integer G smaller is output and the output from the output terminal _{T out} if not opened.
Therefore, the prior application / Embodiment 19 in FIG. 50 is a circuit further referred to as “a synchronous NOR / NUNDER circuit (or a synchronous AND / UNDER circuit) having one input specific integer G”. "become.
In the prior application / Example 19 of FIG. 50, a reverse series circuit of transistors 3 and 4 is used as the bidirectional pull switching means, but the pull switching means is used instead of the bidirectional pull switching means. As in the sixth embodiment in FIG. 37 and the seventh embodiment in FIG. 38, an embodiment using a “reverse blocking type or reverse conducting type” “pull up switching means or pull down switching means” is also possible. is there.

◇ ◆ Prior application / Example 20 shown in Fig. 51 ◆ ◇
The prior application / Example 20 shown in FIG. 51 is an application of the example shown in FIG. 13 of JP-A-2005-236985.
◆ ◇ ◆ 1) When H = G + 2, the specific integer for input is (H + G) / 2. The prior application / Example 20 in FIG. 51 is a “multi-value logic circuit that the inventor calls a synchronous multi-value NOR circuit”, but the gate connection of the transistor 41 is changed from the Q terminal to the Q bar terminal. In this case, the prior application / embodiment 20 in FIG. 51 becomes a “multi-valued logic circuit that the inventor calls a synchronous multi-valued OR circuit”.
For the sake of clarity, “the logic in each case where the D input signal of the D-type flip-flop 27 and the“ Q output signal, Q bar output signal ”match each other, ignoring the time delay associated with the synchronization operation. The “operation”, that is, “inversion / logical operation and non-inversion / logical operation of the original asynchronous type / multilevel logic circuit” is as follows.
◆ a) Inversion / logical operation;
If at least one of the input integers N _in1 , N _in2 , and N _in3 of the input terminals T _in1 , T _in2 , and T _in3 is an integer (H + G) / 2, the output from the output terminal T _out is released. certain output from the T _out integer m is output. Therefore, the “multi-valued logic means having synchronous latching function” of the prior application / embodiment 20 of FIG. 51 is “the synchronous type (multi-valued) in which the present inventor“ has a specific integer for input (H + G) / 2 ”. The circuit is called “NOR circuit”.
◆ b) Non-inversion / logical operation;
Further, when the gate terminal of the transistor 41 is reconnected from the Q terminal to the Q bar terminal, if at least one of the three input integers N _in1 , N _in2 , N _in3 is an integer (H + G) / 2, the output terminal T _The output specific integer m is output from out, and if not, the output from the output terminal T _out is released. Therefore, the “multi-valued logic means having synchronous latching function” of the prior application / embodiment 20 of FIG. 51 is “the synchronous type (multi-valued) in which the present inventor“ has a specific integer for input (H + G) / 2 ”. The circuit is called an “OR circuit”.

◆ ◇ ◆ 2) When H> G + 2, the two specific integers for input are H and G. The prior application / embodiment 20 of FIG. 51 states that “the present inventor“ synchronous (multi-value) NAND circuit / NOUT circuit (or synchronous OR. OUT circuit) ”, but if the gate connection of the transistor 41 is changed from the Q terminal to the Q bar terminal, the prior application / embodiment 20 of FIG. This is a circuit called “synchronous AND / NOUT circuit (or synchronous NOR / OUT circuit)” in which specific integers (values) are H and G ”.
For the sake of clarity, “the logic in each case where the D input signal of the D-type flip-flop 27 and the“ Q output signal, Q bar output signal ”match each other, ignoring the time delay associated with the synchronization operation. The “operation”, that is, “inversion / logical operation and non-inversion / logical operation of the original asynchronous type / multilevel logic circuit” is as follows.
◆ a) Inversion / logical operation;
If at least one of the three input integers N _in1 , N _in2 , N _in3 is “integer between G and H> G”, the output terminal T _out is opened, and if not, the output terminal T _{out is} used for output. The specific integer m is output. For this reason, the prior application / embodiment 20 of FIG. 51 states that “the present inventor“ synchronous (multi-value) NOR / IN circuit (or synchronous AND / NIN circuit) ”.
◆ b) Non-inversion / logical operation;
Further, when the gate terminal of the transistor 41 is reconnected from the Q terminal to the Q bar terminal, at least one of the three input integers N _in1 , N _in2 , and N _in3 is “an integer between H and G> If “G”, the output specific integer m is output, and if not, the output from the output terminal T _out is released. Therefore, the prior application / embodiment 20 of FIG. 51 states that “in addition, the present inventor“ synchronous (multi-value) AND / IN circuit (or synchronous NOR circuit) in which two input integers (values) are H and G ”.・ NIN circuit) ”.

◆ ◇ ◆ 3) In the prior application / Example 20 of FIG. 51, the transistors 2a to 2c, 17a to 17c, the three diodes and the resistors 20a to 20c in the figure are removed, and all the drain terminals of the transistors 1a to 1c are connected. When the open end of the resistor 62 is reconnected to the common drain terminal:
For the sake of clarity, “the logic in each case where the D input signal of the D-type flip-flop 27 and the“ Q output signal, Q bar output signal ”match each other, ignoring the time delay associated with the synchronization operation. The “operation”, that is, “inversion / logical operation and non-inversion / logical operation of the original asynchronous type / multilevel logic circuit” is as follows.
◆ a) Inversion / logical operation;
If at least one of the three input integers N _in1 , N _in2 , and N _in3 is smaller than the integer H, the output from the output terminal T _out is released, and if not, the output specific integer m is output. In other words, if each of the three input integers N _in1 , N _in2 , N _in3 is equal to or larger than the integer H, the output specific integer m is output, otherwise the output from the output terminal T _out is released.
Therefore, the prior application / embodiment 20 of FIG. 51 is a circuit called by the present inventor “a synchronous NOR / UNDER circuit (or a synchronous AND / NUNDER circuit having one input specific integer H)”. It is.
◆ b) Non-inversion / logical operation;
51, when the gate terminal of the transistor 41 is connected from the Q terminal to the Q bar terminal, at least one of the three input integers N _in1 , N _in2 , and N _in3 is greater than the integer H. If it is smaller, the output specific integer m is output, and if not, the output from the output terminal _Tout is released. In other words, if each of the three input integers N _in1 , N _in2 , and N _in3 is equal to or larger than the integer H, the output from the output terminal T _out is released, and if not, the output specific integer m is output.
For this reason, the prior application / Embodiment 18 of FIG. 49 is “a circuit that the present inventor calls a“ synchronous OR / UNDER circuit (or a synchronous NAND / NUNDER circuit) having one input specific integer H ”” become.

◆ ◇ ◆ 4) Remove the transistor 1 a to 1 c, when reconnect all the source of the transistor 17a~17c the power supply line _{V H:}
For the sake of clarity, “the logic in each case where the D input signal of the D-type flip-flop 27 and the“ Q output signal, Q bar output signal ”match each other, ignoring the time delay associated with the synchronization operation. The “operation”, that is, “inversion / logical operation and non-inversion / logical operation of the original asynchronous type / multilevel logic circuit” is as follows.
◆ a) Inversion / logical operation;
If at least one of the three input integers N _in1 , N _in2 , and N _in3 is larger than the integer G, the output from the output terminal T _out is released, and if not, the output specific integer m is output. In other words, if each of the three input integers N _in1 , N _in2 , and N _in3 is equal to or smaller than the integer G, the output specific integer m is output, otherwise the output from the output terminal T _out is released.
For this reason, the prior application / embodiment 20 of FIG. 51 is a circuit called by the present inventor “a synchronous NOR / OVER circuit (or a synchronous AND / NOVER circuit) having one input specific integer G”. It is.
◆ b) Non-inversion / logical operation;
51, when the gate terminal of the transistor 41 is connected from the Q terminal to the Q bar terminal, at least one of the three input integers N _in1 , N _in2 , and N _in3 is greater than the integer G. If it is larger, the output specific integer m is outputted, and if not, the output from the output terminal _Tout is released. In other words, if each of the three input integers N _in1 , N _in2 , N _in3 is equal to or smaller than the integer G, the output from the output terminal T _out is released, otherwise, the output specific integer m from the output terminal T _out. Is output.
For this reason, the prior application / embodiment 20 of FIG. 51 is a circuit further referred to as “a synchronous OR / OVER circuit (or a synchronous NAND / NOVER circuit) in which the input specific integer is G”. become.
51, the reverse series circuit of the transistors 3 and 4 is used as the bidirectional pull switching means. However, the pull switching means is used instead of the bidirectional pull switching means. As in the sixth embodiment in FIG. 37 and the seventh embodiment in FIG. 38, an embodiment using a “reverse blocking type or reverse conducting type” “pull up switching means or pull down switching means” is also possible. is there.

◇ ◆ Prior application / Example 21 shown in Fig. 52 ◆ ◇
In the prior application / embodiment 21 shown in FIG. 52, the synchronizing signal generating means 60 (= synchronizing signal supplying means) and the D-type flip-flop 70 are supplied with power from the same power supply lines V ₀ and V ₋₁ .
Further, the transistors 71 and 72, the diode 39, and the resistor 15 constitute the on / off driving means, and the transistors 73 and 74 constitute the bidirectional pull switching means.
Furthermore, instead of “numerical value discriminating means constituted by transistors 1, 2, 17 and resistors 20, 62”, “numerical value discriminating means constituted by transistors 31 to 33, diode 34 and resistors 20, 62, 67 in FIG. 39”. , “Numerical discriminating means constituted by transistors 31a to 33a, 31b to 33b, diodes 34, 35a and 35b and resistors 20a, 20b, 62 and 67 in FIG. 47” and “transistors 31a to 32a and 31b to FIG. Embodiments using “numerical value discriminating means comprising 32b, 33, diodes 34, 68a, 68b and resistors 20, 62, 67” are also possible.
Then, instead of the “power supply lines V ₋₁ and V ₀ shown in FIG. 52”, the power supply lines V ₀ and V ₁ are used, that is, the respective power supply potentials are raised one by one, transistors 72 to 74, diodes 39 and the resistor 15 can be removed, and the drain terminal of the transistor 71 can be used as the output terminal _Tout . In this case, there is a case where the transistor 71 is used as a reverse conduction type pull-down switching means by forming the built-in diode, and a case where a reverse blocking diode is connected in series to the transistor 71 to reverse block this series circuit. There is also a case of using as a type pull-down switching means. (Another example)
Or, although there is a difference between the N-channel type and the P-channel type, as in the prior application / embodiment 7 of FIG. 38, “a reverse blocking pull-down switching means together with the transistor 73 using the diode 12 instead of the transistor 74” Or “removing the transistor 74 and using the source terminal of the transistor 73 as the output terminal T _out to configure a reverse conduction type pull-down switching means”. (Derived example)
Or, although differences in N-channel and P-channel type there, similarly to the previous application, Embodiment 6 of FIG. 37 and remove the "transistor 73, reverse conducting directly connected to the source or the like of the transistor 74 to the power supply line V _m constituting the pull-up switching unit "or remove the" transistor 73, directly connected to the source or the like of the transistor 74 to the power supply line V _m, the diode 10 inserted and connected between the drain and the output terminal T _out of the transistor 74 Thus, the transistor 74 and the diode 10 constitute reverse blocking pull-up switching means. "
(Derived example)

◇ ◆ Prior application / Example 22 ◆ ◇
Another embodiment (not shown) will be described. The above-mentioned “prior application / Example 1 shown in FIG. 32” is a case where the diode 26 and the resistor 27 are not provided in the multi-value logic circuit of FIG. 9 of “Japanese Patent Laid-Open No. 2005-236985” (Patent Document 3). 32 and the gate of the transistor 24), the D-type flip-flop 27 in FIG. 32 is inserted and connected between the gate of the transistor 24 and the turn of the bidirectional pull switching means. “The off-speed is increased by the transistor 37 etc. in the prior application / embodiment 1 of FIG. 32”.
Similarly, in each of the multi-value logic circuits shown in FIGS. 11, 13, 17, 17, 20, 23 (b), and 25 (b) of Japanese Patent Laid-Open No. 2005-236985, the same thing is applied. Each embodiment is possible.
That is, in each of the multi-valued logic circuits of FIGS. 17 and 20 of Japanese Patent Laid-Open No. 2005-236985, among the two PMOSs, the “both power supply lines V _{m + 1} ” is similarly placed between the drain of the preceding stage PMOS and the gate of the succeeding stage PMOS. · comprising a D-type flip-flop 27 'which is powered from V _m to equal to the insertion and connection.
In the multi-value logic circuit of FIG. 23B of Japanese Patent Laid-Open No. 2005-236985, “both power supply lines V _{m + 1.} It will be equal to inserting and connecting the D-type flip-flop 27 'which is powered from V _m.
Further, in the multi-value logic circuit shown in FIG. 25B of Japanese Patent Laid-Open No. 2005-236985, “power is supplied from both power supply lines V _{m + 1} · V _m similarly between the drain connection points of the four preceding PMOSs and the gate of the subsequent PMOS. The inserted D-type flip-flop 27 "is inserted and connected.
In the same way as “derived from the prior application / Example 1 shown in FIG. 32 to the prior application / Examples 2-7 shown in FIGS. 33 to 38”, the numerical value and the number of the specific integer for input can be changed, Alternatively, by changing the pull switching means to the reverse conduction type or reverse blocking type, or by changing the power line connecting one switch terminal of the pull switching means, Each derived embodiment further derived from “each embodiment of the present invention derived from each embodiment of 2005-236985” is possible. In each of the embodiments of the present invention or each of the embodiments thereof, the bidirectional switching means is turned off by the transistor 37 or the like as in the present invention “first application shown in FIG. 32 / embodiment 1”. Expedited variants are possible. (Derived Example)
In other words, there are derivative examples with and without the transistor 37 and the like.
Regarding the first and second inventions of the prior application, finally, the data input section (eg, the input section of the D terminal) of the binary synchronous flip-flop means which is one of the constituent means is “the input integer is the one of the input integers. If the requirement of the numerical discriminating means for discriminating whether it is “larger or not larger” or “smaller or smaller” than the input specific integer is satisfied, the binary synchronous flip-flop means also serves as the numerical discriminating means. Of course.
◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆
◆◆◆
In the description of the present invention, various common-value logic circuits based on the Fuji algebra and “multi-value logic means and multi-value hazard removal means having a synchronous latching function” disclosed in Japanese Patent Application Laid-Open No. 2012-077504 are disclosed in the description of the present invention. As a precaution, the present inventor explained those techniques in paragraph numbers [0114 to 0237].
◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆

◆◆◆ ＊＊＊＊＊ Various new and multi-valued logic that can express “ambiguity” ********
***
●● 25) Eight new multi-valued logics created by the inventor in the Fuji algebra that were not found in the previous concept, “multi-valued OVER logic, multi-valued NOVER logic, By using each of the multi-value logic circuits of “multi-value UNDER logic, multi-value NUNDER logic, multi-value IN logic, multi-value NIN (nin) logic, multi-value OUT logic, multi-value NOUT logic”. "Ambiguity" can be defined easily and freely and flexibly.
By using each of these multi-valued logic circuits, for example, “ambiguity” can be easily and freely defined and expressed as follows.
◆ Example 1: When expressed in terms of logical numerical values, “approximately the numerical values in this area”. Among 0-9, “3-5”, “4-6”, “≦ 2”, “7 ≦”.
◆ Example 2: When neither Yes (→ numerical value 9) nor No (→ numerical value 0) is attached, the case where neither is attached is represented by the numerical value “4, 5”.
◆ Example 3: When expressing as “Nearly Yes”. “6-7” when it is defined that “numerical value 9 is Yes” and “numerical value 0 is No”.
◆ Example 4: When expressing as “Nearly No”. “2-3” when it is defined that “numerical value 9 is Yes” and “numerical value 0 is No”.
Example 5: When expressing “Gray innocence (→ Numerical value 1) as close as possible to guilty (→ Numerical value 0)” by saying “Suspect is in the interest of the accused”. In other words, when the numerical value 0 means "complete guilt (black)" and the numerical value 9 means "complete innocence (white)", the numerical value 1 expresses "gray innocence that is almost guilty" If.
***
After that, "the person who uses these various new and multi-valued logic" can freely define and express the meaning of each numerical value as they like.

The number of corresponding input integers in each multi-value logic circuit of “multi-value OVER logic, multi-value UNDER logic, multi-value IN logic, multi-value OUT logic” is, for example, “the input specific integer value is 4”. When the number of integers 5, 6, and 7 corresponding to the multi-value IN logic of 8 is narrowed down from a plurality to one, the multi-value logic always becomes multi-value EVEN logic.
→→ paragraph number mentioned above [0169]
In other words, the refinement means focusing from “ambiguity” to “clarity” just like “focusing from“ blurring ”to“ matching ”in the focus of a photo”, so “OVER logic, NOVER ( (NOWBER) logic, UNDER logic, NUNDER logic, IN logic, NIN logic, OUT logic, NOUT logic, and "each of these multi-value logic and multi-value AND logic or multi-value OR logic The present inventor considers that expressing “ambiguity” by “combinatorial logic” is not true, is not out of focus, and is appropriate for reason.
Therefore, using these multi-valued logic and "combination of these multi-valued logic and multi-valued AND logic and multi-valued OR logic", a new "fuzzy logic (completely different from conventional fuzzy logic and fuzzy control technology ( The present inventor thinks that “IMy [aimai] -Control-Technology” (IMy [aimai] -Logic) ”and“ Immy [aimai] -Control-Technology ”can be opened.
This is because in the conventional fuzzy control theory, “mathematical theory of probability and statistics” was introduced to Boolean algebra in order to express “ambiguity” in “numeric values 0 and 1 that clearly express YES and NO”. This is because it is generally quite complicated and difficult to understand.
In the first place, statistics and probabilities do not exist yet for the “ambiguity” that a person (person) defines and expresses in the first place. Defining and expressing itself is completely impossible. In other words, the conventional fuzzy theory has its limits and is impossible.
As can be readily understood from the pronunciation of [aimai], the present inventor named the English name, IMy [aimai], in accordance with the Japanese word “ambiguity”.

◆◆◆ ＊＊＊＊＊＊ New concept computer that doesn't use programs, etc. ＊＊＊＊＊ ◆◆◆
***
◆◆◆ ＊＊＊＊ New Concept Computers
not to use programs etc. ＊＊＊＊ ◆◆◆
***
●● 26) As a multi-value related technique, the present inventor has described “processing result {or previous (or previous) as“ a new concept computer that does not use program software, CPU, etc. ” (Preliminary Processing Results) Memory Type (Alternative Name: Input / Output Pattern Memory Type or Function Memory Type) "Decimal Computer (= Decimal Computers) and the like are disclosed.
→→ (Decimal) Computers of 'Processing-Result or Pre-Processing-Result'-Memoriizing-Type etc. →→ New Concept Computers
This patent's inventor was calling The (Pre-) Processing-Result-Memoriizing-Type 'Input-Output-Pattern-Memoriizing-Typeor Functioning-Temporatory-Memorimizing.
Note that the previous processing includes information collection before information is collected in advance, so naturally, the previous processing results include the previous information processing results in addition to the previous information processing results. Information collection results are also included. Regardless of the previous information processing result, the previous information collection result, the input / output pattern, or the function, both “one or more“ input data or input information ”” and “one or more” The “big data” that is often heard recently can be the new software as it is. In other words, the compatibility between the new concept computer and its “big data” is outstanding.
'The Pre-processing data' information 'Pre-processing data or information' or 'pre-collecting data or information'.
In other words, 'Means of the Pre-processing' inclusion 'pre-processing data or information' and 'pre-collecting data or information'.
This inventor thinks that 'Big Data to become of a topic of convenience of reentry' can direct become 'Present Software' written.
This inventor calls 'The Pre-processing Result Software''The Pres Software Software' for short.
So, in a word, Big Data fit the New Concept Computers very much.

It is quite natural. This is because the big data is a part of the previous processing result software. What is organized in the big data is a part of the previous processing result software, and if the big data is not organized like a truth table, it will not be useful at all. This is because there is no meaning to collect.
It's quiet natural! ! ! Because the Big Data area a part of 'The Presto Software'.
And because 'data put in order' of the Big Data are a part itself of 'The Presult Software', and because, if the Big Data are not put in order like truth tables, the Big Data are no usefulness and no meaning to pre-collecting them at all.
In the new concept computer, it will be called “preprocessing result software {Present (or Presert) software (Present Software) for short. }] (Also known as I / O pattern software or function software) and multi-value logic circuits.
→→ ★ Presult-Memoriizing-Type Computers
The Presult-Memoriizing-Type Computers use 'The Pres Software Software' and multivalue logic circuits etc. .
Further, “Presalting (or Presalting) = Presulting” (also known as patterning or functioning) corresponds to programming, and “Presalter (or Presalter) = Presulter” (also known as patterner) corresponds to the programmer. Or a functioner).
'The PRESULTING' means 'Producing the Presto Software', and 'THE PRESULTERS' mean 'People producing the Prestoware'.

From the above, the present inventor thinks that it is a simple story without having to think about it as “data scientist” that is often said recently in big data. Because, as described above, fill the squares of the large truth table with the numerical values in the ground, “Wash your sweat? Or use a computer”. Because it is just a story. If all the big data is available, the truth table can be completed. The truth table is a logical function representing the relationship and correlation between one or more input “data or information” and one or more output “data or information”.
→→ Patent Document 12 below and paragraph numbers [0071 to 0074, 0087 to 0088] described above.
The use of big data means, for example, that a result of a certain logical function is simply made into a one-dimensional to three-dimensional graph or the like to make it easy to visually grasp the “trend indicated by the big data”.
Or, effectively, “a result of inputting one or more inputs“ data or information ”to the logical function 1”, ie, “the one or more outputs“ data or information ”” is a logical function. Enter in 2. One or more outputs “data or information” of the logic function 2 are further input to the logic function 3. As a result, the relationship and correlation between the “first one or more inputs“ data or information ”” and one or more outputs “data or information” of the logic function 3 are obtained. If necessary, it can be continued with logical functions 4, 5,.
At that time, it is not always necessary to use all “data or information” of each logical function, and there is a method of using only a part of each logical function.
The inventor believes that the “data scientist” is what the inventor originally calls “a patterner or functioner”, and recently “a presalter (or presalter) = Presulter”.
In addition, if all of the “data or information” to be collected is not complete and “there are blanks in the truth table to be created, each blank data is calculated from the average value of the data around the circle, The present inventor believes that it is obtained from the increase / decrease tendency (differentiation) of the surrounding data.
Furthermore, if big data is handled by a computer, it is simpler and faster to use a pre-store (or pre-store) storage computer rather than a conventional program storage computer.

JP2007-035233 (JP2007-035233A). Paragraph numbers [0003-0004, 0024-0034, 0082-0084]. →→ New Concept Computers and Multi-valued Computers, special Decimal Computers. →→ Ther memories have functions to convert 'input-data or input-information' into 'output-data or output-information'. Japanese Utility Model Publication No. 2-5937 ("Multi-valued logic driver", 1990year) "Engine electronic fuel injection system using MOS-ROM (to reduce automobile exhaust gas pollution)". An electronic device to use MOS-ROMs and to inject fuel for an automobile engine. The purchase is to decrease population by it exhaust gas. →→ Three-dimensional “information or data” representing the relationship between a two-dimensional input “information or data” and a one-dimensional output “information or data”. →→ 3 dimension-'information or data 'to express relations between 2 dimension-input-'information or data' and 1 dimension-output-'information or data '. Nikkei Electronics (issued December 18, 1972) (p.116-p.126), NIKKEI ELECTRONICS DEC. 18, 1972. Written by Malcolm Williams {Joseph Lucas (Electrical) Ltd. }, Published by Nikkei Business Publications, Inc. in Japan. (From a new-item of Electronics) "Chapter 7 Application Examples of IC Memory" in "How to Use IC Memory", Authors: Matsuo Nitta, Ryoichi Oomote, Sangyo Publishing Co., Ltd. published 4th edition on June 20, 1978 (June 20, 1978) . →→ Memories have functions to convert 'input-data or input-information' into 'output-data or output-information'. “XX proposes an architecture for computing and storing using only memory, and uses STT-MRAM with high speed and low power consumption”. Writing: Masahide Kimura. ‘An architecture to calculate and memorize some need by using only memories. Sees are fast & low-power STT-MRAMs. 'This news was written by Masahide Kimura. Nikkei Electronics No. 1125 (issued on January 6, 2014) (p.12-p.13), NIKKEI ELECTRONICS JAN. 6, 2014. Published by Nikkei Business Publications, Inc. (In Japan).

In the case of a conventional computer, for example, since “information to be processed” is given and information processing is started and results are output, a long information processing time is required. On the other hand, in the case of this new concept computer, “all the contents to be processed” is known in advance or is completely inferred and grasped. Pre) Information processing result (Result) ”, that is,“ Presert (= Presult. Or Pres.) ”Has already been stored in the memory area. For each “content part that is input”, the “present corresponding to it” is simply read out. For this reason, as a matter of course, the information processing speed is overwhelmingly fast when viewed from the outside of the computer. Whether it looks or not, the real-time processing is extremely advantageous because the information processing speed is actually overwhelmingly fast.
In the future, the “Present storage computer of this new concept” and the “conventional program storage type (or built-in type) computer” will have the possibility that the former will be super-high-performance. The present inventor believes that there is a large or small amount of storage capacity that is permitted or required, “high priority of information processing speed”, “necessity of using multi-valued logic” ”,“ Improvement / advancement of 3D technology of IC and LSI ”,“ Improvement / advancement of each performance of MOS / FET ”,“ In terms of power saving ”,“ Requirement of cooling or suppression of heat generation ” The present inventor is convinced that “the fields of use of both can be distinguished” by “ease of software creation”, “bug occurrence”, “resistance to unauthorized intrusion operation”, and the like.
And the present inventor is convinced that “in the future, there is always a good arrangement of both methods, and both methods may be used in an organic combination”.

In the case of a conventional program storage type computer, a considerable number of instructions (instructions) are processed for “information processing on the input contents” each time, so a considerable amount of power is consumed. The CPU is in the heater state. On the other hand, in the case of a Preset memory type computer, since “information processing for the input contents” is performed only once each time, only one memory access is required, so that the power consumption is overwhelmingly small. That's why if you replace program storage computers around the world with Presto storage computers, you can save a tremendous amount of power. How much energy will it save for nuclear power plants? ? No, how many nuclear power plants do you have (or hundreds)? ?
Also, regarding resistance to unauthorized intrusion operations, in the case of a conventional program storage type computer, an unauthorized intruder abuses “each software, each application software, and system software such as an OS that the intrusion destination computer has”. As such, if you are unprotected, you can take full control of the computer with a “malware that is relatively small compared to the total amount of programs in the system”. On the other hand, in the case of a Presto memory type computer, if it is attempted to completely control the computer completely, it is necessary to rewrite the entire Pres software (= Present Software). It is almost impossible to completely improperly control.
Furthermore, with regard to the storage capacity of the program storage type computer, for example, in the automobile field, the program reaches tens of millions of lines (several times when converted to an address), and the required storage capacity is enormous. In that case, the use of a Prestore memory type computer becomes overwhelmingly advantageous, and its full use gradually enters the field of view.
Then, the compatibility between the Presto storage computer and the cloud computer is considered good. This is because the cloud computer side absorbs and bears the amount of memory required.
And since various functions, characteristic curves and calculations used in fuzzy control can all be expressed in a truth table, it is natural that fuzzy control can be performed using this new concept computer.

◆◆◆ ＊＊＊＊ Information processing means to make malicious programs harmless. ******** ◆◆◆
***
◆◆◆ *** Information-processing-means
to be able to treat unjust-
programs as rubbish ***
***
●● 27) The present inventor discloses “information processing means having an illegal intrusion operation blocking function” in his prior invention “Japanese Patent Application Laid-Open No. 2006-190239 (◆ voluntary withdrawal)” as a multi-value related technique. The inventor voluntarily withdrew this prior invention because of the emergence of urgent situations such as cyber terrorism and cyber war in the past few years.
This prior application technology is based on the idea that “if an unauthorized intrusion occurs, if it is not illegally operated, that is fine”.
For example, in this information processing means, an “instruction (instruction), program or command expressed in a ternary expression (eg, at least one digit of the machine language is a numerical value 2) that can be clearly distinguished from the binary expression. , Etc., and when "external data or external information" expressed in binary representation that is completely unreliable is taken in, "filter means that passes only what is expressed in binary representation (eg: clamp diode) Incorporate it via "Hardware means etc.").
In other words, in this information processing means, only “instructions (instructions), programs or commands” expressed in ternary values are targets of execution, and internal or external “data or information” expressed in binary values is the information. The “external data or external information” that is the target of processing and is expressed in binary is included in the input target. And an external reliable “instruction (instruction), program or command”, etc., or data or information ”expressed in a ternary expression that can be clearly distinguished from the binary expression, Input / output from “input / output port”. →→ Reliable communication example: Quantum communication or other direct communication using people or machines.
As a result, even if this information processing means can be illegally infiltrated, the illegally intruding “illegal program, illegal command”, etc. are not executed at all, so that the information processing means is illegally operated. Is completely absent. The unauthorized program, unauthorized command, etc. are merely harmless and worthless trash “data or information” for the information processing means.
That's why, according to the recent “hands-on countermeasures against unauthorized intrusion operations” and “strong demands for the ultimate countermeasures and measures to end the illegal operations and countermeasures,” this prior application technology can be used immediately. The present inventor thinks that it is not strange to use. In addition, there is “information processing means having a function of preventing unauthorized intrusion operation” disclosed in Japanese Patent Application Laid-Open No. 2011-103124 (for the same reason as that of the above-mentioned prior application, ◆ under self-collection).
By using these intrusion prevention methods, it is possible to eliminate the cyberspace wars (land, sea, air, space, and the fifth battlefield) that have recently become particularly serious problems. Absent.

The compatibility between this intrusion prevention technology and cloud computers is outstanding. This is because, for example, even if the “command (= instruction), program or command” or the like is expressed in three values as described above, the request contents of the client and the processing result contents can be expressed in binary values.
Further, when the difference between the numerical values 1 and 0 is expressed by the difference in frequency, the communication line itself can be used as a frequency filter. In other words, it is not necessary to define and prepare a frequency corresponding to the numerical value 2 from the beginning in the communication means.
By the way, the inventor of the present invention described in the specification of “Japanese Patent Laid-Open No. 2006-190239 (information processing means having an unauthorized intrusion operation blocking function)” was subsequently verified by two American universities in 2010. It was confirmed by an experiment and a paper was published.
→→ The following non-patent document 16.
For this reason, a number of companies, including domestic and overseas automakers, have started moving toward international standardization and international standardization with the aim of ensuring real-time performance and fail-safety. For this reason, the present inventor believes that the above-described real-time property of the new concept computer and the above-described unauthorized intrusion operation prevention technology may be useful.
→→ The following non-patent document 17.
Then, to make sure that there is no misunderstanding regarding Japanese Patent Laid-Open No. 2006-190239, Japanese Patent Laid-Open No. 2006-190239 has a description of “indication of violation of public order and morals”. There has been no warning or punishment from the JPO regarding. This is because the floppy (registered trademark) described in the specification is not known because it is not necessary to clearly indicate that it is a registered trademark.
“Experimental Security Analysis of a Modern Automobile”, “2010 IEEE Symposium on Security and Privacy” Nikkei Electronics No. 1088 (August 6, 2012 issue) p. 49-p. 57 “Ethernet (registered trademark) is on the car to ensure real time and fail-safe”. Published by Nikkei BP on August 6, 2012.

As described above (paragraph number [0043]), the first invention is useful when, for example, the multi-value complete circuit of FIG. 21 is transformed into the multi-value complete circuit of FIG. For example, comparing the multi-value complete circuit of FIG. 21 with the multi-value complete circuit of FIG. 13, the former is mainly composed of a multi-value AND circuit, whereas the latter is mainly composed of a multi-value NOR circuit. Therefore, the number of types of multi-value logic circuits that can be used increases and becomes convenient. The same applies to other inventions. As a result, there is a great potential for utilizing these inventions in the industry.

◆◆ title of the inventions ◆◆
◆ A multivalue NOT-logic two-stage connection means on the basis of the principals of “Hooji algebra”,
◆ a multivalue 'NOT-logic and EVEN-logic' two-stage connection means on the basis of the principals of “Hooji algebra”,
◆ a multivalue EVEN-logic two-stage connection means on the basis of the principals of “Hooji algebra”,
And a multivalue 'EVEN-logic and NOT-logic' two-stage connection means on the basis of the principles of “Hooji algebra”.
■■■ Summary ■■■
■■ Issues ■■ New and multi-valued logic born in Japan, providing new and multi-valued NOT two-stage connection means with new actions and effects based on the principle of “Hooji algebra”.
◆◆ abstract ◆◆
◆ ◇ problem to be solved ◇ ◆
That's to create a new multi-value NOT-logic two-stage connection means etc. who on the basis of the principals of “Hooji allegebra” to be 'a new multiple logical born in Japan', and whische neww.
■■ Solution ■■ Example: Asynchronous or synchronous multi-value NOT means with a specific integer m and an asynchronous or synchronous multi-value NOT means with a specific integer Cm (≠ m) are connected in two stages. connect the first pull resistance "to pull up or down the output voltage subsequent specific to a constant potential v _{Cm (potential} of the power supply line V _Cm)," identify the subsequent output potential preceding potentiostatic v _{m (power} line V _m potential) is connected to a second pull resistor that pulls up or down.
◆ ◇ means for solving problem ◇ ◆
Example: one of the inventions is constructed by the following three connectings.
First connecting of a number of metric metric (NOT) of the number of signatures of the valuation of the number of signatures. Buteach means is iterator unsynchronous-type or synchronous-type.
Secondly connecting a first resistor between the both means so that the first resistor may pull 'the output electric potential of the prestage means' up or down to 'the specific constant electric potential (v Cm) of the rear-stage means'. But the v _Cmis is the electrical potential of the power source line (V _Cm ).
Thirdly connecting a second resistor to the output terminal of the rear-stage means so that the second resistor may pull 'the output electric potential of the rear-stage means' up or down to' the specific constant electric potential (v m) of the prestage means'. _{But the v m is the electric potential} of the power source line (V m).
■■ EFFECT ■■ This is equivalent to changing the multi-value EVEN means from one stage to multi-value NOT two-stage connection means, and the specific integer can be changed from m to Cm. (Example: multi-valued logic complete circuit of FIGS. 21 to 13). Also, unlike ordinary multi-value NOT two-stage connection means (FIG. 2) in which two multi-value NOT means having the same specific integer m are connected, there are more convenient options for distributing or concentrating the load applied to the power source.
◆ ◇ effects ◇ ◆
By this constitution, because we can equivalently change from a multivalue EVEN-logic one-stage means to a multivalue NOT-logic two-stage connection means, and can simultaneously change the specific integer value from 'm' to 'Cm', the latter means (= the invention) is convenient when equivalent changing from a multiple circuit to another one.
For example, when equivalent changing from 'a multivalue logic "completeness of completeness" circuit in fig. 21 'to' that in fig. 13 '.
And the latter means is convenient to increase the choice-range of 'dispersion or concentration' of loads on the power-sources connected with the above multivalue circuits, differently from a normal multivalue NOT-logic two-stage connection means (fig.2) for each of its two NOT-logic means to have the same specific integer value 'm'.
■■■ Technical Field ■■■
The first to fourth invention two "Japan born New multivalued logic," multivalued logic means Fuji algebra (Hooji a lgebra) potential mode (or voltage mode) based on "(or multi-valued logic circuit)" The present invention relates to a combined multi-level logic two-stage connection means.
◆◆ technical field ◆◆
◆ Each of the 1st to 4th invention is with the same value for the multi-valued logistic-and-in-the-contain-and-the-consit-and-the-re-conjugation
The eth multivalue logic 'means or circuits' is both' the the de the ol and the ban and the tents of the principles of the principles of the principles of the principles of the principles.
To explain these modes, first, in the potential mode, each of a plurality of predetermined potentials and each of a plurality of predetermined integers are defined to correspond one-to-one, and then in the voltage mode, a plurality of predetermined potentials are defined. It is defined that each of the voltages corresponds to each of a plurality of predetermined integers one to one.
Exciting thermode, first and foremost const ent ri ent ri ed ent ri ed ent ri ed ent ri ed ent ri ent ri ed ent ent ri ed ent ri er ent ri ent ri er ent ent ri er ent er entre ent er ent ri er ent er ent erinto er erinto er erto er ent ri er fo n
Secondly, in the voltage mode it's defined thateach of fixed plumage, is one by one, one to one, one of the fixed numbers.
For example, the multi-value NOT two-stage connection means of the first invention is “using a complete system such as a multi-value AND circuit, all multi-value logic circuits (or multi-value logic means) regardless of the multi-value number N”. When applied to a multi-valued logic complete circuit (eg, FIG. 21) that can be expressed and configured, a multi-valued logic using a complete system such as a multi-valued NOR circuit that is an equivalent modification of the multi-valued logic complete circuit. A complete circuit (example: FIG. 13) ”can be constructed. This means that when configuring a multi-valued logic complete circuit, the choices of basic / multi-valued logic circuits to be used (eg, multi-valued AND circuit, multi-valued OR circuit, etc.) are increased and convenient. In this case, a multi-value AND circuit or the like may be used, which means that a multi-value NOR circuit or the like may be used.
● “Multi-valued logic complete circuit” is a feature that “all types of multi-valued logic circuits can be expressed and configured with only one or several basic / multi-valued logic circuits (→ complete system)”, “completeness (= Completeness) ”, and the present inventor uses the term“ multi-valued logic complete circuit ”in that sense.
● In addition, not yet (or) it is widely known not "Fuji algebra (Hooji a lgebra)" principles and "a variety of multi-valued logic circuit based on the Fuji algebra" of technology, and, "" synchronization of Patent Document 7 In order to be able to treat the technique of “multi-valued logic means having a latching function and multi-value hazard removal means” ”in the description of the present invention in the same manner as the common technical knowledge, those principles and techniques are designated by paragraph numbers [0049. To 0112] and paragraph numbers [0113 to 0237], the inventor will explain.
In particular, the inventor will explain in detail in paragraph numbers [0083 to 0096] regarding “multi-valued logic complete circuit based on Fuji algebra”, which has already been disclosed in the following Patent Documents 6 to 7. However, the use of the name “Fuji algebra” is from Patent Document 6.
JP 2004-032702 (New multi-value logic circuit based on multi-value logic “Fuji algebra”) JP 2005-198226 (New multi-value logic circuit based on multi-value logic "Fuji algebra") JP 2005-236985 (Multi-valued logic circuit based on new multi-valued logic “Fuji algebra”) Patent No. 5363511 (Japanese Patent Laid-Open No. 2011-097637 greatly corrected, multi-value logic circuit based on new multi-value logic “Fuji algebra”), division of Patent Document 2. JP2011-229069 (multi-value hazard elimination circuit) Japanese Patent Application Laid-Open No. 2012-034345 (Multi-value Hazard Removal Circuit) →→ Each of the multi-value logic complete circuits of FIG. 10 and FIG. JP 2012-077504 (Multi-valued logic means having a synchronous latching function and a multi-valued hazard removal circuit) →→ Each multi-valued logic complete circuit of FIGS. 12 and 14 in Patent Document 7. “Digital Digital Circuits Understandable”, p. 9 line 14 to p. "Complete system" on the first line of 10. Author: Keitaro Sekine, published by OHM Co., Ltd. on July 25, 1997. “Introduction to Logic Circuits”, p. 31 “(8) Complete system”. Author: Ryuji Hamabe, published by Morikita Publishing Co., Ltd. on September 28, 2001. "Multi-value information processing-Post binary electronics-", p. 16-p. 17 “completeness, complete system, complete” description. Author: Tatsuo Higuchi, Michitaka Kameyama, Shokodo published in June 1989.

Claims (4)

"The following multi-value NOT means or the following multi-value synchronous NOT means" and "the following multi-value NOT means or the following multi-value synchronous NOT means" having a specific integer different from this are connected in two stages before and after,
"First potential pulling means for pulling up or pulling down the potential of the outlet means in the previous stage to the specified constant potential in the subsequent stage" and "Pulling the potential of the outlet means in the subsequent stage to the specified constant potential in the preceding stage Multi-value NOT two-stage connection means, characterized in that second potential pulling means for up or pulling down is provided.
■■■ Multi-value NOT means ■■■
When three or three or more predetermined plurals are represented by N,
“N constant potentials that increase or decrease in numerical order from the first constant potential to the Nth constant potential” are supplied, and each constant potential and 0 to (N -1), the first constant potential supply means to the Nth constant potential supply means defined as one-to-one correspondence with the first constant potential in order from the integer 0, "
“Inlet means to be the entrance of one input potential signal”;
“Exit means for exiting output potential signal”;
“One specific constant potential supply means determined in advance among the first constant potential supply means to the Nth constant potential supply means” and the outlet means are connected in one direction when driven off. Or pull-switching means that is bi-directionally off, "
“To“ whether or not the input integer corresponding to the input potential signal is equal to or not equal to the specific integer corresponding to the specific constant potential supply means ”is applied to“ the following two or four threshold potentials ” Numerical determination means for determining whether the determination is positive or negative and outputting the determination result as a determination result signal ",
"On / off drive means that operates based on the determination result signal and drives the pull switching means off if the determination result is affirmative, and on-drives it if negative,"
Multi-value NOT means having
■■ Two or four threshold potentials ■■
(1) “Is equal” means “a positive threshold potential and a negative threshold potential determined in advance with reference to a specific constant potential of the specific constant potential supply means”.
* However, when these constant potentials increase in numerical order from the first constant potential to the Nth constant potential, when the specific integer is 0, only the positive threshold potential may be used, or the specific potential When the integer is (N-1), only the negative threshold potential may be used. On the other hand, when these constant potentials decrease in numerical order from the first constant potential to the Nth constant potential, when the specific integer is 0, only the negative threshold potential may be used, or the specific integer When is (N-1), only the positive threshold potential may be used.
(1) “If not,” “a negative threshold potential determined in advance with reference to a constant potential one higher than the specific constant potential among the first constant potential to the Nth constant potential” and “ A positive threshold potential determined in advance with reference to a constant potential one lower than the specific constant potential among the first constant potential to the Nth constant potential ”.
* However, when these constant potentials increase in numerical order from the first constant potential to the Nth constant potential, when the specific integer is 0, only the negative threshold potential may be used, or the specific potential When the integer is (N−1), only the positive threshold potential may be used. On the other hand, when these constant potentials decrease in numerical order from the first constant potential to the Nth constant potential, when the specific integer is 0, only the positive side threshold potential may be used, or the specific integer When (N-1) is, only the negative threshold potential is sufficient.
■■■ Multi-value synchronous NOT means ■■■
In the multi-value NOT means,
The signal connection between the numerical value determination means and the on / off drive means is temporarily disconnected, and during that time, the determination result signal is input “as is or matched” as a hold signal based on the synchronization signal, and the hold signal A “binary synchronous flip-flop means for outputting the“ positive output signal or complementary output signal ”” to the on / off drive means ”,
"Synchronization signal supply means for supplying the synchronization signal to the binary synchronization flip-flop means" is provided,
The on / off driving means drives the pull switching means on / off based on “the positive output signal or the complementary output signal”, but “the output signal on the basis of the pull switching means indicates the input signal at the time of input”. Multi-value synchronous NOT means for driving off if the determination result is affirmative and driving it on if the determination result is negative. The multi-value NOT two-stage connecting means according to claim 1,
When the subsequent stage is the multi-value NOT means, the multi-value NOT means is “a multi-value EVEN means whose on / off driving means is turned on / off in the opposite direction to the positive / negative of the determination result”. ,
When the subsequent stage is the multi-value synchronous NOT means, the multi-value synchronous NOT means “the on / off drive means drives on / off in the opposite direction to the positive / negative of the determination result at the time of input”. Multi-value NOT / EVEN two-stage connection means characterized by being "multi-value synchronous EVEN means". "The following multi-value EVEN means or the following multi-value synchronous EVEN means" and "the following multi-value EVEN means or the following multi-value synchronous EVEN means" having a specific integer different from this are connected in two stages before and after,
"First potential pulling means for pulling up or pulling down the potential of the outlet means in the previous stage to the specified constant potential in the subsequent stage" and "Pulling the potential of the outlet means in the subsequent stage to the specified constant potential in the preceding stage Multi-value EVEN two-stage connection means, characterized in that second potential pulling means for up or pulling down is provided.
■■■ Multi-value EVEN means ■■■
When three or three or more predetermined plurals are represented by N,
“N constant potentials that increase or decrease in numerical order from the first constant potential to the Nth constant potential” are supplied, and each constant potential and 0 to (N -1), the first constant potential supply means to the Nth constant potential supply means defined as one-to-one correspondence with the first constant potential in order from the integer 0, "
“Inlet means to be the entrance of one input potential signal”;
“Exit means for exiting output potential signal”;
“One specific constant potential supply means determined in advance among the first constant potential supply means to the Nth constant potential supply means” and the outlet means are connected in one direction when driven off. Or pull-switching means that is bi-directionally off, "
“To“ whether or not the input integer corresponding to the input potential signal is equal to or not equal to the specific integer corresponding to the specific constant potential supply means ”is applied to“ the following two or four threshold potentials ” Numerical determination means for determining whether the determination is positive or negative and outputting the determination result as a determination result signal ",
"On / off drive means that operates based on the determination result signal and drives the pull switching means on if the determination result is affirmative;
Multi-valued EVEN means having
■■ Two or four threshold potentials ■■
(1) “Is equal” means “a positive threshold potential and a negative threshold potential determined in advance with reference to a specific constant potential of the specific constant potential supply means”.
* However, when these constant potentials increase in numerical order from the first constant potential to the Nth constant potential, when the specific integer is 0, only the positive threshold potential may be used, or the specific potential When the integer is (N-1), only the negative threshold potential may be used. On the other hand, when these constant potentials decrease in numerical order from the first constant potential to the Nth constant potential, when the specific integer is 0, only the negative threshold potential may be used, or the specific integer When is (N-1), only the positive threshold potential may be used.
(1) “If not,” “a negative threshold potential determined in advance with reference to a constant potential one higher than the specific constant potential among the first constant potential to the Nth constant potential” and “ A positive threshold potential determined in advance with reference to a constant potential one lower than the specific constant potential among the first constant potential to the Nth constant potential ”.
* However, when these constant potentials increase in numerical order from the first constant potential to the Nth constant potential, when the specific integer is 0, only the negative threshold potential may be used, or the specific potential When the integer is (N−1), only the positive threshold potential may be used. On the other hand, when these constant potentials decrease in numerical order from the first constant potential to the Nth constant potential, when the specific integer is 0, only the positive side threshold potential may be used, or the specific integer When (N-1) is, only the negative threshold potential is sufficient.
■■■ Multi-value synchronous EVEN means ■■■
In the multi-value EVEN means,
The signal connection between the numerical value determination means and the on / off drive means is temporarily disconnected, and during that time, the determination result signal is input “as is or matched” as a hold signal based on the synchronization signal, and the hold signal A “binary synchronous flip-flop means for outputting the“ positive output signal or complementary output signal ”” to the on / off drive means ”,
"Synchronization signal supply means for supplying the synchronization signal to the binary synchronization flip-flop means" is provided,
The on / off driving means drives the pull switching means on / off based on “the positive output signal or the complementary output signal”, but “the output signal on the basis of the pull switching means indicates the input signal at the time of input”. Multi-value synchronous type EVEN means that, when the “determination result” is affirmative, drives it on, and when it is negative, drives it off. The multi-value EVEN two-stage connection means according to claim 3,
When the subsequent stage is the multi-value EVEN means, the multi-value EVEN means is “a multi-value NOT means that the on / off drive means drives on / off in the opposite direction to the positive / negative of the determination result”. ,
When the subsequent stage is the multi-value synchronous EVEN means, the multi-value synchronous EVEN means “the on / off drive means is turned on / off in the opposite direction to the positive / negative of the determination result at the time of input”. Multi-value EVEN / NOT two-stage connection means characterized by being "multi-value synchronous NOT means".