CN102436847B - PMOS (P-channel Metal Oxide Semiconductor) pipe band-pass-band-stop changeable threshold circuit and PMOS pipe high-pass-low-pass changeable threshold circuit - Google Patents
PMOS (P-channel Metal Oxide Semiconductor) pipe band-pass-band-stop changeable threshold circuit and PMOS pipe high-pass-low-pass changeable threshold circuit Download PDFInfo
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- CN102436847B CN102436847B CN201110291038.5A CN201110291038A CN102436847B CN 102436847 B CN102436847 B CN 102436847B CN 201110291038 A CN201110291038 A CN 201110291038A CN 102436847 B CN102436847 B CN 102436847B
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Abstract
The invention discloses a PMOS (P-channel Metal Oxide Semiconductor) pipe band-pass-band-stop changeable threshold circuit and PMOS pipe high-pass-low-pass changeable threshold circuit; the PMOS pipe band-pass-band-stop changeable threshold circuit is composed of a NMOS (N-channel metal oxide semiconductor) pipe Q1, a NMOS pipe Q3, a PMOS pipe Q2, a PMOS pipe Q4, a PMOS pipe Q5, a resistor R0 and a resistor R1; the PMOS pipe high-pass-low-pass changeable threshold circuit is composed of a NMOS pipe Q1, a PMOS pipe Q2, a PMOS pipe Q5, a resistor R0 and a resistor R1; another PMOS pipe high-pass-low-pass changeable threshold circuit is composed of a NMOS pipe Q3, a PMOS pipe Q4, a PMOS pipe Q5, a resistor R0 and a resistor R1; the band-pass threshold, the band-stop threshold, the high-pass threshold and the low-pass threshold are adjusted by the reference voltage Vref; and the known technology for controlling the MOS pipe valve value can only control the amplitude of the valve value. The 8-value, 10-value and any k-value dynamic memory units can be embedded into the converting circuit for DRAM (Dynamic Random Access Memory) memory array easily by the changeable threshold circuit provided by the invention for realizing multi-value combined logical circuit and the multi-value time sequence logical circuit and making the circuit structure be the simplest. The PMOS pipe band-pass-band-stop changeable threshold circuit and PMOS pipe high-pass-low-pass changeable threshold circuit is applied to the technical fields of VLSI and other digital IC (integrated circuit), such as FPGA (Field Programmable Gate Array), CPLD (Complex Programmable Logic Device), half or full customized ASIC (Application Specific Integrated Circuit), memory and the like.
Description
(1) technical field
The invention belongs to digital integrated circuit field, specifically a kind of PMOS pipe racks lead to-band resistance and high pass-low pass variable threshold circuit.
(2) background technology
Along with the develop rapidly of MOS integrated circuit technique, integrated scale is increasing, and integrated level is more and more higher, and some shortcomings appear in VLSI (VLSI (very large scale integrated circuit)): 1. first on VLSI substrate, wiring but takies more than 70% silicon area; In programmable logic device (PLD) (as FPGA and CPLD), also needed a large amount of interconnectors able to programme (to comprise connecting valve able to programme, as fuse-type switch, anti-fuse-type switch, floating boom programmed element etc.), each logic function block or I/O are coupled together, complete the circuit of specific function, wiring (comprising programming connecting valve) has accounted for the very large cost of material.The proportion that reduces wiring cost becomes very important problem.2. from communication aspect, adopt multi-valued signal can reduce session number; To every line transmitting digital information, binary signal is minimum a kind of of carry information amount, and multi-valued signal carry information amount is greater than binary signal.3. from information storage aspect, adopt multi-valued signal can improve information storage density, particularly utilize metal-oxide-semiconductor grid capacitance storage information (for dynamic RAM DRAM), because same capacitance stores quantity of information is many-valued larger than two-value, many-valued DRAM can improve information storage density greatly than two-value DRAM.The development of Multivalued devices at present is extensively carried out, and Toshiba matches by the CMOS technology of 70nm and the many-valued technology of 2bit/ unit with Sandisk company, at 146mm
2chip on realized the memory capacity of 8Gbit; Toshiba and U.S. SanDisk have delivered the 16gbitNAND flash memory by adopting the many-valued technology in 43nm technique and 2bit/ unit to realize.The 8Gbit product of Samsung exploitation adopts the CMOS technology of 63nm and the many-valued technology of 2bit/ unit.Succeed in developing and the commercialization of 4 value storeies is important steps of many-valued research, but needs to control or change the switching threshold V of pipe
tn, changing threshold method is in semiconductor fabrication process, to use multistage ion implantation technique, or controls the method control threshold values such as amount of electrons of the grid storage of swimming.Not yet find that there is succeeding in developing more than the DRAM of 4 values.
Semiconductor memory can be divided into read only memory ROM and random access memory ram.And RAM is divided into ambipolar and MOS type two classes.Bipolar RAM operating rate is high, but manufacturing process is complicated, power consumption is large, integrated level is low, is mainly used in the occasion of high speed operation.MOS type RAM is divided into again two kinds of static RAM SRAM and dynamic RAM DRAM (Dynamic Random Access Memory).The principle of DRAM storage information is the charge-storage effect based on metal-oxide-semiconductor grid capacitance.Due to the capacity of grid memory capacitance very little (conventionally at the most several pico farads), and leakage current can not definitely equal zero, so the limited time that electric charge is preserved; For the supplementary electric charge of missing is to avoid the dropout of storage in time, necessary timing gives grid memory capacitance supplementary electric charge, conventionally this operation is called and refreshes or regenerate, and DRAM must be aided with necessary refresh control circuit during work.DRAM be by large rectangle memory cell array be used for the supportive logical circuit of pair array read and write, and compositions such as refresh circuit that maintain integrity of data stored.The simplest available single tube dynamic storage cell in DRAM.Storage unit is to line up matrix type structure by row, column, with the decoding respectively of two decoding schemes.X-direction decoding is called row decoding, its output line X
ibe called word line, it chooses all storage unit of a line in storage matrix.Y-direction decoding is called again column decoding, its output line Y
jbe called bit line.Generally DRAM is designed to word length L
w(a word has L in position
wposition, as 1 be, 4,8 or N position), address decoder is translated to output X
iand Y
jexport when effective, simultaneously the L of a selected word
windividual (as 1,4,8 or N) storage unit, make these selected storage unit carry out read-write operation through read/write control circuit, in each sense data, completed the recovery to the original stored data of storage unit.DRAM read-write control circuit is controlled data message input and output.The control signal of outer bound pair storer has read signal R
d, write signal W
rwith chip selection signal C
setc..The figure place of the inputoutput data of DRAM has 1, and 2,4 or N position.Except multidigit input and output, reduce the number of device pin when improving integrated level, the mode that large capacity DRAM usually adopts 1 input, 1 output and address timesharing to input, has input buffer, output buffer and output latch etc. accordingly.
Prior art and existing problems:
1. the many-valued dynamic storage cell embedding more than 4 values in two-value DRAM is difficult, and two-value data is having and without deciding, being easy to read and write by the electric charge of memory capacitance; Multi-valued signal is read and is write and will distinguish magnitude, conventional amplifier easily forms serious distortion to multi-valued signal, conventional sensor amplifier method is difficult to read multi-valued signal, can not realize 8 values, 10 values, 16 values and K value dynamic storage cell circuit embedding DRAM storage array arbitrarily, not yet find that there is succeeding in developing more than the DRAM of 4 values.For embed the many-valued dynamic storage cell more than 4 values in two-value DRAM, can not, by the many-valued dynamic storage cell of the simple consideration of classic method, must consider the two-value-many-valued change-over circuit and the many-valued-two-value change-over circuit that match with multilevel memory cell simultaneously.
2. in realizing multivalued circuit, prior art is controlled metal-oxide-semiconductor threshold value very large shortcoming: the amplitude of 1. controlling threshold value limited (because of ion implantation concentration limited), open resolution low; And in technique, control threshold amplitude and often can change the performance of metal-oxide-semiconductor, for example the sharp increase that causes cutting off electric current is returned in the reduction of threshold voltage, and the adjustment of threshold voltage has impact to the performance of pipe and stability, stable V
tnand V
tpextremely important.To many-valued memory, the amount of electrons of injecting the grid that swims is continually varying, needs very fine and controls, and each threshold voltage level does not still reach quasi-stationary state.Therefore the voltage-type multivalued circuit of practicality is not more than 4 value circuit at present, and more multivalued circuit application is more difficult.2. can only control the amplitude of threshold value, can not realize the interval character of opening of metal-oxide-semiconductor threshold, often require metal-oxide-semiconductor just to open in the voltage range that input is being stipulated, claim that this is the logical threshold value of band, similar have band to hinder threshold value, high pass threshold value, low pass threshold value.Multivalued gate must have (comprising two-value-many-valued change-over circuit and many-valued-two-value change-over circuit) metal-oxide-semiconductor of multiple unlatching character, just can make circuit structure the simplest, yet only control threshold amplitude, make multivalued circuit structural difference very large, complex structure, affects its realization.3. need to increase the extra operation of Implantation, can only in semiconductor fabrication process, control threshold value, both increased process complexity, again can not after by user, control threshold value, or non-programmable to threshold users.
(3) summary of the invention
Lead to-band hinders and high pass-low pass variable threshold circuit to the present invention seeks to disclose a kind of PMOS pipe racks.
Above-mentioned object realizes by following technical scheme:
1. lead to-band of a kind of PMOS pipe racks of the present invention resistive threshold cirtuit is achieved in that as shown in Figure 6, and lead to-band of described PMOS pipe racks resistive threshold cirtuit is by two NMOS pipe Q
1, Q
3with three PMOS pipe Q
2, Q
4, Q
5, and two resistance R
0, R
1form; Pipe Q
1and Q
2source electrode join, pipe Q
3and Q
4source electrode join, pipe Q
2and Q
4drain electrode meet direct supply V
sS, pipe Q
1, Q
3drain electrode and pipe Q
5grid and resistance R
1one end be connected, this junction is as band resistance output V
out0, resistance R
1the other end and PMOS pipe Q
5source electrode receive direct supply V
dC, NMOS manages Q
1with PMOS pipe Q
4grid meet outer input V
x, PMOS manages Q
2with NMOS pipe Q
3grid meet respectively reference voltage V
ref1and V
ref0, V
dC>=V
x>=V
sS, V
dC>=V
ref1>=V
sS, V
dC>=V
ref0>=V
sS, pipe Q
5drain electrode and resistance R
0one end be connected, this junction is as the logical output of band V
out1, resistance R
0another termination direct supply V
d, V
dC=5.5V, V
sS=0V, V
d=4V; Upper threshold value V
ex1=V
ref1-V
dC+ V
tn1+ | V
tp2|, lower threshold value V
ex0=V
ref0-V
dC-V
tn3-| V
tp4|, meet V
ex1> V
ex0, V wherein
tn1, V
tn3and V
tp2, V
tp4be respectively NMOS pipe Q
1, Q
3with PMOS pipe Q
2, Q
4threshold voltage, V
tn1> 0, V
tn3> 0, V
tp2< 0, V
tp4< 0, the logical output of band V
out1with band resistance output V
out0be transported to respectively controlled PMOS pipe Q
b1and Q
r0grid, pipe Q
b1and Q
r0source electrode meet V
dC, complete thus: 1. work as V
ex1> V
x-V
dC> V
ex0time, pipe Q
b1conducting, otherwise, do not meet V
ex1> V
x-V
dC> V
ex0time, pipe Q
b1cut-off, 2. works as V
ex1> V
x-V
dC> V
ex0time, pipe Q
r0cut-off, otherwise, do not meet V
ex1> V
x-V
dC> V
ex0time, pipe Q
r0conducting; Also input poor V
x-V
dCat the interval (V of band
ex0, V
ex1) in, pipe Q
b1conducting, pipe Q
r0cut-off, the interval (V of band
ex0, V
ex1) by changing reference voltage V
ref1and V
ref0adjust.Note: be connected to band logical-with the PMOS pipe Q of resistive threshold cirtuit
b1be called band general formula variable threshold PMOS pipe, tb=(V
ex0, V
ex1), tb is the logical threshold of band; Be connected to band logical-with the PMOS pipe Q of resistive threshold cirtuit
r0be called band resistive variable threshold PMOS pipe, t/b=(V
ex0, V
ex1), t/b is called band resistance threshold; Symbol tb and t/b are marked on respectively pipe Q
b1and Q
r0by grid, represent respectively pipe Q
b1conducting and pipe Q in the logical threshold of band
r0in band resistance threshold, end.
Of the present invention a kind of have PMOS pipe racks described in above-mentioned 1 logical-PMOS pipe high pass-low pass variable threshold circuit of forming with the part-structure of resistive threshold cirtuit is achieved in that as shown in Figure 7, described PMOS pipe high pass-low pass variable threshold circuit is by a NMOS pipe Q
1with two PMOS pipe Q
2, Q
5, and two resistance R
0, R
1form pipe Q
1and Q
2source electrode join, pipe Q
2drain electrode meet direct supply V
sS, NMOS manages Q
1drain electrode and PMOS pipe Q
5grid and resistance R
1one end be connected, V is exported as high pass in this junction
out1, resistance R
1the other end and pipe Q
5source electrode receive direct supply V
dC, NMOS manages Q
1grid meet outer input V
x, PMOS manages Q
2grid meet reference voltage V
ref1, V
dC>=V
x>=V
sS, V
dC>=V
ref1>=V
sS, pipe Q
5drain electrode and resistance R
0one end be connected, V is exported as low pass in this junction
out0, resistance R
0another termination direct supply V
d, V
d=4V, V
dC=5.5V, V
sS=0V; Upper threshold value V
ex1=V
ref1-V
dC+ V
tn1+ | V
tp2|, V wherein
tn1and V
tp2be respectively NMOS pipe Q
1with PMOS pipe Q
2threshold voltage, V
tn1> 0, V
tp2< 0, high pass output V
out1with low pass output V
out0be transported to respectively controlled PMOS pipe Q
h1and Q
l0grid, pipe Q
h1and Q
l0source electrode meet V
dC, complete thus: 1. work as V
x-V
dC> V
ex1time, pipe Q
h1conducting, otherwise, do not meet V
x-V
dC> V
ex1time, pipe Q
h1cut-off, 2. works as V
x-V
dC> V
ex1time, pipe Q
l0cut-off, otherwise, do not meet V
x-V
dC> V
ex1time, pipe Q
l0conducting; Input V
xat V
x-V
dC> V
ex1time, pipe Q
h1conducting, pipe Q
l0cut-off, V
ex1by changing reference voltage V
ref1adjust.Note: the PMOS pipe Q that is connected to high pass-low pass variable threshold circuit
h1be called high general formula variable threshold PMOS pipe, th=(> V
ex1), th is for claiming high pass threshold; Be connected to the PMOS pipe Q of high pass-low pass variable threshold circuit
l0be called low general formula variable threshold PMOS pipe, t/h=(< V
ex1), t/h is called low pass threshold; Symbol th and t/h are marked on respectively pipe Q
h1and Q
l0by grid, represent respectively pipe Q
h1conducting and pipe Q in high pass threshold
l0conducting in low pass threshold.
Of the present invention have PMOS pipe racks described in above-mentioned 1 logical-another kind of PMOS pipe high pass-low pass variable threshold circuit of forming with the part-structure of resistive threshold cirtuit, be achieved in that as shown in Figure 8, described PMOS pipe high pass-low pass variable threshold circuit is by a NMOS pipe Q
3with two PMOS pipe Q
4, Q
5, and two resistance R
0, R
1form pipe Q
3and Q
4source electrode join, pipe Q
4drain electrode meet direct supply V
sS, NMOS manages Q
3drain electrode and PMOS pipe Q
5grid and resistance R
1one end be connected, V is exported as low pass in this junction
out0, resistance R
1the other end and pipe Q
5source electrode receive direct supply V
dC, NMOS manages Q
3grid meet reference voltage V
ref0, PMOS manages Q
4grid meet outer input V
x, V
dC>=V
x>=V
sS, V
dC>=V
ref0>=V
sS, pipe Q
5drain electrode and resistance R
0one end be connected, V is exported as high pass in this junction
out1, resistance R
0another termination direct supply V
d, V
d=4V, V
dC=5.5V, V
sS=0V; Lower threshold value V
ex0=V
ref0-V
dC-V
tn3-| V
tp4|, V wherein
tn3and V
tp4be respectively NMOS pipe Q
3with PMOS pipe Q
4threshold voltage, V
tn3> 0, V
tp4< 0, high pass output V
out1with low pass output V
out0be transported to respectively controlled PMOS pipe Q
h1and Q
l0grid, pipe Q
h1and Q
l0source electrode meet V
dC, complete thus: 1. work as V
x-V
dC> V
ex0time, pipe Q
h1conducting, otherwise, do not meet V
x-V
dC> V
ex0time, pipe Q
h1cut-off, 2. works as V
x-V
dC> V
ex0time, pipe Q
t0cut-off, otherwise, do not meet V
x-V
dC> V
ex0time, pipe Q
l0conducting; Input V
xat V
x-V
dC> V
ex0time, pipe Q
h1conducting, pipe Q
l0cut-off, V
ex0by changing reference voltage V
ref0adjust.Note: the PMOS pipe Q that is connected to high pass-low pass variable threshold circuit
h1be called high general formula variable threshold PMOS pipe, th=(> V
ex0), th is called high pass threshold; Be connected to the PMOS pipe Q of high pass-low pass variable threshold circuit
l0be called low general formula variable threshold PMOS pipe, t/h=(< V
ex0), t/h is called low pass threshold; Symbol th and t/h are marked on respectively pipe Q
h1and Q
l0by grid, represent respectively pipe Q
h1conducting and pipe Q in high pass threshold
l0conducting in low pass threshold.
The present invention also has following technical characterictic:
(1) according to lead to-band of above-mentioned a kind of PMOS pipe racks resistive threshold cirtuit, or according to a kind of PMOS pipe high pass-low pass variable threshold circuit described in above-mentioned 2, or according to a kind of PMOS pipe high pass-low pass variable threshold circuit described in above-mentioned 3, it is characterized in that: get V
dC=1.8V, V
sS=-3.5V, V
d=0V
(2) according to lead to-band of a kind of PMOS pipe racks described in above-mentioned 1 resistive threshold cirtuit, resistance R in this circuit
1be taken as constant current source I
1, electric current I
1by V
dCflow to pipe Q
1and Q
3drain electrode.
(3) according to a kind of PMOS pipe high pass-low pass variable threshold circuit described in above-mentioned 2, resistance R in this circuit
1be taken as constant current source I
1, electric current I
1by V
dCflow to pipe Q
1.
(4) according to a kind of PMOS pipe high pass-low pass variable threshold circuit described in above-mentioned 3, resistance R in this circuit
1be taken as constant current source I
1, electric current I
1by V
dCflow to pipe Q
3.
Description of contents and advantage that the present invention is concrete are described below:
1. by three kinds of circuit that are closely related of a total inventive concept Uniting: band is logical-with the band of resistive threshold cirtuit interval be V
ex1> V
x-V
dC> V
ex0, and be with interval V
ex1> V
x-V
dC> V
ex0can see V as
ex1-V
dC> V
x(low interval) and V
x-V
dC> V
ex0the combination of (high interval), has shown that high interval and low interval are V
x-V
dC> V
ex0and V
ex1> V
x-V
dC2 high pass-low pass variable threshold circuit can merge into 1 band logical-band resistive threshold cirtuit; Band lead to-includes the composition of high pass-low pass variable threshold circuit with resistive threshold cirtuit; Low interval (V
ex1> V
x-V
dC) negate is high interval (V
x-V
dC> V
ex1), high interval (V
x-V
dC> V
ex0) negate is low interval (V
ex0> V
x-V
dC), therefore high pass-low pass variable threshold circuit be have PMOS pipe racks described in above-mentioned 1 logical-with the part-structure of resistive threshold cirtuit, form, can there be 2 kinds of possible implementations, their circuit structures have general character, note: band lead to-is realized by two branch circuit parallel connections with resistive threshold cirtuit, high pass-low pass variable threshold circuit is taken apart as single branch road and is realized by two parallel branches, take and is with logical-band resistive threshold cirtuit as main.
2., in lead at PMOS pipe racks of the present invention-band resistive threshold cirtuit and high pass-low pass variable threshold circuit, PMOS manages Q
pMOSconducting and cut-off depend on Q
pMOSthe relative source potential of grid poor (negative value), considers Q
pMOSsource electrode meets V
dC, Q
pMOSgrid meets input V
x, by V
x-V
dCdetermine Q
pMOSconducting and cut-off; Work as V
xduring variation, observe emphatically V
xrelative V
dCdifference V
x-V
dC, at Q
pMOSjust from being conducting to cut-off or just from by the end of the conducting poor V of input of moment
x-V
dCvalue be exactly Q
pMOSthreshold value (negative value); For convenience of description, get V
dC=5.5V, V
sS=0V, V
d=4V; The operating voltage V of DRAM in practicality
dCfor 1.8V, for 8 value storage unit being embedded to 2 value DRAM storage matrix, get V
dC=1.8V, V
sS=-3.5V, V
d=0V, although V
dCreduce, consider V
xrelative V
dCdifference V
x-V
dC, its result and aforementioned identical, note: the former is V
dC=5.5V, V
sS=0V, the substrate of PMOS pipe meets supply voltage V
dC(∵ maximum potential is 5.5V), the substrate ground connection of NMOS pipe (∵ potential minimum is 0V); The latter V
dC=1.8V, V
sS=-3.5V, the substrate of PMOS pipe meets supply voltage V
dC(∵ maximum potential is 1.8V), the substrate of NMOS pipe meets V
sS(∵ potential minimum is-3.5V).
PMOS pipe racks of the present invention logical-with the band of resistive threshold cirtuit lead to, with resistance scope and the high pass of high pass-low pass variable threshold circuit, the threshold interval of low pass is by changing reference voltage V
ref1and V
ref0adjust, setting range is wide, easy to adjust, as easy as rolling off a log realization.
Threshold value control technology of the present invention is obviously better than existing PMOS pipe threshold control technology: 1. prior art can only be controlled the amplitude of threshold value, and the amplitude of controlling threshold value limited (because of ion implantation concentration limited), unlatching resolution is low, can not realize the interval character of opening of PMOS pipe threshold, also not control so far the technology in PMOS pipe threshold interval.Show by analysis: multi valued logic often needs PMOS pipe just to open in the voltage range (threshold is interval) of input in regulation, claim that this is the logical threshold value of band, similar needs have band resistance threshold value, high pass threshold value, low pass threshold value; PMOS pipe racks of the present invention is logical-with resistive threshold cirtuit and high pass-low pass variable threshold circuit, overcome the shortcoming of prior art completely, change the present situation of the amplitude of the simple PMOS of control threshold value, the satisfactory control technology that realizes PMOS pipe threshold interval, the interval setting range of PMOS pipe threshold is wide; Be widely used in multivalued gate (comprising two-value-many-valued change-over circuit and many-valued-two-value change-over circuit), be widely used in many-valued dynamic storage cell is embedded to conventional DRAM, make multivalued circuit simple in structure, DRAM capacity significantly increases, and is easy to realize multivalued circuit and the many-valued DRAM that is greater than 4; Note: practical voltage-type multivalued circuit is not more than 4 value circuit at present, and more multivalued circuit application prior art is very difficult.2. prior art need to increase the extra operation of Implantation, can only in semiconductor fabrication process, control threshold value, has both increased process complexity, again can not after by user, control threshold value, or non-programmable to threshold users; Threshold interval of the present invention is by changing reference voltage V
ref1and V
ref0adjust, user adjusts simple and convenient, and setting range is wide, user-programmable.Particularly, reference voltage V
ref1and V
ref0be all the grid of receiving metal-oxide-semiconductor, the grid of metal-oxide-semiconductor is high resistant, reference voltage V
ref1and V
ref0the DC current that absorbs power supply is 0; For obtaining the different reference voltages of a sequence, can be used on direct supply V
dCand V
sSbetween (by common method) bleeder circuit of connecing the series connection of a plurality of resistance realize, also can be used on direct supply V
dCand V
sSthe bleeder circuit of indirect a plurality of diode (or field-effect diode) series connection is realized (also wherein according to circumstances need can resistance in series), and a plurality of diode cathodes are the same with the connection of conventional battery series connection with negative pole connection, as k diode D
1～D
k, D
1positive pole meets direct supply V
dC, D
1negative pole meets D
2positive pole, D
2negative pole meets D
3positive pole, D
3negative pole meets D
4positive pole ..., D
k-2negative pole meets D
k-1positive pole,, D
k-1negative pole meets D
kpositive pole, D
knegative pole meets V
sS(or meet V by R
sS), the different reference voltage V of sequence
refbe all to output to metal-oxide-semiconductor grid, output DC current is almost 0, implements easily.
(4) accompanying drawing explanation
Fig. 1. be the circuit diagram of the relevant a kind of 8 value storage unit embedding 2 value DRAM storage matrix of the present invention;
Fig. 2. be the relevant the first 8 value storage unit M of the present invention
ijcircuit diagram;
Fig. 3. be current source I in Fig. 2
juse resistance R instead
jthe second 8 value storage unit M
ijcircuit diagram;
Fig. 4. be the circuit diagram of the relevant a kind of 2-8 value change-over circuit BMVC of the present invention;
Fig. 5. be the circuit diagram of the relevant a kind of 8-2 value change-over circuit MBVC of the present invention;
Fig. 6. for a kind of PMOS pipe racks of the present invention leads to-band resistive threshold cirtuit and graphical diagram;
Fig. 7. be the first PMOS pipe high pass-low pass variable threshold circuit of the present invention and graphical diagram;
Fig. 8. be the second PMOS pipe high pass-low pass variable threshold circuit of the present invention and graphical diagram;
Fig. 9. be the accurate mirror-image constant flow source circuit diagram of existing a kind of many output and graphical diagram;
Figure 10. for the value of 8 shown in Fig. 1 storage unit embeds 2 circuit that are worth DRAM storage matrix at X
iand Y
jduring for high level, b
j+2, b
j+1, b
j, Y
wRj, Y
rDj, m
j+2, m
j+1, m
jsuccessively upper and lower discrete oscillogram;
Figure 11. for the 2-8 value change-over circuit BMVC shown in Fig. 4 is at X
iand Y
jduring for high level, b
j+2, b
j+1, b
j, f
j7, f
j6, f
j5, f
j4, f
j3, f
j2, f
jsuccessively upper and lower discrete oscillogram;
Figure 12. for the 2-8 value change-over circuit BMVC shown in Fig. 4 is at X
iand Y
jduring for high level, Y
wRj, D
mCij, f
j7, f
j6, f
j5, f
j4, f
j3, f
j2, f
j1successively upper and lower discrete oscillogram; ;
Figure 13. for the 8-2 value change-over circuit MBVC shown in Fig. 5 is at X
iand Y
jduring for high level, D
mij, Y
rDj, th
j4, th
j5, tb
j0, tb
j1, tb
j2, tb
j3, th
j6successively upper and lower discrete oscillogram;
Figure 14. for the 8-2 value change-over circuit MBVC shown in Fig. 5 is at X
iand Y
jduring for high level, m
j+2, m
j+1, m
j, th
j4, th
j5, tb
j0, tb
j1, tb
j2, b
j3, th
j6successively upper and lower discrete oscillogram;
Figure 15. be reference voltage V in lead to-band of the band shown in Fig. 6 resistive threshold cirtuit
ref1and V
ref0get successively 4 class values: 2.2V and 3.85V, 2.2V and 3.3V, 2.2V and 2.2V, 3.3V and 2.2V, pipe Q
5the output of drain electrode is followed successively by tb
j0, tb
j1, tb
j2, tb
j3, input V
xinput-output wave shape figure during for triangular wave bin;
Figure 16. be reference voltage V in lead to-band of the band shown in Fig. 6 resistive threshold cirtuit
ref1and V
ref0get successively 4 class values: 2.2V and 3.85V, 2.2V and 3.3V, 2.2V and 2.2V, 3.3V and 2.2V, pipe Q
5the output of grid is followed successively by t/b
j0, t/b
j1, t/b
j2, t/b
j3, input V
xinput-output wave shape figure during for triangular wave bin;
Figure 17. be reference voltage V in the high pass-low pass variable threshold circuit shown in Fig. 7
ref1be followed successively by 3.85V, 2.2V, V in the high pass-low pass variable threshold circuit shown in Fig. 8
ref0be followed successively by 1.65V and 3.3V, under 4 kinds of reference voltages, manage Q
5the output of drain electrode is followed successively by t/h
j4, t/h
j5, th
j5, th
j6, input V
xinput-output wave shape figure during for triangular wave bin;
Figure 18. be reference voltage V in the high pass-low pass variable threshold circuit shown in Fig. 7
ref1be followed successively by 3.85V, 2.2V, V in the high pass shown in Fig. 8, low pass variable threshold circuit
ref0be followed successively by 1.65V and 3.3V, under 4 kinds of reference voltages, manage Q
5the output of grid is followed successively by th
j4, th
j5, t/h
j5, t/h
j6, input V
xinput-output wave shape figure during for triangular wave bin;
Figure 19. be the circuit diagram of the relevant another kind 8 value storage unit embedding 2 value DRAM storage matrix of the present invention.
(5) embodiment
Below in conjunction with accompanying drawing, the invention will be further described for example.
Embodiment 1: the explanation of PMOS pipe racks of the present invention lead to-band resistance and high pass-low pass variable threshold circuit function:
Referring to lead to-band of the PMOS pipe racks shown in Fig. 6 resistive threshold cirtuit, V in circuit
dC=5.5V, V
sS=0V, V
d=4V, upper threshold value V
ex1=V
ref1-V
dC+ V
tn1+ | V
tp2|, lower threshold value V
ex0=V
ref0-V
dC-V
tn3-| V
tp4|, note: PMOS manages Q
pMOSconducting and cut-off depend on Q
pMOSthe relative source potential of grid poor (negative value), considers Q
pMOSsource electrode meets V
dC, Q
pMOSgrid meets input V
x, V
x-V
dCdetermine Q
pMOSconducting and cut-off, work as V
xduring variation, at Q
pMOSjust from being conducting to cut-off or just from by the end of the conducting V of moment
x-V
dCvalue be exactly Q
pMOSthreshold value (negative value); First analyzer tube Q
1, Q
2branch road, V
g1=V
x, V
g2=V
ref1, pipe Q
1grid to the poor V that is respectively of source potential
gs1, pipe Q
2source electrode to the poor V that is respectively of grid potential
sg2, because pipe Q
1and Q
2two source electrodes join, only when pipe Q
1and Q
2the poor V of two grid voltages
x-V
ref1=V
g1-V
g2=V
gs1+ V
sg2>=V
tn1+ | V
tp2| time, pipe Q
1, Q
2just conducting of branch road, otherwise, V
x-V
ref1< V
tn1+ | V
tp2| (V
x-V
dC< V
ref1-V
dC+ V
tn1+ | V
tp2|=V
ex1), pipe Q
1, Q
2branch road cut-off, works as V
ex1> V
x-V
dCtime, pipe Q
1, Q
2branch road cut-off, otherwise, pipe Q
1, Q
2branch road conducting.Similar approach analyzer tube Q
3, Q
4branch road, V
g4=V
x, V
g3=V
ref0, as pipe Q
3and Q
4the poor V of two grid voltages
ref0-V
x>=V
tn3+ | V
tp4| time, pipe Q
3, Q
4branch road conducting, otherwise, V
ref0-V
x< V
tn3+ | V
tp4| (V
x-V
dC> V
ref0-V
dC-V
tn3-| V
tp4|=V
ex0), pipe Q
3, Q
4branch road cut-off, works as V
x-V
dC> V
ex0time, pipe Q
3, Q
4branch road cut-off, otherwise, pipe Q
3, Q
4branch road conducting.The logical output of band V
out1with band resistance output V
out0be transported to respectively controlled PMOS pipe Q
b1and Q
r0grid, pipe Q
b1and Q
r0source electrode meet V
dC, pipe Q
b1and Q
r0drain electrode connect external circuit; Note: resistance R in figure
0also available NMOS manages Q
0replace (Q
0grid meets Q
5grid, Q
0drain electrode meets Q
5drain electrode, Q
0source electrode meets V
d, manage Q
0replace resistance R
0after, pipe Q
0and Q
5form CMOS phase inverter); Draw thus: 1. work as V
ex1> V
x-V
dC> V
ex0when (in band is interval), pipe Q
1, Q
2branch road and pipe Q
3, Q
4branch road full cut-off, resistance R
3electric current be 0, V
out0=V
dC, make Q
5cut-off, V
out1=V
d, make Q
b1conducting, shows: work as V
ex1> V
x-V
dC> V
ex0when (in band is interval), Q
b1conducting, otherwise, do not meet V
ex1> V
x-V
dC> V
ex0when (band is interval outer), Q
b1cut-off, band interval is (V
ex0, V
ex1), in brief, V
x-V
dCq in band is interval
b1conducting; Be connected to band logical-with the PMOS pipe Q of resistive threshold cirtuit
b1be called band general formula variable threshold PMOS pipe, tb=(V
ex0, V
ex1), claim tb for the logical threshold of band, i.e. the poor V of input
x-V
dCin the logical threshold inner tube conducting of band; 2. work as V
ex1> V
x-V
dC> V
ex0when (in band is interval), Q
1, Q
2branch road and Q
3, Q
4branch road has a branch road conducting, resistance R
3electric current larger, V
out0form low level, make Q
r0cut-off, otherwise, do not meet V
ex1> V
x-V
dC> V
ex0when (band is interval outer), Q
r0conducting, in brief, V
x-V
dCq in band is interval
r0cut-off; Be connected to band logical-with the PMOS pipe Q of resistive threshold cirtuit
r0be called band resistive variable threshold PMOS pipe, t/b=(V
ex0, V
ex1), claim t/b for band resistance threshold, i.e. the poor V of input
x-V
dCin the cut-off of band resistance threshold inner tube, the logical threshold tb of band and band resistance threshold t/b are distinguished by symbol ' b ' and '/b ', and symbol tb and t/b are marked on respectively pipe Q
b0and Q
r0by grid, represent respectively Q
b0conducting and Q in the logical threshold of band
r0in band resistance threshold, end; This band that PMOS pipe racks lead to-is required to meet with resistive threshold cirtuit is just logical, belt-resistance function.Referring to the first PMOS pipe high pass-low pass variable threshold circuit shown in Fig. 7, this circuit structure is the Q leaving out in Fig. 6
3, Q
4branch road also exchanges V
out0and V
out1draw V in figure
out0and V
out1still meet separately Q
l0and Q
h1grid, pipe Q
h1and Q
l0source electrode meet V
dC, pipe Q
h1and Q
l0drain electrode connect external circuit, note: resistance R in figure
0also available NMOS manages Q
0replace (Q
0grid meets Q
5grid, Q
0drain electrode meets Q
5drain electrode, Q
0source electrode meets V
d, manage Q
0replace resistance R
0after, pipe Q
0and Q
5form CMOS phase inverter); By above-mentioned same method analyzer tube Q
1, Q
2branch road, as pipe Q
1and Q
2the poor V of grid voltage
x-V
ref1>=V
tn1+ | V
tp2| time, pipe Q
1, Q
2branch road conducting, otherwise, pipe Q
1, Q
2branch road cut-off, works as V
x-V
dC> V
ex1when (high interval), pipe Q
1, Q
2branch road conducting, now V
out1for low level, make Q
h1conducting; V
out0=V
dC, make Q
l0cut-off; In brief, V
x-V
dCq in high interval
h1conducting, Q
l0cut-off; Be connected to the PMOS pipe Q of high pass-low pass variable threshold circuit
h1be called high general formula variable threshold PMOS pipe, th=(> V
ex1), th is called high pass threshold, i.e. and input difference is greater than the conducting of high pass threshold tube; Be connected to the PMOS pipe Q of high pass-low pass variable threshold circuit
l0be called low general formula variable threshold PMOS pipe, t/h=(< V
ex1), t/h is called low pass threshold, i.e. and input difference is less than the conducting of low pass threshold tube; High pass threshold th and low pass threshold t/h are distinguished by symbol ' h ' and '/h ', and symbol th and t/h are marked on respectively pipe Q
h1and Q
l0by grid, represent respectively pipe Q
h1conducting and pipe Q in high pass threshold
l0conducting in low pass threshold; This is satisfied high pass, the lowpass function of PMOS pipe high pass-low pass variable threshold circuit requirement just.
Referring to the second PMOS pipe high pass-low pass variable threshold circuit shown in Fig. 8, this circuit structure is the Q leaving out in Fig. 6
1, Q
2branch road draws, note: resistance R in figure
0also available NMOS manages Q
0replace (by above-mentioned identical connection, Q
0and Q
5form CMOS phase inverter); By above-mentioned same method analyzer tube Q
3, Q
4branch road, as pipe Q
3and Q
4the poor V of grid voltage
ref0-V
x>=V
tn3+ | V
tp4| time, pipe Q
3, Q
4branch road conducting, otherwise, pipe Q
3, Q
4branch road cut-off, works as V
x-V
dC≤ V
ex0when (low interval), pipe Q
3, Q
4branch road conducting, V
out0for low level, make Q
l0conducting, V
out1=V
dC, make Q
h1cut-off; In brief, V
x-V
dCq in low interval
l0conducting, Q
h1cut-off; Be connected to the PMOS pipe Q of high pass-low pass variable threshold circuit
h1be called high general formula variable threshold PMOS pipe, th=(> V
ex0), th is called high pass threshold, and input difference is greater than the pipe conducting of high pass presentation time; Be connected to the PMOS pipe Q of high pass-low pass variable threshold circuit
l0be called low general formula variable threshold PMOS pipe, t/h=(< V
ex0), t/h is called low pass threshold, and input difference is less than the pipe conducting of low pass presentation time; High pass threshold th and low pass threshold t/h are distinguished by symbol ' h ' and '/h ', and symbol th and t/h are marked on respectively pipe Q
h1and Q
l0by grid, represent respectively pipe Q
h1conducting and pipe Q in high pass threshold
l0conducting in low pass threshold; This is satisfied high pass, the lowpass function of PMOS pipe high pass-low pass variable threshold circuit requirement just.
Above-mentioned band leads to threshold, band resistance threshold, and high pass threshold and low pass threshold comprise voltage range and open two attributes of character, at metal-oxide-semiconductor grid, are marked with symbol tb, t/b, th or t/h represent its attribute.For simplifying, write, the threshold control signal threshold signal tb of metal-oxide-semiconductor grid, threshold signal t/b, threshold signal th or threshold signal t/h represent, before above-mentioned symbol, add ' threshold signal ', with this, represent the connotation of grid control signal.Change V
ref1make V
ex1change the first PMOS pipe high pass-low pass variable threshold circuit diagram 7 (V
ex1=V
ref1-V
dC+ V
tn1+ | V
tp2|) can not realize and be less than V
tn1+ | V
tp2|+V
sS-V
dCupper threshold value V
ex1; Change V
ref0make V
ex0change the second PMOS pipe high pass-low pass variable threshold circuit diagram 8 (V
ex0=V
ref0-V
dC-V
tn3-| V
tp4|) can not realize be greater than-V
tn3-| V
tp4| lower threshold value V
ex0, often need be used in conjunction with two kinds of PMOS pipe high pass-low pass variable threshold circuit.R in Fig. 6～8
1available constant current source I
1replace (electric current I
1by V
dCflow to pipe Q
1and Q
3drain electrode).
Note: routine meets supply voltage V by the substrate of PMOS pipe
dC(∵ maximum potential is V
dC), by the substrate ground connection of NMOS pipe (∵ potential minimum is ground); DRAM operating voltage V
dCbe generally 1.8V and 1.5V, if embed multilevel memory cell in two-value DRAM, memory capacitance C wherein
jwhat store is multi valued logic level, and multi valued logic level maximal value is V
dC(maximum potential), multi valued logic level minimum value is negative supply voltage V
sS(potential minimum), multilevel memory cell operating voltage is at V
dCand V
sSbetween, so the substrate of PMOS pipe still meets DC voltage V
dC(∵ maximum potential is V
dC), but the substrate of NMOS pipe should change into and meets V
sS(∵ potential minimum is V
sS), as V
dC=1.8V, V
sS=-3.5V.In lead to-band resistive threshold cirtuit of above-mentioned band and high pass-low pass variable threshold circuit, get V
dC=5.5V, V
sS=0V, V
d=4V, considers to embed multilevel memory cell now, changes into and gets V
dC=1.8V, V
sS=-3.5V, V
d=0V, because V
ex0and V
ex1according to Q
pMOSjust from being conducting to cut-off or just from by the end of the conducting V of moment
x-V
dCdetermine, although V
dCreduce, but based on relative V
dCthe V that considers of difference
ex0and V
ex1numerical value is constant;
Embodiment 2: to Fig. 6, and the explanation of 7,8 Pspice computer simulation waveform Figure 15～18.
(V in Fig. 6,7,8 in lead to-band of PMOS pipe racks of the present invention resistive threshold cirtuit Fig. 6
dC=5.5V, V
sS=0V, V
d=4.0V), at reference voltage V
ref1and V
ref0get successively 4 class values: 2.2V and 3.85V, 2.2V and 3.3V, 2.2V and 2.2V, 3.3V and 2.2V, input V
xduring for triangular wave bin, threshold signal tb
j0, tb
j1, tb
j2, tb
j3(at pipe Q
5the logical output of the band formation successively that drain electrode is extremely corresponding) Pspice computer simulation waveform shows as 4, Figure 15 top curve; Threshold signal t/b
j0, t/b
j1, t/b
j2, t/b
j3(at pipe Q
5the band resistance output formation successively that grid is corresponding) Pspice computer simulation waveform is 4, Figure 16 top curve, and Figure 15 and Figure 16 curve is bottom triangular wave bin, and all curves tops (maximal value) approach V
dC.With relative V
dCrange of decrease V
x-V
dCjust to V
tpbe as the criterion and check negative pulse and positive pulse, V
tpfor PMOS pipe Q
r0and Q
b1threshold value; In the curve of 4, Figure 15 top lower than V
dCnegative pulse be all in the linear rising area of triangular wave bin or linear decline district, show Q
b1(V in band is interval
ex1> V
x-V
dC> V
ex0) conducting; In the curve of 4, Figure 16 top, approach V
dCpositive pulse be all in the linear rising area of triangular wave bin or linear decline district, show Q
r0(V in band is interval
ex1> V
x-V
dC> V
ex0) cut-off, satisfied band is logical, belt-resistance function.
In Figure 15 and Figure 16, as threshold signal tb
j0, tb
j1, tb
j2, tb
j3t be constantly worth relative V
dCrange of decrease V
x-V
dClower than V
tp, this constantly corresponding PMOS manages Q
b1conducting; As threshold signal t/b
j0, t/b
j1, t/b
j2, t/b
j3t be constantly worth relative V
dCrange of decrease V
x-V
dClower than V
tp, this constantly corresponding PMOS manages Q
r0conducting; As input V
xduring for triangular wave bin, pipe Q
r0and Q
b1the just conducting poor V of input constantly
x-V
dCinstantaneous value is just V respectively
ex0and V
ex1, by Figure 15 and Figure 16, can find successively the V under each reference voltage
ex0and V
ex1measured value is :-2.95V and-2.0V ,-3.45V and-2.0V ,-4.45V and-2.0V ,-4.45V and-0.85V.Under each reference voltage, press V
ex0and V
ex1value computing formula V
ex1=V
ref1-V
dC+ V
tn1+ | V
tp2| and V
ex0=V
ref0-V
dC-V
tn3-| V
tp4| theory of computation value, calculates V
ex0and V
ex1theoretical value is followed successively by :-2.8V and-2.15V ,-3.35V and-2.15V ,-4.45V and-2.15V ,-4.45V and-1.05V.Calculating shows, theoretical value and measured value approach, and the two has minute differences (in 0.2V), and minute differences is because metal-oxide-semiconductor actual threshold in circuit has minor alteration with the change of grid reference voltage.
(this circuit structure is the Q leaving out in Fig. 6 to the first PMOS pipe high pass-low pass variable threshold circuit diagram 7 of the present invention
3, Q
4branch road also exchanges V
out0and V
out1draw), reference voltage V
ref1be followed successively by 3.85V, 2.2V, (this circuit structure is the Q leaving out in Fig. 6 to the second PMOS pipe high pass-low pass variable threshold circuit diagram 8
1, Q
2branch road draws), in Fig. 7 and Fig. 6, V
dC=5.5V, V
sS=0V, V
d=4V, reference voltage V
ref0be followed successively by 1.65V and 3.3V, under 4 kinds of reference voltages, manage Q
5the corresponding low pass that drains and high pass output form threshold signal t/h successively
j4, t/h
j5and th
j6, th
j7, under 4 kinds of reference voltages, manage Q
5the high pass that grid is corresponding and low pass output form threshold signal th successively
j4, th
j5and t/h
j6, t/h
j7, as input V
xduring for triangular wave bin, Pspice computer simulation threshold signal t/h
j4, t/h
j5, th
j6, th
j7waveform shows as 4, Figure 17 top curve; Pspice computer simulation threshold signal th
j4, th
j5, t/h
j6, t/h
j7waveform shows as 4, Figure 18 top curve; Figure 17 and Figure 18 curve is bottom triangular wave bin, and all curve tops (maximal value) approach V
dC.With relative V
dCrange of decrease V
x-V
dCjust to V
tpbe as the criterion and distinguish negative pulse and positive pulse, in the 3rd, 4 curves of Figure 17 and the 1st, 2 curves of Figure 18 lower than V
dCnegative pulse be all in triangular wave bin high interval (cover triangular wave pulse top all minute), show Q
h1in the interval conducting of high pass, in the 1st, 2 curves of Figure 17 and the 3rd, 4 curves of Figure 18 lower than V
dCnegative pulse be all in the low interval of triangular wave bin (cover triangular wave pulse at the bottom of all divide), show Q
l0in low interval conducting; Satisfied high pass, lowpass function.
In Figure 17 and Figure 18, as threshold signal th
j4, th
j5, th
j6, th
j7t be constantly worth relative V
dCrange of decrease V
x-V
dClower than V
tp, this constantly corresponding PMOS manages Q
h1conducting; As threshold signal t/h
j4, t/h
j5, t/h
j6, t/h
j7t be constantly worth relative V
dCrange of decrease V
x-V
dClower than V
tp, this constantly corresponding PMOS manages Q
l0conducting; V
tpfor PMOS pipe Q
l0and Q
h1threshold value.As input V
xduring for triangular wave bin, pipe V
l0and V
h1the just conducting poor V of input constantly
x-V
dCinstantaneous value is just V respectively
ex0and V
ex1, by Figure 17 and Figure 18, can find successively the V under each reference voltage
ex1measured value is :-0.32V and-2.02V, V
ex0measured value is :-5.0V and-3.42V.Under each reference voltage, press V
ex0and V
ex1value computing formula V
ex1=V
ref1-V
dC+ V
tn1+ | V
tp2| and V
ex0=V
ref0-V
dC-V
tn3-| V
tp4| theory of computation value, calculates V
ex1theoretical value is followed successively by :-0.5V and-2.15V, V
ex0theoretical value is followed successively by :-5.0V and-3.35V.Calculating shows, theoretical value and measured value approach, and the two has minute differences (in 0.2V).
Embodiment 3: band lead to-band resistance and high pass-low pass variable threshold circuit application are in multilevel memory cell circuit is embedded to DRAM.
In two-value DRAM, embedding K value storage unit is difficult (K > 4), not yet finds that there is succeeding in developing more than the DRAM of 4 values.Two-value data is having and without deciding, being easy to read and write by the electric charge of memory capacitance; 8 values, the storage unit circuit structure of 10 values and arbitrarily K value DRAM is very simple, but multi-valued signal is read and is write and will distinguish magnitude, very difficult read and write; In two-value DRAM, embed multilevel memory cell, can not consider merely multilevel memory cell by classic method, must consider the two-value-many-valued change-over circuit and the many-valued-two-value change-over circuit that match with multilevel memory cell simultaneously; Adopt band to lead to-be with resistance and high pass-low pass variable threshold circuit, many-valued-two-value change-over circuit (many-valued finger 8 values, 10 values, 16 values and any K value) is just easy to realize.Fig. 1 is for embedding the circuit diagram of 2 value DRAM storage matrix by 8 value storage unit; This 8 value memory cell structure is very simple, show as Fig. 2 and Fig. 3, for 8 value storage unit being embedded to 2 value DRAM storage matrix, need to there is a kind of 8-2 value change-over circuit MBVC shown in a kind of 2-8 value change-over circuit BMVC shown in Fig. 4 and Fig. 5, by Fig. 5, found out, shown MBVC structure is very simple, and this is the result of the lead to-band resistance of application band and high pass-low pass variable threshold circuit; Similar approach can promote the use of 10 values, 16 values and arbitrarily K value.Figure 10～14 are 2-8 value change-over circuit BMVC and 8-2 value change-over circuit MBVC Pspice computer simulation waveform in all cases.Obviously, band lead to-band resistance and high pass-low pass variable threshold circuit also can be widely used in various MULTI-VALUED LOGIC CIRCUIT, comprise many-valued combinational logic circuit and many-valued sequential logical circuit, have wide application prospects.。
Embodiment 4: realize the explanation of 2-8 value change-over circuit BMVC function.
Referring to Fig. 4, V
dC=1.8V, V
sS=-3.5V, V
d=0V, 1. works as b
j+2b
j+1b
j=111 o'clock, f
j7=0, pipe Q
a7conducting, Y
wRjoutput voltage V
yWRj=V
dC(logic 7); 2. work as b
j+2b
j+1b
j=110 o'clock, f
j7=1 and f
j6=0, pipe Q
a7cut-off, pipe Q
a6conducting, V
yWRj=V
dC-V
d(logic 6); 3. work as b
j+2b
j+1b
j=101 o'clock, f
j7=f
j6=1 and f
j5=0, pipe Q
a7, Q
a6cut-off, pipe Q
a5conducting, V
yWRj=V
dC-2V
d(logic 5); 4. work as b
j+2b
j+1b
j=001 o'clock, f
j7=f
j6=f
j5=f
j4=f
j3=f
j2=1 and f
j2=0,6 pipe Q
a7～Q
a2cut-off, pipe Q
a1conducting, V
yWRj=V
dC-6V
d(logical one); 5. work as b
j+2b
j+1b
j=000 o'clock, f
j7=f
j6=f
j5=f
j4=f
j3=f
j2=f
j1=1,7 pipe Q
a7～Q
a1cut-off, V
yWRj=V
sS(logical zero); Show as the Y in Figure 10 and Figure 12
wRj, Y
wRjoutput voltage V
yWRjhave 8 stepped-up voltages, the corresponding decimal system number of binary numeral 000～111 is 0～7, as input b
j+2b
j+1b
j=000～111 o'clock, Y
wRjoutput voltage V
yWRjhave 8 logic level v (0)～v (7), presentation logic 0～7 separately, wherein v (0)=V
sS, v (k)=V
dC-(7-k) V
d, k=1～7.
Embodiment 5: realize the explanation of 8-2 value change-over circuit MBVC function.
Referring to Fig. 5, V
dC=1.8V, V
sS=-3.5V, V
d=0V, considers pipe G
b0mj～G
b3mjgrid band logical-band resistive threshold cirtuit meets input Y
rDj, pipe G
h4mj～G
h6mjgrid through high pass-low pass variable threshold circuit connect input Y
rDj, meet: 1. manage G
h4mjhigh pass threshold th
j4for the height interval that comprises logic level v (4); 2. manage G
h5mjhigh pass threshold th
j5for the height interval that comprises logic level v (6); 3. manage G
h6mjhigh pass threshold th
j6for the height interval that comprises logic level v (7); 4. manage G
b0mjthe logical threshold tb of band
j0for only comprising the band interval of 2 logic level v (2), v (3); 5. manage G
b1mjthe logical threshold tb of band
j0for only comprising the band interval of logic level v (1); 6. manage G
b2mjthe logical threshold tb of band
j0for only comprising the band interval of logic level v (3); 7. manage G
b3mjthe logical threshold tb of band
j0for the band interval that comprises logic level v (5); Consider again output m
j+2take over G
h4mjdrain electrode, output m
j+1meet G
h5mjand G
b0mjdrain electrode, output m
jmeet G
b1mj, G
b2mj, G
b3mjand G
h6mjdrain electrode, the source electrode of all pipes all meets V
dCmanage, as long as wherein have-conducting, i.e. this pipe drain electrode and source electrode conducting, this pipe drain electrode output is exactly high level, so the input/output relation of MBVC is: (1) works as Y
rDjwhile being input as logic 7, pipe G
h4mj, G
h5mj, G
h6mjconducting, output m
j+2m
j+1m
j=111; (2) work as Y
rDjwhile being input as logic 6, pipe G
h4mj, G
h5mjconducting, other manages cut-off, output m
j+2m
j+1m
j=110; (3) work as Y
rDjwhile being input as logic 5, pipe G
h4mj, G
b3mjconducting, other manages cut-off, output m
j+2m
j+1m
j=101; (4) work as Y
rDjwhile being input as logic 4, pipe G
h4mjconducting, other manages cut-off, output m
j+2m
j+1m
j=100; (5) work as Y
rDjwhile being input as logic 3, pipe G
b0mj, G
b2mjconducting, other manages cut-off, output m
j+2m
j+1m
j=011; (6) work as Y
rDjwhile being input as logic 2, pipe G
b0mjconducting, other manages cut-off, output m
j+2m
j+1m
j=010; (7) work as Y
rDjwhile being input as logical one, pipe G
b1mjconducting, other manages cut-off, output m
j+2m
j+1m
j=001; (8) work as Y
rDjwhile being input as logical zero, all pipes all end, output m
j+2m
j+1m
j=000; Represent Y
rDjinput logic 0～7 o'clock, draw corresponding two-value output 000～111, show as Figure 10 Figure 12 and Figure 13.
Embodiment 6: the explanation to Pspice computer simulation waveform Figure 10～14 of Fig. 3～5.
Figure 10 be 8 value storage unit embed 2 value DRAM storage matrix circuit at X
iand Y
jduring for high level, b
j+2, b
j+1, b
j, Y
wRj, Y
rDj, m
j+2, m
j+1, m
jsuccessively upper and lower discrete oscillogram, is found out by figure, as the input b of BMVC in order
j+2b
j+1b
jwhen=000～111 (3 waveforms above), BMVC exports Y
wRjbe 8 value signals 0～8 (the 4th waveforms), the Y that this 8 value signal draws through 8 value storage unit
rDj(the 5th waveform), Y
rDjbe input to MBVC, last MBVC output m
j+2m
j+1m
j=000～111 (3 waveforms below), MBVC has 32 value output m
j+2m
j+1m
j3 the 2 value input b of waveform and BMVC
j+2b
j+1b
jwaveform is identical; Note: X
iand Y
ihigh level and the low level nearly V that respectively does for oneself
dCwith 0; Because of TG
1and TG
2transmission 8 value signals, TG
1and TG
2control signal amplitude is consistent with 8 value signal amplitudes, so by X
ithe row that produces the amplitude increase of another homophase is selected line X
0i, X
0ihigh level and the low level V that respectively does for oneself
dCand V
sS; When row is selected line X
iwhile being high level, corresponding X
0ialso be high level, for easy, accompanying drawing is all by X
iit is low and high level explanation.
Figure 11 is that 2-8 value change-over circuit BMVC is at X
iand Y
jduring for high level, b
j+2, b
j+1, b
j, f
j7, f
j6, f
j5, f
j4, f
j3, f
j2, f
jsuccessively upper and lower discrete oscillogram; Input b as BMVC
j+2b
j+1b
jwhen=000～111 (3 waveforms above), by Figure 11, find out 7 door f in BMVC
j7, f
j6, f
j5, f
j4, f
j3, f
j2, f
joutput waveform (7 waveforms below), f
j7～f
j1take over separately Q
a7～Q
a1grid; Figure 12 is that 2-8 value change-over circuit BMVC is at X
iand Y
jduring for high level, Y
wRj, D
mCij, f
j7, f
j6, f
j5, f
j4, f
j3, f
j2, f
j1successively upper and lower discrete oscillogram, pipe Q
a7～Q
a1at f
j7～f
j1under the effect of (7 waveforms below), Y
wRjoutput has 8 logic level v (0)～v (7), separately counterlogic 0～7 (the 1st waveform above), simultaneously Y
wRjbe transferred to F
sinput D
mCij, D
mcijthere are 8 identical logic levels (the 2nd waveform above); Figure 13 is that 8-2 value change-over circuit MBVC is at X
iand Y
jduring for high level, D
mij, Y
rDj, th
j4, th
j5, tb
j0, tb
j1, tb
j2, tb
j3, th
j6successively upper and lower discrete oscillogram, D
mCijthrough F
sform the 8 value emitter-base bandgap grading output D that waveform is close
mij(the 1st waveform above), D
mijtG through conducting
2outwards export Y
rDj, Y
rDjwaveform and D
mijwaveform identical (the 2nd waveform above); MBVC is at Y
rDjthe logical threshold signal tb of 4 bands of the lower generation of effect
j0, tb
j1, tb
j2, tb
j3(2nd～5 waveforms reciprocal below), generate 3 high pass threshold signal th
j4, th
j5, th
j6(the 3rd, 4 waveforms of positive number and below the 1st waveform reciprocal); Figure 14 is that 8-2 value change-over circuit MBVC is at X
iand Y
jduring for high level, m
j+2, m
j+1, m
j, th
j4, th
j5, tb
j0, tb
j1, tb
j2, tb
j3, th
j6successively upper and lower discrete oscillogram, at threshold signal th
j4, th
j5, tb
j0, tb
j1, tb
j2, tb
j3, th
j6under effect, (1st～7 waveforms reciprocal below), draw MBVC output m
j+2, m
j+1, m
jwaveform (1st～3 waveforms above); Can find out, MBVC exports m
j+2, m
j+1, m
jwaveform and above-mentioned BMVC input b
j+2, b
j+1, b
jwaveform be identical, show that BMVC is converted to 8 value signal Y by 32 values inputs
wRj, this 8 value signal deposits 8 value storage unit in, and 8 value storage unit produce Y
rDj, MBVC is converted to 8 value signals again 32 value signals.
Embodiment 7: other explanation.
Fig. 9 is existing a kind of many output accurate mirror current source (constant current source) circuit diagrams and graphical diagram, for reducing power consumption and improving performance etc., to the constant current source I in Fig. 2 and Fig. 4
j, its constant current source I
jelectric current is got smaller value, and diode used is silicon diode, and On current is got smaller value; Fig. 4 is equally for current source I
0mj, I
1mj, I
2mj, direction of current flows to ground by the drain electrode of respective tube.Conventionally, door f
j7～f
j1with logical formula f
j7～f
j12 expression-forms of same function element, the same function of realization; Door f
j7～f
j1to represent with door symbol, formula f
j7～f
j1to represent with logical formula, and f
j7～f
j1be exactly logical formula f
j7～f
j1output (door f
j7～f
j1output), before it, add ' door ' and ' formula ' can distinguish a f
j7～f
j1with logical formula f
j7～f
j1(before it, adding English alphabet and adding Chinese character has same purpose, but the latter is understandable); Write so easily, otherwise symbol is too many, on the contrary inconvenience; For writing conveniently, can other loaded down with trivial details symbol of similar processing.
Claims (7)
1. lead to-band of a PMOS pipe racks resistive threshold cirtuit, is characterized in that: lead to-band of described PMOS pipe racks resistive threshold cirtuit is by two NMOS pipe Q
1, Q
3with three PMOS pipe Q
2, Q
4, Q
5, and two resistance R
0, R
1form; Pipe Q
1and Q
2source electrode join, pipe Q
3and Q
4source electrode join, pipe Q
2and Q
4drain electrode meet direct supply V
sS, pipe Q
1, Q
3drain electrode and pipe Q
5grid and resistance R
1one end be connected, this junction is as band resistance output V
out0, resistance R
1the other end and PMOS pipe Q
5source electrode receive direct supply V
dC, NMOS manages Q
1with PMOS pipe Q
4grid meet outer input V
x, PMOS manages Q
2with NMOS pipe Q
3grid meet respectively reference voltage V
ref1and V
ref0, V
dC>=V
x>=V
sS, V
dC>=V
ref1>=V
sS, V
dC>=V
ref0>=V
sS, pipe Q
5drain electrode and resistance R
0one end be connected, this junction is as the logical output of band V
out1, resistance R
0another termination direct supply V
d, V
dC=5.5V, V
sS=0V, V
d=4V; Upper threshold value V
ex1=V
ref1-V
dC+ V
tn1+ | V
tp2|, lower threshold value V
ex0=V
ref0-V
dC-V
tn3-| V
tp4|, meet V
ex1> V
ex0, V wherein
tn1, V
tn3and V
tp2, V
tp4be respectively NMOS pipe Q
1, Q
3with PMOS pipe Q
2, Q
4threshold voltage, V
tn1> 0, V
tn3> 0, V
tp2< 0, V
tp4< 0, the logical output of band V
out1with band resistance output V
out0be transported to respectively controlled PMOS pipe Q
b1and Q
r0grid, pipe Q
b1and Q
r0source electrode meet V
dC, complete thus: 1. work as V
ex1> V
x-V
dC> V
ex0time, pipe Q
b1conducting, otherwise, do not meet V
ex1> V
x-V
dC> V
ex0time, pipe Q
b1cut-off, 2. works as V
ex1> V
x-V
dC> V
ex0time, pipe Q
r0cut-off, otherwise, do not meet V
ex1> V
x-V
dC> V
ex0time, pipe Q
r0conducting; Also input poor V
x-V
dCat the interval (V of band
ex0, V
ex1) in, pipe Q
b1conducting, pipe Q
r0cut-off, the interval (V of band
ex0, V
ex1) by changing reference voltage V
ref1and V
ref0adjust.
2. a kind of PMOS pipe racks according to claim 1 leads to-is with resistive threshold cirtuit, it is characterized in that: in described circuit, and resistance R
1be taken as constant current source I
1, electric current I
1by V
dCflow to pipe Q
1and Q
3drain electrode.
3. have PMOS pipe racks claimed in claim 1 logical-PMOS pipe high pass-low pass variable threshold circuit of forming with the part-structure of resistive threshold cirtuit, it is characterized in that: described PMOS pipe high pass-low pass variable threshold circuit is by a NMOS pipe Q
1with two PMOS pipe Q
2, Q
5, and two resistance R
0, R
1form pipe Q
1and Q
2source electrode join, pipe Q
2drain electrode meet direct supply V
sS, NMOS manages Q
1drain electrode and PMOS pipe Q
5grid and resistance R
1one end be connected, V is exported as high pass in this junction
out1, resistance R
1the other end and pipe Q
5source electrode receive direct supply V
dC, NMOS manages Q
1grid meet outer input V
x, PMOS manages Q
2grid meet reference voltage V
ref1, V
dC>=V
x>=V
sS, V
dC>=V
ref1>=V
sS, pipe Q
5drain electrode and resistance R
0one end be connected, V is exported as low pass in this junction
out0, resistance R
0another termination direct supply V
d, V
d=4V, V
dC=5.5V, V
sS=0V; Upper threshold value V
ex1=V
ref1-V
dC+ V
tn1+ | V
tp2|, V wherein
tn1and V
tp2be respectively NMOS pipe Q
1with PMOS pipe Q
2threshold voltage, V
tn1> 0, V
tp2< 0, high pass output V
out1with low pass output V
out0be transported to respectively controlled PMOS pipe Q
h1and Q
l0grid, pipe Q
h1and Q
l0source electrode meet V
dC, complete thus: 1. work as V
x-V
dC> V
ex1time, pipe Q
h1conducting, otherwise, do not meet V
x-V
dC> V
ex1time, pipe Q
h1cut-off, 2. works as V
x-V
dC> V
ex1time, pipe Q
l0cut-off, otherwise, do not meet V
x-V
dC> V
ex1time, pipe Q
l0conducting; Input V
xat V
x-V
dC> V
ex1time, pipe Q
h1conducting, pipe Q
l0cut-off, V
ex1by changing reference voltage V
ref1adjust.
4. a kind of PMOS according to claim 3 manages high pass-low pass variable threshold circuit, it is characterized in that: in described circuit, and resistance R
1be taken as constant current source I
1, electric current I
1by V
dCflow to pipe Q
1.
5. have PMOS pipe racks claimed in claim 1 logical-PMOS pipe high pass-low pass variable threshold circuit of forming with the part-structure of resistive threshold cirtuit, it is characterized in that: described PMOS pipe high pass-low pass variable threshold circuit is by a NMOS pipe Q
3with two PMOS pipe Q
4, Q
5, and two resistance R
0, R
1form pipe Q
3and Q
4source electrode join, pipe Q
4drain electrode meet direct supply V
sS, NMOS manages Q
3drain electrode and PMOS pipe Q
5grid and resistance R
1one end be connected, V is exported as low pass in this junction
out0, resistance R
1the other end and pipe Q
5source electrode receive direct supply V
dC, NMOS manages Q
3grid meet reference voltage V
ref0, PMOS manages Q
4grid meet outer input V
x, V
dC>=V
x>=V
sS, V
dC>=V
ref0>=V
sS, pipe Q
5drain electrode and resistance R
0one end be connected, V is exported as high pass in this junction
out1, resistance R
0another termination direct supply V
d, V
d=4V, V
dC=5.5V, V
sS=0V; Lower threshold value V
ex0=V
ref0-V
dC-V
tn3-| V
tp4|, V wherein
tn3and V
tp4be respectively NMOS pipe Q
3with PMOS pipe Q
4threshold voltage, V
tn3> 0, V
tp4< 0, high pass output V
out1with low pass output V
out0be transported to respectively controlled PMOS pipe Q
h1and Q
l0grid, pipe Q
h1and Q
l0source electrode meet V
dC, complete thus: 1. work as V
x-V
dC> V
ex0time, pipe Q
h1conducting, otherwise, do not meet V
x-V
dC> V
ex0time, pipe Q
h1cut-off, 2. works as V
x-V
dC> V
ex0time, pipe Q
t0cut-off, otherwise, do not meet V
x-V
dC> V
ex0time, pipe Q
l0conducting; Input V
xat V
x-V
dC> V
ex0time, pipe Q
h1conducting, pipe Q
l0cut-off, V
ex0by changing reference voltage V
ref0adjust.
6. a kind of PMOS according to claim 5 manages high pass-low pass variable threshold circuit, it is characterized in that: in described circuit, and resistance R
1be taken as constant current source I
1, electric current 1
1by V
dCflow to pipe Q
3.
7. a kind of PMOS pipe racks according to claim 1 leads to-is with resistive threshold cirtuit, or a kind of PMOS pipe high pass-low pass variable threshold circuit according to claim 3, or a kind of PMOS pipe high pass-low pass variable threshold circuit according to claim 5, it is characterized in that: get V
dC=1.8V, V
sS=-3.5V, V
d=0V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110291038.5A CN102436847B (en) | 2011-09-15 | 2011-09-15 | PMOS (P-channel Metal Oxide Semiconductor) pipe band-pass-band-stop changeable threshold circuit and PMOS pipe high-pass-low-pass changeable threshold circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110291038.5A CN102436847B (en) | 2011-09-15 | 2011-09-15 | PMOS (P-channel Metal Oxide Semiconductor) pipe band-pass-band-stop changeable threshold circuit and PMOS pipe high-pass-low-pass changeable threshold circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102436847A CN102436847A (en) | 2012-05-02 |
| CN102436847B true CN102436847B (en) | 2014-04-02 |
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| CN201110291038.5A Expired - Fee Related CN102436847B (en) | 2011-09-15 | 2011-09-15 | PMOS (P-channel Metal Oxide Semiconductor) pipe band-pass-band-stop changeable threshold circuit and PMOS pipe high-pass-low-pass changeable threshold circuit |
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|---|---|---|---|---|
| CN102426855B (en) * | 2011-10-24 | 2014-04-02 | 黑龙江大学 | 8-value memory cell embedded in DRAM storage matrix, and corresponding conversion circuit thereof |
| CN104333367B (en) * | 2014-10-01 | 2017-05-03 | 黑龙江大学 | K-value and ten-value signal controlled data distributor and data selector |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0643393A2 (en) * | 1993-09-10 | 1995-03-15 | Kabushiki Kaisha Toshiba | Semiconductor memory device having voltage booster circuit |
| CN1109997A (en) * | 1993-12-03 | 1995-10-11 | 株式会社日立制作所 | Semiconductor memory device |
| CN101169969A (en) * | 2006-10-26 | 2008-04-30 | 北京芯技佳易微电子科技有限公司 | Signal amplifier of deep submicron dynamic memory |
-
2011
- 2011-09-15 CN CN201110291038.5A patent/CN102436847B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0643393A2 (en) * | 1993-09-10 | 1995-03-15 | Kabushiki Kaisha Toshiba | Semiconductor memory device having voltage booster circuit |
| CN1109997A (en) * | 1993-12-03 | 1995-10-11 | 株式会社日立制作所 | Semiconductor memory device |
| CN101169969A (en) * | 2006-10-26 | 2008-04-30 | 北京芯技佳易微电子科技有限公司 | Signal amplifier of deep submicron dynamic memory |
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