CN103345936B - Arbitrarily K value and 8 is worth write circuit and the reading circuit of DRAM - Google Patents

Abstract

The present invention relates to a kind of any K value and the write circuit of 8 values DRAM and reading circuit.Write circuit is identical with the architectural feature of reading circuit, and design write circuit makes offer increase the multi-valued signal of Δ than the input of write circuit；Consider the output of memory element than input waveform the ladder that waits less than normal or non-, non-normal multi-valued signal for correcting, is converted to regular (waiting ladder) multi-valued signal by design reading circuit.Write circuit and reading circuit have good quantization shaping operation, work as C_jWhen change in voltage is not across upper and lower two new threshold values, it is easy to recover former multilevel information, there is capacity of resisting disturbance and multilevel information recovery capability.It is mainly used in FPGA, CPLD, half or the full formulation VLSI such as ASIC and memorizer and other digital IC technology field.

Description

Arbitrarily K value and 8 is worth write circuit and the reading circuit of DRAM

Technical field

The present invention be directed to application number: the divisional application of 201110097206.7, belong to digital integrated electronic circuit field, a kind of any K value and the write circuit of 8 value DRAM and reading circuit.

Background technology

Along with developing rapidly of MOS integrated circuit technique, collecting the most increasing, integrated level is more and more higher, and some shortcomings occurs in VLSI (super large-scale integration): first on VLSI substrate, and wiring but takies the silicon area of more than 70%；Also a large amount of interconnector able to programme has been needed (to include that reconfigurable interconnection switchs in PLD (such as FPGA and CPLD), such as fuse-type switch, anti-fuse type switch, floating boom programmed element etc.), each logic function block or input/output are coupled together, completing the circuit of specific function, wiring (including programming connecting valve) account for the cost that material is the biggest.The proportion reducing wiring cost becomes highly important problem.2., from the perspective of information is transmitted, multi-valued signal is used can to reduce session number；To every line transmitting digital information, binary signal is to carry the one that quantity of information is minimum, and multi-valued signal carries and contains much information in binary signal.3. from the perspective of information stores, use multi-valued signal can improve information storage density, in particular with metal-oxide-semiconductor grid capacitance storage information (in dynamic random access memory DRAM), because same electric capacity information memory capacity is many-valued bigger than two-value, many-valued DRAM is greatly improved information storage density than two-value DRAM.The development of Multivalued devices at present is the most extensively carried out, and Toshiba is matched, at 146mm by the CMOS technology of 70nm and the many-valued technology of 2bit/ unit with Sandisk company²Chip on achieve the memory capacity of 8Gbit；Toshiba and U.S. SanDisk have delivered the 16gbitNAND flash memory by using 43nm technique and the many-valued technology of 2bit/ unit to realize.The 8Gbit product of Samsung exploitation uses CMOS technology and the many-valued technology of 2bit/ unit of 63nm.Succeed in developing and the commercialization of 4 value memorizeies is an important step of many-valued research, but needs to control or change the switching threshold V of pipe_tn, changing threshold method is use multipole ion injection technique in semiconductor fabrication process, or the method such as the amount of electrons control threshold value of the grid storage that controls to swim.Not yet it is found to have succeeding in developing of the DRAM more than 4 values.

Semiconductor memory can be divided into read only memory ROM and random access memory ram.And RAM is divided into ambipolar and MOS type two class.Bipolar RAM operating rate is high, but manufacturing process is complicated, power consumption is big, integrated level is low, is mainly used in the occasion of high speed operation.MOS type RAM is divided into again static RAM SRAM and dynamic random access memory DRAM (DynamicRandomAccessMemory) two kinds.The principle of DRAM storage information is charge-storage effect based on metal-oxide-semiconductor grid capacitance.Due to the capacity the least (being generally only a few pico farad) of grid storage electric capacity, and leakage current can not definitely be equal to zero, so the limited time that electric charge preserves；In order to supplement the electric charge missed in time to avoid the dropout of storage, it is necessary to timing supplements electric charge to grid storage electric capacity, generally it is referred to as this operation refreshing or regeneration, the refresh control circuit of necessity during DRAM work, must be aided with.DRAM is by big rectangle memory cell array and the supportive logic circuit for reading array and write, and maintains the refreshing circuit etc. of integrity of data stored to form.Simplest available single tube dynamic storage cell in DRAM.Memory element is to line up matrix type structure by row, column, decodes respectively with two decoding circuits.X is referred to as row decoding to decoding, and its output lead is referred to as wordline, and it chooses all memory element of a line in storage matrix.Y-direction decoding is also called column decoding, and its output lead is referred to as bit line.Because single tube dynamic storage cell reads as destructive reading every time, store electric capacity electric capacity C on bit line_BElectric charge is provided, make storage capacitance charge reduce, need to recover immediately, every bit line is connected to sensitivity recovery/sense amplifier, after employing sensitivity recovery/sense amplifier, while reading data, complete the recovery of stored data original to memory element every time.General is that (i.e. one word has n position in word length n position by DRAM design, such as 4,8 or N position), address decoder is translated each wordline output effective time, there is n (such as 4,8 or N number of) memory element is the most selected, makes these selected memory element be written and read operation through read/write control circuit, and DRAM read-write control circuit controls data message input and output.The control signal of outer bound pair memorizer has read signal R_D, write signal W_RWith chip selection signal C_SEtc..The figure place of the inputoutput data of DRAM has 1,2,4 or N position.In addition to many bit input and outputs, in order to reduce the number of device pin while improving integrated level, Large Copacity DRAM usually uses 1 input, 1 output and the mode of address timesharing input, has input buffer, output buffer and output latch etc. accordingly.

Prior art and existing problems:

1. to being stored in the multi-valued signal that DRAM stores in electric capacity, read data be difficult (two-value data be by storage electric capacity electric charge with and without determining, it is easy to read；Multi-valued signal reads magnitude to be distinguished, and multi-valued signal is likely to occur decay and deformation in the transmission, conventional amplifiers formation easy to multi-valued signal serious distortion, can not get DRAM specification waits ladder multi-valued signal input and output, conventional sense amplifiers method can not read multi-valued signal, any K value and the storage unit circuit of 8 values DRAM can not be realized, be not yet found to have succeeding in developing of the DRAM more than 4 values.For overcoming this difficulty, it is impossible to consider the most merely multilevel memory cell, it is necessary to consider the many-valued write circuit that matches with multilevel memory cell and many-valued reading circuit simultaneously.To word length 4,8 or N bit data, then corresponding write circuit and reading circuit have 4,8 or N number of.Write circuit and reading circuit by the specification that requires to obtain DRAM etc. premised on the many-valued input/output signal of ladder, many-valued DRAM memory cell circuit, write circuit and reading circuit should design these three circuit by a total inventive concept, these three kinds of circuit are closely related, but three kinds of circuit quantities different (can not form the entirety of a kind of circuit) time practical, are designed the difficulty that reading can be overcome to be stored in electric capacity multi-valued signal data by a total inventive concept.

2., in realizing multivalued circuit, prior art controls metal-oxide-semiconductor threshold value the biggest shortcoming: 1. control the limited extent (because ion implantation concentration is limited) of threshold value, opens resolution low；And technique controls threshold amplitude and often can change the performance of metal-oxide-semiconductor, such as threshold voltage reduces back the sharp increase causing cut-out electric current, performance and the stability of pipe are had an impact by the adjustment of threshold voltage, stable V_tnExtremely important.To many-valued memory, the amount of electrons injecting the grid that swims is continually varying, controls with needing very fine, and each threshold voltage level does not still reach quasi-stationary state.Therefore the most practical voltage-type multivalued circuit is not more than 4 value circuit, and the application of more multivalued circuit is more difficult.2. the amplitude of threshold value can only be controlled, metal-oxide-semiconductor can not be changed and open character (as change >=t conducting turns on into ＜ t), and multivalued gate must have two kinds of metal-oxide-semiconductors opening character, combinational circuit structure just can be made the simplest, the most many-valued not gate, the many-valued door that moves to right should be identical with the circuit structure of many-valued follower, simply threshold voltage and to open character different.But the most only control the technique of threshold amplitude, and make above-mentioned multivalued gate structural difference very big, structure is complicated, affects it and realizes.3. need to increase the extra operation of ion implanting, threshold value can only be controlled in semiconductor fabrication process, both increased process complexity, again can not after controlled threshold value by user, or non-programmable to threshold users.

K value DRAM (K ＞ 2) custom is commonly referred to as many-valued DRAM, but at design storage unit circuit, in write and reading circuit, circuit structure is the most relevant with K, at this moment K value (address K value DRAM etc.) is write exactly more convenient, and some content introductions, unstructuredness describe or custom address (such as multi-valued signal, multivalued gate) often can be continued to use in the noun unrelated with K value.

Summary of the invention

The present invention seeks to disclose a kind of any K value and the write circuit of 8 values DRAM and reading circuit.

Above-mentioned purpose is realized by following technical scheme:

1. the write circuit of a kind of any K value DRAM of the present invention is achieved in that this write circuit as shown in Figure 4, in the write circuit of described K value DRAM, if K=3,4,5 ... ..；Use K-1=L variable threshold type PMOS Qa_k, k=1,2,3 ... .., L, pipe Qa_kGrid be connected to the input D of write circuit through variable threshold circuit_inj, variable threshold type PMOS Qa_kNew threshold value be ta_k, pipe Qa_kDuring conducting, between source drain, pressure drop is 0；Pipe Qa_kSource electrode meet power supply V_dd, choose V_ddVoltage ratio write circuit input and reading circuit output largest logical level V_DinjAnd V (L)_Douj(L) high Δ, Δ is DC Level Shift downward between voltage follower F input and output；Use L-1 diode Da_n, n=2,3 ... .., L, diode Da_nConducting voltage be V_Don；Da_nPositive pole and negative pole be connected respectively to variable threshold type PMOS Qa_n-1Drain electrode and pipe Qa_nDrain electrode；Pipe Qa_LDrain electrode through constant-current source I_jGround connection, pipe Qa_LDrain electrode meet constant-current source I_jThe electric current flowing through conducting diode keeps same fixed value, at pipe Qa_LDrain electrode formed write circuit output G_wrij, write circuit output G_wrijReceive the write bit line input of storage unit circuit；Choose ta_kD is inputted for write circuit_injAdjacent logic levels V of K value signal_Dinj(k) and V_Dinj(k-1) meansigma methods (V_Dinj(k)+V_Dinj(k-1))/2, i.e. ta_kFor V_Dinj(k) and V_Dinj(k-1) intermediate value, V_Dinj(k) ＞ V_Dinj(k-1)；Write circuit input D_injK value signal and reading circuit output D_outjAnd the specification of DRAM input and output etc. the characteristic of K value signal of ladder be identical: input D_injThe difference of each adjacent logic levels is equal, exports D_outjThe difference of each adjacent logic levels is equal, and input D_injWith output D_outjStepped-up voltage identical, stepped-up voltage is V_Don, namely meet V_Dinj(m)-V_Dinj(m-1)=V_Doutj(m)-V_Doutj(m-1)=V_Don, m=1,2,3 ... .., L, V_Dinj(m) and V_DoutjM () is that write circuit inputs and reading circuit output logical value is the logic level of m respectively；The output G of write circuit_wrijThe ratio high Δ of K value signal of write circuit input in addition to 0 level, 0 level is still 0, and this K value write circuit is also called K value write attack circuit.

2. the reading circuit of a kind of any K value DRAM of the present invention is achieved in that reading circuit is as shown in Figure 5, the reading circuit of this any K value DRAM is the identical architectural feature of the write circuit according to any K value DRAM described in above-mentioned 1 and is formed, in the reading circuit of described K value DRAM, if K=3,4,5 ... ..；Use K-1=L variable threshold type PMOS Qb_k, k=1,2,3 ... .., L, pipe Qb_kGrid be connected to the input G of reading circuit through variable threshold circuit_rdij, variable threshold type PMOS Qb_kNew threshold value be tb_k, pipe Qb_kDuring conducting, between source drain, pressure drop is 0；G_rdijReceive the sense bit line output of storage unit circuit, pipe Qb_kSource electrode meet power supply V_dc, choose V_dcVoltage equal to write circuit input and reading circuit output largest logical level V_DinjAnd V (L)_Douj(L) (i.e. V_dc=V_Dinj(L)=V_Douj(L))；Use L-1 diode Db_n, n=2,3 ... .., L, diode Db_nConducting voltage be V_Don；Db_nPositive pole and negative pole connect variable threshold type PMOS Qb respectively_n-1Drain electrode and pipe Qb_nDrain electrode；Variable threshold type PMOS Qb_LDrain electrode through constant-current source I_jGround connection, pipe Qb_LDrain electrode meet constant-current source I_jThe electric current flowing through conducting diode keeps same fixed value, at pipe Qb_LDrain electrode formed reading circuit output D_outj；Choose tb_kG is inputted for reading circuit_rdijAdjacent logic levels V of K value signal_Grdij(k) and V_Grdij(k-1) meansigma methods (V_Grdij(k)+V_Grdij(k-1))/2, i.e. tb_kFor V_Grdij(k) and V_Grdij(k-1) intermediate value, V_Grdij(k) ＞ V_Grdij(k-1)；Reading circuit output D_outjSignal and write circuit input D_injAnd the specification of DRAM input and output etc. the characteristic of K value signal of ladder be identical: input D_injThe difference of each adjacent logic levels is equal, exports D_outjThe difference of each adjacent logic levels is equal, and input D_injWith output D_outjStepped-up voltage identical, stepped-up voltage is V_Don, namely meet V_Dinj(m)-V_Dinj(m-1)=V_Doutj(m)-V_Doutj(m-1)=V_Don, m=1,2,3 ... .., L, V_Dinj(m) and V_DoutjM () is that write circuit inputs and reading circuit output logical value is the logic level of m respectively；Reading circuit input G_rdijThe nonstandard K value signal from storage unit circuit output, described nonstandard K value signal be exactly contrast DRAM input and output and write circuit input and reading circuit output specification etc. the K value signal of ladder be that logic level amplitude is inconsistent；Reading circuit output D_outjFor the K value signal waiting ladder of specification, i.e. reading circuit, nonstandard K value signal is inputted G_rdijBe converted to the K value signal output D waiting ladder of specification_outj, this K value reading circuit is also called K value and reads correcting circuit.

Note: the storage unit circuit of a kind of any K value DRAM of the present invention is achieved in that as it is shown in figure 1, the storage unit circuit of described K value DRAM is to be stored electric capacity C by the grid of voltage follower F, F_jWith two cmos transmission gate G₁And G₂Composition, uses electric capacity C_jStorage K value signal, voltage follower F includes NMOS tube Q_m1With NPN pipe Q_m2, pipe Q_m1Grid meet electric capacity C_jOne end C_mij, i.e. C_mijFor the input of voltage follower F, C_jOther end ground connection, pipe Q_m1Source electrode adapter Q_m2Grid and resistance R_m1, R_m1Other end ground connection, pipe Q_m2Emitter-base bandgap grading F_olijThrough constant-current source I_jGround connection, Q_m2Emitter-base bandgap grading meets constant-current source I_jMake pipe Q_m2Emitter-base bandgap grading load for constant-current source, pipe Q_m2Emitter-base bandgap grading F_olijFor the output of F, pipe Q_m1Drain electrode and pipe Q_m2Colelctor electrode all meet power supply V_dd, choose V_ddThe input of voltage ratio write circuit and the maximum height Δ of K value logic level of reading circuit output, Δ is DC Level Shift downward between voltage follower F input and output；Transmission gate G₁Input meet write bit line G_wrij, transmission gate G₁Output meet the input C of F_mij, transmission gate G₁Control input meet write pulse w_ri, transmission gate G₂Input meet the output F of F_olij, transmission gate G₂Output meet sense bit line G_rdij, transmission gate G₂Control input meet read pulse r_di, write pulse w_riWith read pulse r_diControl circuit from DRAM；Write pulse w_riCome then, transmission gate G₁Conducting, by write bit line G_wrijK value signal be sent to store electric capacity C_j, electric capacity C_jReceive write bit line G_wrijK value signal, electric capacity C_jK value signal be exactly F input C_mijK value signal；Write pulse w_riFuture then, transmission gate G₁Cut-off, stores electric capacity C_jIt is direct current open circuit with the external world, electric capacity C_jThe K value signal of storage keeps constant, i.e. has memory function；Read pulse r_diCome then, transmission gate G₂Conducting, exports F by F_olijK value signal be sent to sense bit line G_rdij；Write bit line G_wrijWith sense bit line G_rdijIt is individually input and the output of storage unit circuit；Write circuit output is each received in storage unit circuit input and output and reading circuit inputs；The K value signal of F output must be the K value signal corresponding with F input signal, and F input/output information is identical, i.e. F output requires C without information dropout, F output without information dropout_jThe K value signal of storage is the K value signal increased, described in the K value signal that increases be exactly the signal of the high Δ of K value signal inputted than write circuit except 0 level in addition to, wherein 0 level is still 0；C_jThe K value signal increased of storage is the output from write circuit, is i.e. supplied to C_jThe write circuit output of storage signal is also the K value signal increased；C_jThe K value signal that increases of storage is sent to sense bit line G through F_rdij, at G_rdijUpper formation nonstandard K value signal, namely storage unit circuit output is nonstandard K value signal, described nonstandard K value signal be exactly contrast DRAM input and output and write circuit input and reading circuit output specification etc. the K value signal of ladder be that logic level amplitude is inconsistent；Reading circuit input signal is to export G from storage unit circuit_rdijNonstandard K value signal, reading circuit exports the K value signal waiting ladder being storage unit circuit exports the specification that the correction of nonstandard K value signal draws, the K value signal waiting ladder of the specification that this correction draws reads as the correction that storage unit circuit stores information.

In described K value DRAM memory cell circuit, constant-current source I_jCan be by resistance R_jReplace.

The present invention also has techniques below feature:

(1) according to the write circuit of a kind of any K value DRAM described in above-mentioned 1, take K=8, draw the write circuit of 8 values DRAM, as in figure 2 it is shown, wherein use 7 variable threshold type PMOS Qa_k, k=1,2,3 ... .., 7, pipe Qa_kGrid be connected to the input D of write circuit through variable threshold circuit_inj, variable threshold type PMOS Qa_kNew threshold value be ta_k, pipe Qa_kDuring conducting, between source drain, pressure drop is 0；Pipe Qa_kSource electrode meet power supply V_dd, choose V_ddVoltage ratio write circuit input and reading circuit output largest logical level V_DinjAnd V (7)_Douj(7) high Δ, Δ is DC Level Shift downward between the input and output of voltage follower F；Use 6 diode Da_n, n=2,3 ... .., 7, diode Da_nConducting voltage be V_Don；Da_nPositive pole and negative pole be connected respectively to variable threshold type PMOS Qa_n-1Drain electrode and pipe Qa_nDrain electrode；Pipe Qa₇Drain electrode through constant-current source I_jGround connection, pipe Qa₇Drain electrode meet constant-current source I_jThe electric current flowing through conducting diode keeps same fixed value, at pipe Qa₇Drain electrode formed write circuit output G_wrij, write circuit output G_wrijReceive the write bit line input of storage unit circuit；Choose ta_kD is inputted for write circuit_injAdjacent logic levels V of 8 value signals_Dinj(k) and V_Dinj(k-1) meansigma methods (V_Dinj(k)+V_Dinj(k-1))/2, i.e. choose ta_kFor V_Dinj(k) and V_Dinj(k-1) intermediate value, V_Dinj(k) ＞ V_Dinj(k-1)；Write circuit input D_inj8 value signals and reading circuit output D_outjAnd the specification of DRAM input and output etc. the characteristic of 8 value signals of ladder be identical: input D_injThe difference of each adjacent logic levels is equal, exports D_outjThe difference of each adjacent logic levels is equal, and input D_injWith output D_outjStepped-up voltage identical, stepped-up voltage is V_Don, namely meet V_Dinj(m)-V_Dinj(m-1)=V_Doutj(m)-V_Doutj(m-1)=V_Don, m=1,2,3 ... .., 7, V_Dinj(m) and V_DoutjM () is that write circuit inputs and reading circuit output logical value is the logic level of m respectively；Write circuit output G_wrijThe ratio 8 high Δs of value signal of write circuit input in addition to 0 level, 0 level is still 0, and this 8 value write circuit is also called 8 value write attack circuits.

(2) K=8 is taken according in the reading circuit of any K value DRAM described in above-mentioned 2, draw the reading circuit of 8 values DRAM, as shown in Figure 3, the reading circuit of this 8 value DRAM is the identical architectural feature of the write circuit according to 8 values DRAM described in above-mentioned (1) and is formed, and wherein uses 7 variable threshold type PMOS Qb_k, k=1,2,3 ... .., 7, pipe Qb_kGrid be connected to the input G of reading circuit through variable threshold circuit_rdij, variable threshold type PMOS Qb_kNew threshold value be tb_k；Pipe Qb_kDuring conducting, between source drain, pressure drop is 0；G_rdijReceive the sense bit line output of storage unit circuit, pipe Qb_kSource electrode meet power supply V_dc, choose V_dcVoltage equal to write circuit input and reading circuit output largest logical level V_DinjAnd V (7)_Douj(7)；Use 6 diode Db_n, n=2,3 ... .., 7, diode Db_nConducting voltage be V_Don；Db_nPositive pole and negative pole connect variable threshold type PMOS Qb respectively_n-1Drain electrode and pipe Qb_nDrain electrode；Variable threshold type PMOS Qb₇Drain electrode through constant-current source I_jGround connection, pipe Qb₇Drain electrode meet constant-current source I_jThe electric current flowing through conducting diode keeps same fixed value, at pipe Qb₇Drain electrode formed reading circuit output D_outj；Choose tb_kG is inputted for reading circuit_rdijAdjacent logic levels V of 8 value signals_Grdij(k) and V_Grdij(k-1) meansigma methods (V_Grdij(k)+V_Grdij(k-1))/2, i.e. choose tb_kFor V_Grdij(k) and V_Grdij(k-1) intermediate value, V_Grdij(k) ＞ V_Grdij(k-1)；Reading circuit output D_outjSignal and write circuit input D_injAnd the specification of DRAM input and output etc. the characteristic of 8 value signals of ladder be identical: input D_injThe difference of each adjacent logic levels is equal, exports D_outjThe difference of each adjacent logic levels is equal, and input D_injWith output D_outjStepped-up voltage identical, stepped-up voltage is V_Don, i.e. meet V_Dinj(m)-V_Dinj(m-1)=V_Doutj(m)-V_Doutj(m-1)=V_Don, m=1,2,3 ... .., 7, V_Dinj(m) and V_DoutjM () is that write circuit inputs and reading circuit output logical value is the logic level of m respectively；Reading circuit input G_rdijNonstandard 8 value signals from storage unit circuit output, described nonstandard 8 value signals be exactly contrast DRAM input and output and write circuit input and reading circuit output specification etc. 8 value signals of ladder be that logic level amplitude is inconsistent；Reading circuit output D_outjFor 8 value signals waiting ladder of specification, i.e. reading circuit is by nonstandard 8 value signal G_rdijBe converted to the 8 value signal D waiting ladder of specification_outj, this 8 value reading circuit is also called 8 values and reads correcting circuit.

Note: 8 value storage unit circuits corresponding with the write circuit of 8 values DRAM and reading circuit draw as follows；In the storage unit circuit of any K value DRAM, take K=8, choose power supply V_ddThe input of voltage ratio write circuit and the logic level height Δ that output logical value is 7 of reading circuit, Δ is DC Level Shift downward between F input and output, draw the storage unit circuit of 8 values DRAM, show such as Fig. 1, this 8 value DRAM memory cell circuit is stored electric capacity C by the grid of voltage follower F, F_jWith two cmos transmission gate G₁And G₂Composition, uses electric capacity C_jStoring 8 value signals, voltage follower F includes NMOS tube Q_m1With NPN pipe Q_m2, pipe Q_m1Grid meet electric capacity C_jOne end C_mij, i.e. C_mijFor the input of voltage follower F, C_jOther end ground connection, pipe Q_m1Source electrode adapter Q_m2Grid and resistance R_m1, R_m1Other end ground connection, pipe Q_n2Emitter-base bandgap grading F_olijThrough constant-current source I_jGround connection, Q_m2Emitter-base bandgap grading meets constant-current source I_jMake pipe Q_m2Emitter-base bandgap grading load for constant-current source, pipe Q_m2Emitter-base bandgap grading F_olijFor the output of F, pipe Q_m1Drain electrode and pipe Q_m2Colelctor electrode all meet power supply V_dd；Transmission gate G₁Input meet write bit line G_wrij, transmission gate G₁Output meet the input C of F_mij, transmission gate G₁Control input meet write pulse w_ri, transmission gate G₂Input meet the output F of F_olij, transmission gate G₂Output meet sense bit line G_rdij, transmission gate G₂Control input meet read pulse r_di, write pulse w_riWith read pulse r_diControl circuit from DRAM；Write pulse w_riCome then, transmission gate G₁Conducting, by write bit line G_wrij8 value signals be sent to store electric capacity C_j, electric capacity C_jReceive G_wrij8 value signals, electric capacity C_j8 value signals be exactly F input C_mij8 value signals；Write pulse w_riFuture then, transmission gate G₁Cut-off, stores electric capacity C_jIt is direct current open circuit with the external world, electric capacity C_j8 value signals of storage keep constant, i.e. have memory function；Read pulse r_diCome then, transmission gate G₂Conducting, exports F by F_olij8 value signals be sent to sense bit line G_rdij；Write bit line G_wrijWith sense bit line G_rdijIt is individually input and the output of storage unit circuit；Write circuit output is each received in storage unit circuit input and output and reading circuit inputs；8 value signals of voltage follower F output must be 8 value signals corresponding with F input, and F input/output information is identical, i.e. F output requires C without information dropout, F output without information dropout_j8 value signals of storage are 8 value signals increased, described in 8 value signals that increase be exactly the signal of the 8 high Δs of value signal inputted than write circuit except 0 level in addition to, wherein 0 level is still 0；The input signal of storage unit circuit is the output from write circuit, and it is 8 value signals increased that write circuit output is supplied to the signal of storage unit circuit input；Increase 8 value signals and be sent to sense bit line G through F_rdijIt is nonstandard 8 value signals, namely storage unit circuit output is nonstandard 8 value signals, described nonstandard 8 value signals be exactly contrast DRAM input and output and write circuit input and reading circuit output specification etc. 8 value signals of ladder be that logic level amplitude is inconsistent；Reading circuit input signal is nonstandard 8 value signals from storage unit circuit output, reading circuit output be to storage unit circuit output nonstandard 8 value signals correction draw specification wait ladder 8 value signals, the specification that this correction draws wait ladder 8 value signals as to storage unit circuit storage information correction read.

The description of contents that the present invention is concrete is as follows:

(A) advantage of the storage unit circuit of the present invention, write circuit and reading circuit.1. the advantage of storage unit circuit: circuit structure is simple and cost is extremely low.Because K ＞ 2, each electric capacity C_jStorage K value information is bigger than the quantity of information of storage two value informations, it is clear that K the biggest memory element information memory capacity is the most, and C_jBeing metal-oxide-semiconductor grid capacitance, cost is extremely low, it addition, storage unit circuit only uses G₁And G₂Forming with F, circuit structure is simple, highly advantageous to many-valued DRAM；Typically require that the quantity of information that DRAM stores is The more the better, i.e. require that the quantity of storage unit circuit is the bigger the better, it is desirable to each electric capacity C_jThe quantity of information of storage is The more the better, it is desirable to it is the best that circuit structure simply makes to account for silicon area, and the storage unit circuit of the present invention meets this requirement；2. the advantage of reading circuit: have good quantization shaping operation, i.e. has the former multilevel information ability of recovery, and this ability is for anti-interference and refreshing.With sinusoidal wave continuous signal input G_rdijThe output D drawn after reading circuit_outjCurve is discontinuous (be corrected to specification waits ladder) multi-valued signal, shows that reading circuit has the quantization shaping operation that good similar 4 houses 5 enter, as input G_rdijWhen voltage rises or falls (such as electric leakage and interference effect) not across upper and lower two new threshold values, export D_outjBeing still the multilevel information (recovery prime information) waiting ladder of specification, i.e. have the former multilevel information ability of recovery, this ability is used for improving interference free performance and refreshing；3. the advantage of write circuit: there is good quantization shaping operation (the quantization effect that similar 4 houses 5 enter), draw the multilevel information increased of stable satisfied requirement；Sinusoidal wave continuous signal input D_injThe output G drawn after write circuit_wrijCurve is discontinuous multilevel information (multilevel information increased), as input D_injWhen voltage rises or falls (such as interference effect) not across upper and lower two new threshold values, export G_wrijStill recovering former (increasing) multilevel information, i.e. have the former multilevel information ability increased of recovery, this ability can also be used for anti-interference and refreshes.Recover former multilevel information and refresh be both for information for.DRAM amount of storage is the biggest and little being necessary for of silicon area used requires: storage unit circuit quantity is very big, and the quantity of write circuit and reading circuit is the fewest；They quantity.Many-valued DRAM memory cell (including conventional two-value DRAM memory cell) is to line up matrix type structure by row, column, and row decoding output lead i.e. wordline (row select line) chooses all memory element of a line in storage matrix (wordline).To word length n position (such as 4, 8 or N position), row address decoder translate each wordline output effective time, there is n (such as 4, 8 or N number of) memory element the most selected (multilevel information making it store by the cmos transmission gate of this unit and outer connection, the information of carrying out exchange), n root write bit line and sense bit line is had each to connect the memory element on selected this, every write bit line is connected to write circuit, it is connected to reading circuit on every sense bit line, make these selected memory element through reading circuit and write circuit, it is written and read operation by read/write control circuit etc..Multilevel memory cell circuit, many-valued reading circuit and many-valued write circuit are highly important parts, the arbitrarily storage unit circuit of K value and 8 value DRAM keeps very simple structure, is only written different with K value size with reading circuit structure, and its advantage is the most significant.In addition to many bit input and outputs, reduce the number of device pin to improve integrated level simultaneously, Large Copacity DRAM usually uses 1 input, 1 output and the mode of address timesharing input, now memory element still keeps lining up matrix type structure by row, column, and completed the output of data serial incoming serial task, the most even address by DRAM input buffering, output buffering (note: DRAM input and output refer to DRAM data input and output) and address input buffer part and control circuit part etc. and also can use serial input.If storage unit circuit, write circuit and reading circuit are classified as an integrated circuit, being then that cost is high and unpractical, storage unit circuit in practicality, the quantity of write circuit and reading circuit differs widely；Storage unit circuit, write circuit and reading circuit the most spatially differ, and by information characteristics, they are be closely related three kinds of circuit of the inventive concept Uniting total by.

(B) three kinds of circuit focus on information characteristics, i.e. storage unit circuit, and write circuit and reading circuit focus on information: information stores, and information write and information read.The information that storage unit circuit is stored requires without information dropout: what write circuit delivered to storage unit circuit input is the multilevel information increased.Storage unit circuit exports nonstandard multilevel information and requires: nonstandard multilevel information is corrected to the multilevel information output waiting ladder of specification by reading circuit.Storage unit circuit is also to focus on information characteristics, and storage unit circuit has multilevel information storage, and multilevel information receives and multilevel information sends three information characteristics: 1. information receives: write bit line G_wrijMultilevel information be sent to store electric capacity C_j, make electric capacity C_jReceive multilevel information C_mij；2. information storage: G₁Electric capacity C during cut-off_jWith extraneous D.C. resistance almost infinity, use electric capacity C_jMulti-valued signal can well be stored；3. delivering: transmission gate G₂Conducting, the multilevel information of voltage follower F output is sent to sense bit line G_rdij.Storage unit circuit, write circuit and reading circuit have identical important information feature: storage unit circuit input is consistent with the information characteristics of write circuit output, and they are all the multilevel informations increased；Storage unit circuit output is consistent with the information characteristics of reading circuit input, and they are all nonstandard multilevel informations；Write circuit input is consistent with the information characteristics of reading circuit output, they are all the ladder multilevel informations such as grade (note: the ladder multilevel information such as grade of this specification is consistent with the information characteristics of DRAM input and output, and DRAM input and output are exactly DRAM data input and output) of specification.

(C) by total two kinds of write circuits being closely related of inventive concept Uniting and reading circuit, the architectural feature of the reading circuit of any K value DRAM and the write circuit of any K value DRAM is identical, comparison Fig. 4 and Fig. 5, or comparison Fig. 2 and Fig. 3, find out immediately: write circuit is identical with the architectural feature of reading circuit, and (the variable threshold type PMOS of two circuit is identical with the pipe number of diode, connected mode between each pipe is mutually equal), but parameter is different, and function is different.

By any K value DRAM memory cell, write and the identical information feature of reading circuit, a total thinking used in design is expressed as follows:

DRAM input and output are the multi-valued signals of specification, if thinking routinely, electric capacity C_jDirectly receive the multi-valued signal of the specification of DRAM input and preserve, i.e. electric capacity C_jStore is the multi-valued signal of specification, C_jThe multi-valued signal of the specification of storage is through voltage follower F, and the output at F just has the situation of loss information and occurs, and therefore conventional thinking is unavailable.Changing now a thinking design, for ensureing that the output of F does not occur the situation of loss information, the inevitable information characteristics with specification of F input differs, and can use the multi-valued signal increased instead and be sent to electric capacity C_j(i.e. F input), this multi-valued signal increased is required to meet: both can guarantee that F output does not have the situation generation of loss information, and can guarantee that F can export nonstandard multi-valued signal is corrected to the multi-valued signal of specification, read as information correction, make to see that reading is still correct multi-valued signal from the outside, show to read the multi-valued signal with the specification of DRAM input and output identical characteristics through reading circuit, i.e. nonstandard multi-valued signal is corrected to the multi-valued signal of specification by reading circuit；As can be seen here, by above-mentioned information characteristics, and write circuit input and reading circuit output be the requirement of multi-valued signal of specification to design write circuit and reading circuit, then reading difficulty just overcomes.

Accompanying drawing explanation

Fig. 1. a kind of any K value being correlated with for the present invention and the storage unit circuit figure of 8 values DRAM；

Fig. 2. for the write circuit figure of a kind of 8 value DRAM of the present invention；

Fig. 3. for the reading circuit figure of a kind of 8 value DRAM of the present invention；

Fig. 4. for the write circuit figure of a kind of K value DRAM of the present invention；

Fig. 5. for the reading circuit figure of a kind of K value DRAM of the present invention；

Fig. 6. the first the PMOS variable threshold circuit diagram being correlated with for the present invention and variable threshold type PMOS graphical diagram；

Fig. 7. the second PMOS variable threshold circuit diagram being correlated with for the present invention and variable threshold type PMOS graphical diagram；

Fig. 8. for Fig. 6 uses V_dcReplace V_ddThe first PMOS variable threshold circuit diagram and variable threshold type PMOS graphical diagram；

Fig. 9. for Fig. 7 uses V_dcReplace V_ddThe second PMOS variable threshold circuit diagram and variable threshold type PMOS graphical diagram；

Figure 10. for existing a kind of multi output precision mirror-image constant flow source circuit diagram and graphical diagram；

Figure 11. it is worth the storage unit circuit of DRAM, write circuit and reading circuit for the present invention 8 at w_riAnd r_diW under acting on successively_ri、r_di、D_inj、G_wrij、C_mij、F_olij、G_rdijAnd D_outjThe most discrete oscillogram of priority；

Figure 12. the write circuit input D of DRAM it is worth for the present invention 8_injD is exported with reading circuit_outjAt w_riAnd r_diOscillogram under acting on successively；

Figure 13. the write circuit input D of DRAM it is worth for the present invention 8_injWith output G_wrijAt w_riOscillogram under Zuo Yong；

Figure 14. the reading circuit input G of DRAM it is worth for the present invention 8_rdijWith output D_outjAt r_diOscillogram under Zuo Yong；

Figure 15. the input C of the voltage follower F of the storage unit circuit of DRAM it is worth for the present invention 8_mijWith output F_olijThere iing w_riOscillogram during effect；

Figure 16. it is worth the storage unit circuit of DRAM, write circuit and reading circuit for the present invention 8 at w_riAnd r_diD under acting on successively_inj、G_wrij、C_mij、F_olij、G_rdijAnd D_outjThe most discrete oscillogram；

Figure 17. it is worth the write circuit of DRAM at w for the present invention 8_ri=0 transmission gate G₁D is inputted during cut-off and by write circuit_injChange write circuit input D during sine wave into_injG is exported with write circuit_wrijOscillogram；

Figure 18. it is worth the reading circuit of DRAM at r for the present invention 8_di=0 transmission gate G₂G is inputted during cut-off and by reading circuit_rdijChange reading circuit input G during sine wave into_rdijD is exported with reading circuit_outjOscillogram；

Figure 19. for circuit and the graphical diagram of conventional cmos transmission gate.

Detailed description of the invention

The present invention is further illustrated in detail below:

Embodiment 1: the explanation of storage unit circuit informational function.

Storage unit circuit has multilevel information storage, and multilevel information receives and multilevel information sends three informational functions: 1. information receives: found out by Fig. 1, write pulse w_riCome then, transmission gate G₁Conducting, by write bit line G_wrijMultilevel information be sent to store electric capacity C_j, make electric capacity C_jReceive multilevel information C_mij；Electric capacity C_jReception is a charge and discharge process, is to charge or discharge with depending on electric capacity C_jThe information of former storage and the existing information received, discharge and recharge time constant be C_jCapacitance is relevant, C_jIt is generally only a few pico farad, it is impossible to the biggest；2. information storage: write pulse w_riFuture then, transmission gate G₁Cut-off, is found out by Fig. 1, stores electric capacity C_jOnly with NMOS tube Q_m1Grid and cmos transmission gate G₁Output be connected, pipe Q_m1Grid input resistance close to open circuit, G₁Also close to open circuit during cut-off, now electric capacity C_jWith extraneous D.C. resistance almost infinity, use electric capacity C_jMulti-valued signal can well be stored；3. delivering: found out by Fig. 1, read pulse r_diCome then, transmission gate G₂Conducting, is sent to sense bit line G by the multilevel information that voltage follower F exports_rdij, both made electric capacity C_jThere are faint electric leakage and F imperfection, affect F output and be sent to sense bit line G_rdijMultilevel information, but reading circuit still has the ability to be corrected to the multilevel information of correct specification.

Note: transmission gate G₁During cut-off, require C in theory_jBe that direct current is opened a way with the external world, i.e. D.C. resistance is infinitely great, actually C_jBeing high resistant (almost without DC channel) with the external world, actual have faint electric leakage, C_jThe multi-valued signal of storage can only keep certain time, and the most all DRAM need separately to add one and refresh circuit, and periodic refreshing makes it recover former and deposits information.

In storage unit circuit, voltage follower F is critically important, if but F inputs information improper use, and actual F output has the situation losing multilevel information to occur, and uses electric capacity C_j(F input) storage multilevel information is that cost is extremely low, conventional DRAM electric capacity C_jStoring two value informations, the quantity of information of two value informations is minimum, and the quantity of information of multilevel information is higher than two-value, uses electric capacity C_jStorage multilevel information is more to one's profit than storage two value informations.F output has the reason losing multilevel information generation to be described as follows: if electric capacity C_jReceive a desired voltage follower F_AInput, desired voltage follower F_AVoltage amplification factor perseverance be 1, without direct current offset, then F_AOutput voltage and electric capacity C_jVoltage is identical, i.e. F_AOutput and electric capacity C_jThe multilevel information of storage is identical.Not having desired voltage follower in reality, the voltage amplification factor of virtual voltage follower (F in the present invention) is less than 1, and has direct current offset Δ, as electric capacity C_jOn voltage less than Δ time (if logical value is 1, its logic level=V_Don＜ Δ), F is output as 0, i.e. C_jStorage signal logic value is not 0, and F output signal logical value is 0；For the shortcoming overcoming direct current offset, F is avoided to export information dropout, what write circuit was supplied to storage unit circuit input is the multi-valued signal increasing Δ, and the multi-valued signal increasing Δ exports after F is unconventional multi-valued signal, with reading circuit, this is corrected to the multi-valued signal waiting ladder of specification further.Consider input D_injWith output D_outjStepped-up voltage identical, conducting voltage V of stepped-up voltage diode in fact_Don, input D_injWith output D_outjLargest logical level equal to V_DonL times of (LV_Don), so supply voltage V_ddThe above-mentioned high Δ of largest logical level of ratio, Δ is easily calculated by F or surveys out, C_jIt is generally only a few pico farad.

In storage unit circuit, cmos transmission gate shows the circuit and graphical diagram that such as Figure 19, i.e. Figure 19 are conventional cmos transmission gate, and cmos transmission gate is by a P-channel and N-channel enhancement mode MOSFET (i.e. NMOS tube Q_G1With PMOS Q_G2) be formed in parallel, this cmos transmission gate is per se with CMOS inverter (i.e. NMOS tube Q_G4With PMOS Q_G3).Cmos transmission gate circuit is simple, can two-way transmission signals, be commonly used for analog switch.

Embodiment 2: the arbitrarily write circuit of K value and 8 values DRAM meets the proof that design requires.

The arbitrarily write circuit of K value DRAM shows such as Fig. 4, need to prove that meeting design requires: when write circuit inputs D_injLogical value is 0,1,2,3,4 ... .., L-2, L-1, L time, write circuit output G_wrijLogical value is still followed successively by 0,1,2,3,4 ... .., L-2, L-1, L；But G_wrijLogical value counterlogic level V_GwrijN () compares D in addition to 0 level_injLogical value counterlogic level V_DinjN () high Δ (n=1～L), 0 level is still 0, i.e. V_Gwrij(0)=V_Dinj(0)=0V, V_Gwrij(1)=V_Dinj(1)+Δ、V_Gwrij(2)=V_Dinj(2)+Δ、.....、V_Gwrij(L-1)=V_Dinj(L-1)+Δ、V_Gwrij(L)=V_Dinj(L)+Δ, V_Dinj(k) ＞ V_Dinj(k-1)；ta_kAdjacent logic levels V for write circuit input_Dinj(k) and V_Dinj(k-1) intermediate value, meets V_Dinj(k-1) ＜ ta_k＜ V_Dinj(k), k=1,2,3,4 ... .., L-2, L-1, L, i.e. meet inequality 0 ＜ ta₁＜ V_Dinj(1) ＜ ta₂＜ V_Dinj(2) ＜ ta₃＜ V_Dinj(3) ＜ ta₄＜ ... .. ＜ ta_L-2＜ V_Dinj(L-2) ＜ ta_L-1＜ V_Dinj(L-1) ＜ ta_L＜ V_Dinj(L)；Because pipe Qa_kConducting voltage is 0V (or nearly 0V), pipe Qa_kConducting voltage is exactly pipe Qa_kDuring conducting source electrode and drain electrode between pressure drop, pipe Qa_kConducting electric current takes less value (such as 30 μ A), namely constant-current source I_jElectric current takes less value (such as 30 μ A), remembers V_DinjAnd V_GwrijIt is respectively write circuit input D_injWith output G_wrijVoltage (instantaneous value), diode turn-on voltage V_DonEqual to input V_DinjThe stepped-up voltage of K value signal, namely V_DonEqual to V_DinjThe poor V of each adjacent logic levels_Dinj(m)-V_Dinj(m-1), so V_Dinj(m)=mV_Don, supply voltage V_ddThe ratio high Δ of maximum of the K value logic level of the input of write circuit and the output of reading circuit, i.e. V_dd=V_Doutj(L)+Δ=V_Dinj(L)+Δ=LV_Don+Δ。

The input/output relation of write circuit proves as follows: according to above-mentioned inequality 0 ＜ ta₁＜ V_Dinj(1) ＜ ta₂＜ V_Dinj(2) ＜ ta₃＜ V_Dinj(3) ＜ ta₄＜ ... .. ＜ ta_L-2＜ V_Dinj(L-2) ＜ ta_L-1＜ V_Dinj(L-1) ＜ ta_L＜ V_Dinj(L), Fig. 4 find out: 1. work as D_injWhen inputting 0 level, V_Dinj(0) ＜ ta₁, all pipe Qa₁～Qa_LAll end, write circuit output voltage V_Gwrij=V_Dinj(0)=0V, 2. works as D_injWhen inputting 1 level, ta₁＜ V_Dinj(1) ＜ ta₂, pipe Qa₁Conducting, pipe Qa₂～Qa_LCut-off, (L-1) individual diode Da₂～Da_LConducting, V_Gwrij=V_dd-(L-1)V_Don=LV_Don+Δ-(L-1)V_Don=V_Don+ Δ=V_Dinj(1)+Δ, 3. works as D_injWhen inputting 2 level, ta₂＜ V_Dinj(2) ＜ ta₃, pipe Qa₁And Qa₂Conducting, pipe Qa₃～Qa_LCut-off, (L-2) individual diode Da₃～Da_LConducting, V_Gwrij=V_dd-(L-2)V_Don=LV_Don+Δ-(L-2)V_Don=2V_Don+ Δ=V_Dinj(2)+Δ, 4. works as D_injWhen inputting 3 level, ta₃＜ V_Dinj(3) ＜ ta₄, pipe Qa₁～Qa₃Conducting, pipe Qa₄～Qa_LCut-off, (L-3) individual diode Da₄～Da_LConducting, V_Gwrij=V_dd-(L-3)V_Don=LV_Don+Δ-(L-3)V_Don=3V_Don+ Δ=V_Dinj(3)+Δ ... 5. .. works as D_injDuring input L-2 level, ta_L-2＜ V_Dinj(L-2) ＜ ta_L-1, pipe Qa₁～Qa_L-2Conducting, pipe Qa_L-1And Qa_LCut-off, 2 diode Da_L-1And Da_LConducting, V_Gwrij=V_dd-2V_Don=LV_Don+Δ-2V_Don=(L-2) V_Don+ Δ=V_Dinj(L-2)+Δ, 6. works as D_injDuring input L-1 level, ta_L-1＜ V_Dinj(L-1) ＜ ta_L, pipe Qa₁～Qa_L-1Conducting, pipe Qa_LCut-off, 1 diode Da_LConducting, V_Gwrij=V_dd-V_Don=LV_Don+Δ-V_Don=(L-1) V_Don+ Δ=V_Dinj(L-1)+Δ, 7. works as D_injDuring input L level, ta_L＜ V_Dinj(L), pipe Qa₁～Qa_LConducting, V_Gwrij=V_dd=LV_Don+ Δ=LV_Don+ Δ=V_Dinj(L)+Δ.Thus draw the output G of write circuit_wrijThe ratio high Δ of K value signal of write circuit input in addition to 0 level, 0 level is still 0, exports G_wrijIt is the K value signal increased, overcomes the deficiency having DC Level Shift Δ in storage unit circuit between the input and output of voltage follower F.Pspice computer simulation waveform in accompanying drawing also confirms that its correctness.Diode used is silicon diode, and conducting electric current takes smaller value, namely constant-current source I_jElectric current takes less value, and Δ is easy to be calculated by F or survey out.The most desirable slightly larger value of Δ in practicality, thus the output G of gained_wrijBe Δ slightly larger increase signal, what Δ was slightly larger increase signal draws actual G through F_rdijThe unconventional K value signal of input, but have no effect on result, this is because reading circuit can be by any unconventional non-K value signal G waiting ladder_rdijBe converted to the K value signal D waiting ladder of specification_outjAs long as now actual G pressed by reading circuit_rdijThe unconventional K value signal (corresponding Δ is slightly larger) of input designs.

Arbitrarily taking K=8 in the write circuit of K value DRAM, then draw the write circuit of 8 values DRAM, show such as Fig. 2, same method proves that the write circuit of 8 value DRAM meets design requirement.Figure 10 is existing a kind of multi output precision mirror current source (constant-current source) circuit diagram and graphical diagram, for reducing power consumption and improving performance etc., its constant-current source I_jElectric current takes smaller value.

Embodiment 3: the arbitrarily reading circuit of K value and 8 values DRAM meets the proof that design requires.

The arbitrarily reading circuit of K value DRAM shows such as Fig. 5, need to prove that meeting design requires: as the input G of reading circuit_rdijLogical value is 0,1,2,3,4 ... .., L-2, L-1, L time, the input D of reading circuit_outjLogical value is still followed successively by 0,1,2,3,4 ... .., L-2, L-1, L；G_rdij, D_injAnd D_outjLogical value counterlogic level is followed successively by V_Grdij(n), V_Dinj(n) and V_DoutjN () (n=0～L), wherein inputs G_rdijIt is unconventional K value signal, it is desirable to output D_outjThe K value signal waiting ladder of specification, i.e. V_Doutj(0)=V_Dinj(0)=0V, V_Doutj(1)=V_Dinj(1)=V_Don, V_Doutj(2)=V_Dinj(2)=2V_Don, V_Doutj(3)=V_Dinj(3)=3V_Don... ..V_Doutj(L-2)=V_Dinj(L-2)=(L-2) V_Don, V_Doutj(L-1)=V_Dinj(L-1)=(L-1) V_Don, V_Doutj(L)=V_Dinj(L)=LV_Don；tb_kFor input G_rdijAdjacent logic levels V of unconventional K value signal_Grdij(k) and V_Grdij(k-1) intermediate value, meets V_Grdij(k-1) ＜ tb_k＜ V_Grdij(k), k=1,2,3,4 ... .., L-2, L-1, L, i.e. meet inequality 0 ＜ tb₁＜ V_Grdij(1) ＜ tb₂＜ V_Grdij(2) ＜ tb₃＜ V_Grdij(3) ＜ tb₄＜ ... .. ＜ tb_L-2＜ V_Grdij(L-2) ＜ tb_L-1＜ V_Grdij(L-1) ＜ tb_L＜ V_Grdij(L)；Consider pipe Qb_kConducting voltage is 0V (or nearly 0V), pipe Qb_kConducting voltage is exactly pipe Qb_kDuring conducting source electrode and drain electrode between pressure drop, pipe Qb_kConducting electric current takes less value (such as 30 μ A), i.e. constant-current source I_jElectric current takes less value (such as 30 μ A), remembers V_GrdijAnd VD_outjIt is respectively reading circuit input G_rdijWith output D_outjVoltage (instantaneous value), diode turn-on voltage V_DonEqual to output D_outjThe stepped-up voltage of K value signal of specification, namely V_DonEqual to output D_outjThe poor V of each adjacent logic levels_Doutj(m)-V_Doutj(m-1), so V_Doutj(m)=mV_Don, supply voltage V_dcEtc. the input of write circuit and the largest logical level V of the output of reading circuit_DinjAnd V (L)_Doutj(L), V_dc=V_Doutj(L)=LV_Don。

The input/output relation of reading circuit proves as follows: according to above-mentioned inequality 0 ＜ tb₁＜ V_Grdij(1) ＜ tb₂＜ V_Grdij(2) ＜ tb₃＜ V_Grdij(3) ＜ tb₄＜ ... .. ＜ tb_L-2＜ V_Grdij(L-2) ＜ tb_L-1＜ V_Grdij(L-1) ＜ tb_L＜ V_Grdij(L), Fig. 5 find out: 1. work as G_rdijWhen inputting 0 level, V_Grdij(0)=0V, V_Grdij(0) ＜ tb₁, all pipe Qb₁～Qb_LAll end, the output voltage V of reading circuit_Doutj=0V, 2. works as G_rdijWhen inputting 1 level, tb₁＜ V_Grdij(1) ＜ tb₂, pipe Qb₁Conducting, pipe Qb₂～Qb_LCut-off, (L-1) individual diode Db₂～Db_LConducting, V_Doutj=V_dc-(L-1)V_Don=LV_Don-(L-1)V_Don=V_Don=V_Doutj(1), G is 3. worked as_rdijWhen inputting 2 level, tb₂＜ V_Grdij(2) ＜ tb₃, pipe Qb₁And Qb₂Conducting, pipe Qb₃～Qb_LCut-off, (L-2) individual diode Db₃～Db_LConducting, V_Doutj=V_dc-(L-2)V_Don=LV_Don-(L-2)V_Don=2V_Don=V_Doutj(2), G is 4. worked as_rdijWhen inputting 3 level, meet tb₃＜ V_Grdij(3) ＜ tb₄, then pipe Qb₁～Qb₃Conducting, pipe Qb₄～Qb_LCut-off, has (L-3) individual diode Db₄～Db_LConducting, V_Doutj=V_dc-(L-3)V_Don=LV_Don+Δ-(L-3)V_Don=3V_Don=V_Doutj(3) ... 5. .. works as G_rdijDuring input L-2 level, tb_L-2＜ V_Grdij(L-2) ＜ tb_L-1, pipe Qb₁～Qb_L-2Conducting, pipe Qb_L-1And Qb_LCut-off, 2 diode Db_L-1And Db_LConducting, V_Doutj=V_dc-2V_Don=LV_Don-2V_Don=(L-2) V_Don=V_Doutj(L-2), G is 6. worked as_rdijDuring input L-1 level, tb_L-1＜ V_Grdij(L-1) ＜ tb_L, pipe Qb₁～Qb_L-1Conducting, pipe Qb_LCut-off, 1 diode Db_LConducting, V_Doutj=V_dc-V_Don=LV_Don-V_Don=(L-1) V_Don=V_Doutj(L-1), G is 7. worked as_rdijDuring input L level, tb_L＜ V_Grdij(L), pipe Qb₁～Qb_LConducting, V_Doutj=V_dc=LV_Don=V_Doutj(L).Thus draw: although reading circuit input G_wrijIt is unconventional K value signal, and reading circuit output D_outjBut it is that grade the ladder K value signal, i.e. reading circuit of specification are by unconventional K value signal G_rdijBe converted to specification wait ladder K value signal D_outj.Pspice computer simulation waveform in accompanying drawing also confirms that its correctness, and continuous wave (Figure 18) the ladder K value signal D such as can be converted to_outj.Diode used is silicon diode, and conducting electric current takes smaller value.

Arbitrarily taking K=8 in the reading circuit of K value DRAM, then draw the reading circuit of 8 values DRAM, show such as Fig. 3, same method proves that the reading circuit of 8 value DRAM meets design requirement.Figure 10 is existing a kind of multi output precision mirror current source (constant-current source) circuit diagram and graphical diagram, for reducing power consumption and improving performance etc., its constant-current source I_jElectric current takes smaller value.

The explanation of embodiment 4:PMOS pipe variable threshold circuit (being called for short variable threshold circuit).

The first PMOS variable threshold circuit (being called for short the first variable threshold circuit) shows dashed box as left in Fig. 6, and it is by NMOS tube Q₃, PMOS Q₄With resistance R₃Composition, pipe Q₃Grid meet input voltage V_x, pipe Q₄Grid meet reference voltage V_ref, pipe Q₃Drain electrode be this circuit export V_out1, export V_out1Accept control PMOS Q_T1；Change reference voltage V_ref, make Q_T1New threshold value change (amplify, reduce, changes unlatching character and improve unlatching resolution)；Meet the pipe Q of PMOS variable threshold circuit_T1It is referred to as variable threshold type PMOS.If V_dd＞ V_d≥V_tn+|V_tp|, V_dd-V_d≥|V_tp|+V_tn, remember V_extn1=V_ref+V_tn+|V_tp|, V_refIt is respectively V for reference voltage, NMOS and PMOS threshold voltage_tn＞ 0 and V_tp＜ 0.Pipe Q₃And Q₄Grid source potential difference is respectively V_gs3And V_gs4, because Q₃And Q₄Two source electrodes connect, Q₃Drain electrode through resistance R₃Meet power supply V_dd, Q₄Grounded drain, only work as Q₃And Q₄The poor V of two grid voltages_g3-V_g4≥V_tn+|V_tp| time, pipe Q₃And Q₄Just simultaneously turn on, end the most simultaneously.Because of V_g3=V_x, V_g4=V_ref, it follows that: 1. work as V_x-V_ref=V_g3-V_g4≥V_tn+|V_tp|, i.e. input voltage V_x≥V_ref+V_tn+|V_tp|=V_extn1Time, pipe Q₃And Q₄Conducting, resistance R₃On voltage V_out1For the lowest, make Q_T1Conducting；2. V is worked as_x＜ V_extn1Time, Q₃And Q₄Cut-off, V_out1=V_dd, make Q_T1Cut-off；Show, after this variable threshold circuit, to make Q_T1Become V_x≥V_extn1Time conducting, or variable threshold type PMOS Q_T1New threshold value t size become V_extn1, i.e. t=V_extn1, change reference voltage V_ref, make t change, open character and change (Q_T1Become V_xTurn on during >=t).Because of V_dd≥V_ref>=0, t=V_extn1Minima is V_tn+|V_tp|, the first PMOS variable threshold circuit can not realize t less than V_tn+|V_tp| new threshold value, less t also needs with the second PMOS variable threshold circuit realiration.

The second PMOS variable threshold circuit (being called for short the second variable threshold circuit) shows dashed box as left in Fig. 7, and its structure (is included NMOS tube Q by the first PMOS variable threshold circuit₃, PMOS Q₄With resistance R₃) add a CMOS inverter and (include PMOS Q₅With NMOS tube Q₆) composition, wherein pipe Q₄Grid meet input voltage V_x, pipe Q₃Grid meet reference voltage V_ref, pipe Q₃Drain electrode connect CMOS inverter input (pipe Q₅With pipe Q₆Grid), CMOS inverter output (pipe Q₅With pipe Q₆Drain electrode) be this circuit export V_out0, export V_out0Accept control PMOS Q_T0；Change reference voltage V_ref, make Q_T0New threshold value change (amplify, reduce, changes unlatching character and improve unlatching resolution)；Meet the pipe Q of PMOS variable threshold circuit_T0It is referred to as variable threshold type PMOS.If V_dd＞ V_d≥V_tn+|V_tp|, V_dd-V_d≥|V_tp|+V_tn, remember V_extn0=V_ref-V_tn-|V_tp|, NMOS and PMOS variable threshold threshold voltage are respectively V_tn＞ 0 and V_tp＜ 0.Pipe Q₃And Q₄Grid source potential difference is respectively V_gs3And V_gs4, ibid reason, only work as Q₃And Q₄The poor V of two grid voltages_g3-V_g4≥V_tn+|V_tp| time, pipe Q₃And Q₄Just simultaneously turn on, otherwise V_g3-V_g4＜ V_tn+|V_tp|, pipe Q₃And Q₄End simultaneously.Because of V_g3=V_ref, V_g4=V_x, it follows that: 1. work as V_ref-V_x=V_g3-V_g4＜ V_tn+|V_tp|, pipe Q₃And Q₄Cut-off, i.e. input voltage V_x＞ V_ref-V_tn-|V_tp|=V_extn0Time, pipe Q₃And Q₄Cut-off, pipe Q₃Drain electrode (i.e. CMOS inverter input) be V_dd, then pipe Q₅Cut-off and pipe Q₆Conducting, CMOS inverter output V_out0=V_d, make Q_T0Conducting；2. V is worked as_x≥V_extn0Time, Q₃And Q₄Conducting, pipe Q₃Drain electrode (i.e. CMOS inverter input) be the lowest, then pipe Q₆Cut-off and pipe Q₅Conducting, CMOS inverter output V_out0=V_dd, make Q_T0Cut-off.Show, after variable threshold circuit, to make Q_T0Become V_x≥V_extn0Time conducting, i.e. t=V_extn0.Wherein t=V_extn0=V_ref-V_tn-|V_tp| V can be less than_tn+|V_tp|, show variable threshold type PMOS Q_T0New threshold value t size become V_extn0, i.e. t=V_extn0.Change reference voltage V_ref, make t change, open character and change (Q_T0Become V_xTurn on during >=t).Because of V_dd≥V_ref>=0, new threshold value t minima is 0, and maximum is V_dd-V_tn-|V_tp|。

Change reference voltage V_ref, make t change, the first PMOS variable threshold circuit diagram 6 (t=V_extn1=V_ref+V_tn+|V_tp|) can not realize less than V_tn+|V_tp| new threshold value t, the second PMOS variable threshold circuit diagram 7 (t=V_extn0=V_ref-V_tn-|V_tp|) can not realize more than V_dd-V_tn-|V_tp| new threshold value t, often need to two kinds of PMOS variable threshold circuit with the use of.By the V in Fig. 6 and Fig. 7_ddChange V into_dc, show that Fig. 8 and Fig. 9, Fig. 8 can not realize less than V the most respectively_tn+|V_tp| new threshold value t, Fig. 9 can not realize more than V_dc-V_tn-|V_tp| new threshold value t, the most often need to these two kinds of PMOS variable threshold circuit with the use of.R in Fig. 6 and Fig. 7 (including Fig. 8 and Fig. 9)₃Available constant-current source I₃Replace (current direction Q₃Drain electrode).

For obtaining a sequence difference reference voltage V_ref(because sequence variable threshold type PMOS has respective new threshold value ta_kOr tb_k, need to be with different reference voltage V_refRequired new threshold value is obtained) by two kinds of PMOS variable threshold circuit, can be used on and connect the bleeder circuit of multiple resistant series between DC source and ground (by common method) and realize, can be also used in the bleeder circuit that the indirect multiple diodes (or field-effect diode) of DC source and ground connect and realize (the most according to circumstances need also can connect a resistance), multiple diode cathodes are the same with the connection that conventional battery is connected with negative pole connection, such as k diode D₁～D_k, D₁Positive pole meets DC source, D₁Negative pole meets D₂Positive pole, D₂Negative pole meets D₃Positive pole ... .., D_k-2Negative pole meets D_k-1Positive pole, D_k-1Negative pole meets D_kPositive pole, D_kMinus earth (or by R ground connection) realizes, because sequence difference reference voltage V_refIt is all that output is almost 0 to metal-oxide-semiconductor grid, output DC current, it is achieved that get up easily.Heretofore described current source I shows such as Figure 10, is the multi output precision mirror current source of a kind of conventional ground connection.

Embodiment 5: the explanation to Pspice computer simulation waveform Figure 11～16 of Fig. 1～3.

Write pulse w_riWith read pulse r_diControl circuit from DRAM (considers the wordline output W of address decoder_i, read/write controls, and sheet selects, refreshing etc.), at r_diAnd w_riEffect under, Fig. 1～3 is carried out Pspice computer simulation, show that various analog waveform shows such as Figure 11～16, note: w in figure_ri, r_di, D_inj, G_wrij, C_mij, F_olij, G_rdijAnd D_outj8 waveforms be the most each written as V (wri) at each figure abscissa, V (rdi), V (Dinj), V (Gwrij), V (Cmij), V (Folij), V (Grdij), 8 forms with V of V (Doutj), i.e. be written as w in V bracket below respectively_ri, r_di, D_inj, G_wrij, C_mij, F_olij, G_rdijAnd D_outj(wherein subscript changes non-lower target normal font, i.e. wri, rdi, Dinj into, Gwrij, Cmij, Folij, Grdij and Doutj, this is Pspice simulation drawing representation), the most all oscillogram abscissas are all write out by similar representation below, describe the most one by one.Figure 11 is that the storage unit circuit that the present invention 8 is worth DRAM, write circuit and reading circuit are at w_riAnd r_diD under acting on successively_inj、G_wrij、C_mij、F_olij、G_rdijAnd D_outjThe most discrete oscillogram of priority, be followed successively by w by Figure 11 order from top to bottom_ri, r_di, D_inj, G_wrij, C_mij, F_olij, G_rdijAnd D_outj8 waveforms, Figure 12 is at w_riAnd r_diEffect under, D_injAnd D_outj2 waveforms, by w in figure_riAnd r_diReduced height ten times, and be placed on the foot (r of figure_diAt the bottommost of figure, w_riAt r_diTop), as can be seen from Figure 12, the input D of the write circuit of DRAM_injThe output D of curve and reading circuit_outjCurve is the multi-valued signal waiting ladder, with the D of logical value_injAnd D_outjLogic level be equal, meet described requirement, D_outjIt is at r_diChange when (see the bottommost of figure) is come.Figure 13 is at w_riUnder the effect of (see the bottommost of figure), the input D of 8 value DRAM write circuits_injWith output G_wrij2 waveforms, it is seen from figure 13 that input D_injCurve is the multi-valued signal (relatively for following curve) waiting ladder, exports G_wrijCurve is the multi-valued signal (relatively for the non-curve waiting ladder above) increased, with the D of logical value_injAnd G_wrijLogic level (in addition to 0 level is equal) be unequal, thus overcome the deficiency having downward DC Level Shift Δ in storage unit circuit between the input and output of voltage follower F.Figure 14 is at r_diUnder the effect of (see the bottommost of figure), the input G of 8 value DRAM reading circuits_rdjjWith output D_outj2 waveforms, as can be seen from Figure 14, input G_rdijCurve is that less (relatively low curve, with D for ladder_injLadder differs) multi-valued signal, with the D of logical value_injAnd G_rdijLogic level be unequal, export D_outjCurve (of a relatively high curve) is and D_injThe multi-valued signal waiting ladder that ladder is identical, i.e. reading circuit is by unconventional multi-valued signal G_rdijBe converted to the multi-valued signal D waiting ladder of specification_outj, thus overcome the voltage follower F voltage amplification factor deficiency less than 1 in storage unit circuit.Figure 15 is at w_riUnder the effect of (see the bottommost of figure), the input C of the voltage follower F of 8 value DRAM memory cell circuit_mijWith output F_olij2 waveforms, as can be seen from Figure 15, input C_mijCurve is the multi-valued signal (relatively for upper graph, non-ladder such as grade) increased, and exports F_olijCurve (being lower surface curve relatively) is to input C_mijCurve has downward level shift, and amplitude reduces, and shows that in storage unit circuit, voltage follower F there are downward level shift and voltage amplification factor less than 1.Figure 16 is that the storage unit circuit that the present invention 8 is worth DRAM, write circuit and reading circuit are at w_riAnd r_di(r_diAt the bottommost of figure, w_riAt r_diTop) act on successively under D_inj、G_wrij、C_mij、F_olij、G_rdijAnd D_outjThe most discrete oscillogram, be i.e. equivalent to the merging of 6 curves in Figure 13, Figure 14 and Figure 15.

The explanation of the Pspice computer simulation waveform of embodiment 6: Figure 17 and Figure 18.

Main Pspice analog waveform completes in embodiment 5, consider now that write circuit and reading circuit input as situation time sinusoidal wave the most respectively, as the reference further appreciating that write and reading circuit advantage, write circuit input D in order to separate with above-mentioned simulation region during note: this Pspice simulation, during input sine wave_injD is exported with reading circuit_outjEach use symbol IND instead_iAnd OUTD_i(each remain and input D in write circuit_injD is exported with reading circuit_outjOn 2, i.e. symbol is different, and each input represented is identical with output point, is still referred to as write circuit input D during explanation_injD is exported with reading circuit_outj), the then input of the write circuit in 17 D_injD is exported with the reading circuit in Figure 18_outjPspice analog waveform figure abscissa be the most each written as V (INDi) and V (OUTDi), and G_wrij、G_rdijPspice analog waveform figure abscissa below and same as before be written as V (Gwrij), V (Grdij) the most successively.Figure 17 is that the present invention 8 is worth the write circuit of DRAM at w_ri=0 transmission gate G₁During cut-off and input D_injFor input D during sine wave_injWith output G_wrijOscillogram, as can be seen from Figure 17, sinusoidal wave continuous signal input D_injThe output G that curve draws after write circuit_wrijCurve is discontinuous multi-valued signal (but has and increase effect), shows that write circuit has good quantization shaping operation (the quantization effect that similar 4 houses 5 enter), as input D_injWhen voltage rises or falls not across upper and lower two new threshold values, export G_wrijStill can recover former multilevel information, i.e. have the former multilevel information ability of recovery, this ability can be additionally used in refreshing.Figure 18 is that the present invention 8 is worth the reading circuit of DRAM at r_di=0 transmission gate G₂During cut-off and input G_rdijFor input G during sine wave_rdijWith output D_outjOscillogram.As can be seen from Figure 18, sinusoidal wave continuous signal input G_rdijThe output D that curve draws after reading circuit_outjCurve is discontinuous (being corrected to wait ladder) multi-valued signal, shows that reading circuit has good quantization shaping operation (the quantization effect that similar 4 houses 5 enter), as input G_rdijWhen voltage rises or falls not across upper and lower two new threshold values, export D_outjStill can recover former multilevel information, i.e. have the former multilevel information ability of recovery, this ability can be additionally used in refreshing.For improving interference free performance, increase and recover former multilevel information ability, alleviate refresh tasks, can suitably strengthen the numerical value of the storage electric capacity of memory element.It addition, reading circuit input is also the grid of metal-oxide-semiconductor, there is information memory action equally, for improving interference free performance, increase and recover former multilevel information ability, alleviate refresh tasks, its grid input capacitance also with slightly larger be favourable.Embodiment 7: choose ta_kAnd tb_kThe explanation of numerical value.

Theoretical proof above-mentioned (1) and (2) are only required and are met following inequality: prove that (1) only requires satisfied 0 ＜ ta₁＜ V_Dinj(1) ＜ ta₂＜ V_Dinj(2) ＜ ta₃＜ V_Dinj(3) ＜ ta₄＜ ... .. ＜ ta_L-2＜ V_Dinj(L-2) ＜ ta_L-1＜ V_Dinj(L-1) ＜ ta_L＜ V_Dinj(L), it was demonstrated that (2) only require satisfied 0 ＜ tb₁＜ V_Grdij(1) ＜ tb₂＜ V_Grdij(2) ＜ tb₃＜ V_Grdij(3) ＜ tb₄＜ ... .. ＜ tb_L-2＜ V_Grdij(L-2) ＜ tb_L-1＜ V_Grdij(L-1) ＜ tb_L＜ V_Grdij(L)；Find out from proof procedure, in theory the arbitrary value between the new desirable adjacent logic levels of threshold value, it practice, one. by anti-interference requirement, preferably taking the meansigma methods close or equal to adjacent logic levels, the present invention is namely based on anti-interference and requires design；Two. by refresh performance requirement, preferably take the meansigma methods of slightly above adjacent logic levels, make permission discharge charge more, but take into account anti-interference requirement, can only suitable deviation average, it is impossible to deviation average is the biggest；Three. when input voltage is equal to new threshold value, the transition region that output is between adjacent logic levels, the size of transition region depends on that the unlatching resolution of new threshold value is (mathematically ' when input >=new threshold value, then pipe conducting ', it is only preferable, actual without=), this unlatching resolution is preferable, but does not reaches mathematical desirable.

Embodiment 8: use resistance R_jReplace constant-current source I_jExplanation.

' constant-current source I_jIt is taken as resistance R_j' i.e. " in the K value DRAM memory cell circuit described in (4), constant-current source I_jIt is taken as resistance R_j", refer to ' use resistance R in K value DRAM memory cell circuit_jReplace constant-current source I_j', namely resistance R_jOne termination emitter-base bandgap grading F_olij, resistance R_jOther end ground connection, so since pipe Q_m2With resistance R_jConstitute emitter follower.Because emitter-base bandgap grading F_olijThrough constant-current source I_jGround connection i.e. constant-current source I_jOne termination emitter-base bandgap grading F_olij, constant-current source I_jOther end ground connection, now pipe Q_m2With constant-current source I_jConstitute emitter follower；In other words, it is simply that change ' pipe Q_m2Emitter-base bandgap grading F_olijThrough constant-current source I_jGround connection ' it is ' pipe Q_m2Emitter-base bandgap grading F_olijThrough resistance R_jGround connection ', the former uses constant-current source I_jThen Q_m2Emitter current constant, the latter uses resistance R_jThen Q_m2Emitter current non-constant, but (meet I both this_jWith meet R_j) it is all conventional emitter follower structure.Note: pipe Q_m1Source electrode connecting resistance R_m1(R_m1Other end ground connection), i.e. constitute source follower (common drain amplifying circuit).Source follower and emitter follower are conventional circuit, similar with emitter follower (audion common collector amplifying circuit), field effect transistor source follower (common drain amplifying circuit) does not has voltage amplification effect, its voltage gain is less than 1, output voltage is identical with input voltage phase, input resistance is high, and output resistance is low, can be used as impedance transformation.The input resistance of source follower is high, is suitable for meeting storage electric capacity C_j(leaking electricity minimum), the input resistance of emitter follower is low, uncomfortable splice grafting storage electric capacity C_j(electric leakage is big), but the output resistance of source follower is higher than the output resistance of emitter follower, load capacity is poor, for increasing load capacity, the output of source follower can be connect the input of emitter follower, using the output of emitter-base bandgap grading as the output of voltage follower, its output loading capability is just greatly reinforced.

Claims (4)

1. the write circuit of any K value DRAM, it is characterised in that: in the write circuit of described K value DRAM, if K=3,4,5 ...；Use K-1=L variable threshold type PMOS Qa_k, k=1,2,3 ..., L, pipe Qa_kGrid be connected to the input D of write circuit through PMOS variable threshold circuit_inj, variable threshold type PMOS Qa_kNew threshold value be ta_k, pipe Qa_kDuring conducting, between source drain, pressure drop is 0；Pipe Qa_kSource electrode meet power supply V_dd, choose V_ddVoltage ratio write circuit input and reading circuit output largest logical level V_DinjAnd V (L)_Douj(L) high △, △ are DC Level Shifts downward between voltage follower F input and output in the storage unit circuit of any K value DRAM；Use L-1 diode Da_n, n=2,3 ..., L, diode Da_nConducting voltage be V_Don；Da_nPositive pole and negative pole be connected respectively to variable threshold type PMOS Qa_n-1Drain electrode and pipe Qa_nDrain electrode；Pipe Qa_LDrain electrode through constant-current source I_jGround connection, pipe Qa_LDrain electrode meet constant-current source I_jThe electric current flowing through conducting diode keeps same fixed value, at pipe Qa_LDrain electrode formed write circuit output G_wrij, write circuit output G_wrijReceive the write bit line input of storage unit circuit；Choose ta_kD is inputted for write circuit_injAdjacent logic levels V of K value signal_Dinj(k) and V_Dinj(k-1) meansigma methods (V_Dinj(k)+V_Dinj(k-1))/2, i.e. ta_kFor V_Dinj(k) and V_Dinj(k-1) intermediate value, V_Dinj(k) ＞ V_Dinj(k-1)；Write circuit input D_injK value signal and reading circuit output D_outjAnd the specification of DRAM input and output etc. the characteristic of K value signal of ladder be identical: input D_injThe difference of each adjacent logic levels is equal, exports D_outjThe difference of each adjacent logic levels is equal, and input D_injWith output D_outjStepped-up voltage identical, stepped-up voltage is V_Don, namely meet V_Dinj(m)-V_Dinj(m-1)=V_Doutj(m)-V_Doutj(m-1)=V_Don, m=1,2,3 ..., L, V_Dinj(m) and V_DoutjM () is that write circuit inputs and reading circuit output logical value is the logic level of m respectively；The output G of write circuit_wrijThe ratio high △ of K value signal of write circuit input in addition to 0 level, 0 level is still 0, and this K value write circuit is also called K value write attack circuit；

Wherein, the first PMOS variable threshold circuit is by NMOS tube Q₃, PMOS Q₄With resistance R₃Composition, pipe Q₃Grid meet input voltage V_x, pipe Q₄Grid meet reference voltage V_ref, pipe Q₃Drain electrode be this circuit export V_out1, export V_out1Accept control PMOS Q_T1；Change reference voltage V_ref, make Q_T1New threshold value change；Meet the pipe Q of PMOS variable threshold circuit_T1It is referred to as variable threshold type PMOS；If V_dd＞ V_d≥V_tn+∣V_tp, V_dd-V_d≥∣V_tp∣+V_tn, remember V_extn1=V_ref+V_tn+∣V_tp, V_refIt is respectively V for reference voltage, NMOS and PMOS threshold voltage_tn＞ 0 and V_tp＜ 0；Pipe Q₃And Q₄Grid source potential difference is respectively V_gs3And V_gs4, because Q₃And Q₄Two source electrodes connect, Q₃Drain electrode through resistance R₃Meet power supply V_dd, Q₄Grounded drain, only work as Q₃And Q₄The poor V of two grid voltages_g3-V_g4≥V_tn+∣V_tpTime, pipe Q₃And Q₄Just simultaneously turn on, end the most simultaneously, because of V_g3=V_x, V_g4=V_ref, it follows that: 1. work as V_x-V_ref=V_g3-V_g4≥V_tn+∣V_tp, i.e. input voltage V_x≥V_ref+V_tn+∣V_tp=V_extn1Time, pipe Q₃And Q₄Conducting, resistance R₃On voltage V_out1For the lowest, make Q_T1Conducting；2. V is worked as_x＜ V_extn1Time, Q₃And Q₄Cut-off, V_out1=V_dd, make Q_T1Cut-off；Show, after this variable threshold circuit, to make Q_T1Become V_x≥V_extn1Time conducting, or variable threshold type PMOS Q_T1New threshold value t size become V_extn1, i.e. t=V_extn1, change reference voltage V_ref, make t change, open character and change: Q_T1Become V_xTurn on during >=t；Because of V_dd≥V_ref>=0, t=V_extn1Minima is V_tn+∣V_tp, the first PMOS variable threshold circuit can not realize t less than V_tn+∣V_tpNew threshold value, less t also needs with the second PMOS variable threshold circuit realiration；

The second PMOS variable threshold circuit is by NMOS tube Q₃, PMOS Q₄, resistance R₃Forming with CMOS inverter, CMOS inverter includes PMOS Q₅With NMOS tube Q₆, wherein pipe Q₄Grid meet input voltage V_x, pipe Q₃Grid meet reference voltage V_ref, pipe Q₃Drain electrode connect CMOS inverter input, i.e. pipe Q₅With pipe Q₆Grid, CMOS inverter export, i.e. pipe Q₅With pipe Q₆Drain electrode be this circuit export V_out0, export V_out0Accept control PMOS Q_T0；Change reference voltage V_ref, make Q_T0New threshold value change；Meet the pipe Q of PMOS variable threshold circuit_T0It is referred to as variable threshold type PMOS；If V_dd＞ V_d≥V_tn+∣V_tp, V_dd-V_d≥∣V_tp∣+V_tn, remember V_extn0=V_ref-V_tn-V_tp, NMOS and PMOS variable threshold threshold voltage are respectively V_tn＞ 0 and V_tp＜ 0；Pipe Q₃And Q₄Grid source potential difference is respectively V_gs3And V_gs4, ibid reason, only work as Q₃And Q₄The poor V of two grid voltages_g3-V_g4≥V_tn+∣V_tpTime, pipe Q₃And Q₄Just simultaneously turn on, otherwise V_g3-V_g4＜ V_tn+∣V_tp, pipe Q₃And Q₄End simultaneously；Because of V_g3=V_ref, V_g4=V_x, it follows that: 1. work as V_ref-V_x=V_g3-V_g4＜ V_tn+∣V_tp, pipe Q₃And Q₄Cut-off, i.e. input voltage V_x＞ V_ref-V_tn-V_tp=V_extn0Time, pipe Q₃And Q₄Cut-off, pipe Q₃Drain electrode, i.e. CMOS inverter input is for V_dd, then pipe Q₅Cut-off and pipe Q₆Conducting, CMOS inverter output V_out0=V_d, make Q_T0Conducting；2. V is worked as_x≥V_extn0Time, Q₃And Q₄Conducting, pipe Q₃Drain electrode, i.e. CMOS inverter input for the lowest, then pipe Q₆Cut-off and pipe Q₅Conducting, CMOS inverter output V_out0=V_dd, make Q_T0Cut-off；Show, after variable threshold circuit, to make Q_T0Become V_x≥V_extn0Time conducting, i.e. t=V_extn0；Wherein t=V_extn0=V_ref-V_tn-V_tpLess than V_tn+∣V_tp, show variable threshold type PMOS Q_T0New threshold value t size become V_extn0, i.e. t=V_extn0；Change reference voltage V_ref, make t change, open character and change: Q_T0Become V_xTurn on during >=t, because of V_dd≥V_ref>=0, new threshold value t minima is 0, and maximum is V_dd-V_tn-V_tp∣；

Change reference voltage V_ref, make t change, the first PMOS variable threshold circuit, it is impossible to realize less than V_tn+∣V_tpNew threshold value t, the second PMOS variable threshold circuit can not realize more than V_dd-V_tn-V_tpNew threshold value t, often need to two kinds of PMOS variable threshold circuit with the use of；By V_ddChange V into_dc, it is impossible to realize less than V_tn+∣V_tpNew threshold value t, it is impossible to realize more than V_dc-V_tn-V_tpNew threshold value t, the most often need to these two kinds of PMOS variable threshold circuit with the use of；

For obtaining a sequence difference reference voltage V_ref, the bleeder circuit at the indirect multiple resistant series of DC source and ground realizes, or the bleeder circuit connected at the indirect multiple diodes of DC source and ground or field-effect diode realizes.

The write circuit of a kind of any K value DRAM the most according to claim 1, it is characterised in that: take K=8, draw the write circuit of 8 values DRAM, wherein use 7 variable threshold type PMOS Qa_k, k=1,2,3 ..., 7, pipe Qa_kGrid be connected to the input D of write circuit through variable threshold circuit_inj, variable threshold type PMOS Qa_kNew threshold value be ta_k, pipe Qa_kDuring conducting, between source drain, pressure drop is 0；Pipe Qa_kSource electrode meet power supply V_dd, choose V_ddVoltage ratio write circuit input and reading circuit output largest logical level V_DinjAnd V (7)_Douj(7) high △, △ be 8 values DRAM storage unit circuit in voltage follower F input and output between downward DC Level Shift；Use 6 diode Da_n, n=2,3 ..., 7, diode Da_nConducting voltage be V_Don；Da_nPositive pole and negative pole be connected respectively to variable threshold type PMOS Qa_n-1Drain electrode and pipe Qa_nDrain electrode；Pipe Qa₇Drain electrode through constant-current source I_jGround connection, pipe Qa₇Drain electrode meet constant-current source I_jThe electric current flowing through conducting diode keeps same fixed value, at pipe Qa₇Drain electrode formed write circuit output G_wrij, write circuit output G_wrijReceive the write bit line input of storage unit circuit；Choose ta_kD is inputted for write circuit_injAdjacent logic levels V of 8 value signals_Dinj(k) and V_Dinj(k-1) meansigma methods (V_Dinj(k)+V_Dinj(k-1))/2, i.e. choose ta_kFor V_Dinj(k) and V_Dinj(k-1) intermediate value, V_Dinj(k) ＞ V_Dinj(k-1)；Write circuit input D_inj8 value signals and reading circuit output D_outjAnd the specification of DRAM input and output etc. the characteristic of 8 value signals of ladder be identical: input D_injThe difference of each adjacent logic levels is equal, exports D_outjThe difference of each adjacent logic levels is equal, and input D_injWith output D_outjStepped-up voltage identical, stepped-up voltage is V_Don, namely meet V_Dinj(m)-V_Dinj(m-1)=V_Doutj(m)-V_Doutj(m-1)=V_Don, m=1,2,3 ..., 7, V_Dinj(m) and V_DoutjM () is that write circuit inputs and reading circuit output logical value is the logic level of m respectively；Write circuit output G_wrijThe ratio 8 high △ of value signal of write circuit input in addition to 0 level, 0 level is still 0, and this 8 value write circuit is also called 8 value write attack circuits.

3. the identical architectural feature according to the write circuit of any K value DRAM described in claim 1 and the reading circuit of any K value DRAM that formed, it is characterised in that: in the reading circuit of described K value DRAM, if K=3,4,5 ...；Use K-1=L variable threshold type PMOS Qb_k, k=1,2,3 ..., L, pipe Qb_kGrid be connected to the input G of reading circuit through variable threshold circuit_rdij, variable threshold type PMOS Qb_kNew threshold value be tb_k, pipe Qb_kDuring conducting, between source drain, pressure drop is 0；G_rdijReceive the sense bit line output of storage unit circuit, pipe Qb_kSource electrode meet power supply V_dc, choose V_dcVoltage equal to write circuit input and reading circuit output largest logical level V_DinjAnd V (L)_Douj(L)；Use L-1 diode Db_n, n=2,3 ..., L, diode Db_nConducting voltage be V_Don；Db_nPositive pole and negative pole connect variable threshold type PMOS Qb respectively_n-1Drain electrode and pipe Qb_nDrain electrode；Variable threshold type PMOS Qb_LDrain electrode through constant-current source I_jGround connection, pipe Qb_LDrain electrode meet constant-current source I_jThe electric current flowing through conducting diode keeps same fixed value, at pipe Qb_LDrain electrode formed reading circuit output D_outj；Choose tb_kG is inputted for reading circuit_rdijAdjacent logic levels V of K value signal_Grdij(k) and V_Grdij(k-1) meansigma methods (V_Grdij(k)+V_Grdij(k-1))/2, i.e. tb_kFor V_Grdij(k) and V_Grdij(k-1) intermediate value, V_Grdij(k) ＞ V_Grdij(k-1)；Reading circuit output D_outjSignal and write circuit input D_injAnd the specification of DRAM input and output etc. the characteristic of K value signal of ladder be identical: input D_injThe difference of each adjacent logic levels is equal, exports D_outjThe difference of each adjacent logic levels is equal, and input D_injWith output D_outjStepped-up voltage identical, stepped-up voltage is V_Don, namely meet V_Dinj(m)-V_Dinj(m-1)=V_Doutj(m)-V_Doutj(m-1)=V_Don, m=1,2,3 ..., L, V_Dinj(m) and V_DoutjM () is that write circuit inputs and reading circuit output logical value is the logic level of m respectively；Reading circuit input G_rdijThe nonstandard K value signal from storage unit circuit output, described nonstandard K value signal be exactly contrast DRAM input and output and write circuit input and reading circuit output specification etc. the K value signal of ladder be that logic level amplitude is inconsistent；Reading circuit output D_outjFor the K value signal waiting ladder of specification, i.e. reading circuit, nonstandard K value signal is inputted G_rdijBe converted to the K value signal output D waiting ladder of specification_outj, this K value reading circuit is also called K value and reads correcting circuit；Use L-1 diode Da_n, n=2,3 ..., L, diode Da_nConducting voltage be V_Don；Da_nPositive pole and negative pole be connected respectively to variable threshold type PMOS Qa_n-1Drain electrode and pipe Qa_nDrain electrode；Pipe Qa_LDrain electrode through constant-current source I_jGround connection, pipe Qa_LDrain electrode meet constant-current source I_jThe electric current flowing through conducting diode keeps same fixed value, at pipe Qa_LDrain electrode formed write circuit output G_wrij, write circuit output G_wrijReceive the write bit line input of storage unit circuit；Choose ta_kD is inputted for write circuit_injAdjacent logic levels V of K value signal_Dinj(k) and V_Dinj(k-1) meansigma methods (V_Dinj(k)+V_Dinj(k-1))/2, i.e. ta_kFor V_Dinj(k) and V_Dinj(k-1) intermediate value, V_Dinj(k) ＞ V_Dinj(k-1)；Write circuit input D_injK value signal and reading circuit output D_outjAnd the specification of DRAM input and output etc. the characteristic of K value signal of ladder be identical: input D_injThe difference of each adjacent logic levels is equal, exports D_outjThe difference of each adjacent logic levels is equal, and input D_injWith output D_outjStepped-up voltage identical, stepped-up voltage is V_Don, namely meet V_Dinj(m)-V_Dinj(m-1)=V_Doutj(m)-V_Doutj(m-1)=V_Don, m=1,2,3 ..., L, V_Dinj(m) and V_DoutjM () is that write circuit inputs and reading circuit output logical value is the logic level of m respectively；The output G of write circuit_wrijThe ratio high △ of K value signal of write circuit input in addition to 0 level, 0 level is still 0, and this K value write circuit is also called K value write attack circuit；

Wherein, the first PMOS variable threshold circuit is by NMOS tube Q₃, PMOS Q₄With resistance R₃Composition, pipe Q₃Grid meet input voltage V_x, pipe Q₄Grid meet reference voltage V_ref, pipe Q₃Drain electrode be this circuit export V_out1, export V_out1Accept control PMOS Q_T1；Change reference voltage V_ref, make Q_T1New threshold value change；Meet the pipe Q of PMOS variable threshold circuit_T1It is referred to as variable threshold type PMOS；If V_dd＞ V_d≥V_tn+∣V_tp, V_dd-V_d≥∣V_tp∣+V_tn, remember V_extn1=V_ref+V_tn+∣V_tp, V_refIt is respectively V for reference voltage, NMOS and PMOS threshold voltage_tn＞ 0 and V_tp＜ 0；Pipe Q₃And Q₄Grid source potential difference is respectively V_gs3And V_gs4, because Q₃And Q₄Two source electrodes connect, Q₃Drain electrode through resistance R₃Meet power supply V_dd, Q₄Grounded drain, only work as Q₃And Q₄The poor V of two grid voltages_g3-V_g4≥V_tn+∣V_tpTime, pipe Q₃And Q₄Just simultaneously turn on, end the most simultaneously, because of V_g3=V_x, V_g4=V_ref, it follows that: 1. work as V_x-V_ref=V_g3-V_g4≥V_tn+∣V_tp, i.e. input voltage V_x≥V_ref+V_tn+∣V_tp=V_extn1Time, pipe Q₃And Q₄Conducting, resistance R₃On voltage V_out1For the lowest, make Q_T1Conducting；2. V is worked as_x＜ V_extn1Time, Q₃And Q₄Cut-off, V_out1=V_dd, make Q_T1Cut-off；Show, after this variable threshold circuit, to make Q_T1Become V_x≥V_extn1Time conducting, or variable threshold type PMOS Q_T1New threshold value t size become V_extn1, i.e. t=V_extn1, change reference voltage V_ref, make t change, open character and change: Q_T1Become V_xTurn on during >=t；Because of V_dd≥V_ref>=0, t=V_extn1Minima is V_tn+∣V_tp, the first PMOS variable threshold circuit can not realize t less than V_tn+∣V_tpNew threshold value, less t also needs with the second PMOS variable threshold circuit realiration；

The second PMOS variable threshold circuit is by NMOS tube Q₃, PMOS Q₄, resistance R₃Forming with CMOS inverter, CMOS inverter includes PMOS Q₅With NMOS tube Q₆, wherein pipe Q₄Grid meet input voltage V_x, pipe Q₃Grid meet reference voltage V_ref, pipe Q₃Drain electrode connect CMOS inverter input, CMOS inverter input be connected adapter Q₅With pipe Q₆Grid, CMOS inverter be output as this circuit output V_out0, CMOS inverter exports the pipe Q being connected₅With pipe Q₆Drain electrode；Output V_out0Accept control PMOS Q_T0；Change reference voltage V_ref, make Q_T0New threshold value change；Meet the pipe Q of PMOS variable threshold circuit_T0It is referred to as variable threshold type PMOS；If V_dd＞ V_d≥V_tn+∣V_tp, V_dd-V_d≥∣V_tp∣+V_tn, remember V_extn0=V_ref-V_tn-V_tp, NMOS and PMOS variable threshold threshold voltage are respectively V_tn＞ 0 and V_tp＜ 0；Pipe Q₃And Q₄Grid source potential difference is respectively V_gs3And V_gs4, ibid reason, only work as Q₃And Q₄The poor V of two grid voltages_g3-V_g4≥V_tn+∣V_tpTime, pipe Q₃And Q₄Just simultaneously turn on, otherwise V_g3-V_g4＜ V_tn+∣V_tp, pipe Q₃And Q₄End simultaneously；Because of V_g3=V_ref, V_g4=V_x, it follows that: 1. work as V_ref-V_x=V_g3-V_g4＜ V_tn+∣V_tp, pipe Q₃And Q₄Cut-off, i.e. input voltage V_x＞ V_ref-V_tn-V_tp=V_extn0Time, pipe Q₃And Q₄Cut-off, pipe Q₃Drain electrode, i.e. CMOS inverter input is for V_dd, then pipe Q₅Cut-off and pipe Q₆Conducting, CMOS inverter output V_out0=V_d, make Q_T0Conducting；2. V is worked as_x≥V_extn0Time, Q₃And Q₄Conducting, pipe Q₃Drain electrode, i.e. CMOS inverter input for the lowest, then pipe Q₆Cut-off and pipe Q₅Conducting, CMOS inverter output V_out0=V_dd, make Q_T0Cut-off；Show, after variable threshold circuit, to make Q_T0Become V_x≥V_extn0Time conducting, i.e. t=V_extn0；Wherein t=V_extn0=V_ref-V_tn-V_tpLess than V_tn+∣V_tp, show variable threshold type PMOS Q_T0New threshold value t size become V_extn0, i.e. t=V_extn0；Change reference voltage V_ref, make t change, open character and change: Q_T0Become V_xTurn on during >=t, because of V_dd≥V_ref>=0, new threshold value t minima is 0, and maximum is V_dd-V_tn-V_tp∣；

Change reference voltage V_ref, make t change, the first PMOS variable threshold circuit, it is impossible to realize less than V_tn+∣V_tpNew threshold value t, the second PMOS variable threshold circuit can not realize more than V_dd-V_tn-V_tpNew threshold value t, often need to two kinds of PMOS variable threshold circuit with the use of；By V_ddChange V into_dc, it is impossible to realize less than V_tn+∣V_tpNew threshold value t, it is impossible to realize more than V_dc-V_tn-V_tpNew threshold value t, the most often need to these two kinds of PMOS variable threshold circuit with the use of；

For obtaining a sequence difference reference voltage V_ref, the bleeder circuit at the indirect multiple resistant series of DC source and ground realizes, or the bleeder circuit connected at the indirect multiple diodes of DC source and ground or field-effect diode realizes.

The identical architectural feature of a kind of write circuit according to any K value DRAM described in claim 1 the most according to claim 2 and the reading circuit of any K value DRAM that formed, it is characterized in that: take K=8, draw the reading circuit of 8 values DRAM, wherein use 7 variable threshold type PMOS Qb_k, k=1,2,3 ..., 7, pipe Qb_kGrid be connected to the input G of reading circuit through variable threshold circuit_rdij, variable threshold type PMOS Qb_kNew threshold value be tb_k；Pipe Qb_kDuring conducting, between source drain, pressure drop is 0；G_rdijReceive the sense bit line output of storage unit circuit, pipe Qb_kSource electrode meet power supply V_dc, choose V_dcVoltage equal to write circuit input and reading circuit output largest logical level V_DinjAnd V (7)_Douj(7)；Use 6 diode Db_n, n=2,3 ..., 7, diode Db_nConducting voltage be V_Don；Db_nPositive pole and negative pole connect variable threshold type PMOS Qb respectively_n-1Drain electrode and pipe Qb_nDrain electrode；Variable threshold type PMOS Qb₇Drain electrode through constant-current source I_jGround connection, pipe Qb₇Drain electrode meet constant-current source I_jThe electric current flowing through conducting diode keeps same fixed value, at pipe Qb₇Drain electrode formed reading circuit output D_outj；Choose tb_kG is inputted for reading circuit_rdijAdjacent logic levels V of 8 value signals_Grdij(k) and V_Grdij(k-1) meansigma methods (V_Grdij(k)+V_Grdij(k-1))/2, i.e. choose tb_kFor V_Grdij(k) and V_Grdij(k-1) intermediate value, V_Grdij(k) ＞ V_Grdij(k-1)；Reading circuit output D_outjSignal and write circuit input D_injAnd the specification of DRAM input and output etc. the characteristic of 8 value signals of ladder be identical: input D_injThe difference of each adjacent logic levels is equal, exports D_outjThe difference of each adjacent logic levels is equal, and input D_injWith output D_outjStepped-up voltage identical, stepped-up voltage is V_Don, i.e. meet V_Dinj(m)-V_Dinj(m-1)=V_Doutj(m)-V_Doutj(m-1)=V_Don, m=1,2,3 ..., 7, V_Dinj(m) and V_DoutjM () is that write circuit inputs and reading circuit output logical value is the logic level of m respectively；Reading circuit input G_rdijNonstandard 8 value signals from storage unit circuit output, described nonstandard 8 value signals be exactly contrast DRAM input and output and write circuit input and reading circuit output specification etc. 8 value signals of ladder be that logic level amplitude is inconsistent；Reading circuit output D_outjFor 8 value signals waiting ladder of specification, i.e. reading circuit is by nonstandard 8 value signal G_rdijBe converted to the 8 value signal D waiting ladder of specification_outj, this 8 value reading circuit is also called 8 values and reads correcting circuit.