CN111667863A - 1-3 line three-value decoder circuit based on memristor - Google Patents
1-3 line three-value decoder circuit based on memristor Download PDFInfo
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- CN111667863A CN111667863A CN202010567474.XA CN202010567474A CN111667863A CN 111667863 A CN111667863 A CN 111667863A CN 202010567474 A CN202010567474 A CN 202010567474A CN 111667863 A CN111667863 A CN 111667863A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/418—Address circuits
Abstract
The invention discloses a 1-3 line three-value decoder circuit based on a memristor. The invention comprises a positive polarity ternary inverter, two negative polarity ternary inverters and a ternary NOR gate. The input end of the decoder circuit is respectively connected with the input end of the positive polarity ternary phase inverter and the input end of the first negative polarity ternary phase inverter, and the output end of the positive polarity ternary phase inverter is connected with the input end of the second negative polarity ternary phase inverter. The output end of the first negative polarity three-valued inverter is used as the first output end of the three-valued decoder circuit and one input end of the three-valued NOR gate, the output end of the second negative polarity three-valued inverter is used as the second output end of the three-valued decoder circuit and the other input end of the three-valued NOR gate, and the output end of the three-valued NOR gate is used as the third output end of the three-valued decoder circuit. The invention has clear and simple structure and easy realization, can be used for application research in various fields such as multi-value digital logic operation and the like, and has important significance.
Description
Technical Field
The invention belongs to the technical field of circuit design, relates to a three-value digital logic gate circuit, and particularly relates to a 1-3-line three-value decoder circuit design and implementation based on memristors, which are physically realized.
Background
In 1971, the chinese scientist chua hall professor first proposed the concept of memristors, in 2008, hewlett packard research team successfully made nano memristive devices, confirmed the inference of chua hall professor, and further research found that the nonvolatile and nanoscale dimensions of the memristors contributed to the continuation of moore's law, enabling the memristors to be simultaneously calculated and stored.
The unique characteristics of memristors make them have good application prospects in analog circuit design, non-volatile storage, neural networks, digital logic, and the like, as transistors reach physical limits, the tiny size of the memristor's switching behavior is generalized as a replacement device for transistor-based memories.
Conventional digital systems are built on binary numbers, where only logical 0's and 1's are considered. Recently, the concept of multivalued logic became a common research topic, and in 1840, Thomas Fowler in England constructed an early computer using wood in a balanced ternary design. In 1958, the first digital electronic ternary computer Setun was built by Nikolay Brusensov at the national university of Susan Mosco, which is more advantageous than the binary computer in future developments. The main advantage of a ternary number is that it can carry a larger amount of information than a binary number can at the same number of bits, which reduces the complexity of the interconnect and chip area. With the progress of the component manufacturing technology, the possibility is provided for the realization of the ternary logic circuit. In the 80's of the 20 th century, the first three-valued logic gate implementation was introduced based on CMOS using enhancement and depletion transistors. Ternary logic circuits are not only faster and more reliable than binary logic circuits, but also reduce area and interconnect complexity and require less device power consumption.
A memristor is a good candidate for implementing a ternary system because it can handle more than two states without using additional hardware, and can be further divided into different quantization levels to multi-level elements. Practical memristors are compatible with standard CMOS technology, the size of the memristors is relatively small within the range of 2-10nm, and new opportunities are opened up for enhancing novel functions by using the memristors to realize ternary logic operation.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a novel 1-3 line three-value decoder circuit based on memristors.
The technical scheme adopted by the invention for solving the technical problem is as follows:
the invention comprises a positive polarity ternary inverter, two negative polarity ternary inverters and a ternary NOR gate.
The input end of the decoder circuit is respectively connected with the input end of the positive polarity ternary phase inverter and the input end of the first negative polarity ternary phase inverter, and the output end of the positive polarity ternary phase inverter is connected with the input end of the second negative polarity ternary phase inverter.
The output end of the first negative polarity three-valued inverter is used as the first output end of the three-valued decoder circuit and one input end of the three-valued NOR gate, the output end of the second negative polarity three-valued inverter is used as the second output end of the three-valued decoder circuit and the other input end of the three-valued NOR gate, the output end of the three-valued NOR gate is used as the third output end of the three-valued decoder circuit, and the input ends and the three output ends follow the following relations:
when the input end is logic 0, only the first output end of the output is high level, corresponding to logic 2, and the other two output ends are logic 0;
when the input end is logic 1, only the third output end of the output is high level, corresponding to logic 2, and the other two output ends are logic 0;
when the input end is logic 2, only the second output end of the output is high level, corresponding to logic 2, and the other two output ends are logic 0.
The three-value NOR gate consists of a three-value OR gate and a three-value NOR gate, wherein for the three-value NOR gate, the NOT of 0 is 2, the NOT of 1 is 1, the NOT of 2 is 0, and for the three-value NOR gate, the output is the maximum value of two inputs.
The positive-polarity ternary phase inverter and the negative-polarity ternary phase inverter are composed of an NMOS (N-channel metal oxide semiconductor) tube and a memristor, wherein the grid electrode of the NMOS tube is used as the input end of the ternary phase inverter, the source electrode of the NMOS tube is grounded, the drain electrode of the NMOS tube and the positive electrode of the memristor are used as the output end of the ternary phase inverter, and the negative electrode of the memristor and a power supply VCCAnd connecting, wherein the threshold conducting voltage of the NMOS tube in the positive polarity ternary phase inverter is different from the threshold conducting voltage of the NMOS tube in the negative polarity ternary phase inverter.
The invention designs a novel 1-3 line three-value decoder circuit model based on memristors, and the circuit model is clear and simple in structure and easy to implement. The circuit model can be applied to research in multiple fields such as multi-value digital logic operation and the like, and has important significance.
Drawings
FIG. 1a is a memristor-based PTI gate of the present disclosure;
FIG. 1b is a corresponding circuit symbol of FIG. 1 a;
FIG. 2a is a memristor NTI-based gate of the present invention;
FIG. 2b is a corresponding circuit symbol of FIG. 2 a;
FIG. 3 is a block diagram of a memristor-based 1-3-line three-valued decoder circuit of the present disclosure;
FIG. 4 is a circuit schematic of a memristor-based 1-3-line ternary decoder of the present disclosure.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
The circuit block diagram of the 1-3 line three-value decoder circuit model based on the memristor is shown in fig. 3 and is composed of a PTI, two NTIs and a three-value NOR gate, and the circuit model is realized by utilizing the switching characteristic and the memory characteristic of the memristor.
The logic states in the 1-3 line ternary decoder circuit are voltage values, wherein a voltage V is definedCCIs 2V, corresponding to logic 2, voltage VCCAnd/2, 1V corresponds to logic 1, GND is 0V, and corresponds to logic 0. For the three values PTI and NTI, the corresponding truth tables are shown in the following table:
| IN | PTI | NTI |
| 0 | 2 | 2 |
| 1 | 2 | 0 |
| 2 | 0 | 0 |
the circuit shown in fig. 1a can be constructed from the truth table of PTI, and fig. 1b is its corresponding circuit symbol. The threshold turn-on voltage of the first NMOS transistor N1 is 1.5V. The input end of the first memristor M1 is connected with a grid (G1) of a first NMOS transistor N1, a source (S1) is grounded, a drain (D1) is connected with the anode of the first memristor M1, and the cathode of the first memristor M3538 is connected with a power supply VCCAre connected. The voltage of the positive electrode of the first memristor M1 is the output PTI.
When the input end IN is grounded, namely corresponding to the input logic 0, since 0V is smaller than the threshold turn-on voltage of the NMOS tube N1, the NMOS tube N1 is cut off, and the output end is connected to V through a pull-up resistor formed by a memristor M1CCThen the output node voltage is also VCCCorresponding to logic 2.
When the input end IN is connected with VCCAt/2, i.e. corresponding to input logic 1, since VCCThe/2 is smaller than the threshold turn-on voltage of the NMOS transistor N1, so that the NMOS transistor N1 is turned off, and the output end is connected to the V through a pull-up resistor formed by a memristor M1CCThen the output node voltage is also VCCCorresponding to logic 2.
When the input end IN is connected with VCCWhen, i.e. corresponding to input logic 2, since VCCGreater than the threshold turn-on voltage of NMOS transistor N1, and therefore NMOS transistor N1 is turned on. At this time, the current is from the topThe current flows into the negative pole and flows out of the positive pole of the memristor through the memristor M1, so that the resistance value of the memristor M1 is increased to ROFFTherefore, the voltage at the output terminal is 0V, corresponding to logic 0.
The circuit shown in fig. 2a can be constructed according to the truth table of NTI, and fig. 2b is the corresponding circuit symbol. The threshold turn-on voltage of the second NMOS transistor N2 is 0.5V. The input end of the first memristor M2 is connected with the grid (G2) of the second NMOS transistor N2, the source (S2) is grounded, the drain (D2) is connected with the anode of the second memristor M2, and the cathode of the second memristor M3538 is connected with the power supply VCCAnd the voltage of the positive electrode of the second memristor M2 is the output NTI.
When the input end IN is grounded, namely corresponding to the input logic 0, 0V is smaller than the threshold turn-on voltage of the NMOS tube N2, so that the NMOS tube N2 is cut off, and the output end is connected to V through a pull-up resistor formed by a memristor M2CCThen the output node voltage is also VCCCorresponding to logic 2.
When the input end IN is connected with VCCAt/2, i.e. corresponding to input logic 1, since VCCThe/2 is larger than the threshold turn-on voltage of the NMOS transistor N2, so that the NMOS transistor N2 is turned on. At this time, the current flows through the memristor M2 from top to bottom, and the resistance value of the memristor M2 is increased to R since the current flows in from the negative electrode and flows out from the positive electrode of the memristorOFFTherefore, the voltage at the output terminal is 0V, corresponding to logic 0.
When the input end IN is connected with VCCWhen, i.e. corresponding to input logic 2, since VCCGreater than the threshold turn-on voltage of NMOS transistor N2, and therefore NMOS transistor N2 is turned on. At this time, the current flows through the memristor M2 from top to bottom, and the resistance value of the memristor M2 is increased to R since the current flows in from the negative electrode and flows out from the positive electrode of the memristorOFFTherefore, the voltage at the output terminal is 0V, corresponding to logic 0.
For a 1-3 line three-value decoder circuit based on memristors, the circuit structure is a 1-input and 3-output circuit, and the corresponding truth table is shown in the following table:
when the input X is logic 0, only X0 (the first output terminal) is high, corresponding to logic 2, and the rest of X1 and X2 are logic 0.
When the input X is logic 1, only X1 (the third output terminal) is high, corresponding to logic 2, and the rest of X0 and X2 are logic 0.
When the input X is logic 2, only X2 (the second output terminal) is high, corresponding to logic 2, and the rest of X0 and X1 are logic 0.
According to the above input/output logic relationship, a circuit block diagram can be designed as shown in fig. 3.
When the input X is logic 0, the upper PTI results in an output of logic 2, and then the upper NTI outputs X2 as logic 0. The output X0 of the input X through the following NTI is logic 2. The outputs X2 and X0 pass through a nor gate, resulting in an output X1 of logic 0.
When the input X is logic 1, the upper PTI results in an output of logic 2, and then the upper NTI outputs X2 as logic 0. The output X0 of the input X through the following NTI is logic 0. The outputs X2 and X0 pass through a nor gate, resulting in an output X1 of logic 2.
When the input X is logic 2, the upper PTI results in an output of logic 0, and then the upper NTI outputs X2 as logic 2. The output X0 of the input X through the following NTI is logic 0. The outputs X2 and X0 pass through a nor gate, resulting in an output X1 of logic 0.
For a memristor-based 1-3-line three-valued decoder circuit, as shown in fig. 4, specifically, a third memristor M3 and a third NMOS transistor N3 constitute one PTI. The fourth memristor M4 and the fourth NMOS transistor N4 form an NTI. The fifth memristor M5 and the fifth NMOS transistor N5 constitute another NTI. The sixth memristor M6 and the seventh memristor M7 become an or gate TOR in a three-valued nor gate. The eighth memristor M8, the ninth memristor M9, the sixth NMOS transistor N6 and the seventh NMOS transistor N7 form a NOT gate TI in a three-value NOR gate.
The input terminal X is connected to the gate (G3) of the third NMOS transistor N3 and the gate (G5) of the fifth NMOS transistor N5. Negative pole and power supply V of third memristor M3CCAre connected. The anode of the third memristor M3 is connected with the drain (D3) of the third NMOS transistor N3 and the gate (G4) of the fourth NMOS transistorAnd (6) connecting. The source (S3) of the third NMOS transistor N3 is grounded. Negative pole and power supply V of fourth memristor M4CCAre connected. The source (S4) of the fourth NMOS transistor N4 is grounded. The positive electrode of the fourth memristor M4 is connected with the drain (D4) of the fourth NMOS transistor N4, and the output is X2.
Negative pole and power supply V of fifth memristor M5CCAre connected. The source (S5) of the fifth NMOS transistor N5 is grounded. The positive electrode of the fifth memristor M5 is connected with the drain (D5) of the fifth NMOS transistor N5, and the output is X0.
The positive electrode of the sixth memristor M6 is connected with the positive electrode of the fourth memristor M4, and the positive electrode of the seventh memristor M7 is connected with the positive electrode of the fifth memristor M5. The negative electrode of the sixth memristor M6, the negative electrode of the seventh memristor M7, the gate (G6) of the sixth NMOS transistor N6 and the gate (G7) of the seventh NMOS transistor N7 are connected. Eighth memristor M8 cathode and power supply VCCThe positive electrode of the eighth memristor M8 is connected to the drain (D6) of the sixth NMOS transistor N6. The source (S6) of the sixth NMOS transistor N6 is connected to the cathode of the ninth memristor M9 and the drain (D7) of the seventh NMOS transistor N7. The positive electrode of the ninth memristor M9 is grounded. The source (S7) of the seventh NMOS transistor N7 is grounded. The voltage corresponding to the drain (D6) of the sixth NMOS transistor is the output X1.
It should be appreciated by those skilled in the art that the above embodiments are only used for verifying the present invention, and are not to be construed as limiting the present invention, and that the changes and modifications of the above embodiments are within the scope of the present invention.
Claims (1)
1. 1-3 line ternary decoder circuit based on memristor, including a positive polarity ternary inverter, two negative polarity ternary inverters and a ternary NOR gate, its characterized in that:
the input end of the decoder circuit is respectively connected with the input end of the positive polarity ternary phase inverter and the input end of the first negative polarity ternary phase inverter, and the output end of the positive polarity ternary phase inverter is connected with the input end of the second negative polarity ternary phase inverter;
the output end of the first negative polarity three-valued inverter is used as the first output end of the three-valued decoder circuit and one input end of the three-valued NOR gate, the output end of the second negative polarity three-valued inverter is used as the second output end of the three-valued decoder circuit and the other input end of the three-valued NOR gate, the output end of the three-valued NOR gate is used as the third output end of the three-valued decoder circuit, and the input ends and the three output ends follow the following relations:
when the input end is logic 0, only the first output end of the output is high level, corresponding to logic 2, and the other two output ends are logic 0;
when the input end is logic 1, only the third output end of the output is high level, corresponding to logic 2, and the other two output ends are logic 0;
when the input end is logic 2, only the second output end of the output is high level, corresponding to logic 2, and the other two output ends are logic 0;
the three-value NOR gate consists of a three-value OR gate and a three-value NOR gate, wherein for the three-value NOR gate, the NOT logic of 0 is 2, the NOT logic of 1 is 1, the NOT logic of 2 is 0, and for the three-value NOR gate, the output is the maximum value of two inputs;
the positive-polarity ternary phase inverter and the negative-polarity ternary phase inverter are composed of an NMOS (N-channel metal oxide semiconductor) tube and a memristor, wherein the grid electrode of the NMOS tube is used as the input end of the ternary phase inverter, the source electrode of the NMOS tube is grounded, the drain electrode of the NMOS tube and the positive electrode of the memristor are used as the output end of the ternary phase inverter, and the negative electrode of the memristor and a power supply VCCAnd connecting, wherein the threshold conducting voltage of the NMOS tube in the positive polarity ternary phase inverter is different from the threshold conducting voltage of the NMOS tube in the negative polarity ternary phase inverter.
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Cited By (2)
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| CN112332813A (en) * | 2020-11-17 | 2021-02-05 | 杭州电子科技大学 | CMOS mixed type edge memristor D trigger circuit with asynchronous setting and resetting |
| CN113810043A (en) * | 2021-09-03 | 2021-12-17 | 杭州电子科技大学 | Balance three-value decoder circuit based on memristor |
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