CN103117080B - Reading circuit - Google Patents
Reading circuit Download PDFInfo
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- CN103117080B CN103117080B CN201310041874.7A CN201310041874A CN103117080B CN 103117080 B CN103117080 B CN 103117080B CN 201310041874 A CN201310041874 A CN 201310041874A CN 103117080 B CN103117080 B CN 103117080B
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Abstract
The invention discloses a kind of reading circuit, exported for the information of memory cell to be amplified, it includes reference arm mirror-image constant flow source, reference memory unit, decoding control circuit, transmission circuit and output circuit, wherein, the reference arm mirror-image constant flow source includes first with reference to pipe, second with reference to pipe and voltage isolation circuit, the voltage isolation circuit is connected between the grid of the first reference pipe and drain electrode, for by this first with reference to pipe grid leak separate in favor of improve this first refer to pipe saturation conduction, the present invention is separated the grid leak of the first reference pipe to improve first with reference to pipe saturation conduction by accessing a voltage isolation circuit between referring to pipe in reference arm mirror-image constant flow source, so that the present invention is suitably adapted for working during low-voltage such as less than 1.2V, extend the read-out voltage of flash memory.
Description
Technical field
The present invention is on a kind of reading circuit, more particularly to a kind of reading circuit for semiconductor memery circuit.
Background technology
Semiconductor memory is typically considered very important part in digital integrated electronic circuit, and they are for building
Application system based on microprocessor plays vital effect.People are embedding by various memories more and more in recent years
Enter handle its inside, so as to make processor have higher integrated level and faster operating rate, therefore memory array and
The performance of its peripheral circuit just largely determines the working condition of whole system, including speed, power consumption etc..
Mostly important in the various peripheral components of semiconductor memory is exactly reading circuit.Because reading circuit is usual
It is used to the tiny signal when carrying out read operation to memory cell on sampling bit line to change and be amplified, so that it is determined that accordingly
The storage information of memory cell, therefore reading circuit has conclusive influence for the store access time.
Fig. 1 is the circuit diagram of typical reading circuit in the prior art.As shown in figure 1, the reading circuit includes：Ginseng
Examine Mirroring of tributary constant-current source 101, reference memory unit 102, decoding control circuit 103, transmission circuit 104 and output circuit
105, wherein reference arm mirror-image constant flow source 101 includes PMOS P1/P2, and to provide power supply, reference memory unit 102 includes
NMOS tube N1 and 1-4 gate interconnection NMOS tube, N1 grids are connected to N1 source electrodes by a phase inverter INV1, and N1 source electrodes pass through
The NMOS tube of 1-4 gate interconnection is connected with multiple connection wordline WL reference memory unit Cellj (j is, for example, 4 or 8), translates
The one end of code control circuit 103 connects transmission circuit 104, and the other end connects memory cell Cell, and it is connected by three source and drain forms
Nmos pass transistor N2, N3 and N4 composition of series connection, NMOS tube N2-N4 grids difference connection control signal YA, YB and YC, this
Sample, when accessing memory cell Cell, YA/YB/YC puts high level, and NMOS tube N2-N4 is connected, and location information can pass through
Decoding control circuit 103 and transmission circuit 104 are formed at C points；Transmission circuit 104 includes a NMOS tube N5 and phase inverter INV2,
NMOS tube N5 drain electrodes connect P2 drain electrodes, phase inverter INV2 are met between grid and source electrode, and be connected to decoding control circuit 103；Output electricity
Road 105 includes a comparator CMP1 and a phase inverter INV3, comparator CMP1 positive input termination P2 drain electrodes, negative input termination one
Reference voltage Vref, output end connects phase inverter INV3 input, phase inverter INV3 output location informations Soutb.
The reading circuit of prior art also but has the disadvantage that：In the prior art, node A is connected with B, works as electricity
During the voltage reduction of source, in order to ensure that P1 pipes are operated in saturation region, A points are also decreased, and because A points at least compare supply voltage
A low threshold voltage, so when supply voltage as little as certain current potential, or due to process drift or due to temperature
Degree reduction, cause P1 threshold voltage than it is larger when, the current potential of A points will become very low, and at this time the current potential of D points is by A
Point determines that phase inverter INV1 input current potential is very low and does not have clamped effect, so on the one hand causes the position of reference unit
Line voltage becomes very low and the electric current of reference unit is diminished, and the missing of another aspect phase inverter INV1 clamping function can cause
Bit line stablizes slack-off, and the two aspects all can decline the speed of reading.
The content of the invention
The problem of influence reading rate existed for the reading circuit for overcoming above-mentioned prior art, the main object of the present invention exists
In providing a kind of reading circuit, it, will by accessing a voltage isolation circuit between referring to pipe in reference arm mirror-image constant flow source
The grid leak of first reference pipe is separated in favor of while ensureing first with reference to pipe saturation conduction, improving the current potential of A points, so that
It of the invention must be suitably adapted for working during low-voltage such as less than 1.2V, extend the read-out voltage of flash memory.
In view of the above and other objects, the present invention proposes a kind of reading circuit, for the information amplification of memory cell is defeated
Go out, including reference arm mirror-image constant flow source, reference memory unit, decoding control circuit, transmission circuit and output circuit, wherein,
The reference arm mirror-image constant flow source includes first with reference to pipe, second with reference to pipe and voltage isolation circuit, and the voltage isolation circuit connects
Between the grid of the first reference pipe and drain electrode, for the grid leak of the first reference pipe to be separated in favor of in the ginseng of guarantee first
While examining pipe saturation conduction, the current potential of A points is improved.
Further, it is PMOS that first reference, which is managed with the second reference pipe, and the first reference pipe drain electrode connects the reference
Memory cell, the second reference pipe drain electrode connects memory cell by the transmission circuit, the decoding control circuit, while second ginseng
Examine pipe drain electrode and be also connected to the output circuit.
Further, the voltage isolation circuit includes a PMOS, and the PMOS source electrode connects the drain electrode of the first reference pipe, leakage
Pole connects the grid of the first reference pipe.
Further, the voltage isolation circuit also includes the second constant-current source and the 3rd constant-current source, and the PMOS source electrode connects this
The output of second constant-current source, drain electrode connects the output end of the 3rd constant-current source, wherein the electric current of the second constant-current source and the 3rd constant-current source
It is equal.
Further, second constant-current source and the 3rd constant-current source value are 2uA~10uA.
Compared with prior art, a kind of reading circuit of the invention is managed by the first reference in reference arm mirror-image constant flow source
Between access voltage isolation circuit, first is separated in favor of ensureing that first is same with reference to pipe saturation conduction with reference to the grid leak of pipe
When, improve the current potential of A points.I.e. node A voltage is more than the threshold voltage of the first reference pipe, and first leads with reference to pipe in saturation
It is logical, so that the present invention is suitably adapted for working during low-voltage such as less than 1.2V, the read-out voltage of increased flash memory, and can guarantee that reading
Going out circuit can normal work under the aberrations in property caused by various factors.
Brief description of the drawings
Fig. 1 is the circuit diagram of typical reading circuit in the prior art；
Fig. 2 is a kind of circuit structure diagram of the preferred embodiment of reading circuit of the invention.
Embodiment
Below by way of specific instantiation and embodiments of the present invention are described with reference to the drawings, those skilled in the art can
Understand the further advantage and effect of the present invention easily by content disclosed in the present specification.The present invention can also pass through other differences
Instantiation implemented or applied, the various details in this specification also can based on different viewpoints with application, without departing substantially from
Various modifications and change are carried out under the spirit of the present invention.
Fig. 2 is a kind of circuit structure diagram of the preferred embodiment of reading circuit of the invention.As shown in Fig. 2 the bright reading of this law
Going out circuit includes：Reference arm mirror-image constant flow source 201, reference memory unit 202, decoding control circuit 203, transmission circuit 204
And output circuit 205.Wherein reference memory unit 202, decoding control circuit 203 and transmission circuit 204 and output circuit 205
Similarly to the prior art, it will not be described here.
Mirror-image constant flow source 201 is recorded with reference to branch, including first refers to pipe P2 and voltage isolation circuit with reference to pipe P1, second
206, first is PMOS with reference to pipe P2 with reference to pipe P1 and second, and its source electrode is connected to supply voltage Vdd, gate interconnection, first
Reference memory unit 202 is connect with reference to pipe P1 drain electrodes, second passes through transmission circuit 204, decoding control circuit 203 with reference to pipe P2 drain electrodes
Memory cell Cell is met, while P2 drain electrodes are also connected to output circuit 205, voltage isolation circuit 206 is connected to first with reference to pipe P1's
Between grid and drain electrode, for the first reference pipe P1 grid leak to be separated in favor of raising P1 saturation conductions and the wide length of P1 sizes
Than design, in present pre-ferred embodiments, voltage isolation circuit 206 includes a PMOS M1, the second constant-current source I2 and the 3rd
Constant-current source I3, M1 source electrode connects the first reference pipe P1 drain electrode and the second constant-current source I2 output, and its contact is node A, M1 leakage
Pole connects the first reference pipe P1 grid and the 3rd constant-current source I3 output end, and its contact is node B.
In present pre-ferred embodiments, address decoding output YA, YB, YAD, YBD and word line selection signal WL delivers to ginseng
Control pipe NA, the NB conducting of branch road where examining memory cell and selected memory cell, reference memory unit, isolates N pipe N1 source electrodes
It is high after the inverted device of the voltage for low voltage, it is height to promote to isolate N pipes N1 grid, so that with reference to N pipes N1 conductings, ginseng
Mirroring of tributary constant-current source 201 is examined with reference to first with reference to pipe P1 conductings, reference current is produced, reference arm mirror-image constant flow source 201 is defeated
Go out N pipes Vgs and mirror-image constant flow source identical with reference to P pipes P1, so as to export identical or proportional electric current, and selected memory cell
Different electric currents can be produced because of storage content and correspond to different impedances in other words, in the output P pipes of reference arm mirror-image constant flow source 201
(P2) drain electrode forms different voltages, and the output voltage is sent to the in-phase output end of the comparator of sense amplifier, reference circuit
The reference voltage of generation delivers to the inverse output terminal of comparator, so as to be produced and memory cell storage content in comparator output terminal
(the different electron amount of 0 and 1 correspondence) corresponding voltage, buffered rear output obtains the information S of memory cell storageout。
In present pre-ferred embodiments, for P1：
Gate source voltage | Vgs-Vt |=| VB-Vdd-Vth0 |=Vdd-VB- | Vth0 |,
| Vds |=Vdd-VA, Vth0 are P1 threshold voltage.
To ensure that it is interval that P1 is in saturation conduction, it is desirable to：
| Vgs-Vt | ＜ | Vds |
This is equivalent to：
Vdd-VB- | Vth0 | ＜ Vds-VA, i.e.,
VA ＜ VB+ | Vth0 |
In present pre-ferred embodiments, if VA ＜ | Vth1 |, P pipes M1 is not turned on, and node B voltage VB levels off to 0, ginseng
Examine Mirroring of tributary constant-current source 201 not work, now need to improve node A voltage VA, if VA ＞ | Vth1 |, P pipes M1 conductings, section
Point B voltages VB levels off to node A voltage VA, and VA ＜ VB+ can be met easily | Vth0 | condition, and so that reference arm mirror-image constant flow source
201 work.Second electric constant-current source and the 3rd constant current ource electric current are equal, value 2uA~10uA, because the number of reference unit is more
(4 or 8), total current is than larger, generally higher than 150uA, even if there is the second constant-current source and the 3rd constant-current source in design
Mismatch, also do not result in larger error.
It can be seen that, a kind of reading circuit of the invention between the first reference pipe of reference arm mirror-image constant flow source by accessing voltage
Isolation circuit, the first reference pipe P1 grid leak is separated while ensureing first with reference to pipe saturation conduction, to improve A
The current potential of point.I.e. node A voltage is more than the threshold voltage of the first PMOS, and first is in saturation conduction with reference to pipe P1, from
And make it that the present invention is suitably adapted for working during low-voltage such as less than 1.2V, the read-out voltage of increased flash memory, and can guarantee that reading electricity
Road can normal work under the aberrations in property caused by various factors.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.Any
Art personnel can be modified above-described embodiment and changed under the spirit and scope without prejudice to the present invention.Therefore,
The scope of the present invention, should be as listed by claims.
Claims (6)
1. a kind of reading circuit, exported for the information of memory cell to be amplified, including reference arm mirror-image constant flow source, with reference to depositing
Storage unit, decoding control circuit, transmission circuit and output circuit, it is characterised in that：The reference arm mirror-image constant flow source includes the
One is connected to first grid and drain electrode with reference to pipe with reference to pipe, the second reference pipe and voltage isolation circuit, the voltage isolation circuit
Between, for by this first with reference to pipe grid leak separate with ensure this first with reference to pipe saturation conduction while, improve this
The current potential of one reference pipe drain node；The first reference pipe drain electrode connects the reference memory unit, and the second reference pipe drain electrode passes through
The transmission circuit, the decoding control circuit connect memory cell, while the second reference pipe drain electrode is also connected to the output circuit；This
The source electrode of one reference pipe and the second reference pipe is all connected to a supply voltage, gate interconnection.
2. a kind of reading circuit as claimed in claim 1, it is characterised in that：First reference is managed is with the second reference pipe
PMOS.
3. a kind of reading circuit as claimed in claim 2, it is characterised in that：The voltage isolation circuit includes a PMOS, should
PMOS source electrode connects the drain electrode of the first reference pipe, and drain electrode connects the grid of the first reference pipe.
4. a kind of reading circuit as claimed in claim 3, it is characterised in that：The voltage isolation circuit also includes the second constant-current source
And the 3rd constant-current source, the PMOS source electrode connects the output of second constant-current source, and drain electrode connects the output end of the 3rd constant-current source.
5. a kind of reading circuit as claimed in claim 4, it is characterised in that：Second constant-current source and the 3rd constant current ource electric current
It is equal.
6. a kind of reading circuit as claimed in claim 4, it is characterised in that：Second constant-current source and the 3rd constant-current source value
For 2uA~10uA.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310041874.7A CN103117080B (en) | 2013-02-01 | 2013-02-01 | Reading circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310041874.7A CN103117080B (en) | 2013-02-01 | 2013-02-01 | Reading circuit |
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| Publication Number | Publication Date |
|---|---|
| CN103117080A CN103117080A (en) | 2013-05-22 |
| CN103117080B true CN103117080B (en) | 2017-08-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310041874.7A Active CN103117080B (en) | 2013-02-01 | 2013-02-01 | Reading circuit |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20160069146A (en) * | 2014-12-08 | 2016-06-16 | 에스케이하이닉스 주식회사 | Memory device |
| CN105741871B (en) * | 2016-03-11 | 2019-09-06 | 上海华虹宏力半导体制造有限公司 | Sensitive amplifier circuit and memory |
| CN106601278B (en) * | 2016-12-19 | 2019-11-19 | 佛山中科芯蔚科技有限公司 | A kind of sense amplifier |
| TWI708253B (en) * | 2018-11-16 | 2020-10-21 | 力旺電子股份有限公司 | Nonvolatile memory yield improvement and testing method |
| CN110097916B (en) * | 2019-04-30 | 2021-04-02 | 上海华虹宏力半导体制造有限公司 | Memory allowance test circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5134310A (en) * | 1991-01-23 | 1992-07-28 | Ramtron Corporation | Current supply circuit for driving high capacitance load in an integrated circuit |
| CN101800068A (en) * | 2010-03-10 | 2010-08-11 | 上海宏力半导体制造有限公司 | Readout amplifying circuit |
| CN101807422A (en) * | 2010-03-26 | 2010-08-18 | 上海宏力半导体制造有限公司 | Readout amplifying circuit |
-
2013
- 2013-02-01 CN CN201310041874.7A patent/CN103117080B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5134310A (en) * | 1991-01-23 | 1992-07-28 | Ramtron Corporation | Current supply circuit for driving high capacitance load in an integrated circuit |
| CN101800068A (en) * | 2010-03-10 | 2010-08-11 | 上海宏力半导体制造有限公司 | Readout amplifying circuit |
| CN101807422A (en) * | 2010-03-26 | 2010-08-18 | 上海宏力半导体制造有限公司 | Readout amplifying circuit |
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| Publication number | Publication date |
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| CN103117080A (en) | 2013-05-22 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140507 |
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Effective date of registration: 20140507 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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