CN101986389B - Flash memory unit, flash memory device and programming method thereof - Google Patents
Flash memory unit, flash memory device and programming method thereof Download PDFInfo
- Publication number
- CN101986389B CN101986389B CN201010504721.8A CN201010504721A CN101986389B CN 101986389 B CN101986389 B CN 101986389B CN 201010504721 A CN201010504721 A CN 201010504721A CN 101986389 B CN101986389 B CN 101986389B
- Authority
- CN
- China
- Prior art keywords
- bit line
- voltage
- flash memory
- enable signal
- storage unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention discloses a flash memory unit, a flash memory device and a programming method thereof. In the flash memory unit, a word line control grid is arranged between suspension grids of two storage units so that the two storage units can share one word line and the purpose of reducing the area of a chip is fulfilled. In the programming method, a bit line refresh circuit is connected with each bit line of a storage unit array, and the shielding voltage is refreshed during programming, so the shielding voltage is not reduced during programming, and the programming is more accurate and reliable.
Description
Technical field
The present invention about a kind of flash cell, flash memory device and programmed method thereof, particularly about a kind of can the flash cell of shared word line, flash memory device and programmed method thereof.
Background technology
In semiconductor storage, flash memory (flash memory) is a kind of volatile memory, and belongs to Erasable Programmable Read Only Memory EPROM (Erasable Programmable Read-Only Memory, EPROM).The advantage of flash memory is that it can be wiped for whole memory block, and erasing speed is fast, about needs one to two second.Therefore, in recent years, flash memory has applied in various consumption electronic products, such as: digital camera, digital code camera, mobile phone or notebook computer etc.
Generally speaking, flash memory has two grids, a floating grid and a control gate, and wherein floating grid is in order to stored charge, and control gate is then in order to the constrained input of control data.The position of floating grid, under control gate, owing to not being connected with external circuit, is be in floating state.Control gate then usual and wordline (Word Line, WL) connects.The flash memory of this structure is owing to having high programming efficiency, and the structure of wordline also has advantages such as can avoiding " crossing erasing ", is widely used.
In general, when making highdensity semiconductor element on an integrated circuit die, size and power consumption how to reduce each storage unit must be considered as possible, but because the control gate of each storage unit is all connected with a wordline in existing flash memory structure, make chip area larger, be unfavorable for chip design, the size therefore how reducing chip further while improving chip performance is current problem demanding prompt solution.
In sum, the flash memory structure of known prior art is all connected the problem that chip area will be caused to be unfavorable for more greatly chip design with a wordline due to the control gate of each storage unit, therefore, be necessary the technological means proposing to improve in fact, solve this problem.
Summary of the invention
The problem that a wordline will cause chip area to be unfavorable for more greatly chip design is all connected due to each storage unit for what overcome that above-mentioned prior art exists, fundamental purpose of the present invention is to provide a kind of flash memory, it by arranging wordline control gate between the suspended gate of two storage unit, two storage unit share wordline object by this wordline control gate can be reached, reduce chip area, be convenient to chip design.
For reaching above-mentioned and other object, a kind of flash cell of the present invention, at least comprises
Substrate and be formed at the first drain region of substrate, the first source area, the second source area and the second drain region successively;
First bit line and the second bit line, be connected to this first drain region and this second drain region;
First suspended gate and the second suspended gate, be formed at the top of this first source area and this second source area respectively;
First control gate and the second control gate, be formed at the top of this first suspended gate and this second suspended gate respectively; And
Wordline control gate, is formed at this types of flexure, and between this first suspended gate and this second suspended gate.
Further, when carrying out read-write operation to this flash cell, this wordline control gate controls to form raceway groove between this first source area and this second source area.
Comprise a flash memory device for aforementioned flash cell, it comprises:
One memory cell array lining up multirow and multiple row, this memory cell array has many first bit lines, many second bit lines and forms these flash cells multiple of array, often the first control gate of row flash cell, the second control gate and wordline control gate connect together respectively, and often row flash cell is connected with the second bit line with one first bit line respectively;
Bit line refresh circuit, be connected to every bit lines of this memory cell array, the voltage in pairs of bit line during programming refreshes; And
Column selection circuit passband, it is connected with this memory cell array by each bit lines, which data is exported for selecting.
Further, this bit line refresh circuit comprises multiple bit line and refreshes nmos pass transistor, the source electrode that each bit line refreshes nmos pass transistor is connected with every bit lines respectively, one refresh enable signal connects the grid that each bit line refreshes nmos pass transistor, and the drain electrode that each bit line refreshes nmos pass transistor is connected to a secondary shielding voltage.
Further, this refresh enable signal is produced by a refresh enable signal control circuit, this refresh enable signal control circuit comprises logic control circuit and a level displacement shifter of a connection one program enable signal, under the control of this program enable signal, this logic control circuit by generation one low level refresh enable signal to this level displacement shifter, this level displacement shifter is also connected with secondary shielding voltage, produces this refresh enable signal matched with this program voltage.
Further, this flash cell comprises the first storage unit and the second storage unit, and this first bit line is connected to the drain electrode of this first storage unit, and this second bit line is connected to the drain electrode of this second storage unit.
A programmed method for aforementioned flash memory device, comprises the steps:
By all bit line pre-charge to mask voltages;
Except the second bit line that a flash cell after programming unit colleague connects, other all bit lines suspend;
The first bit line connecting this programming unit is charged to a program voltage, and the second bit line of this programming unit column and the first bit line of this programming unit rank rear is connected a constant current source, to obtain a constant low-voltage.
The size of this mask voltage is between this low-voltage and this program voltage.
Further, above-mentioned programmed method also comprises, and during programming, is refreshed this mask voltage by this bit line refresh circuit.
This program voltage representative value is 2.5v-5.5v.
Compared with prior art, the present invention by arranging a wordline control gate between the suspended gate of two storage unit, make two storage unit can share a wordline, reach the object reducing chip area, programmed method of the present invention is refreshed mask voltage during programming by bit line refresh circuit, during making programming, mask voltage can not reduce, and therefore programmes more accurate.
Accompanying drawing explanation
Fig. 1 is a kind of flash memory unit structure schematic diagram of present pre-ferred embodiments;
Fig. 2 is the electrical block diagram of the flash cell of Fig. 1;
Fig. 3 requiredly executes alive situation when being and carrying out " reading " and " writing " operation to the flash cell of Fig. 2;
Fig. 4 is the block scheme that the present invention comprises the flash memory device of Fig. 2 flash cell;
Fig. 5 is the structural representation of memory cell array in Fig. 4
Fig. 6 is refresh enable signal control circuit and sequential chart in the present invention;
Fig. 7 is the circuit diagram that low-voltage produces circuit.
Embodiment
Below by way of specific instantiation and accompanying drawings embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by content disclosed in the present specification.The present invention is also implemented by other different instantiation or is applied, and the every details in this instructions also can based on different viewpoints and application, carries out various modification and change not deviating under spirit of the present invention.
Fig. 1 is a kind of flash memory unit structure schematic diagram of present pre-ferred embodiments.As shown in Figure 1, a kind of flash cell of the present invention, comprising: Semiconductor substrate 10, it has successively the first source area, source area 21, second, drain region 11, first 12 and the second drain region 22; First bit line 14 and the second bit line 15, is connected to the first drain region 11 and the second drain region 22; First suspended gate 16 and the second suspended gate 17, is arranged at the top of the first source area 21 and the second source area 12 respectively, forms the first storage bit unit and the second storage bit unit respectively; First control gate 18 and the second control gate 19, is arranged at the top of the first suspended gate 16 and the second suspended gate 19 respectively; And wordline control gate 20, is positioned at above Semiconductor substrate 10, and between the first suspended gate 16 and the second suspended gate 17, wherein, between each grid and between each grid and Semiconductor substrate 10 by filling insulating material.
Fig. 2 is the electrical block diagram of the flash cell of Fig. 1, wherein BL1 is the first bit line 14, BL2 is the second bit line 15, CG1 is the first control gate 18, CG2 is the second control gate 19, Cell1 is the first storage unit, comprise the first drain region 11, first source area 21, first suspended gate 16 and the first control gate 18, Cell2 is the second storage unit, comprise the second source area 12, second drain region 22, second suspended gate 17 and the second control gate 19, there is between first storage unit Cell1 and the second storage unit wordline control gate 20, wherein, wordline WL connective word line traffic control grid 20.Below the principle of work of cooperation Fig. 3 to flash memory of the present invention is described.
Fig. 3 lists when carrying out " reading " and " writing " operation to the flash cell of Fig. 2 and requiredly executes alive situation, and wherein representative value is V1=0.8-1.6v, V2=0-1v, V3=2-3v, V4=2-6v, V5=5-9v, V6=1-2v, V7=2-6v, Vsp=2.5-5.5v, and Vdp=0.1-0.6v.When carrying out " reading " operation to the first storage unit Cell1 of flash cell, second control gate CG2 applies 2-6v high pressure V4, second bit line BL2 applies 0.8-1.6v voltage V1, no matter the information then on the second storage unit Cell2 second suspended gate why, all can form raceway groove between the drain-source of the second storage unit Cell2 (DS), then the voltage V1 of the second bit line BL2 is sent to the source electrode of the second storage unit Cell2, now wordline WL applies 2-3v high voltage V3, this voltage makes to form raceway groove between the source electrode of two flash cells, therefore the voltage V1 of the second bit line BL2 is sent to the source electrode of the first storage unit Cell1, and now the first control gate CG1 applies 0-1v voltage V2, and the first bit line BL1 ground connection, so can form the electric current relevant to the first suspended gate information between the source and drain of the first storage unit Cell1, typical case is that the first control gate CG1 voltage gets the first suspended gate with or without the threshold voltage mean value of two during information.
And when carrying out " writing " operation to the first storage unit Cell1, because the second control gate CG2 applies 2-6v high pressure V4, second bit line BL2 applies 0.1-0.6v low-voltage Vdp, then the source and drain raceway groove of the second storage unit Cell2 is formed, then the source of the second storage unit Cell2 is low-voltage, now wordline WL gets 1-2v voltage V6 and makes to form raceway groove between the source electrode of two flash cells, and the first control gate CG1 applies 5-9v high pressure V5, this high pressure impels the grid source (GS) of the first storage unit Cell1 breakdown, micro-electric current is by the first suspended gate to the second bit line BL2, the program voltage Vsp applied due to the first bit line BL1 is 2.5-5.5v, it is higher than the low-voltage Vdp of the second bit line BL2, therefore electronics just resides in formation information on the first suspended gate.And to the second storage unit Cell2 " reading " and " writing " operating process and the first storage unit Cell1 similar, be not described in detail in this.
Fig. 4 is the block scheme that the present invention comprises the flash memory device of Fig. 2 flash cell, and Fig. 5 is the structural representation of memory cell array in Fig. 4.Please with reference to Fig. 4 and Fig. 5, a kind of flash memory device of the present invention comprises: memory cell array 310, bit line refresh circuit 320 and column selection circuit passband 330.
Memory cell array 310 is the flash memory cell array lining up multirow and multiple row, it comprises many first bit lines, multiple memory nodes of many second bit lines and formation array, each memory node comprises two flash cells, namely the first storage unit Cell1 in Fig. 2 and the second storage unit Cell2, CG1<m> is the first control gate that m is capable, CG2<m> is the second control gate that m is capable, WL<m> is the wordline that m is capable, CG1<m>, CG2<m> and WL<m> is used by the flash cell of going together mutually, memory node on each row is connected with the second bit line with one first bit line respectively, this first bit line and the second bit line are connected to the drain electrode of the first storage unit Cell1 and the second storage unit Cell2, as shown in Figure 5, arrange for k, BL<k> is the first bit line, BL<k+1> is the second bit line.
When needing to programme to the first storage unit Cell1 of the capable kth row of m, the bit line that this first storage unit Cell1 is adjacent is respectively the first bit line BL<k> and the second bit line BL<k+1>, first, all bit lines (BL<1> to BL<n>) are precharged to a mask voltage Vinh, then, all bit lines are suspended, except the second bit line BL<k+3>, then, first bit line BL<k> is charged to a program voltage Vp, preferred values is between 2.5-5.5v, and the second bit line BL<k+1> is connected a constant current source with the first bit line BL<k+2>, to produce a constant low-voltage Vd, preferred values is between 0.1-0.6v, herein, Vd < Vinh < Vp, a high voltage is applied when giving the second control gate CG2<m>, representative value is as 2-6v, because the second bit line BL<k+1> is low-voltage Vd, then grid leak (GD) high pressure of the second storage unit Cell2 makes drain-source (DS) raceway groove of the second storage unit Cell2 be formed, then the source electrode of the second storage unit Cell2 is low-voltage, now wordline WL<m> applying certain voltage (as 1-2v) makes to form raceway groove (between two source electrodes) between two flash cells (Cell1 and Cell2), and apply a high pressure to the first control gate CG1<m> of the first storage unit Cell1, representative value is 5-9v, this high pressure impels the first storage unit Cell1 breakdown, voltage Vp due to the first bit line BL<k> is greater than the voltage Vp of the second bit line BL<k+1>, then micro-electric current is by suspended gate to the second bit line BL<k+1>, electronics just resides on the suspended gate of the first storage unit Cell1, also the programming to the first storage unit Cell1 is just achieved.
But often owing to there is the leakage of knot, mask voltage Vinh may reduce, this can interfere with is not selected the unit of programming, therefore during programming, often needs to be refreshed mask voltage by bit line refresh circuit.
Bit line refresh circuit 320, be connected to every bit lines of memory cell array 310, it comprises multiple bit line and refreshes nmos pass transistor, the source electrode that each bit line refreshes nmos pass transistor is connected with every bit lines respectively, one refresh enable signal PREBLEN is connected to the grid that all bit lines refresh nmos pass transistor, the drain electrode that each bit line refreshes nmos pass transistor is connected to a secondary shielding voltage Vinh2, when refresh enable signal PREBLEN is high impulse, bit line refreshes nmos pass transistor conducting, voltage on BL<i> (i is 0-n) is refreshed, but due to BL<k>, BL<k+1>, BL<k+2> is by other control circui, BL<k+1> and BL<k+2> is limited to low-voltage Vd, BL<k> is program voltage Vp, because of Vp > Vinh2, therefore the bit line be connected with BL<k> refresh nmos pass transistor drain-source between can not form raceway groove, this bit line refreshes the electric current that NMOS tube can not consume program voltage.
Column selection circuit passband 330, it is connected with memory cell array 310 by each bit lines, for selecting to export which data to sensor amplifier, is also connected with multiple sensor amplifier at the output terminal of column selection circuit passband 330, because this part is conventional circuit design, will not describe in detail at this.
Fig. 6 is refresh enable signal control circuit and sequential chart in the present invention, refresh enable signal control circuit comprises logic control circuit 610 and the level displacement shifter 611 of a connection program enable signal PROGEN, under the control of program enable signal PROGEN, logic control circuit 610 produces a low level refresh enable signal PREBLEN L to level displacement shifter 611, and secondary shielding voltage Vinh2 is another input end of level displacement shifter 611, produce a refresh enable signal PREBLEN matched with program voltage Vp through level displacement shifter 611.
Fig. 7 is the circuit diagram that low-voltage Vd produces circuit, this low-voltage Vd produces circuit and comprises a comparer, a nmos pass transistor and a constant current source, its objective is that generation one is less than the low-voltage Vd of low reference voltage Vdp, this low reference voltage Vdp representative value is between 0.1-0.6v, wherein, low reference voltage Vdp connects comparer negative input end, and low-voltage Vd connects comparer positive input terminal, nmos transistor drain and constant current source respectively.
In sum, the present invention by arranging a wordline control gate between the suspended gate of two storage unit, make two storage unit can share a wordline, reach the object reducing chip area, programmed method of the present invention is refreshed mask voltage during programming by bit line refresh circuit, during making programming, mask voltage can not reduce, and therefore programmes more accurate.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any those skilled in the art all without prejudice under spirit of the present invention and category, can carry out modifying to above-described embodiment and change.Therefore, the scope of the present invention, should listed by claims.
Claims (8)
1. a flash memory device, comprises flash cell, and wherein described in each, flash cell comprises:
Substrate and be formed at the first drain region of substrate, the first source area, the second source area and the second drain region successively;
First bit line and the second bit line, be connected to this first drain region and this second drain region;
First suspended gate and the second suspended gate, be formed at the top of this first source area and this second source area respectively;
First control gate and the second control gate, be formed at the top of this first suspended gate and this second suspended gate respectively; And
Wordline control gate, is formed at this types of flexure, and between this first suspended gate and this second suspended gate;
Described flash memory device also comprises:
Line up the memory cell array of multirow and multiple row, this memory cell array has many first bit lines, many second bit lines and forms these flash cells multiple of array, often the first control gate of row flash cell, the second control gate and wordline control gate connect together respectively, and often row flash cell is connected with the second bit line with one first bit line respectively;
Bit line refresh circuit, be connected to every bit lines of this memory cell array, the voltage in pairs of bit line during programming refreshes; And
Column selection circuit passband, it is connected with this memory cell array by each bit lines, which data is exported for selecting.
2. a kind of flash memory device as claimed in claim 1, it is characterized in that, this bit line refresh circuit comprises multiple bit line and refreshes nmos pass transistor, the source electrode that each bit line refreshes nmos pass transistor is connected with every bit lines respectively, one refresh enable signal connects the grid that each bit line refreshes nmos pass transistor, and the drain electrode that each bit line refreshes nmos pass transistor is connected to a secondary shielding voltage.
3. a kind of flash memory device as claimed in claim 2, it is characterized in that, this refresh enable signal is produced by a refresh enable signal control circuit, this refresh enable signal control circuit comprises logic control circuit and a level displacement shifter of a connection one program enable signal, under the control of this program enable signal, this logic control circuit by generation one low level refresh enable signal to this level displacement shifter, this level displacement shifter is also connected with secondary shielding voltage, produces this refresh enable signal matched with program voltage.
4. a kind of flash memory device as claimed in claim 3, is characterized in that, this flash cell comprises the first storage unit and the second storage unit, and this first bit line is connected to the drain electrode of this first storage unit, and this second bit line is connected to the drain electrode of this second storage unit.
5. a programmed method for flash memory device as claimed in claim 1, comprises the steps:
By all bit line pre-charge to mask voltages;
Except the second bit line that a flash cell after programming unit colleague connects, other all bit lines suspend;
The first bit line connecting this programming unit is charged to a program voltage, and the second bit line of this programming unit column and the first bit line of this programming unit rank rear is all connected a constant current source, to obtain a constant low-voltage.
6. a kind of programmed method as claimed in claim 5, is characterized in that, the size of this mask voltage is between this low-voltage and this program voltage.
7. a kind of programmed method as claimed in claim 6, is characterized in that, this programmed method also comprises, and during programming, is refreshed this mask voltage by this bit line refresh circuit.
8. a kind of programmed method as claimed in claim 7, is characterized in that, this program voltage representative value is 2.5v-5.5v.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010504721.8A CN101986389B (en) | 2010-10-12 | 2010-10-12 | Flash memory unit, flash memory device and programming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010504721.8A CN101986389B (en) | 2010-10-12 | 2010-10-12 | Flash memory unit, flash memory device and programming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101986389A CN101986389A (en) | 2011-03-16 |
| CN101986389B true CN101986389B (en) | 2015-06-24 |
Family
ID=43710732
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010504721.8A Active CN101986389B (en) | 2010-10-12 | 2010-10-12 | Flash memory unit, flash memory device and programming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101986389B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103151356B (en) * | 2013-02-26 | 2017-08-25 | 上海华虹宏力半导体制造有限公司 | A kind of EEPROM memory array structures and its manufacture method |
| CN103871465A (en) * | 2014-03-17 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | Nonvolatile memory and operating method thereof |
| CN105097037A (en) * | 2015-07-17 | 2015-11-25 | 上海华虹宏力半导体制造有限公司 | Reading method of memory device and memory array |
| CN110546708B (en) | 2017-12-15 | 2023-04-21 | 成都锐成芯微科技股份有限公司 | Programming circuit and programming method of flash memory and flash memory |
| CN108492844B (en) * | 2018-03-26 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | Double-split gate flash memory array and programming method thereof |
| CN111489784B (en) * | 2020-04-29 | 2024-02-02 | 上海华虹宏力半导体制造有限公司 | Screening method for embedded flash memory failure |
| CN112365913B (en) | 2020-09-29 | 2021-09-03 | 中天弘宇集成电路有限责任公司 | 3D NAND flash memory programming method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101465161A (en) * | 2008-12-30 | 2009-06-24 | 上海宏力半导体制造有限公司 | Gate-division type flash memory sharing word line |
| CN101640205A (en) * | 2009-08-25 | 2010-02-03 | 上海宏力半导体制造有限公司 | Flash memory |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4050048B2 (en) * | 2000-12-15 | 2008-02-20 | ヘイロ エルエスアイ インコーポレイテッド | Fast switching to fast program and program verification |
| TWI265626B (en) * | 2005-08-19 | 2006-11-01 | Powerchip Semiconductor Corp | Non-volatile memory and manufacturing method and operating method thereof |
-
2010
- 2010-10-12 CN CN201010504721.8A patent/CN101986389B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101465161A (en) * | 2008-12-30 | 2009-06-24 | 上海宏力半导体制造有限公司 | Gate-division type flash memory sharing word line |
| CN101640205A (en) * | 2009-08-25 | 2010-02-03 | 上海宏力半导体制造有限公司 | Flash memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101986389A (en) | 2011-03-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101986389B (en) | Flash memory unit, flash memory device and programming method thereof | |
| CN102314944B (en) | Method for operating semiconductor memory device | |
| CN107204203B (en) | Memory array and reading, programming and erasing operation method thereof | |
| CN107045893B (en) | Circuit for eliminating flash memory programming interference | |
| US8050080B2 (en) | Random access memory with CMOS-compatible nonvolatile storage element in series with storage capacitor | |
| CN102270491B (en) | With the flash memory write circuit that source line voltage compensates | |
| CN103903650B (en) | Memory array and its control method and flash memory | |
| CN102184745B (en) | Flash memory and programmed method thereof | |
| CN102867544A (en) | Method of testing storage array and control device | |
| CN103943138A (en) | Per unit multi-bit storage device | |
| CN104751885A (en) | FLASH chip and erasure or programming method for responding to FLASH chip abnormal power-down | |
| CN101877243B (en) | Static RAM | |
| CN103106922A (en) | Programming method for separating grid memory array | |
| US8913446B2 (en) | Nonvolatile semiconductor memory device | |
| CN103824597A (en) | Memory as well as readout circuit and reading method of memory cell | |
| CN103839586A (en) | Method for regulating erasing voltage of nonvolatile memory | |
| TW200951952A (en) | Random access memory with CMOS-compatible nonvolatile storage element | |
| CN102855930A (en) | Programming control method and apparatus of memory and memory array | |
| CN103811062B (en) | Memory and reading method of memory | |
| CN114005477B (en) | High-reliability common floating gate type Flash memory computing device and array structure | |
| CN106205703B (en) | Memory array and reading, programming and erasing operation method thereof | |
| CN107729586B (en) | EEPROM model circuit, modeling method, simulation method and test structure | |
| CN101866691A (en) | Method for obtaining capacitive coupling rate of flash memory cell | |
| CN116524974A (en) | Memory, time sequence control method and electronic equipment | |
| CN114023364A (en) | Split-gate memory array structure and operation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140516 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20140516 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Zhangjiang hi tech Park No. 818 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |