CN113539327A - Device for realizing rapid logic calculation of phase change memory unit and data retrieval method - Google Patents
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Abstract
The invention relates to a device for realizing rapid logic calculation by a phase change memory cell and a data retrieval method, wherein the device comprises a phase change memory array and a peripheral control circuit, wherein the phase change memory array comprises two phase change memory logic operators; the phase change storage logic operator comprises two phase change storage units, one ends of the two phase change storage units are connected with the same bit line, the other ends of the two phase change storage units are connected with the drain ends of respective gate tubes, the source ends of the gate tubes are grounded, the gate electrode of the gate tube of one phase change storage unit in the phase change storage logic operator is connected with a first word line, and the gate electrode of the gate tube of the other phase change storage unit in the phase change storage logic operator is connected with a second word line; the peripheral control circuit writes initial data information into the phase change memory array, and the gating tube gates the phase change memory unit according to signals on the first word line and the second word line, so that the information stored in the phase change memory unit and the pulse signals on the bit lines perform logic operation. The invention can reduce the data matching calculation amount and realize high-efficiency data retrieval.
Description
Technical Field
The invention relates to the technical field of nonvolatile memory computing, in particular to a device for realizing quick logic computing by a phase change memory unit and a data retrieval method.
Background
With the artificial intelligence of the big data era and the continuous development of the interconnection of everything, data calculation and transmission are more and more frequent. The traditional von neumann computer architecture needs to read data and transmit the data to a computing unit during computation, and returns to a storage unit after computation is completed, so that the computing architecture causes time and power consumption bottlenecks. The memory is also innovated by the explosive increase of data volume, and the phase change memory is a novel nonvolatile memory with excellent performance and leading mass production. The phase change memory is based on chalcogenide compounds, has the advantages of high speed, high density, low power consumption, high reliability, compatibility with a CMOS (complementary metal oxide semiconductor) process and the like, and can realize reversible transformation between a crystalline state and an amorphous state so as to store binary data. The phase change memory is the most potential new memory for the next generation due to its excellent characteristics.
Many students explore an efficient nearest neighbor information retrieval mode, the large-scale data storage and retrieval workload is heavy, the Hamming distance is used as a nearest neighbor retrieval standard, the phase change storage logic is used for completing data retrieval in the storage array, the calculation complexity and hardware consumption are greatly reduced, meanwhile, the nonvolatile Boolean logic is realized in the phase change storage array, and the Hamming distance calculation can be completed. However, in the conventional nonvolatile logic calculation, the nonvolatile characteristic of a storage device is utilized, binary logic input is converted into high-low resistance write operation, the memory needs to be frequently erased and written in the logic calculation, the calculation time is limited by the device write time, and the full logic calculation can be realized.
Disclosure of Invention
The invention aims to provide a device for realizing rapid logic calculation of a phase change memory unit and a data retrieval method, which can realize data retrieval in a phase change memory array, reduce the calculation amount of data matching and realize efficient approximate nearest distance matching.
The technical scheme adopted by the invention for solving the technical problems is as follows: the device comprises a phase change storage array and a peripheral control circuit, wherein the phase change storage array comprises two phase change storage logic operators; the phase change storage logic operator comprises two phase change storage units, one ends of the two phase change storage units are connected with the same bit line, the other ends of the two phase change storage units are connected with the drain ends of respective gate tubes, the source ends of the gate tubes are grounded, the gate electrode of the gate tube of one phase change storage unit in the phase change storage logic operator is connected with a first word line, and the gate electrode of the gate tube of the other phase change storage unit in the phase change storage logic operator is connected with a second word line; the peripheral control circuit writes initial data information into the phase change memory array, and the gate tube gates the phase change memory cell according to signals on the first word line and the second word line, so that the information stored in the phase change memory cell and a pulse signal on a bit line perform logic operation, and the initial data information is processed.
The phase change memory cell has a nonvolatile memory characteristic and a threshold switching characteristic, and the phase change memory cell reversibly transitions between a high resistance state and a low resistance state. The low resistance state is defined as a binary logic "1" and the high resistance state is defined as a binary logic "0".
One phase change storage unit in the phase change storage logic operator is used as a main phase change storage unit, the other phase change storage unit is used as a reverse phase change storage unit, the main phase change storage unit is used for storing input data, and the reverse phase change storage unit is used for storing the input reverse data.
Inputting a set and reset signal to a bit line of the phase change memory, and controlling gating of the main phase change memory unit and the reverse phase change memory unit by a word line; when a SET SET signal is applied to the word line, the device gated by the word line is SET to a low impedance state; when a RESET RESET signal is applied to the word line, the device gated by the word line is set to be in a high-resistance state.
When the exclusive-or logic is realized, the input ends p of the first word line and the second word line and the resistance value state q stored in the phase change memory unit represent input logic, and the gated resistance value state Z of the phase change memory unit represents a logic calculation result; connecting an inverter at the input end of the first word line, and gating the phase change memory cell connected with the first word line when the input logic value of the input end p is '0'; and when the input logic value of the input end p is 1, gating the phase change memory cell connected with the second word line, and reading the resistance state of the phase change memory cell gated by the gate tube to realize the XOR logic calculation operation.
When the exclusive-nor logic is realized, the input ends p of the first word line and the second word line and the resistance value state q stored in the phase change memory unit represent input logic, and the gated resistance value state Z of the phase change memory unit represents a logic calculation result; connecting an inverter to the input end of the second word line, and gating the phase change memory cell connected with the second word line when the input logic value of the input end p is '0'; and when the input logic value of the input end p is 1, gating the phase change memory cell connected with the first word line, and reading the resistance state of the phase change memory cell gated by the gate tube to realize the exclusive-nor logic calculation operation.
The writing of the initial data information into the phase change memory array by the peripheral control circuit means that the storage state of each bit of data of the data set is correspondingly written into each phase change memory cell in the phase change memory array by the peripheral control circuit.
The technical scheme adopted by the invention for solving the technical problems is as follows: there is also provided a method of data retrieval using the computing device described above, comprising the steps of:
(1) writing a retrieval data set in the phase change memory array in advance through the peripheral control circuit;
(2) taking query data as logic input to control the voltage of the first word line and the second word line, and carrying out exclusive-or logic operation on the query data and the retrieval data set stored in the phase change memory array;
(3) applying a read current at the bit line;
(4) and calculating Hamming distances between a plurality of groups of data sets obtained by the bit line voltage and the query data, screening out data information corresponding to the minimum Hamming distance, and outputting.
Advantageous effects
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects: the phase change memory cell parallel Boolean logic calculation is completed in the memory array by using the double-word-line 2T2R phase change memory cell and the peripheral control circuit, the retrieval data set and the reverse data set thereof are pre-stored in the phase change memory array by the write circuit, the query data and the retrieval data set in the memory cell are efficiently matched, the Hamming calculation can be realized in parallel among a plurality of word lines, the logic calculation is controlled by a gating word line, the erasing operation is not related, the operation time is not limited by the state conversion time of the memory device, the nonvolatile characteristic of the phase change memory cell is used for expressing the output result by the resistance value, the similar matching of the database is realized by a plurality of modules at the same time, the matching speed is greatly increased, the durability of the device can be improved, the service life is greatly prolonged, and the retrieval efficiency is greatly improved.
Drawings
FIG. 1 is a schematic diagram of a phase change memory cell model;
FIG. 2 is a schematic diagram of a phase change memory dual wordline 2T2R cell structure;
FIG. 3 is a schematic diagram illustrating the XOR logic operation of the phase change memory cell;
FIG. 4 is a schematic diagram illustrating the XNOR logic operation of the phase change memory cell;
FIG. 5 is a schematic diagram of a phase change memory cell XOR logic calculation truth table and calculation formula;
FIG. 6 is a schematic diagram of a truth table and equations for XNOR logic calculation of a phase change memory cell;
FIG. 7 is a diagram illustrating Hamming distance calculation of a phase change memory array.
Detailed Description
The invention will be further illustrated with reference to the following specific examples. It should be understood that these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Further, it should be understood that various changes or modifications of the present invention may be made by those skilled in the art after reading the teaching of the present invention, and such equivalents may fall within the scope of the present invention as defined in the appended claims.
The embodiment of the invention relates to a device for realizing fast logic calculation by phase change memory cells, which comprises a phase change memory array and a peripheral control circuit, wherein the phase change memory array is composed of two phase change memory logic operators, and each phase change memory logic operator is of a double word line 2T2R structure composed of two phase change memory cells. As shown in fig. 1, one end of each of the two phase change memory cells is connected to the same bit line, the other end of each of the two phase change memory cells is connected to the drain of the corresponding gate tube, the source of the gate tube is grounded, the gate of the gate tube of one phase change memory cell in the phase change memory logical operator is connected to the first word line, and the gate of the gate tube of the other phase change memory cell is connected to the second word line. As shown in fig. 2, in the phase change memory array, word lines in a double word line 2T2R structure in the same row are connected together to form a memory row of the phase change memory array; the bit lines of the double word line 2T2R structure in the same column are connected together to form a memory column of the memory array. The peripheral control circuit writes initial data information into the phase change memory array, and the gate tube gates the phase change memory cell according to signals on the first word line and the second word line, so that the information stored in the phase change memory cell and a pulse signal on a bit line perform logic operation, and the initial data information is processed.
In the present embodiment, one phase change memory cell in the phase change memory logical operator is used as a main phase change memory cell, and the other phase change memory cell is used as a reverse phase change memory cell, where the main phase change memory cell is used to store input data, and the reverse phase change memory cell is used to store input reverse data.
The dual wordline 2T2R model shares a bitline, one bitline storing a single bit data point. And inputting a set and reset signal into the bit line of the phase change memory, and controlling the gating of the main phase change memory unit and the reverse phase change memory unit by the word line. When a SET SET signal is applied to the word line, the device gated by the word line is SET to a low impedance state; when a RESET RESET signal is applied to the word line, the device gated by the word line is set to be in a high-resistance state.
The embodiment initializes the resistance state of the phase change memory unit to be an amorphous state and writes the state into the retrieval data set, and the phase change memory can be reversibly switched between a high resistance state and a low resistance state according to the threshold switching characteristic of the phase change memory, wherein the resistance value of the high resistance state is defined as logic '0' and the low resistance state is defined as logic '1'. When writing '1', applying a gating signal on a word line WL to enable the gating tube to work in a saturation region, applying a SET signal SET on a bit line BL, and grounding a source end; when writing "0", a RESET signal RESET is written to the bit line, a gate signal is applied to the word line WL, and the source terminal is grounded.
The input signals of the embodiment are word line gating signals and array storage resistance values respectively, the logic calculation result is output to a read resistance value state, exclusive or and logic calculation can be completed only by one step, the double-word line 2T2R model can realize logic functions, the high-density low-power consumption characteristic of phase change storage is fully utilized, the initialization operation and erasing operation are not needed, the parallel logic calculation can be realized in a large-scale phase change storage array, and the applications such as data retrieval, data encryption and the like are completed in the storage array.
An input signal of a definition input end p is input from a double word line end, q is a stored phase change memory array retrieval data set, Z is a final calculation result of a phase change memory unit, and the resistance value of the phase change memory unit is not changed in the calculation process.
When exclusive-or (XOR) logic is realized, the double word line input end p and the resistance state q stored in the phase change memory unit represent input logic, and the gated phase change memory unit resistance state Z represents a logic calculation result. Wherein: the XOR logic performs the calculation within the PCRAM array, as shown in fig. 3, by connecting an inverter to the first wordline input of the dual wordline 2T2R configuration. When the input logic value of p is '0', gating the phase change memory cell connected with the first word line; and the p input logic value is 1, the phase change memory unit connected with the second word line is gated, the resistance value state of the phase change unit can be read after the gating tube is gated, the XOR logic calculation operation is realized, otherwise, the phase change memory device is not gated, and the state cannot be read. As shown in FIG. 5, the XOR logical operation is expressedThe formula is as follows:
when the exclusive nor (XNOR) logic is realized, the resistance state q stored by the double word line input end p and the phase change memory cell represents the input logic, and the resistance state Z of the gated phase change memory cell represents the logic calculation result. Wherein: the XNOR logic implements the computation within the PCRAM array, as shown in fig. 4, terminating an inverter at the second wordline of the dual wordline 2T2R structure. When the input logic value of p is '0', gating the phase change memory cell connected with the second word line; the p input logic value is 1, the phase change memory unit connected with the first word line is gated, the resistance value state of the phase change unit can be read after the gating tube is gated, XNOR logic calculation operation is achieved, otherwise the phase change memory device is not gated, and the state cannot be read. As shown in fig. 6, the exclusive nor logic operation expression is:
the nearest neighbor retrieval utilizes a matching function to calculate the perception distance between two data, wherein the perception distance can be a measure of the similarity between the data and can be calculated through a Hamming distance. In the data retrieval process, a data set is retrieved as stored nonvolatile initial data, the value of the data set is stored through a peripheral writing circuit, and query data is converted into a word line voltage signal through a peripheral control circuit in logic calculation, so that the gating of the dual word line 2T2R device is controlled. And judging different data bits of the query data and the stored retrieval data set by using XOR logic, and counting the number of the different data bits after XOR operation of the query data and the stored retrieval data set in the storage array to realize Hamming distance calculation so as to judge the similarity of the data contents. The device only needs to read, so that parallel processing can be realized, data can be retrieved according to storage columns, and the memory computing capacity of the phase change storage unit is fully utilized.
Hamming distance calculation is done in the array. The search data p represents input data, and the word line voltage is determined in accordance with the input. q denotes a pre-stored database, which has been previously stored in the phase change memory before the logical calculation, and one bit line stores one set of search data. According to the word line voltage set by the input image, applying a reading current Ir on the bit line, comparing the reading current Ir with the bit line output voltage, wherein all matched models have no conducted low-resistance units, and the corresponding bit line voltage is higher; the lower the matching degree, the more the low resistance cells are turned on, and the lower the output bit line voltage is. Ideally, when the hamming distance is zero, the voltage is highest, otherwise, the hamming distance and the voltage are approximately inverse functions, and the design can more quickly find the model with the closest hamming distance. The calculation of the Hamming distance can be realized, the larger the Hamming distance is, the larger the difference of the data is, and the smaller the Hamming distance is, the higher the approximation degree of the query data and the retrieval moral target data is. The memory array calculates the Hamming distance and utilizes the gating and reading voltage of the device, and does not relate to the consumption of the writing time and the power consumption of the device.
FIG. 7 illustrates the implementation of phase change memory logic computation and data retrieval in a phase change memory cell. And with the double-word line 2T2R cell structure, the cell gated by the phase change memory array is the calculated Hamming distance, and the retrieval of the identification data in the retrieval database is obtained by reading the bit line voltage calculation result. And the database retrieval is realized by multiple modules simultaneously, so that the matching speed is greatly increased.
The steps of realizing Hamming distance calculation and finishing data quick retrieval in the phase change memory array are as follows:
(1) initial data is written in the phase change memory array in advance, namely, a retrieval data set is prestored in the double word line structure, and one group in each bit line storage data set is used as a logic variable q to participate in calculation;
(2) taking query data as a logic input p for controlling word line voltage, and carrying out exclusive or logic operation on the query data and a prestored data set stored in the phase change storage array;
(3) applying a read current to the bit line;
(4) and calculating the voltage of the bit line to obtain the Hamming distances between the multiple groups of data sets and the query data, screening out the data information corresponding to the minimum Hamming distance, and outputting.
In the traditional calculation process, data of a storage unit needs to be read out and transmitted to a calculation unit to finish operation, and a calculation result is transmitted to the storage unit to be stored. By utilizing the nonvolatile characteristic of the phase change memory cell, the calculation integration calculation becomes a new hot point in the memory array implementation, but the current logic calculation in the memory is based on the nonvolatile characteristic, and the large-scale multi-step logic cascade requires frequent reading and writing of the memory cell, so that a larger calculation amount is brought. The invention changes the method of taking the voltage signal as the logic input in the traditional logic circuit and improves the problem of frequent erasing and cascading of the state logic on the nonvolatile memory in the nonvolatile memory logic calculation. Internal calculation is realized in the double-word-line 2T2R phase-change memory cell, logic calculation is gated by using a device, a data transmission process is not needed, a storage result is not needed to be written, and calculation and storage are realized in one step.
The invention discloses a phase change memory, which is a novel nonvolatile memory based on the nonvolatile characteristic of the phase change memory, and is characterized in that a double-word line 2T2R device structure is used for realizing single-ended nonvolatile logic calculation, an XOR logic gate circuit for realizing the ultrahigh data retrieval function of the phase change memory is provided, a retrieval data set is stored in a phase change unit, logic input is converted into a gating signal, XOR logic calculation is carried out on query data and a storage data set to realize data matching degree retrieval, and Hamming distance is counted, namely the number of different data bits after XOR operation of the query data and the storage data set is counted in a storage array. The data retrieval is realized in the storage array, the stored data storage value is not changed, the transmission power consumption is reduced, the risk of data leakage in the carrying process is reduced, and the data encryption processing is better realized. The method overcomes the frequent data transmission between the traditional von Neumann architecture calculation and storage, stores large-scale data in a nonvolatile storage array, can realize nonvolatile Boolean logic calculation under the condition of not changing data storage, and calculates Hamming distance to realize rapid data retrieval. Meanwhile, the characteristics of high density and low power consumption of the phase change memory are utilized, a writing process is not needed, the power consumption is greatly reduced, the calculation process is simplified, the data retrieval time consumption is reduced, and the area consumption is reduced. The method realizes logic calculation in the phase change memory array, can realize special data storage and rapid retrieval, and can further realize reconfigurable array design.
Claims (8)
1. A device for realizing rapid logic calculation by a phase change memory unit is characterized by comprising a phase change memory array and a peripheral control circuit, wherein the phase change memory array comprises two phase change memory logic operators; the phase change storage logic operator comprises two phase change storage units, one ends of the two phase change storage units are connected with the same bit line, the other ends of the two phase change storage units are connected with the drain ends of respective gate tubes, the source ends of the gate tubes are grounded, the gate electrode of the gate tube of one phase change storage unit in the phase change storage logic operator is connected with a first word line, and the gate electrode of the gate tube of the other phase change storage unit in the phase change storage logic operator is connected with a second word line; the peripheral control circuit writes initial data information into the phase change memory array, and the gate tube gates the phase change memory cell according to signals on the first word line and the second word line, so that the information stored in the phase change memory cell and a pulse signal on a bit line perform logic operation, and the initial data information is processed.
2. The phase change memory cell implemented fast logic computation apparatus of claim 1, wherein the phase change memory cell has a non-volatile storage characteristic and a threshold switching characteristic, the phase change memory cell reversibly transitioning between a high resistance state and a low resistance state.
3. The phase change memory cell implemented fast logic computation apparatus of claim 1, wherein one of the phase change memory logical operators is a main phase change memory cell for storing input data and the other phase change memory cell is an inverted phase change memory cell for storing input inverted data.
4. The phase change memory cell implemented fast logic computation apparatus of claim 3, wherein a set and reset signal is inputted to the bit line of the phase change memory, and a word line controls the gating of the main phase change memory cell and the inverted phase change memory cell; when a SET SET signal is applied to the word line, the device gated by the word line is SET to a low impedance state; when a RESET RESET signal is applied to the word line, the device gated by the word line is set to be in a high-resistance state.
5. The device for realizing fast logic calculation of the phase change memory cell as claimed in claim 4, wherein when the exclusive-or logic is realized, the input ends p of the first word line and the second word line and the resistance state q stored in the phase change memory cell represent input logic, and the gated resistance state Z of the phase change memory cell represents a logic calculation result; connecting an inverter at the input end of the first word line, and gating the phase change memory cell connected with the first word line when the input logic value of the input end p is '0'; and when the input logic value of the input end p is 1, gating the phase change memory cell connected with the second word line, and reading the resistance state of the phase change memory cell gated by the gate tube to realize the XOR logic calculation operation.
6. The device for realizing fast logic calculation of the phase change memory cell according to claim 4, wherein when the exclusive nor logic is realized, the input ends p of the first word line and the second word line and the resistance state q stored in the phase change memory cell represent input logic, and the gated resistance state Z of the phase change memory cell represents a logic calculation result; connecting an inverter to the input end of the second word line, and gating the phase change memory cell connected with the second word line when the input logic value of the input end p is '0'; and when the input logic value of the input end p is 1, gating the phase change memory cell connected with the first word line, and reading the resistance state of the phase change memory cell gated by the gate tube to realize the exclusive-nor logic calculation operation.
7. The phase change memory cell implemented fast logic computing apparatus of claim 1, wherein the peripheral control circuitry writes initial data information into the phase change memory array by writing storage states of respective bits of data of a data set into respective phase change memory cells in the phase change memory array.
8. A method for implementing a fast logic computation apparatus for data retrieval using a phase change memory cell as claimed in any one of claims 1 to 7, comprising the steps of:
(1) writing a retrieval data set in the phase change memory array in advance through the peripheral control circuit;
(2) taking query data as logic input to control the voltage of the first word line and the second word line, and carrying out exclusive-or logic operation on the query data and the retrieval data set stored in the phase change memory array;
(3) applying a read current at the bit line;
(4) and calculating Hamming distances between a plurality of groups of data sets obtained by the bit line voltage and the query data, screening out data information corresponding to the minimum Hamming distance, and outputting.
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