CN101763891A - Phase-change memory unit and operation method thereof - Google Patents
Phase-change memory unit and operation method thereof Download PDFInfo
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- CN101763891A CN101763891A CN200810207691A CN200810207691A CN101763891A CN 101763891 A CN101763891 A CN 101763891A CN 200810207691 A CN200810207691 A CN 200810207691A CN 200810207691 A CN200810207691 A CN 200810207691A CN 101763891 A CN101763891 A CN 101763891A
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Abstract
The invention belongs to the technical field of microelectronics, in particular to a phase-change memory unit with high reliability and high density and a storage operation method thereof. Two phase-change storage units and two gating triodes form a storage unit. The two phase-change storage units and the two gating triodes share the same word line and are connected with different bit lines. The invention has the advantages that the 1T1R four-state multi-value storage density can be achieved under the condition that the array area is not sacrificed, the influence of the fluctuation of a process to data readout is greatly improved, and the danger of erroneous readout nearly does not exist.
Description
Technical field
The invention belongs to microelectronics technology, specifically belong to the memory technology field, relate in particular to a kind of phase-changing memory unit and method of operating thereof.
Background technology
Phase transition storage is a kind of new type of solid state semiconductor nonvolatile memory, and its storage is based on the chalcogenide compound material (as Ge
2Se
2Te
5, the GST) rapid phase transition under the electric pulse effect.Phase-changing memory unit shows as a variable resistor on electrology characteristic, carrying out reversible transformation under the electric impulse signal effect between " high-impedance state " and " low resistance state ".Be embodied in pulse, storage medium can be heated to fusing point cooling suddenly then, it is programmed into the amorphous state (claiming the RESET attitude again) with high resistivity with precipitous negative edge; The pulse that slowly descends on the contrary then makes grain growth, and it is programmed into the crystalline state (claiming the SET attitude again) with low-resistivity.Above-mentioned two kinds of programming operations are called as respectively and reset (RESET) and programme (SET).Phase transition storage has lot of advantages, as: non-volatile, device size is little, has extended cycle life (＞10
13), high reading speed, and and the favorable compatibility of modern CMOS technology etc.These characteristics make phase transition storage be considered to have one of candidate of competitive power in the novel non-volatilization storer of future generation.
At present, phase-change memory cell is divided into two kinds of monodrome storage and many-valued storages, and phase-change memory cell of monodrome storage representation only is used for storing one data, and phase-change memory cell of many-valued storage representation is used for storing the data more than.When phase change cells is applied to monodrome when storage, the resistance of phase change cells only exists high resistant and two kinds of situations of low-resistance, is used for representative data " 0 " and " 1 "; When phase change cells was applied to many-valued storage, just must there be two or more stable status in the resistance of phase change cells.If there are four kinds of resistance states, so just can represent two bit binary data with these four kinds of states, i.e. " 00 ", " 01 ", " 10 " and " 11 ", and such phase change cells just can be stored two bit binary data, and storage density is doubled.
In the monodrome storage of phase change cells, under the situation about constantly dwindle in characteristic dimension, the influence of technological fluctuation growing with each passing day, the phase change resistor of diverse location on the same silicon chip, the error of its physical dimension is compared its absolute growth and more and more be can not ignore, even finally cause phase change resistor resistance under equal state of diverse location that very big difference is also arranged, corresponding resistance distribution range has the trend of dispersing, and causes the gap in these two kinds of resistance intervals of high resistant and low-resistance more to reduce.When phase change cells is used for many-valued storage, need between these two Standard resistance ranges, insert two Standard resistance ranges again, this quite difficulty that just becomes, because the gap between the adjacent Standard resistance range becomes littler, and in case the scope of two adjacent resistance correspondences overlaps, just have the danger that data are misread out, this will badly influence reliability of products.
At present, phase transition storage mainly contains 3 kinds of structure: 0T1R, 1T1R and 2T2R structure, and wherein T represents gate tube, and R represents phase change memory resistance.The 0T1R structure is the simplest, and storage density is the highest, and 1T1R takes second place, and 2T2R uses two gate tubes and two memory resistor to be used as a storage unit, so storage density is minimum.0T1R and 1T1R structure have a lot of something in commons: in the read operation process, the both adopts unit line output, and different information states needs when output and a certain reference source compares and realizes differentiating.2T2R comes down to two 1T1R common (complementation), 12 binary information of storage, two phase change resistors wherein are in high-impedance state and low resistance state respectively, when the first phase change memory resistance is in high-impedance state, when the second phase change memory resistance was in low resistance state, representative storage data were " 0 "; Be in low resistance state and work as the first phase change memory resistance, when the second phase change memory resistance was in high-impedance state, representative storage data were " 1 ".During read operation, two bit lines that link to each other with two phase change memory resistance are applied the identical voltage of reading, because the resistance value difference of two phase change memory resistance, electric current on two bit lines is also different, current-differencing on this two bit lines is input to sense amplifier, and the result of sense amplifier output has promptly reflected the state of storage.2T2R compares own first memory resistor and second memory resistor, thereby need not to add reference source circuit.
Along with the continuous reduction of characteristic dimension,, use the 0T1R and the 1T1R scheme that add the differentiation of reference source realization state to go bankrupt substantially in case overlapping appears in the scope of the adjacent resistance correspondence of phase change cells.Yet for the 2T2R structure, because it adopts 12 system data of storage of 2 1T1R complementary structures, and these two 1T1R structures are owing to the adjacent disturbing effects such as technological fluctuation that are subjected to much at one of position, and therefore the phase change resistor R in these two 1T1R structures will have much at one variation under various interference.Like this, when adopting double dight wire complementary output and peripheral sense amplifier that double dight wire output information is carried out the difference amplification, the influence that various interference produce on 2 phase change resistor R is a common-mode signal for sense amplifier all, and its influence will be eliminated fully.This shows that 2T2R has promoted antijamming capability, guaranteed the reliability of data access, but but sacrificed the density of storage.
Summary of the invention
The purpose of this invention is to provide and a kind ofly can reduce the problem of misreading out because of data that technological fluctuation causes between the phase-change memory cell, do not sacrifice the phase-changing memory unit and the method for operating thereof of the storage density of storage unit again.
Purpose of the present invention realizes by following method and step:
Phase-change memory cell provided by the present invention comprises word line, first gate tube, the first phase change memory resistance, second gate tube, the second phase change memory resistance, first bit line, second bit line.The control end of first gate tube of phase-change memory cell and the control end of second gate tube are connected in same word line, and first end and first gate tube of the first phase change memory resistance are connected in series, and second end of the first phase change memory resistance is electrically connected with first bit line; First end and second gate tube of the second phase change memory resistance are connected in series, and second end of the second phase change memory resistance is electrically connected with second bit line.The first phase change memory resistance and the second phase change memory resistance all have first, second, third resistance states, and phase-changing memory unit is by the ratio definition of data state of the first phase change memory resistance and the second phase change memory resistance.
In phase-change memory cell provided by the present invention, the resistance ratio of the 3rd resistance states of first resistance states of the first phase change memory resistance and the second phase change memory resistance is defined as first data mode, the resistance ratio of second resistance states of first resistance states of the first phase change memory resistance and the second phase change memory resistance is defined as second data mode, the resistance ratio of first resistance states of second resistance states of the first phase change memory resistance and the second phase change memory resistance is defined as the 3rd data mode, and the resistance ratio of first resistance states of the 3rd resistance states of the first phase change memory resistance and the second phase change memory resistance is defined as the 4th data mode.
In phase-change memory cell provided by the present invention, the GeSbTe compound that described phase change memory resistance is nitrating, the crystalline resistance of the GeSbTe compound that its first resistance states is a nitrating, the 3rd resistance states is the amorphous state resistance of the GeSbTe compound of nitrating, and second resistance states is the intermediate state resistance of the GeSbTe compound of nitrating.
In phase-change memory cell provided by the present invention, described gate tube is a bipolar transistor, and the control end of gate tube is the base stage of bipolar transistor, and first end of phase change memory resistance is connected with the emitter of bipolar transistor.
Simultaneously, the invention provides the peripheral circuit that is connected with phase-change memory cell of the present invention, comprising:
Be connected with first bit line, be used for first current mirror module that replication stream is crossed the electric current of the first phase change memory resistance;
Be connected with second bit line, be used for second current mirror module that replication stream is crossed the electric current of the second phase change memory resistance;
Amplifier, its input end are connected with the output terminal of first current mirror module, second current mirror module respectively;
Coding circuit, its input end is connected with amplifier out.
In the peripheral circuit of phase-change memory cell provided by the present invention, the number of amplifier is three, and current mirror module comprises reference current source and three metal-oxide-semiconductors that are used for current mirror.
The method of operating of phase-change memory cell of the present invention comprises write operation method and read operation method, wherein:
Write operation: (1) first gate tube and the second gate tube gating; (2) the first phase change memory resistance and the second phase change memory resistance two ends apply the write operation electric signal respectively and are operated to a kind of resistance states in first, second and the 3rd resistance states.
Read operation: (1) first gate tube and the second gate tube gating; (2) first phase change memory resistance apply identical read operation electric signal respectively with the second phase change memory resistance two ends, read the current value that flows through the first phase change memory resistance and the second phase change memory resistance respectively; (3) current value that flows through the first phase change memory resistance and the current value that flows through the second phase change memory resistance are compared, according to fiducial value sense data state.
After (1) step in the write operation process, before (2) step, apply the erase operation electric signal respectively to the first phase change memory resistance and the second phase change memory resistance two ends, the described first phase change memory resistance and the second phase change memory resistance are operated to the 3rd resistance states.
In the method for operating of phase-change memory cell provided by the present invention, the gating of gate tube is to apply electric signal by the word line that is connected with gate tube to realize.
In the method for operating of phase-change memory cell provided by the present invention, during read operation, the first current mirror module output of the current value of the first phase change memory resistance by being connected with first bit line, the second current mirror module output of the current value of the second phase change memory resistance by being connected with second bit line, described relatively is to receive the output signal of first current mirror module and second current mirror module and export fiducial value by comparer, and data mode is determined according to the fiducial value that comparer exports scrambler to.
In the method for operating of phase-change memory cell provided by the present invention, write operation signal can be the voltage pulse signal of different pulse heights, and the read operation signal is can voltage pulse signal or one of current pulse signal.
By phase-change memory cell provided by the present invention and with peripheral circuit and method of operating that this storage unit is complementary, can realize the four attitudes storages and the storage operation thereof of phase-change memory cell.Because in the structure of this storage unit, the first phase change memory resistance and the second phase change memory resistance can adjacently form, space length between the two can be very little, and therefore the technological fluctuation that is subjected between the first phase change memory resistance and the second phase change memory resistance is very little; Simultaneously, this phase-change memory cell utilizes the ternary storage characteristics of phase change memory resistance, utilizes the different store statuss that define of the ratio of the first phase change memory resistance and the second phase change memory resistance, therefore can realize many-valued storage, therefore, this phase-change memory cell has the big characteristics of storage density.
Description of drawings
Fig. 1 is a multi-value phase change storage unit resistance distribution schematic diagram, and wherein 101 is low-resistance distribution ranges, the 104th, and the high resistant distribution range, 102 and 103 is middle resistance distribution ranges.
Fig. 2 be two kinds of GST resistivity with the annealing temperature change curve, wherein 201 be GST resistivity with the annealing temperature change curve, the 202nd, the GST resistivity of nitrating 10% is with the annealing temperature change curve.
Fig. 3 is the ternary resistance distribution schematic diagram of phase change resistor, wherein R
1Be first resistance (low-resistance) distribution range, R
2Be second resistance (middle resistance) distribution range, R
3It is the 3rd resistance (high resistant) distribution range.
Fig. 4 is the resistance value ratio distribution schematic diagram of phase change resistor, wherein R
3/ R
1, R
2/ R
1, R
1/ R
2And R
1/ R
3It is the distribution range of four kinds of resistance ratios.
Fig. 5 is the structural representation of phase-change memory cell, wherein 501 is first bit lines, 502 is second bit lines, the 503rd, word line, B00 is first gate tube that links to each other with word line 503, R00 is first memory resistor that links to each other with word line 503, and B01 is second gate tube that links to each other with word line 503, and R01 is second memory resistor that links to each other with word line 503.
Fig. 6 is phase-change memory cell and read operation circuit diagram thereof, and wherein 601 is first bit lines, and 602 is second bit lines, 603, the 604th, current replication module, 605,606,607th, comparison amplifier, 608 coding circuits, the 609th, the amplification of current replication module, the 610th, current source, M
0, M
1, M
2It is the metal-oxide-semiconductor that is used for current mirror.
When Fig. 7 is the storage of unit four attitudes, read table as a result under every kind of state
Fig. 8 is the state transition graph of ternary memory resistor, and wherein 801 is first resistance states, and 802 is second resistance states, and 803 is the 3rd resistance states, the 804th, and first SET pulse, 805 is second SET pulse, the 806th, the RESET pulse.
Specific embodiments
Below in conjunction with specific embodiment, the present invention is further elaborated.Embodiment only is used for the present invention is done explanation rather than limitation of the present invention.
A phase-change memory cell, shown in Figure of description 5, phase-change memory cell 500 is 2B (Bipolar, bipolar transistor) 2R (Resistance, memory resistor) structure of storage unit, phase-change memory cell 500 comprises the first bipolar transistor B00, the second bipolar transistor B01, the first phase change memory resistance R 00, the second phase change memory resistance R 01, first bit line 501 and second bit line 502, wherein the base stage of the base stage of the first bipolar transistor B00 and the second bipolar transistor B01 is connected in same word line 503, one end of the first phase change memory resistance R 00 and the first bipolar transistor B00 emitter are connected in series, the other end of the first phase change memory resistance is electrically connected with first bit line 501, one end of the second phase change memory resistance R 01 and the second bipolar transistor B01 emitter are connected in series, and the other end of the second phase change memory resistance R 01 is electrically connected with second bit line 502.In the present embodiment, bipolar transistor is the positive-negative-positive triode, when gate voltage is 0V on the word line 503, represents that this word line is a selected state, when applying voltage on the word line 503 and be Vdd, represents that this word line is selected state not; When voltage on the bit line is read-write operation voltage, represent that this bit line is a selected state, when voltage on the bit line is 0V, represent that this bit line is selected state not; When word line 503 is chosen when choosing simultaneously with bit line 501, the first bipolar transistor B00 gating, thereby the first phase change memory resistance R, 01 gating, therefore can apply voltage on word line and bit line carries out operations such as RESET, SET to the first phase change memory resistance R 01.Storage unit 500 is come the definition of data state by the ratio of the resistance states between the first phase change memory resistance R 00 and the second phase change memory resistance R 01.The first phase change memory resistance R 00 and the second phase change memory resistance R 01 are identical phase change memory resistance, and all tool can be at the first resistance states R
1, the second resistance states R
2, the 3rd resistance states R
3Between back and forth the conversion, phase change memory resistance is the GeSbTe compound of nitrating in the present embodiment, the first resistance states R
1Be the crystalline resistance of the GeSbTe compound of nitrating, the 3rd resistance states R
3Be the amorphous state resistance of the GeSbTe compound of nitrating, second resistance states 2 is the intermediate state resistance of the GeSbTe compound of nitrating.For realizing this 2B2R phase-change memory cell four attitudes storage, the first resistance states R of the first phase change memory resistance R 00
1The 3rd resistance states R with the second phase change memory resistance R 01
3Resistance ratio be defined as first data mode, the first resistance states R of the first phase change memory resistance R 00
1The second resistance states R with the second phase change memory resistance R 01
2Resistance ratio be defined as second data mode, the second resistance states R of the first phase change memory resistance R 00
2The first resistance states R with the second phase change memory resistance R 01
1Resistance ratio be defined as the 3rd data mode, the 3rd resistance states R of the first phase change memory resistance R 00
3The first resistance states R with the second phase change memory resistance R 01
1Resistance ratio be defined as the 4th data mode; Also be R
1/ R
3, R
1/ R
2, R
2/ R
1And R
3/ R
1Four kinds of resistance ratios are as four kinds of store statuss, thereby the resistance value ratio of having realized phase change resistor shown in Figure 4 distributes, and four store statuss have better anti-disturbance performance each other.
A kind of phase-change memory cell provided by the present invention and read operation circuit thereof are shown in Figure of description 6.Read operation circuit diagram 600 comprise be connected with first bit line, be used for first current mirror module 603 that replication stream is crossed the electric current of the first phase change memory resistance, be connected with second bit line, be used for second current mirror module 604 that replication stream is crossed the electric current of the second phase change memory resistance, the amplifier 605,606,607 that input end is connected with the output terminal of first current mirror module, second current mirror module respectively, the coding circuit 608 that input end is connected with amplifier out.Current mirror module comprises reference current source 610, three metal-oxide-semiconductor M that are used for current mirror
0, M
1, M
2
The process of 2B2R structure read operation is that the resistance with a unit and its complementation unit compares, according to sense data as a result relatively.Two phase change resistors in the 2B2R structure are chosen in three resistances respectively, ratio exists four kinds of different situations, and the output of sensor amplifier is binary, promptly has only " 0 " or " 1 " two kinds of situations, and only using a sensor amplifier is can't satisfy comparative result multifarious.Therefore, used three sensor amplifiers here, the input of each sensor amplifier has nothing in common with each other, and like this, for choosing of the different resistances of two phase change resistors in the 2B2R structure, the output result of each sensor amplifier also has nothing in common with each other.Wherein first output of second of first current mirror module output and second current mirror module is connected to first sensor amplifier, first output of first current mirror module and first output of second current mirror module are connected to second sensor amplifier, first output of first current mirror module and second output of second current mirror module are connected to the 3rd sensor amplifier, and the output of three sensor amplifiers is connected to coding circuit.
During read operation, first gate tube and the second gate tube gating, the first phase change memory resistance applies identical read operation electric signal respectively with the second phase change memory resistance two ends, since the resistance difference of the phase change resistor that connects on two bit lines, the electric current I that flows through on first bit line and second bit line
1And I
2Also different.By two current replication modules this two-way electric current is duplicated respectively, the multiple that duplicates is respectively 1 times and r times, is the current replication module in the frame of broken lines, has adopted standard current mirror to carry out current replication, and metal-oxide-semiconductor is of a size of (W/1) among the figure
1=(W/1)
0, (W/1)
2=r * (W/1)
0, sensor amplifier SA
0Will " r I doubly
1" and " I
2" compare SA
1With " I
1" and " I
2" compare SA
2With " I
1" and " r I doubly
2" compare, the comparative result of three sensor amplifiers draws 2 bit binary data through coding circuit, and this 2 bit binary data has promptly reflected the store status of this 2B2R storage unit.
Claims (14)
1. phase-changing memory unit, comprise word line, first gate tube, the first phase change memory resistance, second gate tube, the second phase change memory resistance, first bit line, second bit line, it is characterized in that the first phase change memory resistance and the second phase change memory resistance all have first, second, third resistance states.
2. phase-changing memory unit according to claim 1, it is characterized in that described phase change memory resistance first resistance states is the crystalline resistance state of phase change memory resistance, the 3rd resistance states is the amorphous state resistance of phase change memory resistance, and second resistance states is the intermediate state resistance of phase change memory resistance.
3. phase-changing memory unit according to claim 1, it is characterized in that phase-changing memory unit passes through the resistance ratio definition of data state of the first phase change memory resistance and the second phase change memory resistance, the resistance ratio of the 3rd resistance states of first resistance states of the first phase change memory resistance and the second phase change memory resistance is defined as first data mode, the resistance ratio of second resistance states of first resistance states of the first phase change memory resistance and the second phase change memory resistance is defined as second data mode, the resistance ratio of first resistance states of second resistance states of the first phase change memory resistance and the second phase change memory resistance is defined as the 3rd data mode, and the resistance ratio of first resistance states of the 3rd resistance states of the first phase change memory resistance and the second phase change memory resistance is defined as the 4th data mode.
4. phase-changing memory unit according to claim 1, it is characterized in that the GeSbTe compound that described phase change memory resistance is nitrating, first resistance states is the crystalline resistance of the GeSbTe compound of nitrating, the 3rd resistance states is the amorphous state resistance of the GeSbTe compound of nitrating, and second resistance states is the intermediate state resistance of the GeSbTe compound of nitrating.
5. phase-changing memory unit according to claim 1 is characterized in that described gate tube is a bipolar transistor, and the control end of gate tube is the base stage of bipolar transistor.
6. phase-changing memory unit according to claim 5 is characterized in that first end of described phase change memory resistance is connected with the emitter of bipolar transistor.
7. phase-change memory cell according to claim 1, it is characterized in that comprising in its peripheral circuit (1) be connected with first bit line, be used for first current mirror module that replication stream is crossed the electric current of the first phase change memory resistance; (2) be connected with second bit line, be used for second current mirror module that replication stream is crossed the electric current of the second phase change memory resistance; (3) coding circuit that is connected with amplifier out of amplifier (4) input end that is connected with the output terminal of first current mirror module, first current mirror module respectively of input end.
8. phase-changing memory unit according to claim 7, the quantity that it is characterized in that described amplifier is three.
9. phase-changing memory unit according to claim 7 is characterized in that described current mirror module comprises reference current source and three metal-oxide-semiconductors that are used for current mirror.
10. the method for operating of a phase-changing memory unit as claimed in claim 1, the step that it is characterized in that write operation is (1) first gate tube and the second gate tube gating, and (2) the first phase change memory resistance and the first phase change memory resistance two ends apply the write operation electric signal respectively and are operated to a kind of resistance states in first, second and the 3rd resistance states; The step of read operation is (1) first gate tube and the second gate tube gating, (2) first phase change memory resistance apply identical read operation electric signal respectively and read the current value that flows through the first phase change memory resistance and the second phase change memory resistance respectively with the second phase change memory resistance two ends, (3) current value that flows through the first phase change memory resistance and the current value that flows through the second phase change memory resistance are compared, according to fiducial value sense data state.
11. method of operating according to claim 10, it is characterized in that after (1) step in the write operation process, the first phase change memory resistance and the first phase change memory resistance two ends are applied the erase operation electric signal respectively before (2) step, the first phase change memory resistance and the first phase change memory resistance are operated to the 3rd resistance states.
12. method of operating according to claim 10, the gating that it is characterized in that described gate tube are to apply electric signal by the word line that is connected with gate tube to realize.
13. method of operating according to claim 10 is characterized in that described write operation signal can be the voltage pulse signal of different pulse heights, the read operation signal can be voltage pulse signal or current pulse signal.
14. method of operating according to claim 10, when it is characterized in that read operation, the first current mirror module output of the current value of the first phase change memory resistance by being connected with first bit line, the second current mirror module output of the current value of the second phase change memory resistance by being connected with second bit line, relatively be to receive the output signal of first current mirror module and second current mirror module and export fiducial value by comparer, data mode is determined according to the fiducial value that comparer exports scrambler to.
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| CN112015367A (en) * | 2020-08-26 | 2020-12-01 | 上海新氦类脑智能科技有限公司 | Nonvolatile Boolean logic operation unit, method and device |
| CN112015367B (en) * | 2020-08-26 | 2024-05-31 | 上海新氦类脑智能科技有限公司 | Nonvolatile Boolean logic operation unit, method and device |
| CN113539327A (en) * | 2021-07-09 | 2021-10-22 | 中国科学院上海微系统与信息技术研究所 | Device for realizing rapid logic calculation of phase change memory unit and data retrieval method |
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Application publication date: 20100630 |