CN102270498A - Low-power phase change memory and writing operation method thereof - Google Patents
Low-power phase change memory and writing operation method thereof Download PDFInfo
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- CN102270498A CN102270498A CN2010101912660A CN201010191266A CN102270498A CN 102270498 A CN102270498 A CN 102270498A CN 2010101912660 A CN2010101912660 A CN 2010101912660A CN 201010191266 A CN201010191266 A CN 201010191266A CN 102270498 A CN102270498 A CN 102270498A
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Abstract
The invention provides a low-power phase change memory and a writing operation method thereof, and belongs to the technical field of phase change memory. The phase change memory provided by the invention comprises a phase change memory cell array, a column decoder, a row decoder, a writing driving module, a read circuit module, a latch and a comparison circuit module. The comparison circuit module is used for controlling whether a writing driving signal inputs into the column decoder. A column address is input into the column decoder to realize column selection of the phase change memory cell array; a row address is input into the row decoder to realize row selection of the phase change memory cell array. A data signal read out by the read circuit module is stored and sent to the comparison circuit module through the latch. A writing data signal is simultaneously input into the writing driving module and the comparison circuit module. The phase change memory has characteristic of low power consumption.
Description
Technical field
(Phase Change Memory, PCM) technical field are specifically related to a kind of phase transition storage and write operation method thereof with the comparator circuit module to the present invention relates to phase transition storage.
Background technology
Storer occupies an important position in semi-conductor market, because portable electric appts is constantly universal, the share of nonvolatile memory in whole storage market is also increasing, and wherein the nonvolatile memory share more than 90% is occupied by FLASH.But because the requirement of stored charge, FLASH can not expand with the technology generation development is unrestricted, and the limit that report prediction FLASH technology is arranged is about 32nm, and this just forces people to seek the more superior nonvolatile memory of future generation of performance.
Phase transition storage (Phase Change Memory, PCM) as a kind of emerging nonvolatile memory,, read-write number of times fast, data hold time, cellar area, multivalued storage in read or write speed and easily ratio dwindle (Scaling-dowm) and have great advantage, the phase change memory continuous advancement in technology makes it to become one of the strongest rival of the following non-volatile memory technology mainstream product in the market.Phase transition storage generally adopts chalcogenide material, as Ge-Se-Te (be called for short GST), changes between amorphous state and the polycrystalline attitude can realizing under the effect of electric homenergic.Crystalline state has different electrology characteristics with amorphous state, and the resistivity of crystalline state is far smaller than amorphous state resistivity, thereby can be used for the storage of information 1 or 0.Be called reset operation (Reset) by crystalline state (low resistance state) to amorphous state (high-impedance state) transformation, be called set operation (Set) to crystalline state (low resistance state) transformation by amorphous state (high-impedance state).
Figure 1 shows that programming operation, the read operation signal schematic representation of phase transition storage.As shown in Figure 1, wherein, its pulse signal is current impulse or potential pulse, and 11 is the Reset operating impulse, and 12 is the Set operating impulse, and 13 are the read operation pulse.In the write operation Reset process, apply height and short Reset operating impulse 11, phase transition storage is changed to high resistant from low-resistance, realizes writing the process of " 0 ", is referred to as " reset write operation "; In the write operation Set process, apply low relatively and long Set operating impulse 12, phase transition storage is changed to low-resistance from high resistant, realizes the process of one writing, is referred to as " set-write operation ".For avoid read operation cause the mistake write operation and since the ratio of the high resistant of phase transition storage and low-resistance generally greater than 10
3Power, the height of read operation pulse 13 generally are significantly smaller than write operation pulse (11 and 12) highly.Therefore, compare in the operating process of storer, power consumption mainly concentrates on the write operation process, particularly in the Reset operating process.
Figure 2 shows that the structural representation block diagram of the phase transition storage of prior art.As shown in Figure 2, phase transition storage 100 comprises phase-changing memory cell array 110, line decoder 120, column decoder 130, writes driver module 140, reading circuit module 150, wherein, the row address of output inputs to line decoder 120 from address latch (meaning not shown in the figures provides), the column address of exporting from address latch inputs to column decoder 130, write driver module 140 input control signals to column decoder 130, reading circuit module 150 is used for reading the data of memory cell array.
Figure 3 shows that the partial phase change memory cell array structure synoptic diagram of Fig. 2.As shown in Figure 3, schematically provided two row, three row phase-change memory cells, this phase-changing memory cell array comprises compares storage unit 111,112,113,114,115,116.In conjunction with Fig. 2 and shown in Figure 3, the write operation process of this phase change memory 100 is made basic explanation.At first, by address latch line of input address to line decoder 120, thereby choose in the memory cell array certain the row, to choose WLi behavior example shown in Figure 3, all conductings of gate tube in all storage unit 111,112,113 of this row.Secondly, by from write driver module 140, importing write signal, write signal is applied on the phase-change memory cell of every bit lines by column decoder then, for example, all apply write signal on all bit line BLi-1, Bli among Fig. 3, the BLi+1, all phase-change memory cells 111,112,113 on the word line WLi all realize writing " 0 " or one writing operation simultaneously.In the read operation process, by line of input address, column address are chosen certain phase-change memory cell of comparing in the memory cell array 110 to line decoder 120, column decoder 130 respectively by address latch; The reading circuit module applies read signal on certain bit lines by column decoder then, reads the data of certain phase-change memory cell.In sum, the write operation process of phase transition storage is full line operation, and the read operation process is a unit operations one by one.The shortcoming of the phase transition storage of Cun Zaiing is like this: in the row that need write no matter whether the data of the storage of phase-change memory cell identical with the data that write, all need to carry out write operation, thereby the possibility that has redundant write operation, for example, when phase-change memory cell 111,112,113 is write " 0 ", if the data of phase change memory single 112,113 original storages are exactly " 0 ", so the writing of phase change memory single 112,113 " 0 " being operated is exactly redundant operation.Write operation is the major part of the power consumption of phase transition storage operation, and redundant operation will be wasted the power consumption of phase transition storage greatly.Therefore, phase transition storage shown in Figure 2 has the too high shortcoming of relative power consumption.
Summary of the invention
The technical problem to be solved in the present invention is to solve the too high problem of power consumption that the redundant write operation in the phase transition storage brings.
For solving the problems of the technologies described above, phase transition storage provided by the invention comprises phase-changing memory cell array, column decoder, line decoder, write driver module, reading circuit module, the input column address realizes to column decoder in the column selection of phase-changing memory cell array that line of input address to the row of line decoder realization phase-changing memory cell array is chosen; Also comprise latch and be used to control and write the comparator circuit module whether drive signal inputs to column decoder; The data-signal of reading of reading circuit module is by latch stores and input to the comparator circuit module, and write data signal inputs to simultaneously writes driver module and comparator circuit module.
As one of them embodiment, wherein, described comparator circuit module comprises XOR gate and NMOS pipe, the write data signal inputs to first end of XOR gate, described latch outputs signal to second end of XOR gate, the series connection of described NMOS pipe places to be write between driver module and the column decoder, and the output terminal of XOR gate connects the grid of NMOS pipe.
As another embodiment, wherein, described comparator circuit module comprises together or door and PMOS pipe, the write data signal inputs to together or first end of door, described latch outputs signal to together or second end of door, the series connection of described PMOS pipe places to be write between driver module and the column decoder, and the output terminal of XOR gate connects the grid of PMOS pipe.
According to phase transition storage provided by the invention, wherein, described phase transition storage also comprises the address latch that is used to export row address and column address.Described phase transition storage also comprises and is used to control line decoder, column decoder, writes driver module, the Logic control module of the sequential relationship between the reading circuit module, latch.
The present invention provides the write operation method of this phase transition storage simultaneously, may further comprise the steps:
(1) difference line of input address, column address are to line decoder and column decoder;
(2) read the data of the storage unit of the phase-changing memory cell array of choosing the current address by the reading circuit module;
(3) the reading circuit module data output of reading and be stored to latch;
(4) data-signal that requires to write inputs to the comparator circuit module simultaneously and writes driver module;
(5) by the comparator circuit module, whether the data-signal that the judgement requirement writes is identical with the data-signal of latch; If be judged as "Yes", the write signal of writing driver module output transfers to column decoding; If be judged as "No", the write signal of writing driver module output does not transfer to column decoding.
According to write operation method provided by the invention, wherein, in the step (5), described comparator circuit module comprises NMOS pipe and XOR gate; If the data-signal that requirement writes is identical with the data-signal of latch, then represent the data of phase-change memory cell of the current address of choosing identical with the data that require to write, then be judged as "Yes", the XOR gate output low level of comparator circuit module, NMOS manages conducting; If the data-signal that requirement writes and the data-signal of latch are inequality, then be judged as "No", the XOR gate output low level of comparator circuit module, NMOS manages shutoff.
According to write operation method provided by the invention, wherein, finish in described step (1), step (2), the read operation process of step (3) before write operation.
Technique effect of the present invention is, contrasts phase transition storage of the prior art, and by increasing latch and reading circuit module, the data-signal of reading of reading circuit module is by latch stores and input to the comparator circuit module; If the data-signal of reading is identical with the data-signal that current requirement writes, the comparator circuit module makes the write signal of writing driver module output not transfer to column decoder, thereby avoids redundant write operation; Therefore, the phase transition storage that provides of this invention has the relatively low characteristics of power consumption.
Description of drawings
Fig. 1 is programming operation, the read operation signal schematic representation of phase transition storage;
Fig. 2 is the structural representation block diagram of the phase transition storage of prior art;
Fig. 3 is the partial phase change memory cell array structure synoptic diagram of Fig. 2;
Fig. 4 is the first example structure schematic block diagram of phase transition storage provided by the invention;
Fig. 5 is the second example structure schematic block diagram of phase transition storage provided by the invention;
Figure 6 shows that the write operation method schematic flow sheet of phase transition storage.
Embodiment
What introduce below is a plurality of some in may embodiment of the present invention, aims to provide basic understanding of the present invention, is not intended to confirm key of the present invention or conclusive key element or limits claimed scope.
Figure 4 shows that the first example structure schematic block diagram of phase transition storage provided by the invention.As shown in Figure 4, phase transition storage 200 comprises phase-changing memory cell array 210, line decoder 220, column decoder 230, writes driver module 240, reading circuit module 250, latch 250, XOR gate 280, NMOS pipe 290, wherein the common comparator circuit modules (among the figure shown in the frame of broken lines) of forming of XOR gate 280 and NMOS pipe 290.The row address of output inputs to line decoder 220 from address latch (meaning not shown in the figures provides), the column address of exporting from address latch inputs to column decoder 230, and line decoder and column decoder can be decoded from choosing certain row or certain row of storage array to row address, column address respectively.Phase-changing memory cell array 210 is made up of by the cross arrangement of word line bit line a plurality of phase-change memory cells, phase-changing memory cell array structure shown in Figure 3 also can be a part that becomes memory cell array 210, the version of phase-change memory cell is 1T1R, but its specific constructive form is not limited by the present invention.Write driver module 240 and be used for the pulse signal that " 0 " or one writing are write in output, the data-signal that requirement writes (Din) is from writing driver module 240 inputs, write the pulse signal of then corresponding this data-signal that writes of output of driver module, the for example Reset pulse among Fig. 1, Set pulse, this pulse signal is used to act on the phase change memory resistance of phase-changing memory cell array, thereby can realize write operation, in this invention, Reset pulse, Set pulse are defined as " write signal ", are different from " write data signal " that driver module is write in input.Reading circuit module 250 comprises that (Sensing Amplifer, SA), it applies the read pulse signal in phase-changing memory cell array and by the sense amplifier read data signal by reading circuit for reading circuit and sense amplifier.The data that reading circuit module 250 is read (Dout) export in the latch 260, latch 260 can be used for storing from the output of reading circuit module, the data of the current row of choosing the phase-changing memory cell array, when write operation, latch 260 can input to the XOR gate 280 in the comparator circuit module successively with the data (with high level or low level form) of storage then.XOR gate 280 is used to judge whether the data-signal that current requirement writes is identical with the signal of latch 260 outputs, if identical then output low level, if inequality then export high level.The signal of XOR gate 280 outputs is used for controlling NMOS pipe 290, if XOR gate 280 output high level, then NMOS manages 290 conductings, and the data-signal that requires to write can transfer to column decoder 230 by the corresponding write signal of writing the driver module generation, thereby write signal can put on the bit line; If XOR gate 280 output low levels, then the NMOS pipe turn-offs, and the data-signal that requires to write can not transfer to column decoder 230 by the corresponding write signal of writing the driver module generation.In addition, line decoder 220, column decoder 230, the sequential relationship write between driver module 240, reading circuit module 250, the latch 250 can be controlled by the Logic control module (not shown).
Figure 5 shows that the second example structure schematic block diagram of phase transition storage provided by the invention.Comparison diagram 4 and shown in Figure 5, its key distinction is the comparator circuit module of dotted portion among the figure, in this embodiment, the comparator circuit module by with or door and PMOS manage and to form, with or door 380 be used to judge whether the signal that data-signal that current requirement writes and latch 260 export identical, if identical then export high level, if inequality then output low level.Signals same or door 380 outputs are used for controlling PMOS pipe 390, if same or door 380 output low levels, then PMOS manages 390 conductings, and the data-signal that requires to write can transfer to column decoder 230 by the corresponding write signal of writing the driver module generation, thereby write signal can put on the bit line; If with or door 380 output high level, then PMOS pipe 390 turn-offs, and requires the data-signal that writes can not transfer to column decoder 230 by the corresponding write signal of writing driver module and producing.
The write operation method of phase transition storage embodiment illustrated in fig. 4 further, is provided.Figure 6 shows that the write operation method schematic flow sheet of phase transition storage.In conjunction with Fig. 4 and shown in Figure 6, the write operation method of this embodiment is elaborated.
Step S21, line of input address and column address.
In this step, respectively line of input address and column address can be chosen the phase-change memory cell of current address correspondence to line decoder and column decoding by line decoder and column decoder by address latch.
Step S22 reads the data of the storage unit of choosing the current address by the reading circuit module.
In this step, the reading circuit of reading circuit module applies the read pulse signal in the phase-change memory cell of choosing, and reads the data of the phase-change memory cell of choosing by the sense amplifier of reading circuit module.
Step S23, the data output that the reading circuit module is read also is stored to latch.
In this step, latch input effective control signal, the data of the phase-change memory cell that the current address that the reading circuit module is read is chosen input in the latch stores, and after latch was imported invalid control signal, the data that the reading circuit module is read can be stored in latch always.
More preferably, above step S21, step S22, step S23 also can finish in the read operation process of before storer, are latched in the latch after the data of appropriate address storage are read.
Step S24, the data-signal that requires to write inputs to the comparator circuit module simultaneously and writes driver module.
In this step, the data-signal (" 0 " or " 1 ") that requires to write inputs to and writes driver module, inputs to an end of the XOR gate of comparator circuit module simultaneously, the output terminal of another termination latch of XOR gate.
Step S25, whether the data-signal that the judgement requirement writes is identical with the data-signal of latch.
In this step,, realize determining step by the XOR gate in the comparator circuit module.If the data-signal that requirement writes is identical with the data-signal of latch, then represent the data of phase-change memory cell of the current address of choosing identical with the data that require to write, be judged as "Yes", the XOR gate output low level, NMOS manages conducting, enter step S261, the write signal of writing driver module output transfers to column decoder.If the data-signal that requirement writes and the data-signal of latch are inequality, then represent the data of phase-change memory cell of the current address of choosing inequality with the data that require to write, be judged as "No", XOR gate output high level, NMOS manages shutoff, enter step S262, the output write signal of writing driver module does not transfer to column decoder.
So far, the phase transition storage of this embodiment write operation process is finished.Can further carry out the write operation of the phase-change memory cell of next address.By the said method step, redundant write operation when having avoided data that the data of phase-change memory cell storage and requirement are write identical, though might be how a read operation step, but because the power consumption of read operation is well below the power consumption of write operation, can reduce the write operation power consumption of this phase transition storage generally greatly, this phase transition storage has low in power consumption.
Above example has mainly illustrated storer of the present invention and write operation method thereof.Although only the some of them embodiments of the present invention are described, those of ordinary skills should understand, and the present invention can be in not departing from its purport and scope implements with many other forms.Therefore, example of being showed and embodiment are regarded as illustrative and not restrictive, and under situation about not breaking away from as defined spirit of the present invention of appended each claim and scope, the present invention may be contained various modifications and replacement.
Claims (8)
1. phase transition storage, comprise phase-changing memory cell array, column decoder, line decoder, write driver module, reading circuit module, the input column address realizes to column decoder in the column selection of phase-changing memory cell array that line of input address to the row of line decoder realization phase-changing memory cell array is chosen; It is characterized in that, also comprise latch and be used to control and write the comparator circuit module whether drive signal inputs to column decoder; The data-signal of reading of reading circuit module is by latch stores and input to the comparator circuit module, and write data signal inputs to simultaneously writes driver module and comparator circuit module.
2. phase transition storage according to claim 1, it is characterized in that, described comparator circuit module comprises XOR gate and NMOS pipe, the write data signal inputs to first end of XOR gate, described latch outputs signal to second end of XOR gate, the series connection of described NMOS pipe places to be write between driver module and the column decoder, and the output terminal of XOR gate connects the grid of NMOS pipe.
3. phase transition storage according to claim 1, it is characterized in that, described comparator circuit module comprises together or door and PMOS pipe, the write data signal inputs to together or first end of door, described latch outputs signal to together or second end of door, the series connection of described PMOS pipe places to be write between driver module and the column decoder, and the output terminal of XOR gate connects the grid of PMOS pipe.
4. phase transition storage according to claim 1 is characterized in that described phase transition storage also comprises the address latch that is used to export row address and column address.
5. phase transition storage according to claim 1 is characterized in that, described phase transition storage also comprises and is used to control line decoder, column decoder, writes driver module, the Logic control module of the sequential relationship between the reading circuit module, latch.
6. the write operation method of a phase transition storage as claimed in claim 1 is characterized in that, may further comprise the steps:
(1) difference line of input address, column address are to line decoder and column decoder;
(2) read the data of the storage unit of the phase-changing memory cell array of choosing the current address by the reading circuit module;
(3) the reading circuit module data output of reading and be stored to latch;
(4) data-signal that requires to write inputs to the comparator circuit module simultaneously and writes drive block;
(5) by the comparator circuit module, whether the data-signal that the judgement requirement writes is identical with the data-signal of latch; If be judged as "Yes", the write signal of writing driver module output transfers to column decoding; If be judged as "No", the write signal of writing driver module output does not transfer to column decoding.
7. write operation method according to claim 6 is characterized in that, in the step (5), described comparator circuit module comprises NMOS pipe and XOR gate; If the data-signal that requirement writes is identical with the data-signal of latch, then represent the data of phase-change memory cell of the current address of choosing identical with the data that require to write, then be judged as "Yes", the XOR gate output low level of comparator circuit module, NMOS manages conducting; If the data-signal that requirement writes and the data-signal of latch are inequality, then be judged as "No", the XOR gate output low level of comparator circuit module, NMOS manages shutoff.
8. write operation method according to claim 6 is characterized in that, finishes in described step (1), step (2), the read operation process of step (3) before write operation.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103594112A (en) * | 2013-10-31 | 2014-02-19 | 华为技术有限公司 | Write operation method for phase change memory and device |
| US9305647B2 (en) | 2013-10-31 | 2016-04-05 | Huawei Technologies Co., Ltd. | Write operation method and device for phase change memory |
| CN107170478A (en) * | 2016-03-08 | 2017-09-15 | 东芝存储器株式会社 | Semiconductor memory system |
| CN112767981A (en) * | 2021-03-10 | 2021-05-07 | 中电海康无锡科技有限公司 | Read-write control circuit for STT-MRAM |
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| US20080151656A1 (en) * | 2006-12-25 | 2008-06-26 | Elpida Memory, Inc. | Semiconductor memory device and write control mehod therefor |
| CN101656102A (en) * | 2008-08-21 | 2010-02-24 | 海力士半导体有限公司 | Semiconductor memory device and driving method thereof |
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| US20080151656A1 (en) * | 2006-12-25 | 2008-06-26 | Elpida Memory, Inc. | Semiconductor memory device and write control mehod therefor |
| CN101656102A (en) * | 2008-08-21 | 2010-02-24 | 海力士半导体有限公司 | Semiconductor memory device and driving method thereof |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103594112A (en) * | 2013-10-31 | 2014-02-19 | 华为技术有限公司 | Write operation method for phase change memory and device |
| US9305647B2 (en) | 2013-10-31 | 2016-04-05 | Huawei Technologies Co., Ltd. | Write operation method and device for phase change memory |
| CN103594112B (en) * | 2013-10-31 | 2017-01-18 | 华为技术有限公司 | Write operation method for phase change memory and device |
| CN107170478A (en) * | 2016-03-08 | 2017-09-15 | 东芝存储器株式会社 | Semiconductor memory system |
| CN107170478B (en) * | 2016-03-08 | 2020-10-27 | 东芝存储器株式会社 | Semiconductor memory device with a memory cell having a plurality of memory cells |
| CN112767981A (en) * | 2021-03-10 | 2021-05-07 | 中电海康无锡科技有限公司 | Read-write control circuit for STT-MRAM |
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