CN117215522A - Memristor-based balanced three-value multiplier circuit - Google Patents

Memristor-based balanced three-value multiplier circuit Download PDF

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CN117215522A
CN117215522A CN202311272100.5A CN202311272100A CN117215522A CN 117215522 A CN117215522 A CN 117215522A CN 202311272100 A CN202311272100 A CN 202311272100A CN 117215522 A CN117215522 A CN 117215522A
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memristor
balanced
circuit
positive electrode
nmos tube
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王晓媛
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Hangzhou Dianzi University
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Hangzhou Dianzi University
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Abstract

The invention discloses a balanced three-value multiplier circuit based on a memristor, which belongs to the technical field of circuit design and comprises a balanced three-value single-variable logic circuit F 22 And balancing the ternary multiplexer circuit. One path of input signal B is input into the balanced three-value multiplexer circuit, and the other path passes through the balanced three-value single-variable logic circuit F 22 Thereafter, a balanced three-value multiplexer circuit is input. The input signal a is directly input to the balanced three-value multiplexer circuit, and the balanced three-value multiplexer circuit output is the output of the balanced three-value multiplexer circuit. The invention has the characteristics of clear and simple structure through modularized design.

Description

Memristor-based balanced three-value multiplier circuit
Technical Field
The invention belongs to the technical field of circuit design, and particularly relates to a balanced three-value multiplier circuit based on a memristor.
Background
With the advent of the big data age, digital circuits have more and more data information to process. Conventional digital circuit designs are based on binary logic, but due to the small single-wire information carrying capability, it has been difficult for binary logic to meet some design requirements. In contrast, three-value logic is of interest to researchers due to its higher information carrying capacity and more logic functions.
In the design of a three-value logic circuit, a scheme of constructing a circuit by MOSFET, carbon nanotube field effect transistor (Carbon Nanotube Field Effect Transistor, CNTFET), resonant tunneling diode (Resonant Tunneling Diodes, RTD), and the like is known. These circuits require a large number of logic gates to be designed, which makes the circuit structure more complex. The memristor has the advantages of small size, low power consumption, integration with the traditional CMOS process and the like, and provides a new thought and direction for the construction of a three-value logic circuit.
The three-value logic is of two types of balanced three values of { 1,0,1} and unbalanced three values of {0,1,2} or {0, -1, -2 }. The balanced three-value logic has a unified representation form for positive and negative numbers without setting sign bits, and the operation of one-bit addition and multiplication has symmetry. By utilizing the characteristics, the three-value logic circuit with simple structure and symmetry is designed. According to the background, the balanced three-value multiplier circuit based on the memristor is designed, and has certain significance for the development of modern digital circuits.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a balanced three-valued multiplier circuit based on a memristor multiplexer and a univariate logic circuit.
The technical scheme adopted for solving the technical problems is as follows:
the invention comprises a balanced three-valued multiplier circuit, in particular a balanced three-valued single variable logic circuit F 22 And a balanced three-value multiplexer (MUX 3: 1) circuit.
One path of input signal B is input into the balanced three-value multiplexer circuit, and the other path passes through the balanced three-value single-variable logic circuit F 22 Later, input balanced three-value multiplexer circuit; the input signal a is directly input to the balanced three-value multiplexer circuit, and the balanced three-value multiplexer circuit output is the output of the balanced three-value multiplexer circuit.
Balanced three-value single variable logic circuit F 22 The memristor comprises two memristors and two MOS tubes, and is specifically as follows:
input terminal B and first NMOS tube T 1 Gate of (2), second NMOS transistor T 2 Is connected with the grid electrode of the power supply; first memristor M 1 Is connected with the power supply V DD The positive electrode is connected with the second memristor M at the same time 2 Is a negative electrode of the first NMOS tube T 1 Is connected with the drain electrode of M8, and a second memristor M 2 Positive electrode of (a) and a second NMOS tube T 2 Is connected with the drain electrode of the first NMOS tube T 1 And a second NMOS tube T 2 Source and supply-V of (2) DD Are connected.
Balanced three-value single variable logic circuit F 22 When the input is logic-1, circuit F 22 The output signal of (2) is 1; when the input is logic 0, circuit F 22 The output signal of (2) is 0; when the input is logic 1, circuit F 22 The output signal of (2) is-1.
The balanced three-value multiplexer circuit consists of fourteen memristors and five MOS tubes, and is specifically as follows:
input terminal A and fourth memristor M 4 Is a negative electrode of the third NMOS tube T 3 Gate of (d), fourth NMOS transistor T 4 Gate of (d) and sixth NMOS transistor T 6 Is connected with the grid electrode of the power supply; input terminal B and thirteenth memristor M 13 Is connected to the negative electrode of the battery.
Eighth memristor M 8 Positive electrode of (a) and ninth memristor M 9 Positive electrode of (c) and fourteenth memristor M 14 Is connected with the positive electrode of the ninth memristor M 9 Is connected with the third memristor M 3 Positive electrode of (a) and third NMOS transistor T 3 Is connected with the drain electrode of the third memristor M 3 Is connected with the power supply V DD Connected with a third NMOS tube T 3 With power supply-V DD Are connected.
Fourth memristor M 4 Positive electrode of (a) and fourth NMOS tube T 4 Drain electrode of (d) and fifth NMOS transistor T 5 A fourth NMOS tube T connected with the source electrode 4 Source of (d) and power supply V DD Connected with a fifth NMOS tube T 5 Gate and power supply V of (2) DD And a fifth memristor M 5 Is connected with the cathode of the fifth memristor M 5 Positive electrode of (a) and fifth NMOS tube T 5 And a tenth memristor M 10 Is connected with the cathode of the tenth memristor M 10 The positive electrode of (a) and the eleventh memristor M 11 Positive electrode of (a) and fifteenth memristor M 15 An eleventh memristor M is connected with the positive electrode of 11 The negative electrode of (2) is grounded.
Sixth memristor M 6 Is connected with the power supply V DD The positive electrode is connected with the sixth NMOS tube T at the same time 6 Drain electrode of (d) and seventh NMOS transistor T 7 Gate of (C) is connected with a seventh NMOS tube T 7 Drain of (d) and seventh memristor M 7 Positive electrode of (c) and twelfth memristor M 12 Is connected with the negative electrode of the seventh memristor M 7 Is connected with the power supply V DD Connected with a sixth NMOS tube T 6 Seventh NMOS tube T 7 Source and supply-V of (2) DD Connected to a twelfth memristor M 12 Positive electrode of (c) and thirteenth memristor M 13 Positive electrode of (c) and sixteenth memristor M 16 Is connected to the positive electrode of the battery.
Fourteenth memristor M 14 Is the negative pole of the fifteenth memristor M 15 Is of (c) and sixteenth memristor M 16 Is connected to the negative electrode of the capacitor to obtain an output MUL.
Balanced three-value multiplexer circuit, when input is logic-1, output signal of balanced three-value multiplexer circuit is I -1 The method comprises the steps of carrying out a first treatment on the surface of the When the input is logic 0, the output signal of the balanced three-value multiplexer circuit is I 0 The method comprises the steps of carrying out a first treatment on the surface of the When the input is logic 1, the output signal of the balanced three-value multiplexer circuit is I 1 。
The invention has the following characteristics and beneficial effects:
the balanced three-valued multiplier circuit based on the multiplexer of the memristor and the single-variable logic circuit has the characteristics of clear and simple structure through modularized design. Specifically, the whole circuit only uses seven MOS transistors and sixteen memristors, and compared with other memristor-based half adder design methods, the whole circuit has the advantage that the number of used circuit elements is small. In addition, the power consumption under the technical scheme is measured to be small, namely the dynamic power is only 4.56mW, which has important significance for application research of the three-value logic circuit.
Drawings
FIG. 1 is a block diagram of a balanced three-valued multiplier circuit based on memristors of the present disclosure;
FIG. 2 is a schematic diagram of a balanced three-valued multiplier circuit based on memristors in accordance with the present disclosure.
Detailed Description
The preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The circuit block diagram of the memristor-based balanced three-value multiplier designed by the invention is shown in figure 1, and is composed of a balanced three-value single-variable logic circuit F 22 And a MUX3:1 circuit. The logic state in the circuit is the voltage value, where V DD 1V, pairShould logic "1"; GND is 0V, corresponding to logic "0"; V-V DD is-1V, corresponding to logic "-1". The truth table of the balanced three-valued multiplier designed by the invention is shown in the following table 1:
TABLE 1
Where a and B represent two input signals and MUL represents the output signal of the multiplier.
When the input signals A, B are all logical "-1", the input terminals A, B are all connected to-V DD Single variable logic circuit U 1 The output of (a) is a logic "1", multiplexer circuit U 2 Is gated as I -1 The logic value of the output signal MUL is I -1 Is a logical value of "1".
When the input signals A, B are respectively logical "-1" and "-0", the input terminals A, B are respectively connected to-V DD GND, single variable logic circuit U 1 The output of (a) is a logic "0", multiplexer circuit U 2 Is gated as I -1 The logic value of the output signal MUL is I -1 Is "0".
When the input signals A, B are respectively logical "-1" and "-1", the input terminals A, B are respectively connected to-V DD 、V DD Single variable logic circuit U 1 The output of (a) is a logical "-1", multiplexer circuit U 2 Is gated as I -1 The logic value of the output signal MUL is I -1 A logical value of "-1").
When the input signals A, B are respectively logic "0" and "1", i.e. the input terminals A, B are respectively connected to GND and-V DD Single variable logic circuit U 1 The output of (a) is a logic "1", multiplexer circuit U 2 Is gated as I 0 The logic value of the output signal MUL is I 0 Is "0".
When the input signals A, B are all logic "0", i.e. the input terminals A, B are all connected to GND, the single-variable logic circuit U 1 The output of (a) is a logic "0", multiplexer circuit U 2 Is gated as I 0 The logic value of the output signal MUL is I 0 Is "0".
When the input signal A, B is respectively logic "0" and "1", the input terminal A, B is respectively connected to GND and V DD Single variable logic circuit U 1 The output of (a) is a logical "-1", multiplexer circuit U 2 Is gated as I 0 The logic value of the output signal MUL is I 0 Is "0".
When the input signals A, B are respectively logic "1" and "1", the input terminals A, B are respectively connected to V DD 、-V DD Single variable logic circuit U 1 The output of (a) is a logic "1", multiplexer circuit U 2 Is gated as I 1 The logic value of the output signal MUL is I 1 A logical value of "-1").
When the input signals A, B are respectively logical "1" and "0", the input terminals A, B are respectively connected to V DD GND, single variable logic circuit U 1 The output of (a) is a logic "0", multiplexer circuit U 2 Is gated as I 1 The logic value of the output signal MUL is I 1 Is "0".
When the input signals A, B are all logic "1" and "1", the input terminals A, B are all connected to V DD Single variable logic circuit U 1 The output of (a) is a logical "-1", multiplexer circuit U 2 Is gated as I 1 The logic value of the output signal MUL is I 1 Is a logical value of "1".
From the relationship between the inputs and outputs of the truth table of the balanced three-valued multiplier described above, a detailed circuit structure of the balanced three-valued multiplier circuit block diagram shown in fig. 1 can be constructed, as shown in fig. 2.
For a balanced three-valued multiplier circuit, the input A and the fourth memristor M 4 Is a negative electrode of the third NMOS tube T 3 Gate of (d), fourth NMOS transistor T 4 Gate of (d) and sixth NMOS transistor T 6 Is connected with the grid electrode of the power supply; input terminal B and first NMOS tube T 1 Gate of (2), second NMOS transistor T 2 Gate of (c) and thirteenth memristor M 13 Is connected to the negative electrode of the battery.
First memristor M 1 Is connected with the power supply V DD The positive electrode is connected with the second memristor M at the same time 2 Is a negative electrode of the first NMOS tube T 1 Is connected with the drain electrode of M8, and a second memristor M 2 Positive electrode of (a) and a second NMOS tube T 2 Is connected with the drain electrode of the first NMOS tube T 1 And a second NMOS tube T 2 Source and supply-V of (2) DD Connected with an eighth memristor M 8 Positive electrode of (a) and ninth memristor M 9 Positive electrode of (c) and fourteenth memristor M 14 Is connected with the positive electrode of the ninth memristor M 9 Is connected with the third memristor M 3 Positive electrode of (a) and third NMOS transistor T 3 Is connected with the drain electrode of the third memristor M 3 Is connected with the power supply V DD Connected with a third NMOS tube T 3 With power supply-V DD Are connected.
Fourth memristor M 4 Positive electrode of (a) and fourth NMOS tube T 4 Drain electrode of (d) and fifth NMOS transistor T 5 A fourth NMOS tube T connected with the source electrode 4 Source of (d) and power supply V DD Connected with a fifth NMOS tube T 5 Gate and power supply V of (2) DD And a fifth memristor M 5 Is connected with the cathode of the fifth memristor M 5 Positive electrode of (a) and fifth NMOS tube T 5 And a tenth memristor M 10 Is connected with the cathode of the tenth memristor M 10 The positive electrode of (a) and the eleventh memristor M 11 Positive electrode of (a) and fifteenth memristor M 15 An eleventh memristor M is connected with the positive electrode of 11 The negative electrode of (2) is grounded.
Sixth memristor M 6 Is connected with the power supply V DD The positive electrode is connected with the sixth NMOS tube T at the same time 6 Drain electrode of (d) and seventh NMOS transistor T 7 Gate of (C) is connected with a seventh NMOS tube T 7 Drain of (d) and seventh memristor M 7 Positive electrode of (c) and twelfth memristor M 12 Is connected with the negative electrode of the seventh memristor M 7 Is connected with the power supply V DD Connected with a sixth NMOS tube T 6 Seventh NMOS tube T 7 Source and supply-V of (2) DD Connected to a twelfth memristor M 12 Positive electrode of (c) and thirteenth memristor M 13 Positive electrode of (c) and sixteenth memristor M 16 Is connected to the positive electrode of the battery.
Fourteenth memristor M 14 Is the negative pole of the fifteenth memristor M 15 Is of (c) and sixteenth memristor M 16 Is connected to the negative electrode of the capacitor to obtain an output MUL.
It will be appreciated by persons skilled in the art that the above embodiments are merely for the purpose of verifying the invention, and are not intended to limit the invention, and that changes and modifications to the above embodiments fall within the scope of the invention as long as they fall within the scope of the invention.

Claims (5)

1. The balanced three-valued multiplier circuit based on the memristor is characterized by comprising a balanced three-valued single-variable logic circuit F 22 A balanced three-value multiplexer circuit;
one path of input signal B is input into the balanced three-value multiplexer circuit, and the other path passes through the balanced three-value single-variable logic circuit F 22 Later, input balanced three-value multiplexer circuit;
the input signal a is directly input to the balanced three-value multiplexer circuit, and the balanced three-value multiplexer circuit output is the output of the balanced three-value multiplexer circuit.
2. The memristor-based balanced three-valued multiplier circuit of claim 1, wherein the balanced three-valued multiplexer circuit comprises fourteen memristors and five MOS transistors, in particular as follows:
input terminal A and fourth memristor M 4 Is a negative electrode of the third NMOS tube T 3 Gate of (d), fourth NMOS transistor T 4 Gate of (d) and sixth NMOS transistor T 6 Is connected with the grid electrode of the power supply; input terminal B and thirteenth memristor M 13 Is connected with the negative electrode of the battery;
eighth memristor M 8 Positive electrode of (a) and ninth memristor M 9 Positive electrode of (c) and fourteenth memristor M 14 Is connected with the positive electrode of the ninth memristor M 9 Is connected with the third memristor M 3 Positive electrode of (a) and third NMOS transistor T 3 Is connected with the drain electrode of the third memristor M 3 Is connected with the power supply V DD Connected with a third NMOS tube T 3 With power supply-V DD Are connected;
fourth memristor M 4 Positive electrode of (a) and fourth NMOS tube T 4 Drain electrode of (d) and fifth NMOS transistor T 5 A fourth NMOS tube T connected with the source electrode 4 Source of (d) and power supply V DD Connected with a fifth NMOS tube T 5 Gate and power supply V of (2) DD And a fifth memristor M 5 Is connected with the cathode of the fifth memristor M 5 Positive electrode of (a) and fifth NMOS tube T 5 And a tenth memristor M 10 Is connected with the cathode of the tenth memristor M 10 The positive electrode of (a) and the eleventh memristor M 11 Positive electrode of (a) and fifteenth memristor M 15 An eleventh memristor M is connected with the positive electrode of 11 Is grounded;
sixth memristor M 6 Is connected with the power supply V DD The positive electrode is connected with the sixth NMOS tube T at the same time 6 Drain electrode of (d) and seventh NMOS transistor T 7 Gate of (C) is connected with a seventh NMOS tube T 7 Drain of (d) and seventh memristor M 7 Positive electrode of (c) and twelfth memristor M 12 Is connected with the negative electrode of the seventh memristor M 7 Is connected with the power supply V DD Connected with a sixth NMOS tube T 6 Seventh NMOS tube T 7 Source and supply-V of (2) DD Connected to a twelfth memristor M 12 Positive electrode of (c) and thirteenth memristor M 13 Positive electrode of (c) and sixteenth memristor M 16 Is connected with the positive electrode of the battery;
fourteenth memristor M 14 Is the negative pole of the fifteenth memristor M 15 Is of (c) and sixteenth memristor M 16 Is connected to the negative electrode of the capacitor to obtain an output MUL.
3. The memristor-based balanced three-valued multiplier circuit of claim 2, wherein the balanced three-valued single-variable logic circuit F 22 The memristor comprises two memristors and two MOS transistors, and is specifically as follows:
input terminal B and first NMOS tube T 1 Gate of (2), second NMOS transistor T 2 Is connected with the grid electrode of the power supply; first memristorM 1 Is connected with the power supply V DD The positive electrode is connected with the second memristor M at the same time 2 Is a negative electrode of the first NMOS tube T 1 Is connected with the drain electrode of M8, and a second memristor M 2 Positive electrode of (a) and a second NMOS tube T 2 Is connected with the drain electrode of the first NMOS tube T 1 And a second NMOS tube T 2 Source and supply-V of (2) DD Are connected.
4. A memristor-based balanced three-valued multiplier circuit as claimed in any one of claims 1 to 3, characterized by a balanced three-valued single variable logic circuit F 22 When the input is logic-1, circuit F 22 The output signal of (2) is 1; when the input is logic 0, circuit F 22 The output signal of (2) is 0; when the input is logic 1, circuit F 22 The output signal of (2) is-1.
5. The memristor-based balanced three-valued multiplier circuit of claim 4, wherein when the balanced three-valued multiplexer circuit input is a logic-1, the output signal of the balanced three-valued multiplexer circuit is I -1 The method comprises the steps of carrying out a first treatment on the surface of the When the input is logic 0, the output signal of the balanced three-value multiplexer circuit is I 0 The method comprises the steps of carrying out a first treatment on the surface of the When the input is logic 1, the output signal of the balanced three-value multiplexer circuit is I 1 。
CN202311272100.5A 2023-09-27 2023-09-27 Memristor-based balanced three-value multiplier circuit Pending CN117215522A (en)

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