CN202617076U - Early termination asynchronous comparator - Google Patents

Early termination asynchronous comparator Download PDF

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CN202617076U
CN202617076U CN 201220161907 CN201220161907U CN202617076U CN 202617076 U CN202617076 U CN 202617076U CN 201220161907 CN201220161907 CN 201220161907 CN 201220161907 U CN201220161907 U CN 201220161907U CN 202617076 U CN202617076 U CN 202617076U
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asynchronous
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input
comparison unit
termination
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姜小波
叶德盛
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South China University of Technology SCUT
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Abstract

本实用新型公开了一种提前终止异步比较器，由至少一个两位异步比较单元及一个终止判断电路构成，两个以上的异步比较单元级联后与终止判断电路构成多位终止异步比较器；所述异步比较单元级联后，每个两位异步比较单元的小于信号输出端、大于信号输出端与终止判断电路的输入端连接，异步比较单元的相等信号输出端从高位到低位依次连接，最低位异步比较单元的相等信号输出端与终止判断电路的相等信号输入端连接，所述终止判断电路输出大于或相等信号、完成信号、小于信号输出端；本实用新型利用异步电路结构的特点，通过统一的信号和终止判断电路，可以控制数据的计算，减少不必要的运算，相比于同步比较器，降低了功耗。

The utility model discloses an early-termination asynchronous comparator, which is composed of at least one two-bit asynchronous comparison unit and a termination judgment circuit, and more than two asynchronous comparison units are cascaded together with the termination judgment circuit to form a multi-bit termination asynchronous comparator; After the asynchronous comparison unit is cascaded, the less than signal output terminal and the greater than signal output terminal of each two-bit asynchronous comparison unit are connected to the input terminal of the termination judgment circuit, and the equal signal output terminals of the asynchronous comparison unit are sequentially connected from high to low, The equal signal output end of the lowest bit asynchronous comparison unit is connected with the equal signal input end of the termination judgment circuit, and the termination judgment circuit outputs a greater than or equal signal, a completion signal, and a less than signal output end; the utility model utilizes the characteristics of the asynchronous circuit structure, Through the unified signal and termination judgment circuit, the calculation of data can be controlled, unnecessary calculation can be reduced, and the power consumption is reduced compared with the synchronous comparator.

Description

The asynchronous comparator of a kind of premature termination
Technical field
The utility model relates to electronic technology field, the asynchronous comparator of particularly a kind of premature termination.
Background technology
Along with IC design gets into the deep submicron process technology, power consumption becomes the factor that people consider and pay close attention to gradually.The particularly quick growth of personal computing devices and mobile communication terminal presses for through Low-power Technology and reduces packaging cost and improve reliability of products.Therefore low power dissipation design becomes an important directions of IC design, through from system design, logical design to physical Design and the whole IC design flow process that realizes of technology.On the other hand, the low power dissipation design of basic processing unit is the important content of low power dissipation design.Comparator is the important basic processing unit of digital system, and traditional comparator power consumed is bigger.The low power dissipation design of comparator is significant for the power consumption that reduces system.
Sync comparator is parallel computation, as long as input is arranged, all data all can walk abreast and carry out computing, obtain comparative result at last.That is to say that each data of input all can be carried out computing.But according to the knowledge of probability theory, two random numbers compare, and preceding 3 probability that just can compare the result reach 87.5%.Along with the increase of bit wide, therefore the computing that sync comparator has increasing numerical digit there is no need has consumed increasing power consumption.
To this problem, press for the comparator of a kind of low-power consumption of design, fundamentally reduce the number of times of comparison operation, thereby reduce power consumption.
The utility model content
The purpose of the utility model is to overcome the shortcoming and deficiency that prior art exists, and the utility model proposes the asynchronous comparator of a kind of premature termination, and the utility model can directly apply to the asynchronous LDPC decoder of low-power consumption.
The utility model adopts following technical scheme:
The asynchronous comparator of a kind of premature termination is made up of at least one two asynchronous comparing unit and a termination decision circuitry; Constitute multidigit with the termination decision circuitry after the plural asynchronous comparing unit cascade and stop asynchronous comparator; After the said asynchronous comparing unit cascade; Each two asynchronous comparing unit less than signal output part, be connected with the input that stops decision circuitry greater than signal output part; The equal signal output of asynchronous comparing unit connects from a high position to the low level successively; The equal signal output of the asynchronous comparing unit of lowest order is connected with the equal signal input that stops decision circuitry; Said termination decision circuitry be output as the asynchronous comparator of said premature termination greater than or equal signal, completion signal, less than signal output part, signal to be detected is input to the input of asynchronous comparing unit;
The precharging signal end of said asynchronous comparing unit is connected with the precharging signal end that stops decision circuitry;
Said asynchronous comparing unit is made up of PMOS pipe, NMOS pipe, inverter 1, inverter 2, inverter 3; Said P representes the PMOS pipe, and N representes the NMOS pipe; P wherein 1, P 2, P 3, P 4, P 5, P 6Source electrode connect power supply, P 2, P 3, P 5, N 20Grid connect precharging signal, N 20Source class ground connection;
P 1, P 2, N 1, N 3Drain electrode and the input of inverter 1 join P 1Grid and the output of inverter 1 join, as output greater than signal;
P 3, P 4, N 6Drain electrode and the input of inverter 2 join P 4Grid and the output of inverter 2 join, as the output of equal signal;
P 5, P 6,N 15, N 18Drain electrode and the input of inverter 3 join P 6Grid and the output of inverter 3 join, as output less than signal;
N 3, N 6, N 15Grid connect input as equal signal;
N 4And N 9Grid connect input as asynchronous comparing unit A 0 , N 1And N 13Grid connect the input of asynchronous comparing unit A 1
N 10And N 17Grid connect the input of asynchronous comparing unit B 0 , N 14And N 19Grid connect the input of asynchronous comparing unit B 1 , N 7And N 16Grid connect the input of asynchronous comparing unit , N 11And N 18Grid connect the input of asynchronous comparing unit
Figure 722DEST_PATH_IMAGE002
, N 5And N 8Grid connect the input of asynchronous comparing unit
Figure 353206DEST_PATH_IMAGE003
, N 2And N 12Grid connect the input of asynchronous comparing unit
Figure 358071DEST_PATH_IMAGE004
, N 1Source electrode and N 2Drain electrode join N 3Source electrode and N 4Drain electrode join N 4Source electrode and N 5Drain electrode join N 6Source electrode and N 7And N 9Drain electrode join N 7Source electrode and N 8Drain electrode join N 9Source electrode and N 10Drain electrode join N 15Source electrode and N 16Drain electrode join N 16Source electrode and N 17Drain electrode join N 5, N 8, N 10, N 17Source electrode and N 11, N 13Drain electrode join N 11Source electrode and N 12Drain electrode join N 13Source electrode and N 14Drain electrode join N 2, N 12, N 14, N 19Source electrode and N 20Drain electrode join N 20Source ground.
Said termination decision circuitry comprise output greater than or the dynamic logic circuit of equal signal, output less than dynamic logic circuit and a logic sum gate of signal, the output of said two dynamic logic circuits is connected respectively to the input of logic sum gate.
The beneficial effect of the utility model:
The utility model utilizes the characteristics of asynchronous circuit structure, through unified signal with stop decision circuitry, calculating that can control data reduces unnecessary computing.Simultaneously, the asynchronous comparator that the asynchronous comparator of being made up of two asynchronous comparing unit is formed than other modes has more the advantage of speed and power consumption aspect.Therefore, than sync comparator, the utility model has reduced power consumption.
Description of drawings
Fig. 1 is the sketch map of the asynchronous comparator of a kind of premature termination;
Fig. 2 is the structure chart of the asynchronous comparator of a kind of premature termination;
Fig. 3 is the structure chart of two asynchronous comparing units among Fig. 2;
Fig. 4 is the structure chart that stops decision circuitry among Fig. 2.
Embodiment
Below in conjunction with embodiment and accompanying drawing, the utility model is done to specify further, but the execution mode of the utility model is not limited thereto.
Embodiment
The sketch map of the asynchronous comparator of a kind of premature termination as shown in Figure 1: input signal is precharging signal PRE, the first input signal Data1, the second input signal Data2; Wherein precharging signal PRE is the signal of control circuit work, and the first input signal Data1 and the second input signal Data2 are the data-signals that need compare computing; Said output signal: accomplish signal DONE, greater than or equal signal output GT_or_EQ and less than signal output LT; Wherein accomplish signal DONE and represent that comparison operation accomplishes; Comparator is no longer worked; Greater than or equate that output signal GT or EQ representes first input signal more than or equal to second input signal, less than output signal indication first input signal less than second input signal.
Be illustrated in figure 2 as the structure chart of the asynchronous comparator of a kind of premature termination, constitute by at least one two asynchronous comparing unit and a termination decision circuitry; Constitute multidigit with the termination decision circuitry after the plural asynchronous comparing unit cascade and stop asynchronous comparator; After the said asynchronous comparing unit cascade; Each two asynchronous comparing unit less than signal output part LT, be connected with the input that stops decision circuitry greater than signal output part GT; The equal signal output EQ of asynchronous comparing unit connects from a high position to the low level successively; The equal signal output EQ of the asynchronous comparing unit of lowest order is connected with the equal signal input that stops decision circuitry; Said termination decision circuitry be output as the asynchronous comparator of said premature termination greater than or equal signal GT or EQ, accomplish signal DONE, less than signal output part LT, signal to be detected is input to the input Data of asynchronous comparing unit;
The precharging signal PRE end of said asynchronous comparing unit is connected with the precharging signal end PRE that stops decision circuitry;
First input signal and second input signal are as input signal; Be directly inputted in two asynchronous comparing units, begin computing, if the high position of the two equates from a high position; Then the equal signal EQ of this position output effectively is input in the asynchronous comparing unit of next bit and compares.If the two is high-order unequal, then equal signal EQ is output as 0, and the asynchronous comparing unit of all low levels of this back will can not carry out computing.Stop decision circuitry then according to all export, export less than the equal signal of signal output and lowest order greater than signal; Through computing; Produce to accomplish signal DONE, greater than or equal signal output GT or EQ and less than signal output, this circuit structure can guarantee following characteristics, for the input signal of many bits; If obtain the comparative result of first input signal and second input signal at high potential, so whole asynchronous comparator just can obtain corresponding result at once and accomplish signal.
Be illustrated in figure 4 as the structure chart that stops decision circuitry; Said termination decision circuitry comprise output greater than or the dynamic logic circuit of equal signal, output less than dynamic logic circuit and a logic sum gate of signal, the output of said two dynamic logic circuits is connected respectively to or the input of door.For greater than or equal signal GT or EQ output; Its pull-down circuit is a N+1 NMOS pipe in parallel; Connect with the NMOS pipe that a grid is a precharging signal; The grid of N wherein NMOS pipe is N respectively and (comprises greater than signal output GT [N-1] greater than the output signal; Greater than signal output GT [N-2];, greater than signal output GT [0]), the grid of another one NMOS pipe is equal signal output; For exporting less than signal LT; Its pull-down circuit is a N NMOS pipe in parallel; Connect with the NMOS pipe that a grid is a precharging signal; The grid of N wherein NMOS pipe be respectively N less than signal output (comprise less than signal output LT[N-1]; Less than signal output LT [N-2];, less than signal output LT [0]); The output of this two parts dynamic logic circuit is connected respectively to or door, produces at last to accomplish signal DONE.
Be illustrated in figure 3 as the structure chart of two asynchronous comparing units, said asynchronous comparing unit is made up of PMOS pipe, NMOS pipe, inverter 1, inverter 2, inverter 3; Said P representes the PMOS pipe, and N representes the NMOS pipe; P wherein 1, P 2, P 3, P 4, P 5, P 6Source electrode connect power supply, P 2, P 3, P 5, N 20Grid connect precharging signal, N 20Source class ground connection;
P 1, P 2, N 1, N 3Drain electrode and the input of inverter 1 join P 1Grid and the output of inverter 1 join, as output GT greater than signal;
P 3, P 4, N 6Drain electrode and the input of inverter 2 join P 4Grid and the output of inverter 2 join, as the output EQ of equal signal;
P 5, P 6,N 15, N 18Drain electrode and the input of inverter 3 join P 6Grid and the output of inverter 3 join, as output LT less than signal;
N 3, N 6, N 15Grid connect input EQ_in as equal signal;
N 4And N 9Grid connect input as asynchronous comparing unit A 0 , N 1And N 13Grid connect the input of asynchronous comparing unit A 1
N 10And N 17Grid connect the input of asynchronous comparing unit B 0 , N 14And N 19Grid connect the input of asynchronous comparing unit B 1 , N 7And N 16Grid connect the input of asynchronous comparing unit , N 11And N 18Grid connect the input of asynchronous comparing unit
Figure 216623DEST_PATH_IMAGE002
, N 5And N 8Grid connect the input of asynchronous comparing unit
Figure 751510DEST_PATH_IMAGE003
, N 2And N 12Grid connect the input of asynchronous comparing unit
Figure 864959DEST_PATH_IMAGE004
, N 1Source electrode and N 2Drain electrode join N 3Source electrode and N 4Drain electrode join N 4Source electrode and N 5Drain electrode join N 6Source electrode and N 7And N 9Drain electrode join N 7Source electrode and N 8Drain electrode join N 9Source electrode and N 10Drain electrode join N 15Source electrode and N 16Drain electrode join N 16Source electrode and N 17Drain electrode join N 5, N 8, N 10, N 17Source electrode and N 11, N 13Drain electrode join N 11Source electrode and N 12Drain electrode join N 13Source electrode and N 14Drain electrode join N 2, N 12, N 14, N 19Source electrode and N 20Drain electrode join N 20Source ground.
The realization function of two asynchronous comparing units is following: have one to be low level, this not computing of circuit when precharging signal perhaps equates input signal; When the input of precharging signal and equal signal was high level, circuit carried out work.If A 1 A 0 Greater than B 1 B 0 , then be output as high level greater than signal, equate the output signal and be low level less than signal output; If A 1 A 0 Less than B 1 B 0 , then be output as high level less than signal, be low level greater than signal output and equal signal output; If A 1 A 0 Equal B 1 B 0 , then equal signal is output as high level, is low level greater than signal output with less than signal output.
The foregoing description is the utility model preferred implementation; But the execution mode of the utility model is not limited by the examples; Other any do not deviate from change, the modification done under spirit and the principle of the utility model, substitutes, combination, simplify; All should be the substitute mode of equivalence, be included within the protection range of the utility model.

Claims (3)

1.一种提前终止异步比较器，其特征在于，由至少一个两位异步比较单元及一个终止判断电路构成；两个以上的异步比较单元级联后与终止判断电路构成多位终止异步比较器，所述异步比较单元级联后，每个两位异步比较单元的小于信号输出端、大于信号输出端与终止判断电路的输入端连接，异步比较单元的相等信号输出端从高位到低位依次连接，最低位异步比较单元的相等信号输出端与终止判断电路的相等信号输入端连接，所述终止判断电路输出为所述提前终止异步比较器的大于或相等信号、完成信号、小于信号输出端，待检测信号输入到异步比较单元的输入端； 1. An early termination asynchronous comparator is characterized in that it is composed of at least one two-position asynchronous comparison unit and a termination judgment circuit; more than two asynchronous comparison units are cascaded to form a multi-position termination asynchronous comparator with the termination judgment circuit , after the asynchronous comparison unit is cascaded, the less than signal output terminal and the greater than signal output terminal of each two-bit asynchronous comparison unit are connected to the input terminal of the termination judgment circuit, and the equal signal output terminals of the asynchronous comparison unit are sequentially connected from high to low , the equal signal output end of the lowest bit asynchronous comparison unit is connected to the equal signal input end of the termination judgment circuit, and the output of the termination judgment circuit is the greater than or equal signal, completion signal, and less than signal output end of the early termination asynchronous comparator, The signal to be detected is input to the input terminal of the asynchronous comparison unit;    所述异步比较单元的预充电信号端与终止判断电路的预充电信号端连接。 The precharge signal terminal of the asynchronous comparison unit is connected to the precharge signal terminal of the termination judgment circuit. 2.根据权利要求1所述的一种提前终止异步比较器，其特征在于，异步比较单元由PMOS管、NMOS管、反相器1、反相器2、反相器3构成；所述P表示PMOS管，N表示NMOS管；其中P1、P2、P3、P4、P5、P6的源极接电源， P2、P3、P5、N20的栅极接预充电信号，N20的源级接地； 2. A kind of early termination asynchronous comparator according to claim 1, is characterized in that, asynchronous comparison unit is made of PMOS transistor, NMOS transistor, inverter 1, inverter 2, inverter 3; Said P Represents a PMOS transistor, N represents an NMOS transistor; the sources of P 1 , P 2 , P 3 , P 4 , P 5 , and P 6 are connected to the power supply, and the gates of P 2 , P 3 , P 5 , and N 20 are connected to the precharge Signal, source ground of N 20 ;  P1、P2、N1、N3的漏极与反相器1 的输入端相接，P1的栅极与反相器1的输出端相接，作为大于信号的输出端； The drains of P 1 , P 2 , N 1 , and N 3 are connected to the input terminal of the inverter 1, and the gate of P 1 is connected to the output terminal of the inverter 1 as the output terminal of the greater than signal; P3、P4、 N6的漏极与反相器2的输入端相接， P4的栅极与反相器2的输出端相接，作为相等信号的输出端； The drains of P 3 , P 4 , and N 6 are connected to the input terminal of the inverter 2, and the gate of P 4 is connected to the output terminal of the inverter 2 as the output terminal of the equal signal; P5、P6、 N15、N18的漏极与反相器3的输入端相接， P6的栅极与反相器3的输出端相接，作为小于信号的输出端； The drains of P 5 , P 6 , N 15 , and N 18 are connected to the input terminal of the inverter 3, and the gate of P 6 is connected to the output terminal of the inverter 3 as the output terminal of the less than signal; N3、N6 、N15的栅极连接作为相等信号的输入端； The gates of N 3 , N 6 , and N 15 are connected as input terminals of equal signals; N4和N9的栅极连接作为异步比较单元的输入A 0 ， N1和N13的栅极接异步比较单元的输入A 1 ； The gates of N4 and N9 are connected as the input A0 of the asynchronous comparison unit, and the gates of N1 and N13 are connected to the input A1 of the asynchronous comparison unit ; N10和N17的栅极接异步比较单元的输入B 0 ， N14和N19的栅极接异步比较单元的输入B 1 ， N7和N16的栅极接异步比较单元的输入                                                
Figure 2012201619072100001DEST_PATH_IMAGE001
， N11和N18的栅极接异步比较单元的输入， N5和N8的栅极接异步比较单元的输入
Figure DEST_PATH_IMAGE003
， N2和N12的栅极接异步比较单元的输入
Figure 657203DEST_PATH_IMAGE004
， N1的源极与N2的漏极相接， N3的源极与N4的漏极相接， N4的源极与N5的漏极相接， N6的源极与N7和N9的漏极相接， N7的源极与N8的漏极相接， N9的源极与N10的漏极相接， N15的源极与N16的漏极相接， N16的源极与N17的漏极相接， N5、N8、N10、N17的源极与N11、N13的漏极相接， N11的源极与N12的漏极相接， N13的源极与N14的漏极相接， N2、N12、N14、N19的源极与N20的漏极相接， N20的源极接地。 The gates of N 10 and N 17 are connected to the input B 0 of the asynchronous comparison unit, the gates of N 14 and N 19 are connected to the input B 1 of the asynchronous comparison unit, the gates of N 7 and N 16 are connected to the input of the asynchronous comparison unit
Figure 2012201619072100001DEST_PATH_IMAGE001
, the gates of N 11 and N 18 are connected to the input of the asynchronous comparison unit , the gates of N 5 and N 8 are connected to the input of the asynchronous comparison unit
Figure DEST_PATH_IMAGE003
, the gates of N2 and N12 are connected to the input of the asynchronous comparison unit
Figure 657203DEST_PATH_IMAGE004
, the source of N1 is connected to the drain of N2 , the source of N3 is connected to the drain of N4 , the source of N4 is connected to the drain of N5 , the source of N6 is connected to the N 7 is connected to the drain of N9 , the source of N7 is connected to the drain of N8 , the source of N9 is connected to the drain of N10 , the source of N15 is connected to the drain of N16 The source of N 16 is connected to the drain of N 17 , the sources of N 5 , N 8 , N 10 and N 17 are connected to the drains of N 11 and N 13 , the source of N 11 is connected to the drain of N 12 The drain of N 13 is connected to the drain of N 14 , the sources of N 2 , N 12 , N 14 , and N 19 are connected to the drain of N 20 , and the source of N 20 is grounded. 3.根据权利要求1所述一种提前终止异步比较器，其特征在于所述终止判断电路包括输出大于或相等信号的动态逻辑电路、输出小于信号的动态逻辑电路及一个逻辑或门，所述两个动态逻辑电路的输出端分别连接到或门的输入端。 3. A kind of early termination asynchronous comparator according to claim 1, it is characterized in that said termination judgment circuit comprises the dynamic logic circuit of output greater than or equal signal, the dynamic logic circuit of output less than signal and a logical OR gate, said The output terminals of the two dynamic logic circuits are respectively connected to the input terminals of the OR gate.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102638252A (en) * 2012-04-17 2012-08-15 华南理工大学 Early-terminated asynchronous comparator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102638252A (en) * 2012-04-17 2012-08-15 华南理工大学 Early-terminated asynchronous comparator

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