CN202617076U - Early termination asynchronous comparator - Google Patents

Early termination asynchronous comparator Download PDF

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CN202617076U
CN202617076U CN 201220161907 CN201220161907U CN202617076U CN 202617076 U CN202617076 U CN 202617076U CN 201220161907 CN201220161907 CN 201220161907 CN 201220161907 U CN201220161907 U CN 201220161907U CN 202617076 U CN202617076 U CN 202617076U
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asynchronous
signal
input
join
comparing unit
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姜小波
叶德盛
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South China University of Technology SCUT
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South China University of Technology SCUT
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Abstract

Disclosed in the utility model is an early termination asynchronous comparator that is formed by at least one two-bit asynchronous comparison unit and a termination determination circuit. To be specific, more than two asynchronous comparison units are in cascade connection and then the whole connection and the termination determination circuit form a multi-bit termination asynchronous comparator. After the cascade connection of the asynchronous comparison units, a less-than signal output terminal and a greater-than signal output terminal of each two-bit asynchronous comparison unit are connected with an input terminal of the termination determination circuit; equal signal output terminals of the asynchronous comparison units are successively connected from a high bit to a low bit; and an equal signal output of a lowest-bit asynchronous comparison unit is connected with an equal signal input terminal of the termination determination circuit. Besides, the termination determination circuit outputs are greater-than or equal signal, completion signal and less-than signal output terminals. According to the utility model, a characteristic of an asynchronous circuit structure is utilized; and data calculation is controlled by the unified signal and the termination determination circuit, so that unnecessary calculation is reduced. And compared with a synchronous comparator, the provided asynchronous comparator enables power consumption to be reduced.

Description

The asynchronous comparator of a kind of premature termination
Technical field
The utility model relates to electronic technology field, the asynchronous comparator of particularly a kind of premature termination.
Background technology
Along with IC design gets into the deep submicron process technology, power consumption becomes the factor that people consider and pay close attention to gradually.The particularly quick growth of personal computing devices and mobile communication terminal presses for through Low-power Technology and reduces packaging cost and improve reliability of products.Therefore low power dissipation design becomes an important directions of IC design, through from system design, logical design to physical Design and the whole IC design flow process that realizes of technology.On the other hand, the low power dissipation design of basic processing unit is the important content of low power dissipation design.Comparator is the important basic processing unit of digital system, and traditional comparator power consumed is bigger.The low power dissipation design of comparator is significant for the power consumption that reduces system.
Sync comparator is parallel computation, as long as input is arranged, all data all can walk abreast and carry out computing, obtain comparative result at last.That is to say that each data of input all can be carried out computing.But according to the knowledge of probability theory, two random numbers compare, and preceding 3 probability that just can compare the result reach 87.5%.Along with the increase of bit wide, therefore the computing that sync comparator has increasing numerical digit there is no need has consumed increasing power consumption.
To this problem, press for the comparator of a kind of low-power consumption of design, fundamentally reduce the number of times of comparison operation, thereby reduce power consumption.
The utility model content
The purpose of the utility model is to overcome the shortcoming and deficiency that prior art exists, and the utility model proposes the asynchronous comparator of a kind of premature termination, and the utility model can directly apply to the asynchronous LDPC decoder of low-power consumption.
The utility model adopts following technical scheme:
The asynchronous comparator of a kind of premature termination is made up of at least one two asynchronous comparing unit and a termination decision circuitry; Constitute multidigit with the termination decision circuitry after the plural asynchronous comparing unit cascade and stop asynchronous comparator; After the said asynchronous comparing unit cascade; Each two asynchronous comparing unit less than signal output part, be connected with the input that stops decision circuitry greater than signal output part; The equal signal output of asynchronous comparing unit connects from a high position to the low level successively; The equal signal output of the asynchronous comparing unit of lowest order is connected with the equal signal input that stops decision circuitry; Said termination decision circuitry be output as the asynchronous comparator of said premature termination greater than or equal signal, completion signal, less than signal output part, signal to be detected is input to the input of asynchronous comparing unit;
The precharging signal end of said asynchronous comparing unit is connected with the precharging signal end that stops decision circuitry;
Said asynchronous comparing unit is made up of PMOS pipe, NMOS pipe, inverter 1, inverter 2, inverter 3; Said P representes the PMOS pipe, and N representes the NMOS pipe; P wherein 1, P 2, P 3, P 4, P 5, P 6Source electrode connect power supply, P 2, P 3, P 5, N 20Grid connect precharging signal, N 20Source class ground connection;
P 1, P 2, N 1, N 3Drain electrode and the input of inverter 1 join P 1Grid and the output of inverter 1 join, as output greater than signal;
P 3, P 4, N 6Drain electrode and the input of inverter 2 join P 4Grid and the output of inverter 2 join, as the output of equal signal;
P 5, P 6,N 15, N 18Drain electrode and the input of inverter 3 join P 6Grid and the output of inverter 3 join, as output less than signal;
N 3, N 6, N 15Grid connect input as equal signal;
N 4And N 9Grid connect input as asynchronous comparing unit A 0 , N 1And N 13Grid connect the input of asynchronous comparing unit A 1
N 10And N 17Grid connect the input of asynchronous comparing unit B 0 , N 14And N 19Grid connect the input of asynchronous comparing unit B 1 , N 7And N 16Grid connect the input of asynchronous comparing unit , N 11And N 18Grid connect the input of asynchronous comparing unit
Figure 722DEST_PATH_IMAGE002
, N 5And N 8Grid connect the input of asynchronous comparing unit
Figure 353206DEST_PATH_IMAGE003
, N 2And N 12Grid connect the input of asynchronous comparing unit
Figure 358071DEST_PATH_IMAGE004
, N 1Source electrode and N 2Drain electrode join N 3Source electrode and N 4Drain electrode join N 4Source electrode and N 5Drain electrode join N 6Source electrode and N 7And N 9Drain electrode join N 7Source electrode and N 8Drain electrode join N 9Source electrode and N 10Drain electrode join N 15Source electrode and N 16Drain electrode join N 16Source electrode and N 17Drain electrode join N 5, N 8, N 10, N 17Source electrode and N 11, N 13Drain electrode join N 11Source electrode and N 12Drain electrode join N 13Source electrode and N 14Drain electrode join N 2, N 12, N 14, N 19Source electrode and N 20Drain electrode join N 20Source ground.
Said termination decision circuitry comprise output greater than or the dynamic logic circuit of equal signal, output less than dynamic logic circuit and a logic sum gate of signal, the output of said two dynamic logic circuits is connected respectively to the input of logic sum gate.
The beneficial effect of the utility model:
The utility model utilizes the characteristics of asynchronous circuit structure, through unified signal with stop decision circuitry, calculating that can control data reduces unnecessary computing.Simultaneously, the asynchronous comparator that the asynchronous comparator of being made up of two asynchronous comparing unit is formed than other modes has more the advantage of speed and power consumption aspect.Therefore, than sync comparator, the utility model has reduced power consumption.
Description of drawings
Fig. 1 is the sketch map of the asynchronous comparator of a kind of premature termination;
Fig. 2 is the structure chart of the asynchronous comparator of a kind of premature termination;
Fig. 3 is the structure chart of two asynchronous comparing units among Fig. 2;
Fig. 4 is the structure chart that stops decision circuitry among Fig. 2.
Embodiment
Below in conjunction with embodiment and accompanying drawing, the utility model is done to specify further, but the execution mode of the utility model is not limited thereto.
Embodiment
The sketch map of the asynchronous comparator of a kind of premature termination as shown in Figure 1: input signal is precharging signal PRE, the first input signal Data1, the second input signal Data2; Wherein precharging signal PRE is the signal of control circuit work, and the first input signal Data1 and the second input signal Data2 are the data-signals that need compare computing; Said output signal: accomplish signal DONE, greater than or equal signal output GT_or_EQ and less than signal output LT; Wherein accomplish signal DONE and represent that comparison operation accomplishes; Comparator is no longer worked; Greater than or equate that output signal GT or EQ representes first input signal more than or equal to second input signal, less than output signal indication first input signal less than second input signal.
Be illustrated in figure 2 as the structure chart of the asynchronous comparator of a kind of premature termination, constitute by at least one two asynchronous comparing unit and a termination decision circuitry; Constitute multidigit with the termination decision circuitry after the plural asynchronous comparing unit cascade and stop asynchronous comparator; After the said asynchronous comparing unit cascade; Each two asynchronous comparing unit less than signal output part LT, be connected with the input that stops decision circuitry greater than signal output part GT; The equal signal output EQ of asynchronous comparing unit connects from a high position to the low level successively; The equal signal output EQ of the asynchronous comparing unit of lowest order is connected with the equal signal input that stops decision circuitry; Said termination decision circuitry be output as the asynchronous comparator of said premature termination greater than or equal signal GT or EQ, accomplish signal DONE, less than signal output part LT, signal to be detected is input to the input Data of asynchronous comparing unit;
The precharging signal PRE end of said asynchronous comparing unit is connected with the precharging signal end PRE that stops decision circuitry;
First input signal and second input signal are as input signal; Be directly inputted in two asynchronous comparing units, begin computing, if the high position of the two equates from a high position; Then the equal signal EQ of this position output effectively is input in the asynchronous comparing unit of next bit and compares.If the two is high-order unequal, then equal signal EQ is output as 0, and the asynchronous comparing unit of all low levels of this back will can not carry out computing.Stop decision circuitry then according to all export, export less than the equal signal of signal output and lowest order greater than signal; Through computing; Produce to accomplish signal DONE, greater than or equal signal output GT or EQ and less than signal output, this circuit structure can guarantee following characteristics, for the input signal of many bits; If obtain the comparative result of first input signal and second input signal at high potential, so whole asynchronous comparator just can obtain corresponding result at once and accomplish signal.
Be illustrated in figure 4 as the structure chart that stops decision circuitry; Said termination decision circuitry comprise output greater than or the dynamic logic circuit of equal signal, output less than dynamic logic circuit and a logic sum gate of signal, the output of said two dynamic logic circuits is connected respectively to or the input of door.For greater than or equal signal GT or EQ output; Its pull-down circuit is a N+1 NMOS pipe in parallel; Connect with the NMOS pipe that a grid is a precharging signal; The grid of N wherein NMOS pipe is N respectively and (comprises greater than signal output GT [N-1] greater than the output signal; Greater than signal output GT [N-2];, greater than signal output GT [0]), the grid of another one NMOS pipe is equal signal output; For exporting less than signal LT; Its pull-down circuit is a N NMOS pipe in parallel; Connect with the NMOS pipe that a grid is a precharging signal; The grid of N wherein NMOS pipe be respectively N less than signal output (comprise less than signal output LT[N-1]; Less than signal output LT [N-2];, less than signal output LT [0]); The output of this two parts dynamic logic circuit is connected respectively to or door, produces at last to accomplish signal DONE.
Be illustrated in figure 3 as the structure chart of two asynchronous comparing units, said asynchronous comparing unit is made up of PMOS pipe, NMOS pipe, inverter 1, inverter 2, inverter 3; Said P representes the PMOS pipe, and N representes the NMOS pipe; P wherein 1, P 2, P 3, P 4, P 5, P 6Source electrode connect power supply, P 2, P 3, P 5, N 20Grid connect precharging signal, N 20Source class ground connection;
P 1, P 2, N 1, N 3Drain electrode and the input of inverter 1 join P 1Grid and the output of inverter 1 join, as output GT greater than signal;
P 3, P 4, N 6Drain electrode and the input of inverter 2 join P 4Grid and the output of inverter 2 join, as the output EQ of equal signal;
P 5, P 6,N 15, N 18Drain electrode and the input of inverter 3 join P 6Grid and the output of inverter 3 join, as output LT less than signal;
N 3, N 6, N 15Grid connect input EQ_in as equal signal;
N 4And N 9Grid connect input as asynchronous comparing unit A 0 , N 1And N 13Grid connect the input of asynchronous comparing unit A 1
N 10And N 17Grid connect the input of asynchronous comparing unit B 0 , N 14And N 19Grid connect the input of asynchronous comparing unit B 1 , N 7And N 16Grid connect the input of asynchronous comparing unit , N 11And N 18Grid connect the input of asynchronous comparing unit
Figure 216623DEST_PATH_IMAGE002
, N 5And N 8Grid connect the input of asynchronous comparing unit
Figure 751510DEST_PATH_IMAGE003
, N 2And N 12Grid connect the input of asynchronous comparing unit
Figure 864959DEST_PATH_IMAGE004
, N 1Source electrode and N 2Drain electrode join N 3Source electrode and N 4Drain electrode join N 4Source electrode and N 5Drain electrode join N 6Source electrode and N 7And N 9Drain electrode join N 7Source electrode and N 8Drain electrode join N 9Source electrode and N 10Drain electrode join N 15Source electrode and N 16Drain electrode join N 16Source electrode and N 17Drain electrode join N 5, N 8, N 10, N 17Source electrode and N 11, N 13Drain electrode join N 11Source electrode and N 12Drain electrode join N 13Source electrode and N 14Drain electrode join N 2, N 12, N 14, N 19Source electrode and N 20Drain electrode join N 20Source ground.
The realization function of two asynchronous comparing units is following: have one to be low level, this not computing of circuit when precharging signal perhaps equates input signal; When the input of precharging signal and equal signal was high level, circuit carried out work.If A 1 A 0 Greater than B 1 B 0 , then be output as high level greater than signal, equate the output signal and be low level less than signal output; If A 1 A 0 Less than B 1 B 0 , then be output as high level less than signal, be low level greater than signal output and equal signal output; If A 1 A 0 Equal B 1 B 0 , then equal signal is output as high level, is low level greater than signal output with less than signal output.
The foregoing description is the utility model preferred implementation; But the execution mode of the utility model is not limited by the examples; Other any do not deviate from change, the modification done under spirit and the principle of the utility model, substitutes, combination, simplify; All should be the substitute mode of equivalence, be included within the protection range of the utility model.

Claims (3)

1. the asynchronous comparator of premature termination is characterized in that, is made up of at least one two asynchronous comparing unit and a termination decision circuitry; Constitute multidigit with the termination decision circuitry after the plural asynchronous comparing unit cascade and stop asynchronous comparator; After the said asynchronous comparing unit cascade; Each two asynchronous comparing unit less than signal output part, be connected with the input that stops decision circuitry greater than signal output part; The equal signal output of asynchronous comparing unit connects from a high position to the low level successively; The equal signal output of the asynchronous comparing unit of lowest order is connected with the equal signal input that stops decision circuitry; Said termination decision circuitry be output as the asynchronous comparator of said premature termination greater than or equal signal, completion signal, less than signal output part, signal to be detected is input to the input of asynchronous comparing unit;
The precharging signal end of said asynchronous comparing unit is connected with the precharging signal end that stops decision circuitry.
2. the asynchronous comparator of a kind of premature termination according to claim 1 is characterized in that, asynchronous comparing unit is made up of PMOS pipe, NMOS pipe, inverter 1, inverter 2, inverter 3; Said P representes the PMOS pipe, and N representes the NMOS pipe; P wherein 1, P 2, P 3, P 4, P 5, P 6Source electrode connect power supply, P 2, P 3, P 5, N 20Grid connect precharging signal, N 20Source class ground connection;
P 1, P 2, N 1, N 3Drain electrode and the input of inverter 1 join P 1Grid and the output of inverter 1 join, as output greater than signal;
P 3, P 4, N 6Drain electrode and the input of inverter 2 join P 4Grid and the output of inverter 2 join, as the output of equal signal;
P 5, P 6,N 15, N 18Drain electrode and the input of inverter 3 join P 6Grid and the output of inverter 3 join, as output less than signal;
N 3, N 6, N 15Grid connect input as equal signal;
N 4And N 9Grid connect input as asynchronous comparing unit A 0 , N 1And N 13Grid connect the input of asynchronous comparing unit A 1
N 10And N 17Grid connect the input of asynchronous comparing unit B 0 , N 14And N 19Grid connect the input of asynchronous comparing unit B 1 , N 7And N 16Grid connect the input of asynchronous comparing unit
Figure 2012201619072100001DEST_PATH_IMAGE001
, N 11And N 18Grid connect the input of asynchronous comparing unit , N 5And N 8Grid connect the input of asynchronous comparing unit
Figure DEST_PATH_IMAGE003
, N 2And N 12Grid connect the input of asynchronous comparing unit
Figure 657203DEST_PATH_IMAGE004
, N 1Source electrode and N 2Drain electrode join N 3Source electrode and N 4Drain electrode join N 4Source electrode and N 5Drain electrode join N 6Source electrode and N 7And N 9Drain electrode join N 7Source electrode and N 8Drain electrode join N 9Source electrode and N 10Drain electrode join N 15Source electrode and N 16Drain electrode join N 16Source electrode and N 17Drain electrode join N 5, N 8, N 10, N 17Source electrode and N 11, N 13Drain electrode join N 11Source electrode and N 12Drain electrode join N 13Source electrode and N 14Drain electrode join N 2, N 12, N 14, N 19Source electrode and N 20Drain electrode join N 20Source ground.
3. according to the asynchronous comparator of the said a kind of premature termination of claim 1; It is characterized in that said termination decision circuitry comprise output greater than or the dynamic logic circuit of equal signal, output less than dynamic logic circuit and a logic sum gate of signal, the output of said two dynamic logic circuits is connected respectively to or the input of door.
CN 201220161907 2012-04-17 2012-04-17 Early termination asynchronous comparator Expired - Fee Related CN202617076U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102638252A (en) * 2012-04-17 2012-08-15 华南理工大学 Early-terminated asynchronous comparator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102638252A (en) * 2012-04-17 2012-08-15 华南理工大学 Early-terminated asynchronous comparator

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