CN109756207A - A kind of TSPC edge triggered flip flop with automatic feedback gated clock - Google Patents
A kind of TSPC edge triggered flip flop with automatic feedback gated clock Download PDFInfo
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- CN109756207A CN109756207A CN201811390164.4A CN201811390164A CN109756207A CN 109756207 A CN109756207 A CN 109756207A CN 201811390164 A CN201811390164 A CN 201811390164A CN 109756207 A CN109756207 A CN 109756207A
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Abstract
The present invention relates to a kind of TSPC edge triggered flip flops with automatic feedback gated clock, automatic feedback door control clock circuit is integrated in TSPC edge triggered flip flop internal circuit, XOR logic is realized using circuit topological structure, and using transmission gate replacement and gate logic, a kind of low-power consumption TSPC edge triggered flip flop with automatic feedback gated clock function is formd.Compared with the TSPC trigger of standard, trigger dynamic power consumption of the invention is lower, and changes to clock frequency insensitive.In the identical situation of digital circuit scale, using TSPC edge triggered flip flop proposed by the present invention compared with existing gate controlled clock unit technology, the digital integrated electronic circuit chip area of generation is smaller, can also reduce rear end design complexities.
Description
Technical field
The invention belongs to digital standard unit fields in ultra-large digital integrated electronic circuit, are related to a kind of with automatic feedback
The TSPC edge triggered flip flop of gated clock is a kind of Novel low power consumption d type flip flop.
Background technique
The circuit topological structure of TSPC edge triggered flip flop is as shown in Figure 1, be shown in document: B.Razavi, " TSPC Logic-A
Circuit for All Seasons, " IEEE Solid-State Circuits Magazine, vol.8, no.4, pp.10-
13,2016；The first order is the phase inverter of a PMOS tube clock, and the second level is dynamic inverter, and the third level is by NMOS tube clock
The phase inverter of control.The specific working principle is as follows: when CLK is low level, input inverter is defeated in the D of nodes X up-sampling reverse phase
Enter.The dynamic inverter of the second level is in pre-charge state.When CLK rising edge arrives, second level phase inverter evaluation.If X
It is high level at CLK rising edge, then node Y discharges.When CLK is high level, third level phase inverter evaluation, on Y node
Value be output to QN.Q is obtained by fourth stage phase inverter.
Relative to common hypotactic d type flip flop, TSPC edge triggered flip flop structure is simpler, and speed is faster.But it works
When this edge triggered flip flop it is more demanding to clock slope because the slow clock of variation can make clock PMOS and NMOS tube while lead
It is logical, to increase dynamic power consumption.
In order to reduce the dynamic power consumption of the digital circuit based on TSPC edge triggered flip flop, gate controlled clock unit is generally used.
Gated clock can actively close flip-flop operation clock so that its in the state of not needing without overturning, be finally reached
Reduce the purpose of dynamic power consumption.Gate controlled clock unit can be divided into the gate controlled clock unit without latch and the door based on latch
Control clock unit.In door control clock circuit without latch, by one and door/or Men Shixian, circuit is simple, but signal holds
It is also easy to produce burr.This problem can be solved with based on the gate controlled clock unit circuit of latch.Document discloses one kind in [2]
Gating structure is fed back, as shown in Fig. 2, seeing document: A Enwanweike Venus, a kind of " digital circuits section, " China,
2015.；Also standard XOR gate and and Men Shixian are used.In actual use, these gate controlled clock units are all gate level circuits, in number
When word circuit rear end is comprehensive, script reality can be passed through by gate controlled clock unit circuit production at a part of digital standard cell library
The gating strategy of existing digital circuit blocks.After gate controlled clock unit is added, the rear end design of digital circuit needs to be laid out cloth again
The workload of line and post-simulation, the Design of Digital Circuit for being increases.
Summary of the invention
Technical problems to be solved
In order to avoid the shortcomings of the prior art, the present invention proposes a kind of side TSPC with automatic feedback gated clock
Along trigger, power consumption can be further decreased, and simplifies rear end design cycle.
Technical solution
A kind of TSPC edge triggered flip flop with automatic feedback gated clock, it is characterised in that including 27 metal-oxide-semiconductors, M1~
M11 constitutes one with the TSPC edge triggered flip flop resetted, and M12 and M13, M14 and M15 separately constitute two phase inverters, and M16~
M23 constitutes XOR logic unit, and M24 and M25 form phase inverter, M26 and M27 group gated transmission gate cell；M1 source electrode connects
VSS, drain electrode are connected with M2 drain electrode, and M2 source electrode and M3 drain electrode connect, and M3 source electrode connects VDD；M4 source electrode connects VSS, drain electrode and the source M5
Pole connection, M5 drain electrode are connected with M6 drain electrode, and M6 source electrode connects VDD；M7 source electrode meets VSS, and drain electrode connect with M8 source electrode, M8 drain and
The connection of M9 source electrode, M9 drain electrode are connected with M10 drain electrode, and M10 source electrode connects VDD；M12 source electrode meets VSS, and drain electrode is connected with M13 drain electrode,
M13 source electrode connects VDD；M14 source electrode meets VSS, and M14 drain electrode is connected with M15 drain electrode, and M15 source electrode connects VDD；M16 source electrode meets VSS,
Drain electrode is connect with M17 source electrode, and M17 drain electrode is connected with M18 drain electrode, and M18 source electrode and M19 drain electrode connect, and M19 source electrode connects VDD；
M20 source electrode meets VSS, and drain electrode is connect with M21 source electrode, and M21 drain electrode is connected with M22 drain electrode, and M22 source electrode and M23 drain electrode connect, M23
Source electrode connects VDD；M24 source electrode meets VSS, and drain electrode is connected with M25 drain electrode, and M25 source electrode connects VDD；M1, M3, M12, M13, M16 and
It is connect after M23 gate connected in parallel with input D signal, M1 drain electrode is connect with M5 grid, and M5 drain electrode is connect with M8 and M10 grid, M9 leakage
Pole drains with M11 and M14, M15, M20 and M21 grid are connect, and M14 drain electrode is connect with M17 and M18 grid, M17 and M21 leakage
Pole is connect with the grid of M25, M24 and M26；M24 drain electrode is connect with M27 grid；After M26 and M27 sources connected in parallel with M9, M4, M6
It is connected with M2 grid；The drain electrode of M26 and M27 connects, and exports CLK signal；The gate connected in parallel and DN of M12 drain electrode and M19 and M20；
M7 is connect with M11 gate connected in parallel with RST.
Beneficial effect
A kind of TSPC edge triggered flip flop with automatic feedback gated clock proposed by the present invention, when automatic feedback is gated
Clock circuit integration realizes XOR logic in TSPC edge triggered flip flop internal circuit, using circuit topological structure, and uses biography
Defeated door replaces and gate logic, forms a kind of low-power consumption TSPC edge triggered flip flop with automatic feedback gated clock function.With
The TSPC trigger of standard is compared, and trigger dynamic power consumption of the invention is lower, and is changed to clock frequency insensitive.In number
In the identical situation of circuit scale, TSPC edge triggered flip flop proposed by the present invention and existing gate controlled clock unit technology phase are used
Than the digital integrated electronic circuit chip area of generation is smaller, can also reduce rear end design complexities.
1) innovative point of the invention is specifically included that using 8 simplified pipe NOR gate circuit topological structures, manage instead of tradition 10
NOR gate circuit reduces the area of element circuit.2) using the replacement of transmission gate cell and gate cell, unit has been further reduced
The area of circuit.3) newly-designed Clock gating is encapsulated in TSPC edge triggered flip flop, by extract the unit line and
Electric information can be fabricated to standard digital circuitry unit, and the rear end for digital integration integrated circuit is comprehensive.It is new by calling
Type TSPC flip-flop element can be such that the digital integrated electronic circuit rear end of low-power consumption designs easier.
Detailed description of the invention
Fig. 1 is TSPC d type flip flop；
Fig. 2 is a kind of digital circuits section (2015)；
Fig. 3 is the TSPC edge triggered flip flop schematic diagram proposed by the present invention with automatic gated clock；
Fig. 4 is TSPC edge triggered flip flop Transient result standard TSPC edge triggered flip flop and of the invention；
When Fig. 5 is D toggle frequency 50MHz, two kinds of d type flip flop power consumption comparisons；
Fig. 6 is clock frequency when being 1GHz, two kinds of d type flip flop power consumptions comparisons.
Specific embodiment
Now in conjunction with embodiment, attached drawing, the invention will be further described:
The present invention has weighed the factor of area, power consumption and design difficulty etc., proposes a kind of with automatic feedback door
The TSPC edge triggered flip flop novel circuit structure of clock is controlled, schematic diagram is as shown in Figure 3.
Connection relationship are as follows:
M1 source electrode meets VSS, and drain electrode is connected with M2 drain electrode, and M2 source electrode and M3 drain electrode connect, and M3 source electrode connects VDD；M4 source electrode
VSS is met, drain electrode is connect with M5 source electrode, and M5 drain electrode is connected with M6 drain electrode, and M6 source electrode connects VDD；M7 source electrode meets VSS, drain electrode and M8
Source electrode connection, M8 drain electrode are connect with M9 source electrode, and M9 drain electrode is connected with M10 drain electrode, and M10 source electrode connects VDD；M12 source electrode meets VSS,
Drain electrode is connected with M13 drain electrode, and M13 source electrode connects VDD；M14 source electrode meets VSS, and M14 drain electrode is connected with M15 drain electrode, and M15 source electrode connects
Meet VDD；M16 source electrode meets VSS, and drain electrode is connect with M17 source electrode, and M17 drain electrode is connected with M18 drain electrode, and M18 source electrode and M19 drain electrode connect
It connects, M19 source electrode connects VDD；M20 source electrode meets VSS, and drain electrode is connect with M21 source electrode, and M21 drain electrode is connected with M22 drain electrode, M22 source electrode
It drains and connects with M23, M23 source electrode connects VDD；M24 source electrode meets VSS, and drain electrode is connected with M25 drain electrode, and M25 source electrode connects VDD；
It is connect after M1, M3, M12, M13, M16 and M23 gate connected in parallel with input D signal, M1 drain electrode is connect with M5 grid, M5 drain electrode and M8
It is connected with M10 grid, M9 drain electrode is connect with M11 drain electrode and M14, M15, M20 and M21 grid, M14 drain electrode and M17 and M18 grid
Pole connection, M17 and M21 drain electrode are connect with the grid of M25, M24 and M26；M24 drain electrode is connect with M27 grid；M26 and M27 source electrode
It is connect after parallel connection with M9, M4, M6 and M2 grid；The drain electrode of M26 and M27 connects, and exports CLK signal；M12 drain electrode and M19 and M20
Gate connected in parallel and DN；M7 is connect with M11 gate connected in parallel with RST.
The operation principle of the present invention is that:
1, M1~M11 constitutes the TSPC edge triggered flip flop with reset, and wherein D is input signal, and GCLK is inside
Work clock.When RSTn is low level, the trigger reset, QN is high level；When RSTn is high level, in the upper of GCLK
Edge is risen, the data at the end D are written in register, so that
2, M12 and M13, M14 and M15 form two phase inverters, respectively obtainWith
3, totally 8 metal-oxide-semiconductors constitute XOR logic unit to M16~M23, and input signal is respectively D, DN, Q, QN, passes through electricity
Road transport is calculated to obtain feedback control signal FB, so thatTruth table is as shown in table 1:
1 feedback control signal FB truth table of table
| D | (DN) | Q | (QN) | FB | MOS working condition |
| 0 | 1 | 0 | 1 | 0 | M20 and M21 conducting |
| 0 | 1 | 1 | 0 | 1 | M22 and M23 conducting |
| 1 | 0 | 0 | 1 | 1 | M18 and M19 conducting |
| 1 | 0 | 1 | 0 | 0 | M16 and M17 conducting |
4, M24 and M25 forms phase inverter, so that
5, M26 and M27 group gated transmission gate cell, input clock CLK, output clock are GCLK, control signal difference
For FB and FBN.When FB is high level and FBN is low level, GCLK=CLK, TSPC edge triggered flip flop is worked normally；When FB is
When low level and FBN are high level, transmission gate is closed, and each node of TSPC edge triggered flip flop keeps the value of Last status, is not sent out
Raw overturning；
In conclusion can automatically detect trigger input and output end in TSPC edge triggered flip flop proposed by the present invention
Signal level generates closing transmission gate signal FB and FBN, makes inside when input terminal D is identical with the signal level of output end Q
Work clock GCLK failure；When the signal level difference of input terminal D and output end Q, generate conducting transmission gate signal FB and
FBN keeps internal work clock identical with external drive clock.This mechanism avoids that d type flip flop internal circuit is unnecessary to be turned over
Turn, thereby reduces power consumption.Using this d type flip flop, Method at Register Transfer Level (RTL) combinational logic circuit can also do not turned over
Turn, to reduce the power consumption of entire digital circuit.
The present invention is directed to the demand of digital circuit low power dissipation design, proposes that a kind of circuit of novel TSPC edge triggered flip flop is opened up
Structure is flutterred, automatic feedback door control clock circuit is integrated in the trigger, the purpose is to further decrease TSPC edge triggered flip flop
Dynamic power consumption, thus reduce the overall power based on TSPC trigger digital integrated electronic circuit.Meanwhile it is feedback gated clock is electric
Road is encapsulated in TSPC edge triggered flip flop, simplifies digital integrated electronic circuit rear end design cycle.
Claims (1)
1. a kind of TSPC edge triggered flip flop with automatic feedback gated clock, it is characterised in that including 27 metal-oxide-semiconductors, M1~
M11 constitutes one with the TSPC edge triggered flip flop resetted, and M12 and M13, M14 and M15 separately constitute two phase inverters, and M16~
M23 constitutes XOR logic unit, and M24 and M25 form phase inverter, M26 and M27 group gated transmission gate cell；M1 source electrode connects
VSS, drain electrode are connected with M2 drain electrode, and M2 source electrode and M3 drain electrode connect, and M3 source electrode connects VDD；M4 source electrode connects VSS, drain electrode and the source M5
Pole connection, M5 drain electrode are connected with M6 drain electrode, and M6 source electrode connects VDD；M7 source electrode meets VSS, and drain electrode connect with M8 source electrode, M8 drain and
The connection of M9 source electrode, M9 drain electrode are connected with M10 drain electrode, and M10 source electrode connects VDD；M12 source electrode meets VSS, and drain electrode is connected with M13 drain electrode,
M13 source electrode connects VDD；M14 source electrode meets VSS, and M14 drain electrode is connected with M15 drain electrode, and M15 source electrode connects VDD；M16 source electrode meets VSS,
Drain electrode is connect with M17 source electrode, and M17 drain electrode is connected with M18 drain electrode, and M18 source electrode and M19 drain electrode connect, and M19 source electrode connects VDD；
M20 source electrode meets VSS, and drain electrode is connect with M21 source electrode, and M21 drain electrode is connected with M22 drain electrode, and M22 source electrode and M23 drain electrode connect, M23
Source electrode connects VDD；M24 source electrode meets VSS, and drain electrode is connected with M25 drain electrode, and M25 source electrode connects VDD；M1, M3, M12, M13, M16 and
It is connect after M23 gate connected in parallel with input D signal, M1 drain electrode is connect with M5 grid, and M5 drain electrode is connect with M8 and M10 grid, M9 leakage
Pole drains with M11 and M14, M15, M20 and M21 grid are connect, and M14 drain electrode is connect with M17 and M18 grid, M17 and M21 leakage
Pole is connect with the grid of M25, M24 and M26；M24 drain electrode is connect with M27 grid；After M26 and M27 sources connected in parallel with M9, M4, M6
It is connected with M2 grid；The drain electrode of M26 and M27 connects, and exports CLK signal；The gate connected in parallel and DN of M12 drain electrode and M19 and M20；
M7 is connect with M11 gate connected in parallel with RST.
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| CN111769826A (en) * | 2020-06-19 | 2020-10-13 | 易兆微电子(杭州)股份有限公司 | TSPC trigger with setting and resetting functions |
| CN112257376A (en) * | 2020-10-28 | 2021-01-22 | 海光信息技术股份有限公司 | Method and device for planning feed-through path, electronic equipment and storage medium |
| CN112311385A (en) * | 2020-10-31 | 2021-02-02 | 拓维电子科技(上海)有限公司 | Gate-controlled clock circuit |
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Cited By (4)
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| CN112311385A (en) * | 2020-10-31 | 2021-02-02 | 拓维电子科技(上海)有限公司 | Gate-controlled clock circuit |
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