CN105162438A - TSPC (True Single Phase Clock) type data flip-flop (DFF) capable of reducing glitch - Google Patents

Abstract

The invention discloses a TSPC type D flip-flop for reducing burrs, which comprises a first-stage inverter structure, a second-stage inverter structure, a third-stage inverter structure and a reset tube. The present invention theoretically analyzes the factors affecting the burr of the traditional TSPC type flip-flop, improves the structure and optimizes the parameters, reduces the influence of the DFF burr, improves the performance of the DFF, improves and reduces the power consumption of the circuit while maintaining the stability of the circuit operation, and realizes the digital system Requirements for low power consumption and compact area of the basic digital unit. Compared with the traditional TSPC circuit, the DFF burr of the structure of the present invention is significantly reduced, and has obvious advantages in terms of stability and power consumption.

Description

A TSPC Type D Flip-Flop with Reduced Glitch

technical field

The invention relates to a TSPC (TrueSinglePhaseClock, true single-phase clock) type D flip-flop that reduces burrs, specifically a high-speed master-slave type D flip-flop with a reset structure, which belongs to digital signal technology.

Background technique

With the rapid development of CMOS integrated circuit technology, the scale of integration on a single chip is getting larger and larger, and the clock frequency is increasing rapidly, which has higher requirements for the speed of various circuits. Timing and counting digital circuits are almost an essential part of an integrated system, and their speed directly affects system performance. Due to the continuous advancement of VLSI technology, the operating speed requirements of digital systems continue to increase. A flip-flop is a commonly used component in a digital system, and its performance has a great influence on the performance of the entire system. At present, many researches and applications of flip-flops are based on D flip-flops, which have higher requirements for the speed of DFF.

The addition of traditional synchronous or asynchronous adding counters is limited by the delay of the carry chain. When the number of counting digits increases, it is difficult for the counter to work under the high-frequency counting clock. At present, the application occasions of high-speed and high-precision counters are increasing day by day. If the area factor is taken into consideration, ordinary addition and subtraction counters cannot meet the requirements. As an important counting circuit, the Linear Feedback Shift Counter (LFSR) is favored especially in the field of high-speed integrated circuits. The LFSR counter only uses D flip-flops and exclusive/exclusive OR gates, so the delay does not depend on the number of bits of the counter, but is only related to the delay of a single DFF and exclusive/exclusive OR gates. The problem caused by the limitation of the working speed of the traditional D flip-flop is that the speed of the counter drops more obviously. In addition, the time-to-digital conversion circuit (TDC) is an important timing circuit, and its main composition is a counter. The counter counts the number of cycles of a fixed cycle pulse signal, and the value is multiplied by the cycle to realize the digital quantification of time. , The counter is mainly composed of D flip-flops and a small number of combinational logic gates.

In digital integrated circuits, there are many types of D flip-flops. According to different logic functions, flip-flops can be divided into RS, JK, D and T flip-flops and other types. According to different circuit structures, they can be divided into master-slave structures. , Sensitive amplifier structure and maintaining blocking structure, etc. Different types of D flip-flops have different performance advantages. For example, the operating frequency of a TDC circuit using DFF is usually high, and the area is required to be as compact as possible. This puts forward higher requirements for the D flip-flop of the dynamic structure type. The traditional TSPC type suffers from glitches and charge sharing, so that the potential of the Qb terminal is not ideal high and low levels, that is, the high level is not the ideal VDD, and the low potential is not the ideal GND. This phenomenon results in variations in charge and discharge times. Although adding transistors at key points can alleviate this problem, it will limit the operating speed of the flip-flop and consume more power.

Contents of the invention

Purpose of the invention: In order to overcome the deficiencies in the prior art, the present invention provides a novel TSPC type D flip-flop, which reduces the glitch and power consumption of the D flip-flop, and on this basis ensures higher operating speed and smaller area of the layout.

Technical scheme: in order to achieve the above object, the technical scheme adopted in the present invention is:

A TSPC-type D flip-flop that reduces glitches, including a first-stage inverter, a second-stage inverter, a third-stage inverter, and a reset structure. The specific structure is as follows:

The first-stage inverter includes No. 1 PMOS transistor MP1, No. 2 PMOS transistor MP2, No. 3 PMOS transistor MP3 and No. 1 NMOS transistor MN1; wherein, the gate of No. 1 PMOS transistor MP1 is connected to the clock signal CLK, and the gate of No. 1 PMOS transistor MP1 is connected to the clock signal CLK. The drain of the PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2 and used as the first output terminal of the first-stage inverter; the drain of the second PMOS transistor MP2 is connected to the source of the third PMOS transistor MP3; The drain of the No. PMOS transistor MP3 is connected to the drain of the No. 1 NMOS transistor MN1 and used as the No. 2 output terminal of the first-stage inverter; the gate of the No. 2 PMOS transistor MP2 is connected to the gate of the No. 1 NMOS transistor MN1 and As the input terminal of the first-stage inverter; the source of the first NMOS transistor MN1 is grounded; the gate of the third PMOS transistor MP3 is connected to the clock signal CLK;

The second-stage inverter includes No. 4 PMOS transistor MP4, No. 2 NMOS transistor MN2, No. 3 NMOS transistor MN3, No. 4 NMOS transistor MN4, and No. 5 NMOS transistor MN5; wherein, the gate of No. 4 PMOS transistor MP4 and The gate of the fourth NMOS transistor MN4 and the drain of the second NMOS transistor MN2 are connected and used as the first input terminal of the second-stage inverter; the gate of the second NMOS transistor MN2 is used as the second input terminal of the second-stage inverter Input terminal; the drain of the fourth PMOS transistor MP4 is connected to the drain of the third NMOS transistor MN3 and used as the output end of the second-stage inverter; the gate of the third NMOS transistor MN3 is connected to the clock signal CLK, and the gate of the third NMOS transistor MN3 is connected to the clock signal CLK. The source of MN3 is connected to the drain of the fourth NMOS transistor MN4; the source of the second NMOS transistor MN2 is connected to the source of the fourth NMOS transistor MN4 and the drain of the fifth NMOS transistor MN5; the gate of the fifth NMOS transistor MN5 The pole is connected to the clock signal CLK, and the source of the fifth NMOS tube MN5 is grounded;

The third-stage inverter includes No. 5 PMOS transistor MP5 and No. 6 NMOS transistor MN6; wherein, the gate of No. 5 PMOS transistor MP5 is connected to the gate of No. 6 NMOS transistor MN6 and serves as the gate of the third-stage inverter Input terminal; the drain of the fifth PMOS transistor MP5 is connected to the drain of the sixth NMOS transistor MN6 and used as the output of the third-stage inverter; the source of the fifth PMOS transistor MP5 is connected to the power supply VDD; the sixth NMOS transistor MN6 The source of the ground;

The reset structure includes the sixth PMOS transistor MP6 and the seventh NMOS transistor MN7; the gate of the sixth PMOS transistor MP6 is connected to the reset signal R, the source of the sixth PMOS transistor MP6 is connected to the power supply VDD, and the drain of the sixth PMOS transistor MP6 The pole is connected to the source of the first PMOS transistor MP1; the gate of the seventh NMOS transistor MN7 is connected to the reset signal R, and the drain of the seventh NMOS transistor MN7 is connected to the first output terminal of the first stage inverter and the second stage inverter The No. 1 input terminal of the device, the source of the No. 7 NMOS transistor MN7 is grounded;

The input terminal of the first-stage inverter is connected to the input signal D of the TSPC type D flip-flop, the No. 1 output terminal of the first-stage inverter is connected to the No. 1 input terminal of the second-stage inverter, and the first-stage inversion The No. 2 output of the inverter is connected to the No. 2 input of the second-stage inverter, the output of the second-stage inverter is connected to the input of the third-stage inverter, and the output of the third-stage inverter outputs TSPC The output signal Q of the type D flip-flop.

Preferably, the size of the second NMOS transistor MN2 is larger than the size of the third NMOS transistor MN3 and the size of the fourth NMOS transistor MN4; this structure enables the second NMOS transistor MN2 to pull down the node y2 to GND faster, so that the low The level can be quickly transferred to the output signal Q.

In the circuit structure of the present invention, the combination of the NMOS transistor and the PMOS transistor of the reset structure can realize fast reset at high level and ensure normal operation at low potential at the same time.

Beneficial effects: the TSPC-type D flip-flop with reduced burrs provided by the present invention has the following advantages: 1. Compared with the existing TSPC-type structure, it can avoid the occurrence of an error state in the flip-flop caused by the burr problem, and can make The potential of the output terminal of Qb is close to the ideal high and low levels, that is, the high level is the ideal VDD, and the low potential is the ideal GND; to the delay of the output Q; in the present invention, the reset signal tube is only placed in the first-stage inverter position, reducing the transmission delay of the flip-flop; 3, compared with the existing TSPC type flip-flop, the present invention proposes a A TSPC flip-flop has a more streamlined structure, a smaller layout area, and a simple reset structure, and is more suitable for use in high-speed counters.

Description of drawings

Figure 1 and Figure 2 are two classic TSPC type D flip-flop structures;

Figure 3 is a simulation timing diagram of a classic D flip-flop;

Fig. 4 is the structure of the TSPC type D flip-flop of initial design;

FIG. 5 is a structure in which a transistor is added to realize a reset function on the basis of FIG. 4 .

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings.

As shown in Figure 5, a TSPC-type D flip-flop that reduces glitches includes a first-stage inverter, a second-stage inverter, a third-stage inverter, and a reset structure. The specific structure is as follows:

The first-stage inverter includes No. 1 PMOS transistor MP1, No. 2 PMOS transistor MP2, No. 3 PMOS transistor MP3 and No. 1 NMOS transistor MN1; wherein, the gate of No. 1 PMOS transistor MP1 is connected to the clock signal CLK, and the gate of No. 1 PMOS transistor MP1 is connected to the clock signal CLK. The drain of the PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2 and used as the first output terminal of the first-stage inverter; the drain of the second PMOS transistor MP2 is connected to the source of the third PMOS transistor MP3; The drain of the No. PMOS transistor MP3 is connected to the drain of the No. 1 NMOS transistor MN1 and used as the No. 2 output terminal of the first-stage inverter; the gate of the No. 2 PMOS transistor MP2 is connected to the gate of the No. 1 NMOS transistor MN1 and As the input terminal of the first-stage inverter; the source of the first NMOS transistor MN1 is grounded; the gate of the third PMOS transistor MP3 is connected to the clock signal CLK;

The second-stage inverter includes No. 4 PMOS transistor MP4, No. 2 NMOS transistor MN2, No. 3 NMOS transistor MN3, No. 4 NMOS transistor MN4, and No. 5 NMOS transistor MN5; wherein, the gate of No. 4 PMOS transistor MP4 and The gate of the fourth NMOS transistor MN4 and the drain of the second NMOS transistor MN2 are connected and used as the first input terminal of the second-stage inverter; the gate of the second NMOS transistor MN2 is used as the second input terminal of the second-stage inverter Input terminal; the drain of the fourth PMOS transistor MP4 is connected to the drain of the third NMOS transistor MN3 and used as the output end of the second-stage inverter; the gate of the third NMOS transistor MN3 is connected to the clock signal CLK, and the gate of the third NMOS transistor MN3 is connected to the clock signal CLK. The source of MN3 is connected to the drain of the fourth NMOS transistor MN4; the source of the second NMOS transistor MN2 is connected to the source of the fourth NMOS transistor MN4 and the drain of the fifth NMOS transistor MN5; the gate of the fifth NMOS transistor MN5 The pole is connected to the clock signal CLK, and the source of the fifth NMOS tube MN5 is grounded;

The third-stage inverter includes No. 5 PMOS transistor MP5 and No. 6 NMOS transistor MN6; wherein, the gate of No. 5 PMOS transistor MP5 is connected to the gate of No. 6 NMOS transistor MN6 and serves as the gate of the third-stage inverter Input terminal; the drain of the fifth PMOS transistor MP5 is connected to the drain of the sixth NMOS transistor MN6 and used as the output of the third-stage inverter; the source of the fifth PMOS transistor MP5 is connected to the power supply VDD; the sixth NMOS transistor MN6 The source of the ground;

The reset structure includes the sixth PMOS transistor MP6 and the seventh NMOS transistor MN7; the gate of the sixth PMOS transistor MP6 is connected to the reset signal R, the source of the sixth PMOS transistor MP6 is connected to the power supply VDD, and the drain of the sixth PMOS transistor MP6 The pole is connected to the source of the first PMOS transistor MP1; the gate of the seventh NMOS transistor MN7 is connected to the reset signal R, and the drain of the seventh NMOS transistor MN7 is connected to the first output terminal of the first stage inverter and the second stage inverter The No. 1 input terminal of the device, the source of the No. 7 NMOS transistor MN7 is grounded;

The input terminal of the first-stage inverter is connected to the input signal D of the TSPC type D flip-flop, the No. 1 output terminal of the first-stage inverter is connected to the No. 1 input terminal of the second-stage inverter, and the first-stage inversion The No. 2 output of the inverter is connected to the No. 2 input of the second-stage inverter, the output of the second-stage inverter is connected to the input of the third-stage inverter, and the output of the third-stage inverter outputs TSPC The output signal Q of the type D flip-flop.

In this case, by analyzing the circuit structure and working principle of the traditional TSPC flip-flop, the cause of the glitch and charge sharing was found; and on this basis, a method to eliminate the glitch and charge sharing was proposed, and a high-performance trigger.

The classic TSPC structures are shown in Figure 1 and Figure 2 respectively. Essentially, the two structures have the same principle and similar structures, and the main difference is that the positions of the clock control signals in the first-stage inverter and the third-stage inverter are different. However, since the relative position of the clock signal CLK between the stages does not change, the function remains unchanged.

Take Figure 1 as an example to briefly illustrate the working principle of the classic TSPC structure: when CLK=0, the input inverter samples the inverted D input on node X. The second (dynamic) inverter is in the precharge state, and node Y is charged to VDD by M6. The third inverter is maintained because both M8 and M9 are off. So during the low phase of the clock, the input to the last (static) inverter holds its original value, so the output Q is in a stable state. On the rising edge of the clock, dynamic inverters M4-M6 are evaluated. If X is high at the rising edge, then node Y discharges. In the high-level phase of the clock, the third inverter M7-M9 is turned on, and the value on the Y node is transmitted to the output Q. Note that during the positive phase of the clock, if the D input toggles high, node X toggles low. So the input must remain stable until the value at node X is transferred to Y before the rising edge of the clock. This is the hold time of the register. The propagation delay of the register is actually the delay of the three inverters. Because the value on node X has to be transferred to output Q. Finally, setup time is the time to enable node X, so the setup time for this structure is one inverter delay.

Note that the TSPC structure in Figure 1 and Figure 2 is subject to burrs and charge sharing, so that the potential of the Qb terminal is no longer the ideal high and low level, that is, the high level is not the ideal VDD, and the low potential is not the ideal GND. Because Qb is connected to an inverter for shaping, the flip-flop can work normally without using the Qb terminal, but the unsatisfactory potential will cause changes in the charging and discharging time. To solve these problems, transistors can be added at key points, but this will limit the working speed of the flip-flop and increase power consumption.

The TSPC shown in Figure 2 consists of nine MOS transistors. When CLK is low and D is high, nodes n1 and y2 are precharged to VDD, and y1 is discharged to GND. If CLK changes from low to high, MN3 and MNS2 are turned on, and Qb becomes low potential. If CLK remains high and D changes from high to low, MN1 is turned off and MP1 is turned on. At this time, n1 and y1 will form charge sharing, and then the impact will be that the potential of y1 exceeds the threshold voltage of MN2. When CLK is at a high level, MNS1 is turned on, and node y2 is slowly discharged, which will cause MP2 to be turned on, and Qb becomes a high potential. Therefore, a flip-flop with this structure may have serious problems in practical applications.

For edge flip-flops, glitch issues can also cause the flip-flop to generate an incorrect state. For example, for FIG. 2, when CLK=0 and D=0, y1 and y2 are precharged to high level. If CLK goes from low to high, node y2 will discharge to low, but not immediately. In other words, y2 maintains a high level in a short period of time, at this time MN3 and MNS2 are turned on, and Qb may become low. However, if the size of MN2 and MNS1 is adjusted, the discharge speed is changed, and y2 needs to be fully discharged before Qb becomes low, then Qb will return to the correct logic value.

For the glitch analysis of the above-mentioned D flip-flop structure, Figure 3 shows the simulation timing diagram of this flip-flop, and the simulation results confirm the above content: when D=0, CK changes from 0 to 1, then Qb appears a direction Under the peak pulse, the high-level amplitude drops by about 0.8V, and this potential is approximately close to the flipping point of the MOS tube. This spike must therefore be eliminated to avoid logic errors. In addition, if D=1, and CLK changes from low to high, an upward spike occurs when Qb keeps low, and the amplitude is approximately 800mV.

The structure of the D flip-flop shown in FIG. 4 is an improved solution, and the flip-flop can solve the problems mentioned above. Similar to the above two circuit structures, the clock signal in Figure 4 also provides driving signals for the four transistors, and the transistor MPS2 driven by CLK can effectively reduce the impact of the charge sharing problem in Figure 2 . In FIG. 2, when CLK=0, the potentials of nodes n1 and y2 are VDD. When CLK=1, the potential of node n1 is not important, but y2 may be high or discharged to low. Based on this, one can consider merging two pull-up transistors. Transistors MPS1 and MPS2 in FIG. 2 can be combined into MPS1 in FIG. 4 . Similarly, MNS1 and MNS2 in FIG. 2 are merged into MNS1 in FIG. 4 . The purpose of merging transistors is to reduce power consumption. The introduction of MNS2 in Figure 4 is to reduce the burr at Qb point.

On the basis of Figure 4, a transistor is added to realize the reset function, as shown in Figure 5. Only placing transistors in the first-stage inverter can reduce the delay caused by reset transistors on the basis of ensuring the realization of the reset function, and at the same time save the layout area compared with the traditional structure.

The above is only a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications are also possible. It should be regarded as the protection scope of the present invention.

Claims (2)

1. reduce a TSPC type d type flip flop for burr, it is characterized in that: comprise first order inverter, second level inverter, third level inverter and resetting structure, concrete structure is as follows:

Described first order inverter comprises a PMOS MP1, No. two PMOS MP2, No. three PMOS MP3 and No. one NMOS tube MN1; Wherein, the grid of a PMOS MP1 connects clock signal clk, and the drain electrode of a PMOS MP1 is connected with the source electrode of No. two PMOS MP2 and as an output of first order inverter; The drain electrode of No. two PMOS MP2 is connected with the source electrode of No. three PMOS MP3; The drain electrode of No. three PMOS MP3 is connected with the drain electrode of a NMOS tube MN1 and as No. two outputs of first order inverter; The grid of No. two PMOS MP2 is connected with the grid of a NMOS tube MN1 and as the input of first order inverter; The source ground of a NMOS tube MN1; The grid of No. three PMOS MP3 connects clock signal clk;

Described second level inverter comprises No. four PMOS MP4, No. two NMOS tube MN2, No. three NMOS tube MN3, No. four NMOS tube MN4 and No. five NMOS tube MN5; Wherein, the drain electrode of the grid of No. four PMOS MP4 and the grid of No. four NMOS tube MN4 and No. two NMOS tube MN2 is connected and as an input of second level inverter; The grid of No. two NMOS tube MN2 is as No. two inputs of second level inverter; The drain electrode of No. four PMOS MP4 is connected with the drain electrode of No. three NMOS tube MN3 and as the output of second level inverter; The grid of No. three NMOS tube MN3 connects clock signal clk, and the source electrode of No. three NMOS tube MN3 is connected with the drain electrode of No. four NMOS tube MN4; The source electrode of No. two NMOS tube MN2 is connected with the drain electrode of the source electrode of No. four NMOS tube MN4 and No. five NMOS tube MN5; The grid of No. five NMOS tube MN5 connects clock signal clk, the source ground of No. five NMOS tube MN5;

Described third level inverter comprises No. five PMOS MP5 and No. six NMOS tube MN6; Wherein, the grid of No. five PMOS MP5 is connected with the grid of No. six NMOS tube MN6 and as the input of third level inverter; The drain electrode of No. five PMOS MP5 is connected with the drain electrode of No. six NMOS tube MN6 and as the output of third level inverter; The source electrode of No. five PMOS MP5 meets power vd D; The source ground of No. six NMOS tube MN6;

Described resetting structure comprises No. six PMOS MP6 and No. seven NMOS tube MN7; Wherein the grid of No. six PMOS MP6 connects the source electrode connection power vd D of reset signal R, No. six PMOS MP6, and the drain electrode of No. six PMOS MP6 connects the source class of a PMOS MP1; The grid of No. seven NMOS tube MN7 connects an output of drain electrode connection first order inverter and an input of second level inverter of reset signal R, No. seven NMOS tube MN7, the source ground of No. seven NMOS tube MN7;

The input signal of the input access TSPC type d type flip flop of first order inverter, an output of first order inverter connects an input of second level inverter, No. two outputs of first order inverter connect No. two inputs of second level inverter, the output of second level inverter connects the input of third level inverter, and the output of third level inverter exports the output signal Q of TSPC type d type flip flop.

2. the TSPC type d type flip flop of reduction burr according to claim 1, is characterized in that: the size of described No. two NMOS tube MN2 is greater than the size of No. three NMOS tube MN3 and the size of No. four NMOS tube MN4.