CN105162438B

CN105162438B - It is a kind of to reduce the TSPC type d type flip flops of burr

Info

Publication number: CN105162438B
Application number: CN201510626563.6A
Authority: CN
Inventors: 郑丽霞; 江琦; 张有志; 王灿; 许其罗; 吴金
Original assignee: Southeast University
Current assignee: Southeast University
Priority date: 2015-09-28
Filing date: 2015-09-28
Publication date: 2017-10-20
Anticipated expiration: 2035-09-28
Also published as: CN105162438A

Abstract

The TSPC type d type flip flops of burr, including first order inverter structure, second level inverter structure, third level inverter structure and reset transistor are reduced the invention discloses a kind of.The present invention influences the factor of burr on traditional TSPC D-flip flops theory analysis, carry out structure improvement and parameter optimization, reduce the influence of DFF burrs, improve DFF performance, improved while holding circuit job stability and reduce circuit power consumption, realize digital display circuit for basic digital units low-power consumption and the requirement of area compact type.Compared with traditional TSPC circuits, the DFF burrs reduction of structure of the present invention is obvious, is had a clear superiority in terms of stability and power consumption.

Description

It is a kind of to reduce the TSPC type d type flip flops of burr

Technical field

Touched the present invention relates to a kind of TSPC (True Single Phase Clock, true single phase clock) type D for reducing burr Device is sent out, specially a kind of high speed master-slave D flip-flop with resetting structure belongs to digital signal technique.

Background technology

Collect increasing on a large scale with developing rapidly for CMOS integrated circuit techniques, on one single chip, and clock frequency Rate rapidly increases, and has higher requirement to the speed of various circuits.Timing, count numbers circuit as in integrated system almost It is an essential part, its speed directly affects systematic function.Due to the continuous progress of VLSI technologies, the fortune of digital display circuit Row rate request is improved constantly.Trigger is a kind of component commonly used in digital display circuit, performance of its performance to whole system Influence is very big.Carried out at present in many trigger researchs and application all based on d type flip flop, the speed to DFF has more High requirement.

Traditional either synchronously or asynchronously up counter addition, is postponed to be limited by carry chain, when counting digit increase, is counted Device is difficult to be operated under high-frequency count clock.At present, the application scenario of high-speed, high precision counter is increasingly increased, if by area Factor is taken into account, and common forward-backward counter can not meet requirement.And linear feedback shift counter (LFSR) conduct A kind of important counting circuit, especially enjoys favor in high speed integrated circuit field.LFSR counter only use d type flip flop and Different/same to OR gate, so digit of the delay independent of counter, only to single DFF and different/related with the delay of OR gate.Tradition D type flip flop because operating rate limitation bring the problem of be：The speed of counter declines more obvious.It is m- when being applied in addition Digital conversion circuit (TDC) is then a kind of important timing circuit, and it is also counter that it, which is constituted main, and counter is solid by statistics The number of cycles of fixed cycle pulse signal, the numerical value is multiplied with the cycle, realizes the digital quantization of time, and counter is mainly touched by D Hair device is simultaneously equipped with a small amount of combinational logic gate circuit composition.

In digital integrated electronic circuit, d type flip flop species is various, logically the difference of function, and trigger can be divided into RS, JK, D With the polytype such as T triggers, according to the difference of circuit structure, can be divided into again master-slave type structure, sense amplifier type structure and Maintain choke structure etc..Different types of d type flip flop, performance advantage emphasis is also different.Such as, using DFF TDC Circuit work frequency is generally higher, while it is as compact as possible to quadrature.This is just proposed more to the d type flip flop of dynamic structure type High request.Traditional TSPC types are shared by burr and electric charge, so that the current potential at Qb ends is not preferable low and high level, i.e., High level is not preferable VDD, and low potential is not preferable GND.This phenomenon causes the change of discharge and recharge time.Although closing Key point, which adds transistor, can alleviate the problem, but this will limit the operating rate of the trigger and consumes more power consumptions.

The content of the invention

Goal of the invention：In order to overcome the deficiencies in the prior art, the present invention provides a kind of new TSPC types D triggerings Device, reduces the burr and power consumption of d type flip flop, and ensures higher operating rate and less chip area on this basis.

Technical scheme：To achieve the above object, the technical solution adopted by the present invention is：

A kind of TSPC type d type flip flops of reduction burr, including first order phase inverter, second level phase inverter, the third level are anti-phase Device and resetting structure, concrete structure are as follows：

The first order phase inverter includes a PMOS MP1, No. two PMOS MP2, No. three PMOS MP3 and No. one NMOS tube MN1；Wherein, PMOS MP1 grid connection clock signal clk, PMOS MP1 drain electrode and No. two PMOS MP2 source electrode connects and is used as an output end of first order phase inverter；No. two PMOS MP2 drain electrode and No. three PMOS MP3 source electrode connection；No. three PMOS MP3 drain electrode connects with NMOS tube MN1 drain electrode and is used as the first order No. two output ends of phase inverter；The grid connection of No. two PMOS MP2 grid and a NMOS tube MN1 is simultaneously anti-as the first order The input of phase device；Number NMOS tube MN1 source ground；No. three PMOS MP3 grid connection clock signal clk；

The second level phase inverter include No. four PMOS MP4, No. two NMOS tube MN2, No. three NMOS tube MN3, No. four NMOS tube MN4 and No. five NMOS tube MN5；Wherein, No. four PMOS MP4 grid and No. four NMOS tube MN4 grid and two Number NMOS tube MN2 drain electrode connects and is used as an input of second level phase inverter；No. two NMOS tube MN2 grid is used as No. two inputs of two grades of phase inverters；No. four PMOS MP4 drain electrode and No. three NMOS tube MN3 drain electrode connect and are used as second The output end of level phase inverter；No. three NMOS tube MN3 grid connection clock signal clk, No. three NMOS tube MN3 source electrode and No. four NMOS tube MN4 drain electrode connection；No. two NMOS tube MN2 source electrode and No. four NMOS tube MN4 source electrode and No. five NMOS tube MN5 Drain electrode connection；No. five NMOS tube MN5 grid connection clock signal clk, No. five NMOS tube MN5 source ground；

The third level phase inverter includes No. five PMOS MP5 and No. six NMOS tube MN6；Wherein, No. five PMOS MP5 Grid and No. six NMOS tube MN6 grid connect and are used as the input of third level phase inverter；No. five PMOS MP5 drain electrode and No. six NMOS tube MN6 drain electrode connects and is used as the output end of third level phase inverter；No. five PMOS MP5 source electrode connects power supply VDD；No. six NMOS tube MN6 source ground；

The resetting structure includes No. six PMOS MP6 and No. seven NMOS tube MN7；Wherein No. six PMOS MP6 grid Reset signal R is connected, No. six PMOS MP6 source electrode connection power vd D, No. six PMOS MP6 drain electrode connect a PMOS Pipe MP1 source class；No. seven NMOS tube MN7 grid connection reset signal R, No. seven NMOS tube MN7 drain electrode connection first order is anti- A number output end of phase device and an input of second level phase inverter, No. seven NMOS tube MN7 source ground；

The input of first order phase inverter accesses the input signal D of TSPC type d type flip flops, and No. one of first order phase inverter is defeated Go out an input of end connection second level phase inverter, the two of No. two output ends connection second level phase inverter of first order phase inverter Number input, the output end of second level phase inverter connects the input of third level phase inverter, and the output end of third level phase inverter is defeated Go out the output signal Q of TSPC type d type flip flops.

It is preferred that, the size of No. two NMOS tube MN2 is more than No. three NMOS tube MN3 size and No. four NMOS tube MN4 Size；The structure enables to No. two NMOS tube MN2 that node y2 quickly is pulled down into GND so that low level can be passed quickly It is defeated to arrive output signal Q.

In the circuit structure of the present invention, NMOS tube and the PMOS combination of resetting structure can realize that high level is replied immediately soon Position, while ensureing low potential normal work.

Beneficial effect：The TSPC type d type flip flops for the reduction burr that the present invention is provided, with following advantage：1st, with it is existing TSPC type structures are compared, and the situation for causing trigger to produce error condition because of Burr Problem can be avoided to occur, can be caused The current potential of Qb output ends is preferable VDD close to preferable low and high level, i.e. high level, and low potential is preferable GND；2nd, it is existing In TSPC D-flip flop structures, due to using front and back stages reset mode, signal D is added to output Q delay；In the present invention Reset signal pipe is disposed only on first order phase inverter position, reduces the transmission delay of trigger；3rd, with existing TSPC D-flip flops Compare, a kind of TSPC triggers proposed by the present invention, structure is more simplified, and chip area is smaller, resetting structure is simple, more applicable In the use in high-speed counter.

Brief description of the drawings

Fig. 1 and Fig. 2 is two kinds of classical TSPC type d type flip flop structures；

Fig. 3 is the emulation timing diagram of classical d type flip flop；

Fig. 4 is the TSPC type d type flip flop structures of initial designs；

Fig. 5 is that the structure that transistor realizes reset function is added on the basis of Fig. 4.

Embodiment

The present invention is further described below in conjunction with the accompanying drawings.

Be illustrated in figure 5 it is a kind of reduce burr TSPC type d type flip flops, including first order phase inverter, second level phase inverter, Third level phase inverter and resetting structure, concrete structure are as follows：

This case is analyzed by the circuit structure to traditional TSPC D-flip flops with operation principle, have found generation hair The reason for thorn and shared electric charge；And on this basis, it is proposed that the method that burr is shared with electric charge is eliminated, is obtained high performance Trigger.

Classical TSPC structures difference is as shown in Figure 1 and Figure 2.Substantially two kinds structural principles are identical, and structure is similar, mainly It is distinguished as clocked signal position in first order phase inverter and third level phase inverter different.But because clock signal clk is between level Relative position does not change, therefore function is constant.

The operation principle of classics TSPC structures is briefly explained by taking Fig. 1 as an example：As CLK=0, input inverter is in nodes X The anti-phase D inputs of up-sampling.Second (dynamic) phase inverter is in pre-charge state, and node Y is charged into VDD by M6.3rd Individual phase inverter is in maintenance state, because M8 and M9 are turned off.Therefore in the low level stage of clock, last (static state) is anti- The input of phase device remains its original value, therefore output Q is in stable state.In the rising edge of clock, dynamic inverter M4- M6 evaluations.If X is high level at rising edge, then node Y discharges.In the 3rd phase inverter of high level stage of clock M7-M9 is turned on, and the value on Y nodes is sent to output Q.Note, in the positive level stage of clock, if D inputs are turned to height Level, then nodes X be turned to low level.Therefore input must keep stable, until value of the nodes X before rising edge clock is passed It is sent to Y.This is holding time for register.The propagation delay of register is actually the delay of three phase inverters.Because Value in nodes X must be transferred to output Q.Finally, setup time is to make the nodes X effective time, so the foundation of the structure Time is a phase inverter delay.

Notice that TSPC structures are shared by burr and electric charge in Fig. 1, Fig. 2, so that the current potential at Qb ends is no longer Preferable low and high level, i.e. high level are not preferable VDD, and low potential is not preferable GND.It is whole because accessing phase inverter progress after Qb Shape, therefore in the case where not using Qb ends, the trigger can normal work, but current potential undesirable will be when will cause discharge and recharge Between change.To solve these problems, transistor can be added in key point, but this will limit the operating rate of the trigger Cause power consumption increase simultaneously.

TSPC shown in Fig. 2 is made up of 9 MOS transistors.When CLK is low level and D is high level, node n1, y2 are pre- VDD is charged to, and y1 is discharged to GND.If CLK changes from low to high, MN3 and MNS2 conductings, Qb are changed into low potential.If CLK Holding high level is constant and D changes from high to low, MN1 shut-offs, MP1 conductings.Now n1 and y1 will form electric charge and share, and then The influence of generation is the threshold voltage that y1 current potentials exceed MN2.When CLK is high level, MNS1 conductings, node y2 slowly discharges, this MP2 will be caused to turn on, Qb is changed into high potential.Therefore the trigger of this structure is in actual applications it is possible that serious asks Topic.

For edge triggered flip flop, Burr Problem it is also possible that obtaining trigger produces error condition.For example, for Fig. 2, when CLK=0 and D=0, y1 and y2 are precharged to high level.If CLK is uprised by low, node y2 will be discharged to low potential, but this Planting situation will not occur immediately.In other words, y2 keeps high level in the short period of time, and now MN3 and MNS2 is turned on, and Qb can Can step-down.But if adjustment MN2 and MNS1 sizes, change the velocity of discharge, y2 need to be discharged in advance before Qb step-downs, then Qb will be returned to correct logical value.

The burr analysis existed for above-mentioned d type flip flop structure, Fig. 3 gives the emulation timing diagram of this kind of trigger, imitated True result has confirmed the above：Work as D=0, CK is one downward spike of appearance, high level by 0 to 1 change, then Qb Amplitude has fallen 0.8V or so, and the current potential is approximately close to the upset point of metal-oxide-semiconductor.Therefore it is to avoid the occurrence of logic error, it is necessary to Eliminate the spike.In addition, if D=1, CLK change from low to high, then there is a upward point when keeping low level in Qb Peak pulse, amplitude is approximately 800mV.

D type flip flop structure shown in Fig. 4 is this improvement project, and what the trigger can solve that the above mentions asks Topic.Similar with above two circuit structure, the clock signal in Fig. 4 is similarly 4 transistors and provides drive signal, and by CLK The transistor MPS2 of driving, which can effectively reduce charge sharing problem in Fig. 2, to be influenceed.In fig. 2, as CLK=0, node n1 with Y2 current potentials are VDD.Work as CLK=1, node n1 current potentials are inessential, but y2 is probably high level or is discharged to low level.It is based on This, it may be considered that merge two and pull up transistor.Transistor MPS1, MPS2 can be merged into the MPS1 in Fig. 4 in Fig. 2.Similarly, MNS1, MNS2 in Fig. 2 is merged into the MNS1 in Fig. 4.The purpose for merging transistor is introduced to reduce in power consumption, Fig. 4 MNS2 is to reduce the burr of Qb points.

Transistor is added on the basis of Fig. 4 and realizes reset function, as shown in Figure 5.Only place brilliant in first order phase inverter Body pipe is realized in guarantee on the basis of reset function, is reduced because of the delay that reset transistor is brought, while being saved compared to traditional structure Chip area.

Described above is only the preferred embodiment of the present invention, it should be pointed out that：For the ordinary skill people of the art For member, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications also should It is considered as protection scope of the present invention.

Claims

1. a kind of reduce the TSPC type d type flip flops of burr, it is characterised in that：Including first order phase inverter, second level phase inverter, Three-level phase inverter and resetting structure, concrete structure are as follows：

The first order phase inverter includes a PMOS MP1, No. two PMOS MP2, No. three PMOS MP3 and a NMOS tube MN1；Wherein, PMOS MP1 grid connection clock signal clk, PMOS MP1 drain electrode and No. two PMOSs MP2 source electrode connects and is used as an output end of first order phase inverter；No. two PMOS MP2 drain electrode and No. three PMOSs MP3 source electrode connection；No. three PMOS MP3 drain electrode connects with NMOS tube MN1 drain electrode and is used as first order phase inverter No. two output ends；The grid connection of No. two PMOS MP2 grid and a NMOS tube MN1 is simultaneously used as first order phase inverter Input；Number NMOS tube MN1 source ground；No. three PMOS MP3 grid connection clock signal clk；

The second level phase inverter includes No. four PMOS MP4, No. two NMOS tube MN2, No. three NMOS tube MN3, No. four NMOS tubes MN4 and No. five NMOS tube MN5；Wherein, No. four PMOS MP4 grid and No. four NMOS tube MN4 grid and No. two NMOS Pipe MN2 drain electrode connects and is used as an input of second level phase inverter；No. two NMOS tube MN2 grid is anti-as the second level No. two inputs of phase device；No. four PMOS MP4 drain electrode is connected and anti-phase as the second level with No. three NMOS tube MN3 drain electrode The output end of device, No. four PMOS MP4 source electrode meets power vd D；No. three NMOS tube MN3 grid connection clock signal clk, three The drain electrode connection of number NMOS tube MN3 source electrode and No. four NMOS tube MN4；No. two NMOS tube MN2 source electrode and No. four NMOS tube MN4 Source electrode and No. five NMOS tube MN5 drain electrode connection；No. five NMOS tube MN5 grid connection clock signal clk, No. five NMOS Pipe MN5 source ground；

The third level phase inverter includes No. five PMOS MP5 and No. six NMOS tube MN6；Wherein, No. five PMOS MP5 grid Connected with No. six NMOS tube MN6 grid and be used as the input of third level phase inverter；No. five PMOS MP5 drain electrode and No. six NMOS tube MN6 drain electrode connects and is used as the output end of third level phase inverter；No. five PMOS MP5 source electrode meets power vd D；Six Number NMOS tube MN6 source ground；

The resetting structure includes No. six PMOS MP6 and No. seven NMOS tube MN7；Wherein No. six PMOS MP6 grid connection Reset signal R, No. six PMOS MP6 source electrode connection power vd D, No. six PMOS MP6 drain electrode connects a PMOS MP1 Source class；No. seven NMOS tube MN7 grid connection reset signal R, No. seven NMOS tube MN7 drain electrode connection first order phase inverter A number input of a number output end and second level phase inverter, No. seven NMOS tube MN7 source ground；

The input of first order phase inverter accesses the data input signal D of TSPC type d type flip flops, and No. one of first order phase inverter is defeated Go out an input of end connection second level phase inverter, the two of No. two output ends connection second level phase inverter of first order phase inverter Number input, the output end of second level phase inverter connects the input of third level phase inverter, and the output end of third level phase inverter is defeated Go out the output signal Q of TSPC type d type flip flops.

2. the TSPC type d type flip flops of reduction burr according to claim 1, it is characterised in that：No. two NMOS tube MN2 Size be more than No. three NMOS tube MN3 size and No. four NMOS tube MN4 size.