CN106571825A - Asynchronous clock signal generation circuit based on TSPC circuit - Google Patents
Asynchronous clock signal generation circuit based on TSPC circuit Download PDFInfo
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- CN106571825A CN106571825A CN201610975801.9A CN201610975801A CN106571825A CN 106571825 A CN106571825 A CN 106571825A CN 201610975801 A CN201610975801 A CN 201610975801A CN 106571825 A CN106571825 A CN 106571825A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
- H03M1/125—Asynchronous, i.e. free-running operation within each conversion cycle
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
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Abstract
The invention discloses an asynchronous clock signal generation circuit based on a TSPC (True Single Phase Clocked) circuit. The circuit is used for generating an asynchronous clock signal inside an analog-to-digital conversion (ADC) chip. The circuit comprises a TSPC trigger with a reset function, a TSPC trigger chain, and other function units. The asynchronous clock signal generation circuit has the following advantages: the asynchronous clock signal generation circuit based on a TSPC circuit is provided to overcome long conversion time of the existing ADC synchronous control circuit; the conversion speed of the circuit is improved; as the circuit contains a TSPC trigger with a reset function, error output signals generated due to uncertainty of nodes X and Y are eliminated; and the reliability of the asynchronous clock signal generation circuit is improved.
Description
Technical field
The present invention relates to the asynchronous clock signal that analog-to-digital conversion ADC chip internal is used produces circuit field, especially relate to
And a kind of asynchronous clock signal based on TSPC circuits produces circuit.
Background technology
Circuit design can be categorized as synchronous circuit and Asynchronous circuit design.Synchronous circuit makes its subsystem using clock pulses
Synchronous operation, and asynchronous circuit does not use clock pulses to do synchronization, its subsystem is believed using special " beginning " and " completing "
Number synchronize them.Because asynchronous circuit has following advantages：Without clock skew problem, low power consumption, average potency rather than most
Difference efficiency, modularity, combined and reusability, therefore in recent years to asynchronous circuit research quickly increase.Asynchronous circuit is main
It is combinational logic circuit, for producing the read-write control signal pulse of address decoder, first in first out buffering or memory, it is patrolled
All it doesn't matter for volume output and any clock signal, and the burr that decoding output is produced typically can be monitored.Synchronous circuit is
The circuit being made up of sequence circuit (register or various triggers) and combinational logic circuit, its all operations is all strict
Complete under clock control.These sequence circuits share same clock, and all of state change is all the rising in clock
What edge or trailing edge were completed.
During successive approximation (Successive Approximation Register, SAR) analog-digital converter belongs to
Uniform velocity analog-digital converter, its maximum feature is low-power consumption, easily realizes zero quiescent dissipation.Therefore, using SAR ADC low-power consumption
Characteristic, improves SAR ADC conversion speeds, is highly significant so as to substitute the high speed high power consumption analog-digital converter such as pipeline system ADC
Research direction.It is the big hot topic research directions of current SAR ADC mono- to improve SAR ADC conversion speeds.SAR ADC are by progressively forcing
Near method obtains a N positions result and at least wants N+1 to walk completing analog-to-digital conversion, wherein 1 step is used to sample, N is walked for turning
Change.Conversion is often walked and is made up of three part-times：Control circuit time delay, DAC stabilization times, comparator resolving time.This three part
Time delay is closely related with technique.So speed can be improved by adjusting control circuit.
SAR ADC control circuits on the whole for include it is synchronous and asynchronous two kinds.Synchronization control circuit needs a frequency
Rate is about (N+1) fsInternal clocking, and it is the same often to walk time of conversion consumption when changing.Asynchronous control circuit system
Clock frequency and system switching rate are equal, and the rear SAR ADC that sampled automatically generate the clock needed for conversion.And often walk and convert
After automatically begin to next step conversion, often walk conversion consumption time be different.Often walk the time of conversion and remaining signal
(surplus) is relevant.Surplus is bigger, and comparator is differentiated faster, completes to compare sooner.Because surplus is bigger, certain step is converted
It is faster, and synchronous method to be arranged and can only meet most slow situation when often walk conversion time, so asynchronous control circuit is than synchronous control
Circuit processed is faster.
The content of the invention
The purpose of the present invention is the deficiency for above-mentioned existing ADC synchronization control circuits conversion consumption time length, there is provided one
Plant the asynchronous clock signal based on true single-phase clock control (True Single Phase Clocked, TSPC) circuit to produce
Circuit, so as to further improve the conversion speed of circuit.
Synchronization control circuit is with the minimum of a value of the ratio of the elapsed time of asynchronous control circuit：
If N is sufficiently large, ratio can be with abbreviation as 0.5.As can be seen here asynchronous controlling method is in terms of conversion speed is improved
It is fairly effective.
In order to realize foregoing invention purpose, the present invention is employed the following technical solutions：
Asynchronous clock signal based on TSPC circuits produces circuit, when the electric route internal of asynchronous clock signal generation is asynchronous
Clock circuit, valid signal generating circuits and clkc signal generating circuits are constituted；
The internal asynchronous clock circuit is made up of ten TSPC flip-flop circuits, wherein, the internal asynchronous clock electricity
The input termination VDD signal of first trigger on road, trigger connects the valid signals of valid signal generating circuits output,
The termination that resets CLK signal, the output signal of first trigger is clk1；The input of second trigger terminates first triggering
The output end of device, trigger connects the valid signals, the termination that resets CLK signal, and the output signal of second trigger is
clk2；The output end of the 3rd trigger input second trigger of termination, trigger connects the valid signals, reset terminal
CLK signal is connect, the output signal of the 3rd trigger is clk3；The output of the 4th trigger input the 3rd trigger of termination
End, trigger connects the valid signals, the termination that resets CLK signal, and the output signal of the 4th trigger is clk4；With this
Analogize, the output of previous stage obtains successively signal clk1～clk10 as the input of rear stage；Clkc signal generating circuits are most
Produce internal work clock by the way that the signal clk10, the valid signals and the CLK signal are connected by OR gate eventually
Signal clkc.
Typical TSPC flip-flop circuits are by first order phase inverter, second level phase inverter, the 3rd pole phase inverter and resetting structure
Constitute；The first order phase inverter includes two PMOSs M2 and M3, NMOS tube M1；Wherein M3 tube grids and M1 tube grids
Phase inverter is connected to form and as the input of data, the grid of M2 pipes is connected with clock signal clk, as control data from
One-level is delivered to the gate of the second level；The second level phase inverter includes two NMOS tubes M4 and M5, PMOS M6；M6 is managed
Be connected access CLK signal with M4 pipes, and the output node X of first order phase inverter is connected with M5 tube grids, and anti-phase as the second level
The input of device；The 3rd pole phase inverter includes two NMOS tubes M7 and M8, PMOS M9；M8 tube grids connect CLK signal
For controlling the transmission between second level phase inverter and third level phase inverter, M9 pipes are connected to Y nodes with the grid of M7 pipes, and
Connect with the output end of second level phase inverter.
The resetting structure includes first order reset circuit, the first order reset circuit by two PMOSs M12 and
M13, a NMOS tube M11 composition, M11 pipes constitute phase inverter with M12 pipes；Cause when the rising edge of reset signal RES arrives
M13 pipes are turned on, and nodes X is pulled to VDD level, and wrong signal is produced because of the uncertain of nodes X so as to eliminate.
The resetting structure also includes a second level reset circuit, and the second level reset circuit is by NMOS tube M10
Composition, the drain electrode of M10 pipes is connected with Y nodes, and grid connects RES signals.The M10 pipes conducting when signal RES rising edges arrive, Y sections
Point is pulled to ground level, and wrong output signal is produced because of the uncertain of node Y so as to eliminate.
The valid signal generating circuits pass through an OR circuit by the differential signal that comparator comparative result is exported
Produce, the valid signal generating circuits further include signal input tube, PMOS M3, NMOS being made up of M1 and M2 pipes
Pipe M4, PMOS M5, wherein M1 tube grids meet signal C1 and meet signal C2 with M2 tube grids and compare what is exported by comparator
Differential signal, the drain electrode of M1, M2 pipe links together and connects with the source electrode of PMOS M3 as PMOS M5 and NMOS tube M4
Gate input, the source electrode of M5 pipes is connected to form the output end of circuit with the drain electrode of M4 pipes, exports the valid signals.
The clkc signal generating circuits include NMOS tube M1～M3, PMOS M4, M6 and NMOS tube M5, the NMOS tube
M1～M3 is signal input tube；The grid of wherein NMOS tube M1 meets signal clk10, and the grid of NMOS tube M2 connects the signal
Valid, the grid of NMOS tube M3 meets signal CLK；The source electrode phase that the drain electrode of NMOS tube M1～M3 links together with PMOS M4
The gate input as PMOS M6 and NMOS tube M5 is connect, the source electrode of PMOS M6 is connected to be formed with the drain electrode of NMOS tube M5
The output end of circuit, clkc signals described in final output.
The main operational principle of the application：As CLK=0, input inverter up-samples the D inputs of phase inverter in nodes X.
Second dynamic inverter is in pre-charge state, and node Y is charged to into VDD by M6.3rd phase inverter is in maintenance state,
Because M8 and M9 are turned off.Therefore in the low level stage of clock, the input of last (static state) phase inverter remains its original
The value come, thus output Q is in stable state.In the rising edge of clock, dynamic inverter M4-M6 evaluations.If X is rising
It is high level along place, then node Y discharges.In the 3rd phase inverter M7-M9 conducting of high level stage of clock, on Y nodes
Value be sent to output Q.In the positive level stage of clock, if D inputs are turned to high level, nodes X is turned to low level.
Therefore input must keep stable, until value of the nodes X before rising edge clock is sent to Y.The uncertainty of X, Y point can be
Next cycle affects the data conversion of ADC, therefore the application respectively increases a reset circuit at X, Y point.Reset circuit by
Tetra- metal-oxide-semiconductor compositions of M10-M13.M10 pipes are the reset transistor of Y nodes, move to node when reset signal RES rising edge arrives
Ground potential.M11-M13 is the reset transistor of X nodes, and node is moved to VDD points position when reset signal RES rising edge arrives.
Compared with prior art, the invention has the beneficial effects as follows：There is provided a kind of based on true single-phase clock control circuit
Asynchronous clock signal produces circuit, overcomes the shortcomings of that the existing ADC synchronization control circuits conversion consumption time is long, further improves electricity
The conversion speed on road, and due to the TSPC triggers comprising reset function so as to eliminate because nodes X, Y uncertain and produce
The output signal of raw mistake, improves the reliability that asynchronous clock signal produces circuit.
Description of the drawings
Fig. 1 is TSPC circuit structures of the present invention；
Fig. 2 is internal clock circuit of the present invention；
Fig. 3 is the asynchronous sequential that circuit of the present invention is produced；
Fig. 4 is that clkc signals of the present invention produce gate circuit；
Fig. 5 is valid signal generating circuits；
Specific embodiment
Accompanying drawing being for illustration only property explanation, it is impossible to be interpreted as the restriction to this patent；It is attached in order to more preferably illustrate the present embodiment
Scheme some parts to have omission, zoom in or out, do not represent the size of actual product；
To those skilled in the art, it can be to understand that some known features and its explanation may be omitted in accompanying drawing
's.Technical scheme is described further with reference to the accompanying drawings and examples.
It is illustrated in figure 1 typical TSPC flip-flop circuits.Including first order phase inverter, second level phase inverter, the 3rd extremely anti-
Phase device and resetting structure, concrete structure is as follows：
The first order phase inverter includes two PMOSs M2 and M3, NMOS tube M1；Wherein M3 tube grids are managed with M1
Grid is connected to form phase inverter and as the input of data, and the grid of M2 pipes is connected with clock signal clk, used as control data
The gate of the second level is delivered to from the first order.
The second level phase inverter includes two NMOS tubes M4 and M5, PMOS M6；M6 manages the access that is connected with M4 pipes
CLK signal, the input that the output of first order phase inverter is connected as second level phase inverter with M5 tube grids.This grade of phase inverter is
State phase inverter, in pre-charge state, VDD is charged to by M6 by node Y.The gate status phase whether turned on the pipe of M5 pipes
Close.
The one-level reset circuit is by two PMOSs M12 and M13, a NMOS tube M11 composition.M11 is managed and M12 pipe groups
Into phase inverter, M13 pipes are caused to turn on when the rising edge of reset signal RES arrives, nodes X is pulled to VDD level, so as to disappear
The signal of mistake is produced except the uncertainty because of nodes X.
The 3rd pole phase inverter includes two NMOS tubes M7 and M8, PMOS M9；M8 tube grids connect CLK signal use
Transmission between control second level phase inverter and third level phase inverter.M9 manages the second level phase inverter that is connected with the grid of M7 pipes
Output end.
The second level reset circuit is made up of NMOS tube M10, and the drain electrode of M10 pipes is connected with Y nodes, and grid connects
RES signals.The M10 pipes conducting when signal RES rising edges arrive, Y nodes are pulled to ground level, so as to eliminate because of node Y not
Certainty and produce mistake output signal.
As CLK=0, input inverter up-samples the D inputs of phase inverter in nodes X.Second dynamic inverter is in
Pre-charge state, VDD is charged to by M6 by node Y.3rd phase inverter is in maintenance state, because M8 and M9 are turned off.Cause
, in the low level stage of clock, the input of last (static state) phase inverter remains its original value, thus output Q is in for this
Stable state.In the rising edge of clock, dynamic inverter M4-M6 evaluations.If X is high level at rising edge, then section
Point Y discharges.In the 3rd phase inverter M7-M9 conducting of high level stage of clock, the value on Y nodes is sent to output Q.When
In the positive level stage of clock, if D inputs are turned to high level, nodes X is turned to low level.Therefore input must keep steady
It is fixed, until value of the nodes X before rising edge clock is sent to Y.The uncertainty of X, Y point can affect ADC in next cycle
Data conversion, therefore the application respectively increases a reset circuit at X, Y point.Reset circuit is by tetra- mos pipe groups of M10-M13
Into.M10 pipes are the reset transistor of Y nodes, and node is moved to ground potential when reset signal RES rising edge arrives.M11-M13 is X
The reset transistor of node, node is moved to VDD points position when reset signal RES rising edge arrives.
Fig. 2 is shown as ADC inside asynchronous clock circuit, and circuit is made up of ten triggers, the internal circuit knot of trigger
Structure is as shown in Figure 1.The input termination VDD signal of first trigger of circuit, trigger connects valid signals, the termination that resets CLK
Signal, output signal is clk1.The output end of input first trigger of termination of second trigger, trigger connects
Valid signals, the termination that resets CLK signal, output signal is clk2.3rd trigger is input into the defeated of second trigger of termination
Go out end, trigger connects valid signals, the termination that resets CLK signal, output signal is clk3.4th trigger input termination
The output end of the 3rd trigger, trigger connects valid signals, the termination that resets CLK signal, and output signal is clk4.With this
Analogize, the output of previous stage obtains successively signal clk1～clk10 as the input of rear stage.Signal clk10 and signal
Valid, signal CLK are connected by OR gate and produce internal work clock signal clkc.When signal clk1～clk10 is with clkc signals
Sequence is as shown in Figure 3.
Clkc signal generating circuits are as shown in Figure 4.NMOS tube M1～M3 is signal input tube.M1 tube grids connect signal
The grid of clk10, M2 pipe meets signal valid, and the grid of M3 pipes meets signal CLK.The drain electrode of M1～M3 pipes link together with
The gate input that the source electrode of PMOS M4 connects as PMOS M6 and NMOS tube M5.The drain electrode phase of the source electrode of M6 pipes and M5 pipes
Connection forms the output end of circuit, exports clkc signals.
Valid signals are produced by the differential signal that comparator comparative result is exported by an OR circuit.Such as Fig. 5 institutes
Show, M1 and M2 pipes are signal input tube.M1 tube grids meet signal C1 and meet signal C2 with M2 tube grids and compare institute for comparator
The differential signal of output.The drain electrode of M1, M2 pipe links together and connects as PMOS M5 and NMOS with the source electrode of PMOS M3
The gate input of pipe M4.The source electrode of M5 pipes is connected to form the output end of circuit with the drain electrode of M4 pipes, exports valid signals.
Obviously, the above embodiment of the present invention is only intended to clearly illustrate example of the present invention, and is not right
The restriction of embodiments of the present invention.For those of ordinary skill in the field, may be used also on the basis of the above description
To make other changes in different forms.There is no need to be exhaustive to all of embodiment.It is all this
Any modification, equivalent and improvement made within the spirit and principle of invention etc., should be included in the claims in the present invention
Protection domain within.
Claims (10)
1. the asynchronous clock signal based on TSPC circuits produces circuit, it is characterised in that：The asynchronous clock signal produce circuit by
Internal asynchronous clock circuit, valid signal generating circuits and clkc signal generating circuits are constituted；
The internal asynchronous clock circuit is made up of ten TSPC flip-flop circuits, wherein, the internal asynchronous clock circuit
The input termination VDD signal of first trigger, trigger connects the valid signals of valid signal generating circuits output, resets
Termination CLK signal, the output signal of first trigger is clk1；Input first trigger of termination of second trigger
Output end, trigger connects the valid signals, the termination that resets CLK signal, and the output signal of second trigger is clk2；
The output end of the 3rd trigger input second trigger of termination, trigger connects the valid signals, the termination that resets CLK
Signal, the output signal of the 3rd trigger is clk3；The output end of the 4th trigger input the 3rd trigger of termination, touches
Signalling connects the valid signals, the termination that resets CLK signal, and the output signal of the 4th trigger is clk4；By that analogy,
The output of previous stage obtains successively signal clk1～clk10 as the input of rear stage；
Clkc signal generating circuits eventually through by the signal clk10, the valid signals and the CLK signal pass through or
Door connects and produces internal work clock signal clkc.
2. the asynchronous clock signal based on TSPC circuits according to claim 1 produces circuit, it is characterised in that:It is described
TSPC flip-flop circuits are made up of first order phase inverter, second level phase inverter, the 3rd pole phase inverter and resetting structure.
3. the asynchronous clock signal based on TSPC circuits according to claim 2 produces circuit, it is characterised in that:Described
One-level phase inverter includes two PMOSs M2 and M3, NMOS tube M1；Wherein M3 tube grids are connected to form instead with M1 tube grids
Phase device and as the input of data, the grid of M2 pipes is connected with clock signal clk, is delivered to from the first order as control data
The gate of the second level.
4. the asynchronous clock signal based on TSPC circuits according to claim 2 produces circuit, it is characterised in that:Described
Two grades of phase inverters include two NMOS tubes M4 and M5, PMOS M6；M6 manages the access CLK signal that is connected with M4 pipes, the first order
The output node X of phase inverter is connected with M5 tube grids, and as the input of second level phase inverter.
5. the asynchronous clock signal based on TSPC circuits according to claim 2 produces circuit, it is characterised in that:Described
Three pole phase inverters include two NMOS tubes M7 and M8, PMOS M9；It is anti-for controlling the second level that M8 tube grids connect CLK signal
Transmission between phase device and third level phase inverter, M9 pipes and the grid of M7 pipes are connected to Y nodes, and with second level phase inverter
Output end connects.
6. the asynchronous clock signal based on TSPC circuits according to claim 2 produces circuit, it is characterised in that:It is described multiple
Bit architecture includes first order reset circuit, and the first order reset circuit is by two PMOSs M12 and M13, NMOS tube M11
Composition, M11 pipes constitute phase inverter with M12 pipes.
7. the asynchronous clock signal based on TSPC circuits according to claim 6 produces circuit, it is characterised in that:It is described multiple
Bit architecture also includes a second level reset circuit, and the second level reset circuit is made up of NMOS tube M10, the leakage of M10 pipes
Pole is connected with Y nodes, and grid connects RES signals.
8. the asynchronous clock signal based on TSPC circuits according to claim 1 produces circuit, it is characterised in that:It is described
Valid signal generating circuits are produced by the differential signal that comparator comparative result is exported by an OR circuit.
9. the asynchronous clock signal based on TSPC circuits according to claim 8 produces circuit, it is characterised in that:It is described
Valid signal generating circuits further include signal input tube, PMOS M3, NMOS tube M4, PMOS being made up of M1 and M2 pipes
Pipe M5, wherein M1 tube grids connect signal C1 and M2 tube grids and meet signal C2 and compared the differential signal for exporting by comparator,
The drain electrode of M1, M2 pipe link together connect with the source electrode of PMOS M3 as PMOS M5 and NMOS tube M4 grid be input into
End, the source electrode of M5 pipes is connected to form the output end of circuit with the drain electrode of M4 pipes, exports the valid signals.
10. the asynchronous clock signal based on TSPC circuits according to claim 1 produces circuit, it is characterised in that:It is described
Clkc signal generating circuits include NMOS tube M1～M3, PMOS M4, M6 and NMOS tube M5, and NMOS tube M1～M3 is signal
Input pipe；The grid of wherein NMOS tube M1 meets signal clk10, and the grid of NMOS tube M2 meets the signal valid, NMOS tube M3
Grid meets signal CLK；The drain electrode of NMOS tube M1～M3 link together connect with the source electrode of PMOS M4 as PMOS M6 with
The gate input of NMOS tube M5, the source electrode of PMOS M6 is connected to form the output end of circuit with the drain electrode of NMOS tube M5, most
The clkc signals are exported eventually.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610975801.9A CN106571825A (en) | 2016-11-07 | 2016-11-07 | Asynchronous clock signal generation circuit based on TSPC circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610975801.9A CN106571825A (en) | 2016-11-07 | 2016-11-07 | Asynchronous clock signal generation circuit based on TSPC circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109639268A (en) * | 2018-11-20 | 2019-04-16 | 珠海市杰理科技股份有限公司 | D type flip flop and phase frequency detector circuit |
| CN113945834A (en) * | 2021-09-30 | 2022-01-18 | 王一雄 | High-frequency clock jitter measuring circuit, device, system and method |
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| WO1997015116A3 (en) * | 1995-10-17 | 1997-05-15 | Forskarpatent I Linkoeping Ab | Tspc latches and flipflops |
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| WO1997015116A3 (en) * | 1995-10-17 | 1997-05-15 | Forskarpatent I Linkoeping Ab | Tspc latches and flipflops |
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| CHUN-CHENG LIU等: "A 10-bit 50Ms/s SAR ADC With a Monotonic Capacitor Switching Procedure", 《IEEE JOURNAL OF SOLID-STATE CIRCUITS》 * |
| PRAGADA V SATYA CHALLAYYA NAIDU等: "A 10-Bit 50-MS/s 11.9μW SAR ADC with CM Biased Capacitor Switching Method", 《2016 INTERNATIONAL CONFERENCE ON INVENTIVE COMPUTATION TECHNOLOGIES(ICICT)》 * |
| 汪正锋: "用于植入式医疗设备的超低功耗SAR ADC设计", 《中国优秀硕士学位论文全文数据库信息科技辑》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109639268A (en) * | 2018-11-20 | 2019-04-16 | 珠海市杰理科技股份有限公司 | D type flip flop and phase frequency detector circuit |
| CN113945834A (en) * | 2021-09-30 | 2022-01-18 | 王一雄 | High-frequency clock jitter measuring circuit, device, system and method |
| CN113945834B (en) * | 2021-09-30 | 2024-03-19 | 王一雄 | High-frequency clock jitter measuring circuit, device, system and method |
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Application publication date: 20170419 |