CN109639268A - D type flip flop and phase frequency detector circuit - Google Patents
D type flip flop and phase frequency detector circuit Download PDFInfo
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- CN109639268A CN109639268A CN201811385705.4A CN201811385705A CN109639268A CN 109639268 A CN109639268 A CN 109639268A CN 201811385705 A CN201811385705 A CN 201811385705A CN 109639268 A CN109639268 A CN 109639268A
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- effect tube
- flip flop
- type flip
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
Abstract
The present invention relates to a kind of d type flip flop and phase frequency detector circuits.Wherein, d type flip flop constitutes true single clock logical construction dynamic D trigger by input circuit, precharging circuit and output circuit, realizes the basic function of d type flip flop.Meanwhile by the first latch cicuit, stablize the current potential of d type flip flop precharging circuit output end when working frequency is lower, to expand the operating frequency range of d type flip flop.Meanwhile phase frequency detector expands the operating frequency range of phase frequency detector by using the first d type flip flop and the second d type flip flop of wide operating frequency range.Simultaneously, after introducing control signal, by the first control module and the second control module, make reference clock signal and the phase difference of feedback clock signal in π to 2 π, the reset signal of output to the first d type flip flop and the second d type flip flop will not be generated by resetting feed circuit, to eliminate phase demodulation blind area.Based on this, a kind of wide working frequency is provided, without phase demodulation blind area and the fast phase frequency detector of lock speed.
Description
Technical field
The present invention relates to IC design technical fields, more particularly to a kind of d type flip flop and phase frequency detector electricity
Road.
Background technique
Phaselocked loop (phase locked loop PLL) circuit is integrated electricity as a kind of typical feedback control circuit
Indispensable important component in road.Currently, with the development of technology, phase-locked loop circuit is widely used in communication technology neck
In domain.
Wherein, as an important component of phase-locked loop circuit, phase frequency detector is to constitute feedback control circuit
An important ring.Traditional phase frequency detector mainly includes the phase frequency detector based on d type flip flop, and traditional phase frequency detector
It can be by increasing delay time come deadband eliminating phenomenon.
However, traditional d type flip flop cisco unity malfunction in low frequency, limits the frequency acquisition model of phase frequency detector
It encloses.Meanwhile by way of increasing delay time come deadband eliminating phenomenon, in two input signal phases of phase frequency detector
When nearly 2 π of differential, the clock edge to arrive in reseting procedure will be lost, so that mistake occurs for output polarity, that is, reflect
Phase blind area phenomenon.When the working frequency of phase frequency detector is very high, phase demodulation blind area phenomenon can seriously affect the lock of phase frequency detector
Constant speed degree.
Summary of the invention
Based on this, it is necessary to when traditional d type flip flop is in low frequency aiming at the problem that cisco unity malfunction, provide a kind of D touching
Send out device.
A kind of d type flip flop, including input circuit, precharging circuit, output circuit and the first latch cicuit；
The input terminal of input circuit is for accessing logic input signal, and the clock signal terminal of input circuit is for when accessing
Clock signal, the input terminal of the output end connection precharging circuit of input circuit；
The clock signal terminal of precharging circuit is used for incoming clock signal, and the reset terminal of precharging circuit resets letter for accessing
Number, the input terminal of the output end connection output circuit of precharging circuit；
The clock signal terminal of output circuit is used for incoming clock signal, and the output end of output circuit is defeated for exporting logic
Signal out；
The clock signal terminal of first latch cicuit is used for incoming clock signal, and the reset terminal of the first latch cicuit is for connecing
Enter reset signal, the output end of the latch control terminal connection precharging circuit of the first latch cicuit；
The confession of the feeder ear of input circuit, the feeder ear for prestoring circuit, the feeder ear of output circuit and the first latch cicuit
Electric end is used to access operating voltage；
The public affairs of the common end of input circuit, the common end for prestoring circuit, the common end of output circuit and the first latch cicuit
End is used to connection common potential end altogether.
Input circuit includes the first field-effect tube, the second field-effect tube and third field-effect in one of the embodiments,
Pipe；
The source electrode of first field-effect tube is the feeder ear of input circuit, and the grid of the first field-effect tube is input circuit
Input terminal, the source electrode of drain electrode the second field-effect tube of connection of the first field-effect tube；
The grid of second field-effect tube is the clock signal terminal of input circuit, and the drain electrode of the second field-effect tube is input electricity
The output end on road；
The drain electrode of drain electrode the second field-effect tube of connection of third field-effect tube, the grid of third field-effect tube are input electricity
The input terminal on road, the source electrode of third field-effect tube are the common end of input circuit.
Precharging circuit includes the 4th field-effect tube, the 5th field-effect tube, the 6th field-effect in one of the embodiments,
Pipe and the 7th field-effect tube；
The source electrode of 4th field-effect tube is the feeder ear of precharging circuit, and the grid of the 4th field-effect tube is precharging circuit
Reset terminal, the source electrode of drain electrode the 5th field-effect tube of connection of the 4th field-effect tube；
The grid of 5th field-effect tube is the clock signal terminal of precharging circuit, and the drain electrode of the 5th field-effect tube is precharge
The output end on road, and connect the drain electrode of the 6th field-effect tube；
The grid of 6th field-effect tube is the input terminal of precharging circuit, and the source electrode of the 6th field-effect tube connects the 7th effect
Should pipe drain electrode；
The grid of 7th field-effect tube is the clock signal terminal of precharging circuit, and the source electrode of the 7th field-effect tube is precharge
The common end on road.
Output circuit includes the 8th field-effect tube, the 9th field-effect tube, the tenth field-effect in one of the embodiments,
Pipe, the 11st field-effect tube and the second latch cicuit；
The source electrode of 8th field-effect tube is the feeder ear of output circuit, and the grid of the 8th field-effect tube is output circuit
Clock signal terminal, the drain electrode of drain electrode the 9th field-effect tube of connection of the 8th field-effect tube, and connect the input of the second latch cicuit
End, the output end of the second latch cicuit are the output end of output circuit；
The grid of 9th field-effect tube connects the drain electrode of the 11st field-effect tube, and is the input terminal of output circuit, and the 9th
The source electrode of field-effect tube connects the drain electrode of the tenth field-effect tube, and the grid of the tenth field-effect tube is the clock signal of output circuit
The source electrode of end, the tenth field-effect tube and the 11st field-effect tube is the common end of output circuit.
The second latch cicuit includes the first not circuit and the second not circuit in one of the embodiments,；
The input terminal of first not circuit is the input terminal of the second latch cicuit, and connects the output of the second not circuit
End；
The output end of first not circuit connects the input terminal of the second not circuit, and is the output of the second latch cicuit
End.
The first latch cicuit includes the 12nd field-effect tube, the 13rd field-effect tube, the in one of the embodiments,
14 field-effect tube, the 15th field-effect tube, the 16th field-effect tube and the 17th field-effect tube；
The source electrode of 12nd field-effect tube and the source electrode of the 16th field-effect tube are the feeder ear of the first latch cicuit, the
The source electrode of 15 field-effect tube and the source electrode of the 17th field-effect tube are the common end of the first latch cicuit；
The grid of 13rd field-effect tube is the reset terminal of the first latch cicuit, and the grid of the 14th field-effect tube is the
The clock signal terminal of one latch cicuit；
The source electrode of drain electrode the 13rd field-effect tube of connection of 12nd field-effect tube, the source electrode of the 14th field-effect tube connect
Connect the drain electrode of the 15th field-effect tube；
The grid of 12nd field-effect tube connects the drain electrode of the 16th field-effect tube and the drain electrode of the 17th field-effect tube；
The drain electrode connection drain electrode of the 14th field-effect tube of 13rd field-effect tube, the grid of the 16th field-effect tube and
The grid of 17th field-effect tube, and be the latch control terminal of the first latch cicuit.
Above-mentioned d type flip flop constitutes true single clock logical construction by input circuit, precharging circuit and output circuit
Dynamic D trigger realizes the basic function of d type flip flop.Meanwhile by the first latch cicuit, stablize d type flip flop in work frequency
The current potential of precharging circuit output end when rate is lower, to expand the operating frequency range of d type flip flop.
Meanwhile present invention is alternatively directed to phase frequency detectors will appear phase demodulation blind area, influence the lock speed of phase frequency detector
Problem provides a kind of phase frequency detector.
A kind of phase frequency detector, including the first d type flip flop, the second d type flip flop, first control circuit, second control circuit
With reset feed circuit；Wherein, the first d type flip flop and the second d type flip flop are above-mentioned d type flip flop；
Each clock signal terminal is for accessing reference clock signal, each clock letter in the second d type flip flop in first d type flip flop
Number end for accessing feedback clock signal；
The first input end of first control circuit is used for incoming control signal, and the second input terminal of first control circuit is used
In access feedback clock signal, the third input terminal of first control circuit connects the output of output circuit in the first d type flip flop
End, the output end of first control circuit connect the input terminal of input circuit in the first d type flip flop；
The first input end of second control circuit is used for incoming control signal, and the second input terminal of second control circuit is joined
Clock signal is examined, the third input terminal of second control circuit connects the output end of output circuit in the second d type flip flop, the second control
The output end of circuit processed connects the input terminal of input circuit in the second d type flip flop；
The output end connection of output circuit resets the first input end of feed circuit, the 2nd D triggering in first d type flip flop
The output end connection of output circuit resets the second input terminal of feed circuit in device；Reset the output end connection the of feed circuit
Each reset terminal in each reset terminal and the second d type flip flop in one d type flip flop.
First control circuit includes the first OR-NOT circuit and the first NAND gate circuit in one of the embodiments,；
One input terminal of the first OR-NOT circuit is the first input end of first control circuit, and another input terminal is first
Second input terminal of control circuit；One input terminal of output end the first NAND gate circuit of connection of the first OR-NOT circuit, first
Another input terminal of NAND gate circuit is the third input terminal of first control circuit.
Second control circuit includes the second OR-NOT circuit and the second NAND gate circuit in one of the embodiments,；
One input terminal of the second OR-NOT circuit is the first input end of second control circuit, and another input terminal is second
Second input terminal of control circuit；One input terminal of output end the second NAND gate circuit of connection of the second OR-NOT circuit, second
Another input terminal of NAND gate circuit is the third input terminal of second control circuit.
Resetting feed circuit in one of the embodiments, includes third NAND gate circuit and third not circuit；
One input terminal of third NAND gate circuit is the first input end for resetting feed circuit, third NAND gate circuit
Another input terminal resets the second input terminal of feed circuit, the output end connection third not circuit of third NAND gate circuit
Input terminal；The output end of third not circuit is the output end for resetting feed circuit.
It in one of the embodiments, further include the first buffered gate and the second buffered gate；
Each clock signal terminal is used to pass sequentially through input terminal and the output end access of the first buffered gate in first d type flip flop
Reference clock signal, each clock signal terminal is used to pass sequentially through the input terminal and output end of the second buffered gate in the second d type flip flop
Access feedback clock signal.
Resetting feed circuit in one of the embodiments, further includes third buffered gate and the 4th buffered gate；
The output end of the input terminal connection third buffered gate of third NAND gate circuit, the input terminal of third buffered gate connect
Connect the output end of output circuit in the first d type flip flop；
Another input terminal of third NAND gate circuit connects the output end of the 4th buffered gate, the input terminal of the 4th buffered gate
Connect the output end of output circuit in the first d type flip flop.
Resetting feed circuit in one of the embodiments, further includes delay circuit；
The output end of third NAND gate circuit connects the input terminal of third not circuit by delay circuit.
Above-mentioned phase frequency detector is opened up by using the first d type flip flop and the second d type flip flop of wide operating frequency range
Open up the operating frequency range of phase frequency detector.Meanwhile after introducing control signal, passes through the first control module and second and control
Module makes reference clock signal and the phase difference of feedback clock signal in π to 2 π, and output will not be generated by resetting feed circuit
To the reset signal of the first d type flip flop and the second d type flip flop, to eliminate phase demodulation blind area.Based on this, a kind of wide work frequency is provided
Rate, without phase demodulation blind area and the fast phase frequency detector of lock speed.
Detailed description of the invention
Fig. 1 is the d type flip flop circuit modular structure figure of an embodiment；
Fig. 2 is d type flip flop graphical diagram；
Fig. 3 is the d type flip flop circuit diagram of an embodiment；
Fig. 4 is the d type flip flop circuit diagram of another embodiment；
Fig. 5 is the phase frequency detector function structure chart of an embodiment；
Fig. 6 is the phase frequency detector building-block of logic of an embodiment；
Fig. 7 is the working waveform figure of phase frequency detector.
Specific embodiment
Purpose, technical solution and technical effect for a better understanding of the present invention, below in conjunction with drawings and examples
Further explaining illustration is carried out to the present invention.State simultaneously, embodiments described below for explaining only the invention, and
It is not used in the restriction present invention
The embodiment of the present invention provides a kind of d type flip flop.
Fig. 1 is the d type flip flop circuit modular structure figure of an embodiment, as shown in Figure 1, the d type flip flop of an embodiment
Including input circuit 100, precharging circuit 101, output circuit 102 and the first latch cicuit 103；
The input terminal D of input circuit 100 is for accessing logic input signal, the clock signal terminal clk of input circuit 100
For incoming clock signal, the input terminal of the output end a connection precharging circuit 101 of input circuit 100；
Fig. 2 is a d type flip flop graphical diagram, as shown in Fig. 2, traditional d type flip flop includes for accessing logic input signal
Input terminal D1, for the clock signal terminal clk1 of incoming clock signal, the reset terminal reset1 for accessing reset signal,
For exporting the output end Q1 of logic output signal and for the output end Q1 of anti-phase output inverted logic output signal1.Its
In, in the present embodiment, the input terminal D of input circuit 100 is the function of conventional D flip flop input terminal D1, this embodiment party
In formula, each clock signal terminal clk is the function of conventional D flip flop input terminal clk1, and the output end Q of output circuit 102 is
The function of conventional D flip flop output end Q1, each reset terminal reset are the function of conventional D flip flop reset terminal reset1.
Wherein, in the present embodiment, input circuit 100 is used to receive low level letter in its clock signal terminal clk
Number, input circuit 100 realizes output end a to the reverse phase of input terminal D, i.e. inverter circuit can be selected in input circuit 100.
Fig. 3 is the d type flip flop circuit diagram of an embodiment in one of the embodiments, as shown in figure 3, input circuit
100 include the first field-effect tube M1, the second field-effect tube M2 and third field-effect tube M3；
The source electrode of first field-effect tube M1 is the feeder ear VDD of input circuit 100, and the grid of the first field-effect tube M1 is
The source electrode of the second field-effect tube M2 of drain electrode connection of the input terminal D, the first field-effect tube M1 of input circuit 100；
The grid of second field-effect tube M2 is the clock signal terminal clk of input circuit 100, the leakage of the second field-effect tube M2
The extremely output end a of input circuit 100；
The drain electrode of the second field-effect tube M2 of drain electrode connection of third field-effect tube M3, the grid of third field-effect tube M3 are
The source electrode of the input terminal D of input circuit 100, third field-effect tube M3 are the common end VSS of input circuit 100.
Wherein, the first field-effect tube M1, the second field-effect tube M2 and third field-effect tube M3 constitute inverter circuit,
When the received clock signal of clock signal terminal clk is jumped from low level to high level, if input terminal D accesses low level signal,
Output end a output is high level signal.N-channel field effect is selected as preferably embodiment, a first field-effect tube M1
Ying Guan, the second field-effect tube M2 select N-channel field-effect tube, and third field-effect tube M3 selects P-channel field-effect transistor (PEFT) pipe.It needs
It is bright, it is combined in conjunction with different clocks signal and field-effect tube type selecting, based on the inverter functionality for realizing input circuit 100
Under the premise of, the first field-effect tube M1, the second field-effect tube M2 and third field-effect tube M3 are not limited to above-mentioned type selecting.
The clock signal terminal clk of precharging circuit 101 is used for incoming clock signal, the reset terminal reset of precharging circuit 101
For accessing reset signal, the input terminal of the output end b connection output circuit 102 of precharging circuit 101；
Wherein, precharging circuit 101 is used for when its clock signal terminal clk receives low level signal, and output end b is pre-
Charge to high level.
In one of the embodiments, as shown in figure 3, precharging circuit 101 includes the 4th field-effect tube M4, the 5th effect
It should pipe M5, the 6th field-effect tube M6 and the 7th field-effect tube M7；
The source electrode of 4th field-effect tube M4 is the feeder ear VDD of precharging circuit 101, and the grid of the 4th field-effect tube M4 is
The source electrode of the 5th field-effect tube M5 of drain electrode connection of the reset terminal reset, the 4th field-effect tube M4 of precharging circuit；
The grid of 5th field-effect tube M5 is the clock signal terminal clk of precharging circuit 101, the leakage of the 5th field-effect tube M5
The extremely output end b of precharging circuit 101, and connect the drain electrode of the 6th field-effect tube M6；
The grid of 6th field-effect tube M6 is the input terminal of precharging circuit 101, the source electrode connection the of the 6th field-effect tube M6
The drain electrode of seven field-effect tube M7；
The grid of 7th field-effect tube M7 is the clock signal terminal clk of precharging circuit 101, the source of the 7th field-effect tube M7
The extremely common end VSS of precharging circuit 101.
N-channel field-effect tube, the 5th field-effect tube are selected as preferably embodiment, a 4th field-effect tube M4
M5 selects N-channel field-effect tube, and the 6th field-effect tube M6 selects P-channel field-effect transistor (PEFT) pipe, and the 7th field-effect tube M7 selects P-channel
Field-effect tube.It should be noted that being combined in conjunction with different clocks signal and field-effect tube type selecting, based on realization clock signal
By under the premise of output end b preliminary filling to high level when end clk receives specific clock signal, the 4th field-effect tube M4, the 5th
Effect pipe M5, the 6th field-effect tube M6 and the 7th field-effect tube M7 are not limited to above-mentioned type selecting.
The clock signal terminal clk of output circuit 102 is used for incoming clock signal, and the output end Q of output circuit 102 is used for
Export logic output signal；
Wherein, output circuit 102 is used to the output end b of precharging circuit 101 carrying out anti-phase output, i.e. output circuit 102
Inverter circuit can be selected.
In one of the embodiments, as shown in figure 3, output circuit 102 includes the 8th field-effect tube M8, the 9th effect
It should pipe M9, the tenth field-effect tube M10, the 11st field-effect tube M11 and the second latch cicuit 200；
The source electrode of 8th field-effect tube M8 is the feeder ear VDD of output circuit 102, and the grid of the 8th field-effect tube M8 is
The drain electrode of the 9th field-effect tube M9 of drain electrode connection of the clock signal terminal clk, the 8th field-effect tube M8 of output circuit 102, and even
The input terminal of the second latch cicuit 200 is connect, the output end of the second latch cicuit 200 is the output end Q of output circuit 102；
The grid of 9th field-effect tube M9 connects the drain electrode of the 11st field-effect tube M11, and is the defeated of output circuit 102
Enter and hold b, the source electrode of the 9th field-effect tube M9 connects the drain electrode of the tenth field-effect tube M10, and the grid of the tenth field-effect tube M10 is
The source electrode of the clock signal terminal clk, the tenth field-effect tube M10 and the 11st field-effect tube M11 of output circuit 102 are output
The common end VSS of circuit 102.
N-channel field-effect tube, the 9th field-effect tube are selected as preferably embodiment, a 8th field-effect tube M8
M9 selects P-channel field-effect transistor (PEFT) pipe, and the tenth field-effect tube M10 selects P-channel field-effect transistor (PEFT) pipe, and the 11st field-effect tube M11 selects P
Channel field-effect pipe.It should be noted that being combined in conjunction with different clocks signal and field-effect tube type selecting, based on realization clock
Under the premise of output end b is carried out anti-phase output when signal end clk receives specific clock signal, the 8th field-effect tube M8, the
Nine field-effect tube M9, the tenth field-effect tube M10 and the 11st field-effect tube M11 are not limited to above-mentioned type selecting.
The clock signal terminal clk of first latch cicuit 103 is used for incoming clock signal, the reset of the first latch cicuit 103
End reset is for accessing reset signal, the output end b of the latch control terminal connection precharging circuit 102 of the first latch cicuit 103；
Wherein, the output end b of precharging circuit 102, can be due to field-effect in precharging circuit 102 after preliminary filling to high level
The reason of junction capacitance, constantly electric discharge can reduce current potential.When clock signal frequency is higher, discharge time is very short, and current potential is insufficient
To change the output state of d type flip flop.When clock signal frequency is lower, the discharge time of output end b is long, leads to output end b
Become level, change the output state of d type flip flop, and then mistake is caused to jump.In the present embodiment, it can be latched by first
Circuit 103 stablizes the high level state of the output end b of precharging circuit 102, mistake jump caused by preventing because of electric discharge.Wherein,
One latch cicuit 103 has the function of latch structure, with stablize output end b on behalf of interior.
In one of the embodiments, as shown in figure 3, the first latch cicuit 103 includes the 12nd field-effect tube M12, the
13 field-effect tube M13, the 14th field-effect tube M14, the 15th field-effect tube M15, the 16th field-effect tube M16 and the tenth
Seven field-effect tube M17；
The source electrode of 12nd field-effect tube M12 and the source electrode of the 16th field-effect tube M16 are the first latch cicuit 103
The source electrode of feeder ear VDD, the 15th field-effect tube M15 and the source electrode of the 17th field-effect tube M17 are the first latch cicuit 103
Common end VSS；
The grid of 13rd field-effect tube M13 is the reset terminal reset of the first latch cicuit 103, the 14th field-effect tube
The grid of M14 is the clock signal terminal clk of the first latch cicuit 103；
The source electrode of the 13rd field-effect tube M13 of drain electrode connection of 12nd field-effect tube M12, the 14th field-effect tube M14
Source electrode connect the 15th field-effect tube M15 drain electrode；
The grid of 12nd field-effect tube M12 connects the drain electrode and the 17th field-effect tube of the 16th field-effect tube M16
The drain electrode of M17；
The drain electrode of the 14th field-effect tube M14 of drain electrode connection of 13rd field-effect tube M13, the 16th field-effect tube M16
Grid and the 17th field-effect tube M17 grid, and be the first latch cicuit 103 latch control terminal.
P-channel field-effect transistor (PEFT) pipe, the 13rd effect are selected as preferably embodiment, a 12nd field-effect tube M12
Should pipe M13 select N-channel field-effect tube, the 14th field-effect tube M14 select P-channel field-effect transistor (PEFT) pipe, the 15th field-effect tube
M15 selects P-channel field-effect transistor (PEFT) pipe, and the 16th field-effect tube M16 selects N-channel field-effect tube, the 17th field-effect tube M17 choosing
With P-channel field-effect transistor (PEFT) pipe.It should be noted that being combined in conjunction with different clocks signal and field-effect tube type selecting, based on realization lock
Storage structure, under the premise of the current potential to stablize output end b, the 12nd field-effect tube M12, the 13rd field-effect tube M13,
14 field-effect tube M14, the 15th field-effect tube M15, the 16th field-effect tube M16 and the 17th field-effect tube M17 are not limited to
Above-mentioned type selecting.
The feeder ear VDD of input circuit 100, the feeder ear VDD for prestoring circuit 101, output circuit 102 feeder ear VDD
Access operating voltage is used to the feeder ear VDD of the first latch cicuit 103；
Operating voltage can make feeder ear VDD be in logic-high state.Wherein, the size of operating voltage can be according to reality
The job requirement of border d type flip flop determines.
The common end VSS of input circuit 100, the common end VSS for prestoring circuit 101, output circuit 102 common end VSS
Connection common potential end is used to the common end VSS of the first latch cicuit 103.
Wherein, the voltage at common potential end is low-voltage, and each common end VSS can be made to be in logic low state.Generally
Ground, common potential end are ground terminal.
The d type flip flop of an above-mentioned embodiment is made up of input circuit 100, precharging circuit 101 and output circuit 102
True single clock logical construction dynamic D trigger, realizes the basic function of d type flip flop.Meanwhile passing through the first latch cicuit
103, stablize the current potential of d type flip flop 102 output end b of precharging circuit when working frequency is lower, to expand the work of d type flip flop
Frequency range.
Fig. 4 is the d type flip flop circuit diagram of another embodiment in one of the embodiments, as shown in figure 4, the second lock
Depositing circuit 200 includes the first not circuit INV1 and the second not circuit INV2；
The input terminal of the second latch cicuit of input terminal 200 of first not circuit INV1, and connect the second not circuit
The output end of INV2；
The output end of first not circuit INV1 connects the input terminal of the second not circuit INV2, and latches electricity for second
The output end on road 200.
Wherein, by the reverse phase of the reverse phase of the first not circuit INV1 and the second not circuit INV2, for logic output letter
Number stable common-mode point is provided, stablizes the output state of d type flip flop.
The embodiment of the present invention also provides a kind of phase frequency detector.
Fig. 5 is the phase frequency detector function structure chart of an embodiment, as shown in figure 5, the frequency and phase discrimination of an embodiment
Device includes the first d type flip flop DFF0, the second d type flip flop DFF1, first control circuit 300, second control circuit 301 and resets
Feed circuit 302；Wherein, the first d type flip flop DFF0 and 2-D trigger DFF1 is the D triggering of any of the above-described embodiment
Device；
Each clock signal terminal clk is for accessing reference clock signal Fref, the second d type flip flop in first d type flip flop DFF0
Each clock signal terminal clk is for accessing feedback clock signal Fbck in DFF1；
The first input end of first control circuit 300 is used for incoming control signal Fast_en, first control circuit 300
Second input terminal connects the first D triggering for accessing feedback clock signal Fbck, the third input terminal of first control circuit 300
The output end Q of output circuit in device DFF0, the output end of first control circuit 300, which connects, inputs electricity in the first d type flip flop DFF0
The input terminal D on road；
The first input end of second control circuit 301 is used for incoming control signal Fast_en, and the of second control circuit
It is defeated in two input terminal reference clock signal Fref, the third input terminal connection 2-D trigger DFF1 of second control circuit 301
The input terminal of input circuit in the output end Q of circuit out, the output end connection 2-D trigger DFF1 of second control circuit 301
D；
Wherein, first control circuit 300 and second control circuit 301 are used for the control signal Fast_en according to access,
Phase frequency detector is set to be in express lock mode or normal mode of operation.In a normal mode of operation, provided by the present embodiment
The working method of phase frequency detector and common phase frequency detector is no different.Under express lock mode, in reference clock signal Fref
For phase difference with feedback clock signal Fbck in 0~π, reset can be generated by resetting feedback module 302 in each phase cycling
Signal；Reference clock signal Fref and feedback clock signal Fbck phase difference in π~2 π, reset feedback module 302 not
Reset signal can be generated, to eliminate phase demodulation blind area.
Fig. 6 is the phase frequency detector building-block of logic of an embodiment in one of the embodiments, as shown in Fig. 6,
First control circuit 300 includes the first OR-NOT circuit nor0 and the first NAND gate circuit nand0；
An input terminal of first OR-NOT circuit nor0 is the first input end of first control circuit 300, another input terminal
For the second input terminal of first control circuit 300；The output end of first OR-NOT circuit nor0 connects the first NAND gate circuit
An input terminal of nand0, another input terminal of the first NAND gate circuit nand0 are that the third of first control circuit 300 inputs
End.
In one of the embodiments, as shown in fig. 6, second control circuit 301 include the second OR-NOT circuit nor1 and
Second NAND gate circuit nand1；
An input terminal of second OR-NOT circuit nor1 is the first input end of second control circuit 301, another input terminal
For the second input terminal of second control circuit 301；The output end of second OR-NOT circuit nor1 connects the second NAND gate circuit
An input terminal of nand1, another input terminal of the second NAND gate circuit nand1 are that the third of second control circuit 301 inputs
End.
The output end Q connection of output circuit resets the first input end UP of feed circuit 302 in first d type flip flop DFF0,
The output end Q connection of output circuit resets the second input terminal DN of feed circuit 302 in second d type flip flop DFF0；Reset feedback
Each reset terminal in each reset terminal reset and the second d type flip flop DFF1 in the first d type flip flop DFF0 of output end connection of circuit 302
reset。
Wherein, the first input end UP for resetting feed circuit 302 makees the output all the way of phase frequency detector, resets feedback electricity
The second input terminal DN on road 302 makees the another output of phase frequency detector.Wherein, first input end UP and the second input terminal DN
Output can by the rising edge of clock signal trigger export.
In one of the embodiments, as shown in fig. 6, resetting feed circuit 302 includes third NAND gate circuit nand2
With third not circuit inv0；
An input terminal of third NAND gate circuit nand2 be reset feed circuit 302 first input end UP, third with
Another input terminal of not circuit nand2 resets the second input terminal DN of feed circuit 302, third NAND gate circuit nand2's
The input terminal of output end connection third not circuit inv0；The output end of third not circuit inv0 is to reset feed circuit 302
Output end.
Wherein, the output end of feed circuit 302 is resetted for each multiple into the first d type flip flop DFF0 according to certain trigger
Each reset terminal reset output reset signal in the end reset and the second d type flip flop DFF1 of position.
Below with the working method of the phase frequency detector of the present embodiment, the phase frequency detector of the present embodiment is explained:
Fig. 7 is the working waveform figure of phase frequency detector, as shown in fig. 7, in the initial state, the first D in phase frequency detector
Trigger DDF0 output end Q current potential qup and the second d type flip flop DDF1 output end Q current potential qdn are reset to low level, and at this time
The input terminal D of one d type flip flop DFF0 is high level, and output end Q current potential qup is high level.When control signal Fast_en is
When low level, phase frequency detector work is feedback clock signal in express lock mode, the output of the first OR-NOT circuit nor0
The output of the inversion signal fbckb, the second OR-NOT circuit nor1 of Fbck are the inversion signal of reference clock signal Fref
frefb.When the phase difference of reference clock signal Fref signal and feedback clock signal Fbck signal is 0~π, i.e. in Fig. 7
A~c period.At a moment, reference clock signal Fref rising edge triggers the first d type flip flop DFF0 output end Q current potential qup
For high level.When b moment feedback clock signal Fbck rising edge arrives, the inversion signal frefb of reference clock signal Fref
It is necessarily low level, and output end Q current potential qup is high level, then the output signal after the second NAND gate circuit nand1
D1 is high level.Output end UP and output end the DN jump of phase frequency detector are high level, and generate reset signal and be transmitted to again
Position end reset.Due to the delay time of reset signal, i.e. b~d period or i~j period in Fig. 7.First d type flip flop
The d moment of DFF0 output end Q current potential qup, the second d type flip flop DDF1 output end Q current potential qdn after reset signal resets
For low level.In this case, phase frequency detector work is in general mode.
As c~e of the phase difference of reference clock signal Fref and feedback clock signal Fbck in π~2 π, i.e. in Fig. 7
Period or f~h period.At the e moment, reference clock signal Fref rising edge triggers the first D trigger DFF0 output end
Q current potential qup is high level.At the g moment, when feedback clock signal Fbck rising edge arrives, inversion signal frefb is necessarily high
Level, and output end Q current potential qup is also high level, then output signal d1 is low after the second NAND gate circuit nand1
Level.Such second d type flip flop DFF1 output end Q current potential qdn is that low level reaches so as to avoid the generation of reset signal
The purpose of dead zone-eliminating.In addition, accelerating since phase frequency detector output end UP keeps high level to charge charge pump for a long time
The lock speed of phase frequency detector.
When controlling signal Fast_en is high level, phase frequency detector works in general mode.First d type flip flop DFF0
Input terminal D, the second d type flip flop DFF1 input terminal D be high level signal, working method is identical as common phase frequency detector.
At this point, the phase frequency detector of different mode is suitable for different input frequency situations, the phase frequency detector of the present embodiment is increased
Application flexibility.
Above-mentioned phase frequency detector is triggered by using the first d type flip flop DFF0 of wide operating frequency range and the 2nd D
Device DFF1 expands the operating frequency range of phase frequency detector.Meanwhile after introducing control signal, pass through the first control module
300 and second control module 301, make the phase difference of reference clock signal Fref and feedback clock signal Fbck in π to 2 π,
The reset signal of output to the first d type flip flop DFF0 and the second d type flip flop DFF1 will not be generated by resetting feed circuit 302, to disappear
Except phase demodulation blind area.Based on this, a kind of wide working frequency is provided, without phase demodulation blind area and the fast phase frequency detector of lock speed.
In one of the embodiments, as shown in fig. 6, phase frequency detector further includes the first buffered gate buffer0 and second
Buffered gate buffer1；
Each clock signal terminal clk is used to pass sequentially through the input of the first buffered gate buffer0 in first d type flip flop DFF0
End and output end access reference clock signal Fref, and each clock signal terminal clk is for passing sequentially through in the second d type flip flop DFF1
The input terminal and output end of second buffered gate buffer1 accesses feedback clock signal Fref.
Wherein, the driving capability that reference clock signal Fref is improved by the first buffered gate buffer0, it is slow by second
The driving capability of chongmen buffer1 raising feedback clock signal Fref.
In one of the embodiments, as shown in fig. 6, resetting feed circuit 302 further includes third buffered gate buffer2
With the 4th buffered gate buffer3；
The output end of the input terminal connection third buffered gate buffer2 of third NAND gate circuit nand2, third buffering
The input terminal of door buffer2 connects the output end Q of output circuit in the first d type flip flop DFF0；
Another input terminal of third NAND gate circuit nand2 connects the output end of the 4th buffered gate buffer3, and the 4th is slow
The input terminal of chongmen buffer3 connects the output end Q of output circuit in the second d type flip flop DFF1.
Wherein, the drive of the output end Q of output circuit in the first d type flip flop DFF0 is improved by third buffered gate buffer2
Kinetic force improves the driving energy of the output end Q of output circuit in the second d type flip flop DFF1 by the 4th buffered gate buffer3
Power.
In one of the embodiments, as shown in fig. 6, resetting feed circuit 302 further includes delay circuit delay；
The output end of third NAND gate circuit nand2 is defeated by delay circuit delay connection third not circuit inv0's
Enter end.
Wherein, signal delay time is increased by delay circuit delay, with deadband eliminating.
Each technical characteristic of above embodiments can be combined arbitrarily, for simplicity of description, not to above-described embodiment
In each technical characteristic it is all possible combination be all described, as long as however, the combination of these technical characteristics be not present lance
Shield all should be considered as described in this specification.
Only several embodiments of the present invention are expressed for above embodiments, and the description thereof is more specific and detailed, but can not
Therefore it is construed as limiting the scope of the patent.It should be pointed out that for those of ordinary skill in the art,
Without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection model of the invention
It encloses.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (13)
1. a kind of d type flip flop, which is characterized in that including input circuit, precharging circuit, output circuit and the first latch cicuit；
The input terminal of the input circuit is for accessing logic input signal, and the clock signal terminal of the input circuit is for accessing
Clock signal, the output end of the input circuit connect the input terminal of the precharging circuit；
The clock signal terminal of the precharging circuit is for accessing the clock signal, and the reset terminal of the precharging circuit is for accessing
Reset signal, the output end of the precharging circuit connect the input terminal of the output circuit；
The clock signal terminal of the output circuit is for accessing the clock signal, and the output end of the output circuit is for exporting
Logic output signal；
The clock signal terminal of first latch cicuit is for accessing the clock signal, the reset terminal of first latch cicuit
For accessing the reset signal, the latch control terminal of first latch cicuit connects the output end of the precharging circuit；
The feeder ear of the input circuit, the feeder ear for prestoring circuit, the feeder ear of the output circuit and described first
The feeder ear of latch cicuit is used to access operating voltage；
The common end of the input circuit, the common end for prestoring circuit, the common end of the output circuit and described first
The common end of latch cicuit is used to connection common potential end.
2. d type flip flop according to claim 1, which is characterized in that the input circuit includes the first field-effect tube, second
Field-effect tube and third field-effect tube；
The source electrode of first field-effect tube is the feeder ear of the input circuit, and the grid of first field-effect tube is described
The input terminal of input circuit, the drain electrode of first field-effect tube connect the source electrode of second field-effect tube；
The grid of second field-effect tube is the clock signal terminal of the input circuit, and the drain electrode of second field-effect tube is
The output end of the input circuit；
The drain electrode of the third field-effect tube connects the drain electrode of second field-effect tube, and the grid of the third field-effect tube is
The input terminal of the input circuit, the source electrode of the third field-effect tube are the common end of the input circuit.
3. d type flip flop according to claim 1, which is characterized in that the precharging circuit includes the 4th field-effect tube, the 5th
Field-effect tube, the 6th field-effect tube and the 7th field-effect tube；
The source electrode of 4th field-effect tube is the feeder ear of the precharging circuit, and the grid of the 4th field-effect tube is described
The reset terminal of precharging circuit, the drain electrode of the 4th field-effect tube connect the source electrode of the 5th field-effect tube；
The grid of 5th field-effect tube is the clock signal terminal of the precharging circuit, and the drain electrode of the 5th field-effect tube is
The output end of the precharging circuit, and connect the drain electrode of the 6th field-effect tube；
The grid of 6th field-effect tube is the input terminal of the precharging circuit, and the source electrode of the 6th field-effect tube connects institute
State the drain electrode of the 7th field-effect tube；
The grid of 7th field-effect tube is the clock signal terminal of the precharging circuit, and the source electrode of the 7th field-effect tube is
The common end of the precharging circuit.
4. d type flip flop according to claim 1, which is characterized in that the output circuit includes the 8th field-effect tube, the 9th
Field-effect tube, the tenth field-effect tube, the 11st field-effect tube and the second latch cicuit；
The source electrode of 8th field-effect tube is the feeder ear of the output circuit, and the grid of the 8th field-effect tube is described
The drain electrode of the clock signal terminal of output circuit, the 8th field-effect tube connects the drain electrode of the 9th field-effect tube, and connects
The input terminal of second latch cicuit, the output end of second latch cicuit are the output end of the output circuit；
The grid of 9th field-effect tube connects the drain electrode of the 11st field-effect tube, and is the input of the output circuit
End, the source electrode of the 9th field-effect tube connect the drain electrode of the tenth field-effect tube, and the grid of the tenth field-effect tube is
The source electrode of the clock signal terminal of the output circuit, the tenth field-effect tube and the 11st field-effect tube is the output electricity
The common end on road.
5. d type flip flop according to claim 4, which is characterized in that second latch cicuit includes the first not circuit
With the second not circuit；
The input terminal of first not circuit is the input terminal of second latch cicuit, and connects second not circuit
Output end；
The output end of first not circuit connects the input terminal of second not circuit, and is second latch cicuit
Output end.
6. d type flip flop according to claim 1, which is characterized in that first latch cicuit includes the 12nd field-effect
Pipe, the 13rd field-effect tube, the 14th field-effect tube, the 15th field-effect tube, the 16th field-effect tube and the 17th field-effect
Pipe；
The source electrode of 12nd field-effect tube and the source electrode of the 16th field-effect tube are the confession of first latch cicuit
Electric end, the source electrode of the 15th field-effect tube and the source electrode of the 17th field-effect tube are the public affairs of first latch cicuit
End altogether；
The grid of 13rd field-effect tube is the reset terminal of first latch cicuit, the grid of the 14th field-effect tube
The clock signal terminal of extremely described first latch cicuit；
The drain electrode of 12nd field-effect tube connects the source electrode of the 13rd field-effect tube, the 14th field-effect tube
Source electrode connects the drain electrode of the 15th field-effect tube；
The grid of 12nd field-effect tube connects the drain electrode and the 17th field-effect tube of the 16th field-effect tube
Drain electrode；
The drain electrode, the 16th field-effect tube for connecting the 14th field-effect tube that drain of 13rd field-effect tube
The grid of grid and the 17th field-effect tube, and be the latch control terminal of first latch cicuit.
7. a kind of phase frequency detector, which is characterized in that including the first d type flip flop, the second d type flip flop, first control circuit, second
Control circuit and reset feed circuit；Wherein, first d type flip flop and the second d type flip flop are as in claim 1 to 6
D type flip flop described in any one；
Each clock signal terminal is for accessing reference clock signal, each clock signal in the second d type flip flop in first d type flip flop
End is for accessing feedback clock signal；
The first input end of the first control circuit is used for incoming control signal, the second input terminal of the first control circuit
For accessing the feedback clock signal, the third input terminal of the first control circuit connects defeated in first d type flip flop
The output end of circuit out, the output end of the first control circuit connect the input terminal of input circuit in first d type flip flop；
The first input end of the second control circuit is used for incoming control signal, the second input terminal of the second control circuit
The reference clock signal, the third input terminal of the second control circuit connect output circuit in second d type flip flop
Output end, the output end of the second control circuit connect the input terminal of input circuit in second d type flip flop；
The output end of output circuit connects the first input end for resetting feed circuit in first d type flip flop, and described the
The output end of output circuit connects second input terminal for resetting feed circuit in 2-D trigger；The reset feed circuit
Output end connect in first d type flip flop each reset terminal in each reset terminal and second d type flip flop.
8. phase frequency detector according to claim 7, which is characterized in that the first control circuit includes the first nor gate
Circuit and the first NAND gate circuit；
One input terminal of first OR-NOT circuit is the first input end of the first control circuit, and another input terminal is institute
State the second input terminal of first control circuit；The output end of first OR-NOT circuit connects first NAND gate circuit
One input terminal, another input terminal of first NAND gate circuit are the third input terminal of the first control circuit.
9. phase frequency detector according to claim 7, which is characterized in that the second control circuit includes the second nor gate
Circuit and the second NAND gate circuit；
One input terminal of second OR-NOT circuit is the first input end of the second control circuit, and another input terminal is institute
State the second input terminal of second control circuit；The output end of second OR-NOT circuit connects second NAND gate circuit
One input terminal, another input terminal of second NAND gate circuit are the third input terminal of the second control circuit.
10. phase frequency detector according to claim 7, which is characterized in that the reset feed circuit include third with it is non-
Gate circuit and third not circuit；
One input terminal of the third NAND gate circuit is the first input end for resetting feed circuit, the third NAND gate
The second input terminal of feed circuit is resetted described in another input terminal of circuit, the output end of the third NAND gate circuit connects institute
State the input terminal of third not circuit；The output end of the third not circuit is the output end for resetting feed circuit.
11. phase frequency detector according to claim 7, which is characterized in that further include the first buffered gate and the second buffered gate；
Each clock signal terminal is used to pass sequentially through the input terminal and output termination of first buffered gate in first d type flip flop
Enter reference clock signal, in the second d type flip flop each clock signal terminal be used for pass sequentially through second buffered gate input terminal and
Output end accesses feedback clock signal.
12. phase frequency detector according to claim 10, which is characterized in that the reset feed circuit further includes that third is slow
Chongmen and the 4th buffered gate；
One input terminal of the third NAND gate circuit connects the output end of the third buffered gate, the third buffered gate it is defeated
Enter the output end that end connects output circuit in first d type flip flop；
Another input terminal of the third NAND gate circuit connects the output end of the 4th buffered gate, the 4th buffered gate
Input terminal connects the output end of output circuit in first d type flip flop.
13. phase frequency detector according to claim 10, which is characterized in that the reset feed circuit further includes delay electricity
Road；
The output end of the third NAND gate circuit connects the input terminal of the third not circuit by the delay circuit.
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| CN112564696A (en) * | 2020-12-16 | 2021-03-26 | 东南大学 | Phase frequency detector for delay phase-locked loop |
| CN113098498A (en) * | 2021-04-01 | 2021-07-09 | 南京航空航天大学 | Blind PFD circuit disappears based on recovery mechanism |
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