CN104935333A - High-speed low voltage phase frequency detector circuit - Google Patents
High-speed low voltage phase frequency detector circuit Download PDFInfo
- Publication number
- CN104935333A CN104935333A CN201510345219.XA CN201510345219A CN104935333A CN 104935333 A CN104935333 A CN 104935333A CN 201510345219 A CN201510345219 A CN 201510345219A CN 104935333 A CN104935333 A CN 104935333A
- Authority
- CN
- China
- Prior art keywords
- nmos tube
- circuit
- pmos
- nstspc
- precharge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
The invention relates to a high-speed low voltage phase frequency detector circuit, comprising a precharging NSTSPC circuit, a reset circuit, and a delay unit, namely, adopting a feedforward staggered form reset structure. Rising edge detection is performed on each input signal, after delay, NAND logical operation is performed on the input signal and an original input signal, OR logical operation is performed on the result and a corresponding output (UP or DOWN) phase, so as to cross and connect to a reset terminal of the NSTSPC circuit at the opposite edge to force the NSTSPC circuit at the opposite edge to reset. The precharging NSTSPC circuit is adopted for precharging feedforward staggered reset; under the condition of low working voltage and high phase demodulation frequency, the circuit can guarantee to well suppress a dead zone and a fourth state, and has a phase demodulation range close to between negative 2pi and positive 2pi and good linearity.
Description
Technical field
The invention belongs to analog radio frequency integrated circuit, particularly relate to a kind of novel high speed low pressure frequency and phase discrimination circuit for phase-locked loop.
Background technology
Traditional PFD adopts d type flip flop, is triggered, as shown in Figure 1 by rising edge.Frequency between input signal reference signal REF and feedback signal DIV or phase place are compared, and the frequency of two-way input signal or phase difference are exported with the form of digital quantity (UP and DOWN).F
rEF>f
dIV, or f
rEF=f
dIVbut during the advanced DIV of the phase place of REF, the output UP of PFD is positive pulse, and difference on the frequency between pulse duration with two input signals or phase difference relevant, and DOWN is low level always.On the contrary, f is worked as
dIV>f
rEF, or f
dIV=f
rEFbut during the advanced REF of the phase place of DIV, the output DOWN of PFD is positive pulse, and difference on the frequency between pulse duration with two input signals or phase difference relevant, and to export UP be low level always.Like this, PFD exports the shape of pulse and width and just indicates difference on the frequency between two input signal REF, DIV or phase difference.By the output of UP, DOWN with after result feedback to the reset terminal of two DFF (d type flip flop), carry out synchronous reset.
There is following shortcoming in conventional P FD: 1, the output signals UP of PFD and DOWN are respectively used to the charge and discharge switch controlling subsequent charge pump, realizes frequency or phase difference to be converted to VCO control voltage.But in loop-locking process, phase difference between input signal REF and DIV of PFD close to zero region, PFD exports very narrow pulse, because charge pump switches Nodes exists parasitic capacitance, have certain rise time and fall time, make this pulse that time enough may do not had to arrive high level, thus cannot charge pump switches be opened.The gain of loop reduces to zero, exports phase place and does not lock, so conventional P FD exists deadbanding.2, logical AND generation is carried out by output signals UP and DOWN during conventional P FD reset signal.Owing to causing in a short time with gate delay, occur output signals UP and DOWN (i.e. the 4th state), the appearance of the 4th state can increase the quiescent dissipation of PFD simultaneously.3, due to the metal-oxide-semiconductor grid discharge and recharge time, the most high operation speed of circuit is limited, so the most high operation speed of conventional P FD is restricted.
Summary of the invention
Goal of the invention: for above-mentioned prior art, proposes a kind of high velocity, low pressure phase frequency detector circuit, well can suppress dead band and the 4th state.
Technical scheme: a kind of high velocity, low pressure phase frequency detector circuit, comprises the first precharge NSTSPC circuit, the second precharge NSTSPC circuit, the first delay circuit, the second delay circuit, the first reset circuit, the second reset circuit; Reference signal REF inputs the signal input part of the first precharge NSTSPC circuit, feedback signal DIV inputs the signal input part of the second precharge NSTSPC circuit, described first precharge NSTSPC circuit exports UP signal, and described second precharge NSTSPC circuit exports DOWN signal;
Wherein, described first delay circuit inputs the first reset circuit after being used for carrying out τ 0 time delay to reference signal REF; After described first reset circuit is used for doing NAND Logic computing to reference signal REF and the reference signal REF after τ 0 time delay, the UP signal exported with the first precharge NSTSPC circuit is again done or after logical operation, is exported the reset signal input of the first reset signal to the second precharge NSTSPC circuit;
Described second delay circuit inputs the second reset circuit after being used for carrying out τ 0 time delay to feedback signal DIV; After described second reset circuit is used for doing NAND Logic computing to feedback signal DIV and the feedback signal DIV after τ 0 time delay, the DOWN signal exported with the second precharge NSTSPC circuit is again done or after logical operation, is exported the reset signal input of the second reset signal to the first precharge NSTSPC circuit.
As preferred version of the present invention, described first precharge NSTSPC circuit is identical with the second precharge NSTSPC circuit structure, described precharge NSTSPC circuit comprises PMOS M1, PMOS M2, NMOS tube M3, NMOS tube M4, NMOS tube M5, PMOS M6, NMOS tube M7, NMOS tube M8, and the source electrode of described PMOS M1, PMOS M2, PMOS M6 meets high level VDD; The grid of described PMOS M1, PMOS M2, NMOS tube M5, NMOS tube M7 as CLK signal end, for connecing input signal; The drain electrode of PMOS M1 connects the grid of NMOS tube M3; The drain electrode of PMOS M2 connects the drain electrode of NMOS tube M3 and the grid of NMOS tube M8; The source electrode of NMOS tube M3 connects the drain electrode of NMOS tube M4 and the grid of PMOS M6; The grid of NMOS tube M4 as Reset signal end, for connecing reset signal; The source electrode of NMOS tube M4 connects the drain electrode of NMOS tube M5; The source ground of NMOS tube M5 and NMOS tube M8; The drain electrode of PMOS M6 connects the drain electrode of NMOS tube M7; The source electrode of NMOS tube M7 connects the drain electrode of NMOS tube M8; The drain electrode of PMOS M6 is as the output of precharge NSTSPC circuit.
As preferred version of the present invention, described first reset circuit is identical with the second reset circuit structure, and described reset circuit comprises PMOS M9, PMOS M10, PMOS M11, PMOS M12, PMOS M14, NMOS tube M13, NMOS tube M15, NMOS tube M16, NMOS tube M17, NMOS tube M18; The source electrode of described PMOS M9, PMOS M10, PMOS M11, PMOS M12, PMOS M14 meets high level VDD, the drain electrode of PMOS M9, PMOS M10 connects the grid of NMOS tube M13, and PMOS M9, PMOS M11 are connected described first delay circuit or the second delay circuit output signal with the grid of NMOS tube M16; The grid of PMOS M10, PMOS M12 and NMOS tube M15 is used for meeting reference signal REF or feedback signal DIV; The drain electrode of PMOS M11, PMOS M12 connects the drain electrode of NMOS tube M13 and the grid of NMOS tube M18; The source electrode of NMOS tube M13 connects the drain electrode of NMOS tube M15 and the grid of PMOS M14; The drain electrode of PMOS M14 connects the drain electrode of NMOS tube M17; The source electrode of NMOS tube M15 connects the drain electrode of NMOS tube M16; The source electrode of NMOS tube M16 is connected with ground GND with the source electrode of NMOS tube M18; The source electrode of NMOS tube M17 connects the drain electrode of NMOS tube M18, and the grid of NMOS tube M17 is connected with the first precharge NSTSPC circuit or the second precharge NSTSPC circuit output signal; The drain electrode of NMOS tube M17 is as the signal output part of reset circuit.
Beneficial effect: in high velocity, low pressure phase frequency detector circuit of the present invention, this PFD is by preliminary filling electric-type NSTSPC circuit, reset circuit, delay cell forms, namely adopt feedforward staggered form resetting structure, to carry out after rising edge detection, time delay with original input signal with non-to each input signal simultaneously, its result again with corresponding output (UP or DOWN) phase or after, be cross connected to the reset terminal of opposite side NSTSPC again, by the NSTSPC forced resetting of opposite side.Adopt preliminary filling electric-type NSTSPC, carry out precharge feedforward intersection and reset, under lower operating voltage and higher phase demodulation frequency situation, can ensure well to suppress dead band and the 4th state, have the phase demodulation scope close to positive and negative 2 π and the good linearity.Adopt between the NAND gate circuit simultaneously be connected in series in the two-stage of reset signal generating circuit and the precharge structure of NSTSPC structural similarity, the speed that reset signal is produced improves, to regulate Δ RST resetting time, the increase for deadband eliminating, the 4th state and frequency and phase discrimination scope has optimization clearly.
Accompanying drawing explanation
Fig. 1 is conventional P FD electrical block diagram;
Fig. 2 PFD structural representation of the present invention;
Fig. 3 preliminary filling electric-type NSTSPC electrical block diagram;
Fig. 4 reset circuit structural representation;
Fig. 5 PFD working timing figure of the present invention.
Embodiment
Below in conjunction with accompanying drawing the present invention done and further explain.
As shown in Figure 2, a kind of high velocity, low pressure phase frequency detector circuit, comprises the first precharge NSTSPC circuit, the second precharge NSTSPC circuit, the first delay circuit, the second delay circuit, the first reset circuit, the second reset circuit.Reference signal REF inputs the signal input part of the first precharge NSTSPC circuit, feedback signal DIV inputs the signal input part of the second precharge NSTSPC circuit, first precharge NSTSPC circuit exports UP signal, and the second precharge NSTSPC circuit exports DOWN signal.
Wherein, the first delay circuit inputs the first reset circuit after being used for carrying out τ 0 time delay to reference signal REF.After first reset circuit is used for doing NAND Logic computing to reference signal REF and the reference signal REF after τ 0 time delay, the UP signal exported with the first precharge NSTSPC circuit is again done or after logical operation, is exported the reset signal input of the first reset signal to the second precharge NSTSPC circuit.
Second delay circuit inputs the second reset circuit after being used for carrying out τ 0 time delay to feedback signal DIV.After second reset circuit is used for doing NAND Logic computing to feedback signal DIV and the feedback signal DIV after τ 0 time delay, the DOWN signal exported with the second precharge NSTSPC circuit is again done or after logical operation, is exported the reset signal input of the second reset signal to the first precharge NSTSPC circuit.
First precharge NSTSPC circuit is identical with the second precharge NSTSPC circuit structure, and as shown in Figure 3, precharge NSTSPC circuit comprises two parts, NMOS gate and N-type latch cicuit.NMOS gate actuating logic is assessed, and the output signal of the NMOS gate received is stored on output node D by N-type latch cicuit.By the parasitic capacitance effect of metal-oxide-semiconductor, by TC node, precharge is carried out to metal-oxide-semiconductor M6.The voltage of TC point i.e. M6 grid under the state of precharge compared with higher than the conducting voltage needed for M6, when signal arrives, TC point can discharge rapidly and makes M6 conducting like this, clearly especially can improve state charge/discharge rates under compared with the condition of low suppling voltage like this, thus add the State Transferring operating frequency of fast-circuit hold--evaluation.Thus solve because the metal-oxide-semiconductor grid discharge and recharge time is to the restricted problem of the most high workload speed of circuit, achieve the PFD of low-voltage high speed.
Concrete, precharge NSTSPC circuit comprises PMOS M1, PMOS M2, NMOS tube M3, NMOS tube M4, NMOS tube M5, PMOS M6, NMOS tube M7, NMOS tube M8.The source electrode of PMOS M1, PMOS M2, PMOS M6 meets high level VDD; The grid of PMOS M1, PMOS M2, NMOS tube M5, NMOS tube M7 as CLK signal end, for meeting input reference signal REF or feedback signal DIV; The drain electrode of PMOS M1 connects the grid of NMOS tube M3; The drain electrode of PMOS M2 connects the drain electrode of NMOS tube M3 and the grid of NMOS tube M8; The source electrode of NMOS tube M3 connects the drain electrode of NMOS tube M4 and the grid of PMOS M6; The grid of NMOS tube M4 as Reset signal end, for connecing the reset signal that the first reset circuit or the second reset circuit export; The source electrode of NMOS tube M4 connects the drain electrode of NMOS tube M5; The source ground of NMOS tube M5 and NMOS tube M8; The drain electrode of PMOS M6 connects the drain electrode of NMOS tube M7; The source electrode of NMOS tube M7 connects the drain electrode of NMOS tube M8; The drain electrode of PMOS M6 is as the output of the first precharge NSTSPC circuit or the second precharge NSTSPC circuit.The source electrode of PMOS M6 as the output of precharge NSTSPC circuit, i.e. node D.
First reset circuit is identical with the second reset circuit structure, as shown in Figure 4.Concrete, first reset circuit is identical with the second reset circuit structure, and reset circuit comprises PMOS M9, PMOS M10, PMOS M11, PMOS M12, PMOS M14, NMOS tube M13, NMOS tube M15, NMOS tube M16, NMOS tube M17, NMOS tube M18.The source electrode of PMOS M9, PMOS M10, PMOS M11, PMOS M12, PMOS M14 meets high level VDD, the drain electrode of PMOS M9, PMOS M10 connects the grid of NMOS tube M13, and PMOS M9, PMOS M11 are connected the first delay circuit or the second delay circuit output signal with the grid of NMOS tube M16; The grid of PMOS M10, PMOS M12 and NMOS tube M15 is used for meeting reference signal REF or feedback signal DIV; The drain electrode of PMOS M11, PMOS M12 connects the drain electrode of NMOS tube M13 and the grid of NMOS tube M18; The source electrode of NMOS tube M13 connects the drain electrode of NMOS tube M15 and the grid of PMOS M14; The drain electrode of PMOS M14 connects the drain electrode of NMOS tube M17; The source electrode of NMOS tube M15 connects the drain electrode of NMOS tube M16; The source electrode of NMOS tube M16 is connected with ground GND with the source electrode of NMOS tube M18; The source electrode of NMOS tube M17 connects the drain electrode of NMOS tube M18, and the grid of NMOS tube M17 is connected with the first precharge NSTSPC circuit or the second precharge NSTSPC circuit output signal; The drain electrode of NMOS tube M17 is as the signal output part of reset circuit.As can be seen from its structure, the precharge structure with NSTSPC structural similarity is adopted between the NAND gate circuit that the two-stage of reset signal generating circuit is connected in series, the speed that reset signal is produced improves, to regulate Δ RST resetting time, the increase for deadband eliminating, the 4th state and frequency and phase discrimination scope has optimization clearly.
In high velocity, low pressure phase frequency detector circuit of the present invention, the rising edge of preliminary filling electric-type NSTSPC circuit to input signal REF and DIV judges, produces output signal.Adopt feedforward staggered form resetting structure simultaneously, simultaneously reset circuit carries out rising edge detection to each input signal, by after delay cell time delay with original input signal and non-, its result again with corresponding output (UP or DOWN) mutually or after, be cross connected to the reset terminal of opposite side DFF again, by the preliminary filling electric-type NSTSPC circuit forced resetting of opposite side.Wherein, delay cell determines the pulse duration of reset pulse.
High velocity, low pressure phase frequency detector workflow of the present invention is as follows as shown in Figure 5:
If: f
rEFbe ahead of f
dIV, τ 0 is input reseting pulse width, and the delay circuit be made up of inverter determines.τ is the rising time difference (τ >0) of two input signals; Δ in is by precharge NSTSPC circuit, and input signal (REF and DIV) rising edge sets high the delay time of level for output signal (UP and DOWN); Δ Res, in are from delay time for output signal (that corresponding with REF and DIV is DOWN and the UP) forced resetting of another precharge NSTSPC circuit of the input signal (REF with DIV) of a precharge NSTSPC circuit; Δ Res, out are the delay time of output signal (UP and DOWN) for output signal (DOWN and the UP) forced resetting of another precharge NSTSPC circuit of a precharge NSTSPC circuit.
Time REF rising edge arrives, UP set, when DIV rising edge arrives afterwards, due to the first reset circuit, UP signal, to DOWN signal hold reset state, inhibits the generation of DOWN signal, thus suppresses the appearance of the 4th state; Utilize the second reset unit, carrying out reset to UP signal is by DIV signal instead of DOWN signal.Ensure that the condition of this working stability is: the input pulse reset signal long enough that DIV signal produces resets to UP signal, and the reset of DIV signal to UP signal lags behind DIV signal to the set of DOWN signal and UP signal to the reset of DOWN signal.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (3)
1. a high velocity, low pressure phase frequency detector circuit, its characteristic value in: comprise the first precharge NSTSPC circuit, the second precharge NSTSPC circuit, the first delay circuit, the second delay circuit, the first reset circuit, the second reset circuit; Reference signal REF inputs the signal input part of the first precharge NSTSPC circuit, feedback signal DIV inputs the signal input part of the second precharge NSTSPC circuit, described first precharge NSTSPC circuit exports UP signal, and described second precharge NSTSPC circuit exports DOWN signal;
Wherein, described first delay circuit inputs the first reset circuit after being used for carrying out τ 0 time delay to reference signal REF; After described first reset circuit is used for doing NAND Logic computing to reference signal REF and the reference signal REF after τ 0 time delay, the UP signal exported with the first precharge NSTSPC circuit is again done or after logical operation, is exported the reset signal input of the first reset signal to the second precharge NSTSPC circuit;
Described second delay circuit inputs the second reset circuit after being used for carrying out τ 0 time delay to feedback signal DIV; After described second reset circuit is used for doing NAND Logic computing to feedback signal DIV and the feedback signal DIV after τ 0 time delay, the DOWN signal exported with the second precharge NSTSPC circuit is again done or after logical operation, is exported the reset signal input of the second reset signal to the first precharge NSTSPC circuit.
2. a kind of high velocity, low pressure phase frequency detector circuit according to claim 1, its characteristic value in: described first precharge NSTSPC circuit is identical with the second precharge NSTSPC circuit structure, described precharge NSTSPC circuit comprises PMOS M1, PMOS M2, NMOS tube M3, NMOS tube M4, NMOS tube M5, PMOS M6, NMOS tube M7, NMOS tube M8, and the source electrode of described PMOS M1, PMOS M2, PMOS M6 meets high level VDD; The grid of described PMOS M1, PMOS M2, NMOS tube M5, NMOS tube M7 as CLK signal end, for connecing input signal; The drain electrode of PMOS M1 connects the grid of NMOS tube M3; The drain electrode of PMOS M2 connects the drain electrode of NMOS tube M3 and the grid of NMOS tube M8; The source electrode of NMOS tube M3 connects the drain electrode of NMOS tube M4 and the grid of PMOS M6; The grid of NMOS tube M4 as Reset signal end, for connecing reset signal; The source electrode of NMOS tube M4 connects the drain electrode of NMOS tube M5; The source ground of NMOS tube M5 and NMOS tube M8; The drain electrode of PMOS M6 connects the drain electrode of NMOS tube M7; The source electrode of NMOS tube M7 connects the drain electrode of NMOS tube M8; The drain electrode of PMOS M6 is as the output of precharge NSTSPC circuit.
3. a kind of high velocity, low pressure phase frequency detector circuit according to claim 1, its characteristic value in: described first reset circuit is identical with the second reset circuit structure, and described reset circuit comprises PMOS M9, PMOS M10, PMOS M11, PMOS M12, PMOS M14, NMOS tube M13, NMOS tube M15, NMOS tube M16, NMOS tube M17, NMOS tube M18; The source electrode of described PMOS M9, PMOS M10, PMOS M11, PMOS M12, PMOS M14 meets high level VDD, the drain electrode of PMOS M9, PMOS M10 connects the grid of NMOS tube M13, and PMOS M9, PMOS M11 are connected described first delay circuit or the second delay circuit output signal with the grid of NMOS tube M16; The grid of PMOS M10, PMOS M12 and NMOS tube M15 is used for meeting reference signal REF or feedback signal DIV; The drain electrode of PMOS M11, PMOS M12 connects the drain electrode of NMOS tube M13 and the grid of NMOS tube M18; The source electrode of NMOS tube M13 connects the drain electrode of NMOS tube M15 and the grid of PMOS M14; The drain electrode of PMOS M14 connects the drain electrode of NMOS tube M17; The source electrode of NMOS tube M15 connects the drain electrode of NMOS tube M16; The source electrode of NMOS tube M16 is connected with ground GND with the source electrode of NMOS tube M18; The source electrode of NMOS tube M17 connects the drain electrode of NMOS tube M18, and the grid of NMOS tube M17 is connected with the first precharge NSTSPC circuit or the second precharge NSTSPC circuit output signal; The drain electrode of NMOS tube M17 is as the signal output part of reset circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510345219.XA CN104935333A (en) | 2015-06-19 | 2015-06-19 | High-speed low voltage phase frequency detector circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510345219.XA CN104935333A (en) | 2015-06-19 | 2015-06-19 | High-speed low voltage phase frequency detector circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104935333A true CN104935333A (en) | 2015-09-23 |
Family
ID=54122329
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510345219.XA Pending CN104935333A (en) | 2015-06-19 | 2015-06-19 | High-speed low voltage phase frequency detector circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104935333A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108092661A (en) * | 2018-01-15 | 2018-05-29 | 深圳骏通微集成电路设计有限公司 | Phase discriminator and phase-locked loop circuit |
| CN109639268A (en) * | 2018-11-20 | 2019-04-16 | 珠海市杰理科技股份有限公司 | D type flip flop and phase frequency detector circuit |
| CN110958015A (en) * | 2019-11-22 | 2020-04-03 | 深圳市纽瑞芯科技有限公司 | High-speed clock phase detection circuit without dead zone |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003283313A (en) * | 2002-03-26 | 2003-10-03 | Fujitsu Ltd | Phase comparator and phase-locked loop circuit |
| CN1808907A (en) * | 2004-12-22 | 2006-07-26 | 三星电子株式会社 | Phase-locked loops and its method, phase frequency detector and its method |
| US20080246545A1 (en) * | 2005-12-15 | 2008-10-09 | International Business Machines Corporation | Digital phase and frequency detector |
| CN103312318A (en) * | 2013-05-20 | 2013-09-18 | 浙江大学 | High-accuracy phase frequency detector |
-
2015
- 2015-06-19 CN CN201510345219.XA patent/CN104935333A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003283313A (en) * | 2002-03-26 | 2003-10-03 | Fujitsu Ltd | Phase comparator and phase-locked loop circuit |
| CN1808907A (en) * | 2004-12-22 | 2006-07-26 | 三星电子株式会社 | Phase-locked loops and its method, phase frequency detector and its method |
| US20080246545A1 (en) * | 2005-12-15 | 2008-10-09 | International Business Machines Corporation | Digital phase and frequency detector |
| CN103312318A (en) * | 2013-05-20 | 2013-09-18 | 浙江大学 | High-accuracy phase frequency detector |
Non-Patent Citations (1)
| Title |
|---|
| 韩婷婷 等: "低压高速鉴频鉴相器电路", 《中国集成电路》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108092661A (en) * | 2018-01-15 | 2018-05-29 | 深圳骏通微集成电路设计有限公司 | Phase discriminator and phase-locked loop circuit |
| CN109639268A (en) * | 2018-11-20 | 2019-04-16 | 珠海市杰理科技股份有限公司 | D type flip flop and phase frequency detector circuit |
| CN109639268B (en) * | 2018-11-20 | 2023-05-05 | 珠海市杰理科技股份有限公司 | D trigger and phase frequency detector circuit |
| CN110958015A (en) * | 2019-11-22 | 2020-04-03 | 深圳市纽瑞芯科技有限公司 | High-speed clock phase detection circuit without dead zone |
| CN110958015B (en) * | 2019-11-22 | 2023-05-05 | 深圳市纽瑞芯科技有限公司 | Dead-zone-free high-speed clock phase detection circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101795132B (en) | Potential pull-up circuit and pull-down circuit of I/O port of integrated circuit | |
| CN102291127B (en) | Fully differential reset delay adjustable frequency and phase discriminator | |
| CN105162441A (en) | High-speed low-power-consumption dynamic comparator | |
| CN107944099A (en) | A kind of high-speed, high precision comparator circuit design | |
| CN104113303A (en) | 50% duty ratio clock generation circuit | |
| CN103560768A (en) | Duty ratio regulating circuit | |
| CN104935333A (en) | High-speed low voltage phase frequency detector circuit | |
| CN103312317B (en) | The delay phase-locked loop of quick lock in | |
| CN104639157B (en) | Timing adjusting circuit and conductor integrated circuit device | |
| CN106877863A (en) | OSC circuits on a kind of high stability low-power consumption piece | |
| CN110113047B (en) | Ultra-low jitter coupling type frequency multiplication delay phase-locked loop circuit | |
| CN101977054A (en) | Relaxation-type voltage-controlled oscillator | |
| CN110912542A (en) | Low-power consumption dynamic bias comparator | |
| CN107565965A (en) | A kind of 8 frequency dividings at a high speed and the 9 frequency dividing pre- frequency dividing circuits of bimodulus | |
| CN107302356A (en) | A kind of reset delay phase frequency detector and a kind of phase-locked loop frequency synthesizer | |
| US20170063363A1 (en) | Comparator, electronic circuit, and method of controlling comparator | |
| CN102497201A (en) | True Single-Phase Clock (TSPC) 2/3 dual-mode prescaler with high speed and low power consumption | |
| CN104201880A (en) | Low current mismatch charge pump circuit for resisting process fluctuation under low voltage of phase lock loop | |
| CN105071805A (en) | High-speed low-power-consumption 2/3 dual-modulus prescaler | |
| CN105610434B (en) | A kind of adaptive delay phase-locked loop | |
| CN103532522B (en) | Dutyfactor adjustment circuit, Double-end-to-singlecircuit circuit and oscillator | |
| CN107565953B (en) | Control circuit of jump detector and clock frequency adjusting system | |
| CN106506001B (en) | A kind of high-performance VCO circuit applied to PLL | |
| CN109104170A (en) | A kind of adaptive broadband digital clock interpolation device unit | |
| CN202444477U (en) | High-speed and low-power true single-phase clock 2/3 dual-modulus prescaler |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150923 |