CN110958015B

CN110958015B - Dead-zone-free high-speed clock phase detection circuit

Info

Publication number: CN110958015B
Application number: CN201911159181.1A
Authority: CN
Inventors: 郭啸峰; 陈润; 陈振琪; 陈勇刚; 于鹏
Original assignee: Shenzhen Nuoruixin Technology Co ltd
Current assignee: Shenzhen Nuoruixin Technology Co ltd
Priority date: 2019-11-22
Filing date: 2019-11-22
Publication date: 2023-05-05
Anticipated expiration: 2039-11-22
Also published as: CN110958015A

Abstract

The invention relates to a dead-zone-free high-speed clock phase detection circuit, belonging to the technical field of phase detection circuits in integrated circuit design. The circuit comprises a core circuit and a peripheral circuit, wherein the core circuit comprises an upper half part circuit for generating a negative phase difference DN output signal and a lower half part circuit for generating a positive phase difference UP output signal; the upper half circuit consists of two NMOS transistors M1, M2, a PMOS switching tube M3 and a tiny capacitor C1, and the lower half circuit consists of 3 NMOS transistors M4, M5, M7,1 PMOS switching tube M6 and a tiny capacitor C2; the peripheral circuit is used for generating an inverted signal and an inverted delay signal of the reference clock. The invention has the advantages of no dead zone, high response speed and suitability for high-speed clock phase detection, and simultaneously retains the advantages of no special requirement of the classical structure on the duty ratio of the input clock.

Description

Dead-zone-free high-speed clock phase detection circuit

Technical Field

The invention belongs to the technical field of phase detection circuits in integrated circuit designs, and particularly relates to a dead-zone-free high-speed clock phase detection circuit (phase detector) design.

Background

The high-speed clock (clock frequency is greater than 0.5 GHz) phase detection circuit is mainly used for phase detection modules in Phase Lock Loop (PLL) and Delay Lock Loop (DLL), and is generally called as a phase detector (PFD) which is used for outputting a signal with a specific pulse width (analog acceleration) as a phase difference to a system to adjust the phase difference (analog velocity) according to the phase difference of two clocks, and the specific pulse width is used as a negative feedback.

For the classical PFD structure, as shown in fig. 1, the structure is composed of two D flip-flops with a reset function and an and gate, wherein the input signal terminals D of the two D flip-flops are connected to a power supply vdd, the input clock terminal clk is connected to two input clocks CLKref and CLKvco to be detected, the output terminals Q of the two D flip-flops are connected to the input of the and gate, and the output of the and gate is connected to the reset terminal rst of the two D flip-flops. Wherein the D-flip-flop output signal corresponding to the CLKref signal is UP, which represents the positive phase difference of the CLKref phase minus the CLKvco, and the D-flip-flop output signal corresponding to the CLKvco signal is DN, which represents the negative phase difference of the CLKvco phase minus the CLKref. The working principle is as follows: the output of the two D flip-flops in the initial state is 0, and if CLKref is before, its corresponding D flip-flop outputs 1 first, at this time, the output of the nand gate is still 0, rst is invalid. When CLKvco reaches, its corresponding D flip-flop also outputs 1, at this time the output of the nand gate becomes 1, rst is valid, CLKref is reset from 1 to 0 corresponding to the D flip-flop output, and CLKref is output 1 corresponding to the D flip-flop for a duration of time, that is, pulse width is a positive phase difference between CLKref and CLKvco, otherwise, it is a negative phase difference. However, the current classical structure has a major problem, as shown in fig. 2, the horizontal axis is the phase difference, and the vertical axis is the output pulse width of the PFD: since the response delay of the D flip-flop is generally larger, there is a larger response delay from CLKref/CLKvco and rst to UP/DN, when the phase error approaches 0, there is a dead zone (such as an ellipsograph area in the figure) obviously, the dead zone refers to a non-monotonic continuous interval of the pulse width of the output signal of the PFD at the zero crossing point (almost all applications only concern whether the output near the zero crossing point is monotonically continuous or not, so the dead zone generally refers to a dead zone near the zero crossing point), the size of the non-continuous interval depends on the size of the reset delay of the D flip-flop (for processes of 28nm and above, the reset delay is generally greater than 100 picoseconds, and the dead zone is also greater than 100 picoseconds before calibration), and the value of the dead zone is a value that varies with the process angle of temperature. Meanwhile, due to the design based on a D-trigger, the delay response time determines that the classical PFD structure cannot meet the application of the ultra-high-speed clock (more than 5 GHz), taking a 40nm process as an example, a D trigger with reset in a digital standard cell library (provided by a foundry and realized by a layout representing an optimal digital standard cell) has the fastest reset response time delay of about 100 picoseconds, the fastest clock trigger delay response of about 30 picoseconds and the delay of an AND gate of about 20 picoseconds, so that the classical PFD structure can not meet the phase detection application of the ultra-high-speed clock with the processing time delay of more than 5GHz even if the classical PFD structure adopts the 28nm or 40nm advanced process, the loop delay of the classical PFD structure also exceeds 150 picoseconds, and therefore, even if the classical PFD structure is ideal, the upper limit frequency of the processing time clock cannot generally exceed 3GHz (the inverse of twice delay is the upper limit frequency, namely Fin=1/2T, about 3.3 GHz).

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides a dead zone-free high-speed clock phase detection circuit.

The invention provides a dead zone-free high-speed clock phase detection circuit which is characterized by comprising a core circuit and a peripheral circuit; the core circuit includes: an upper half circuit generating a negative phase difference DN output signal and a lower half circuit generating a positive phase difference UP output signal; the upper half circuit consists of a first NMOS switch tube M1, a second NMOS switch tube M2, a first PMOS switch tube M3 and a first capacitor C1, and the connection relation is as follows: the source electrode of the first NMOS switch tube M1 is grounded, the drain electrode is connected with the source electrode of the second NMOS switch tube M2, and the grid electrode is connected with an inverted delay signal CLKref_bd of which the rising edge is delayed by 60 degrees after the inversion of the input reference clock CLKref; the source electrode of the second NMOS switch tube M2 is connected with the drain electrode of the first NMOS switch tube M1, the drain electrode is connected with the upper polar plate of the first capacitor C1, and the grid electrode is connected with the input signal clock CLKvco; the upper polar plate of the first capacitor C1 is connected with the drains of the second NMOS switch tube M2 and the first PMOS switch tube M3 at the same time, and the lower polar plate of the first capacitor C1 is grounded; the source electrode of the first PMOS switch tube M3 is connected with a power supply, and the grid electrode of the first PMOS switch tube M3 is connected with an inverted signal CLKref_b of an input reference clock CLKref; the upper polar plate of the first capacitor C1 is used as the output of the negative phase difference signal DN at the same time;

the lower half circuit consists of a third NMOS switch tube M4, a fourth NMOS switch tube M5, a fifth NMOS switch tube M7, a second PMOS switch tube M6 and a second capacitor C2, and the connection relation is as follows: the source electrode of the third NMOS switch tube M4 is grounded, the drain electrode is connected with the source electrode of the fourth NMOS switch tube M5, and the grid electrode is connected with the reference clock CLKref; the source electrode of the fourth NMOS switch tube M5 is connected with the drain electrode of the third NMOS switch tube M4, the drain electrode is connected with the upper polar plate of the second capacitor C2, and the grid electrode is connected with the input signal clock CLKvco; the upper electrode plate of the second capacitor C2 is connected with the drain electrode of the fourth NMOS switch tube M5, the drain electrode of the second PMOS switch tube M6 and the source electrode of the fifth NMOS switch tube M7, and the lower electrode plate of the second capacitor C2 is grounded; the source electrode of the second PMOS switch tube M6 is connected with a power supply, the drain electrode is connected with the upper polar plate of the second capacitor C2, and the grid electrode is connected with the input reference clock CLKref; the source electrode of the fifth NMOS switch tube M7 is connected with the upper polar plate of the second capacitor C2, the drain electrode of the fourth NMOS switch tube M5 and the drain electrode of the second PMOS switch tube M6, and the drain electrode of the fifth NMOS switch tube M7 is used for outputting a positive phase difference signal UP;

the grid electrode of the upper half part circuit M2 and the grid electrode of the lower half part circuit M5 are commonly connected with an input signal clock CLKvco to be detected, and the rest parts are independent;

the peripheral circuits are used to generate an inverted signal clkref_b and an inverted delay signal clkref_bd of the reference clock CLKref.

The invention has the characteristics and beneficial effects that:

the proposed structure of the present invention checks the phase difference of the input clocks CLKref and CLKvco based on the charge and discharge of a minute capacitor, the positive phase difference is output through UP, and the negative phase difference is output through DN. Since the whole PFD circuit directly acts on the capacitor and charges/discharges it to generate the phase difference output, the delay from the input clocks CLKref and CLKvco to the output phase differences UP and DN is only the delay of one NMOS or PMOS to charge and discharge the tiny capacitor (about 10 picoseconds), which is far less than the response delay of the classical structure PFD based on D flip-flops. While the reduction in response delay has the advantage that the dead zone can be reduced by an order of magnitude to an acceptable level for the system, so that no additional dead zone cancellation techniques are required, or simple delay matching can make the dead zone a further order of magnitude smaller to accommodate higher performance system requirements.

And compared with the PFD with a classical structure based on a D trigger, the PFD has the advantages of greatly reducing the total response delay of the system, the structure can accept the maximum input clock frequency speed to be detected to be improved by 3 to 4 times compared with the classical PFD structure. Meanwhile, compared with a complex circuit of a D trigger with reset, the circuit is relatively simple, so that the overall power consumption is lower, and the total area is small.

Furthermore, since it is a capacitive charge storage based circuit that is in most cases responsive only to the triggering edge of the clock, it has no special requirement for the duty cycle of the input clock, and even if the input clock duty cycle deviates far from 50%, the structure PFD can still provide an effective detection signal output, and while this is the greatest advantage of the classical structure PFD, the industry and academia including some similar patents describe structures that are still limited by the need for a 50% duty cycle of the input clock.

Drawings

Fig. 1 is a schematic diagram of a conventional phase detection circuit.

Fig. 2 is a schematic diagram of a conventional phase detection circuit.

Fig. 3 is a schematic diagram of a phase detection circuit according to the present invention.

Fig. 4 is a schematic diagram of a peripheral circuit of the phase detection circuit of the present invention.

Fig. 5 is a timing diagram of the working principle of the circuit diagram of the present invention.

Fig. 6 is a diagram illustrating a characteristic example of the present invention.

Detailed Description

The invention provides a dead zone-free high-speed clock phase detection circuit, which is described in detail below with reference to the accompanying drawings and embodiments:

the phase detection circuit of the present invention is shown in fig. 3, and includes a core circuit and a peripheral circuit (not shown). The circuit inputs a clock to be detected as a reference clock CLKref and a signal clock CLKvco, and outputs phase difference signals as UP and DN, wherein UP is a positive phase difference output signal, and DN is a negative phase difference output signal. Clkref_b and clkref_bd are the inverted signal and the inverted delay signal of CLKref, respectively, generated by the peripheral circuitry.

The core circuit of the phase detection circuit of the present invention is divided into two parts, the upper part of the circuit of fig. 3 generates a negative phase difference DN output signal, the lower part of the circuit of fig. 3 generates a positive phase difference UP output signal, while UP and DN provide positive phase adjustment (negative acceleration) as a pull-UP signal and negative phase adjustment (positive acceleration) as a pull-down signal.

The upper half of the core circuit is composed of a first NMOS switch tube M1, a second NMOS switch tube M2, a first PMOS switch tube M3 and a micro capacitor C1, as shown in the upper part of fig. 3, where the capacitance value of C1 may be about 5fF (5 fF is typically the minimum area typical value of the metal finger capacitor in the process library), and for a wideband system, the selection of this value determines the interval of the PFD processing clock frequency, which is small enough to ensure high-speed low-power consumption and small area, and also has sufficient capacity of storing charges to adapt to use of lower frequency) so as to realize charging and discharging at ultra-high speed (several hundred GHz,10 picoseconds). The connection relation is as follows: the source electrode of the first NMOS switch tube M1 is grounded, the drain electrode is connected with the source electrode of the second NMOS switch tube M2, and the grid electrode is connected with an inverted delay signal CLKref_bd of which the rising edge is delayed by 60 degrees after the inversion of the input reference clock CLKref. The source electrode of the second NMOS switch tube M2 is connected to the drain electrode of the first NMOS switch tube M1, the drain electrode is connected to the upper electrode plate of the first capacitor C1, and the gate electrode is connected to the input signal clock CLKvco. The upper electrode plate of the first capacitor C1 is connected with the drain electrodes of the second NMOS switch tube M2 and the first PMOS switch tube M3 at the same time, and the lower electrode plate of the first capacitor C1 is grounded. The first PMOS switch M3 has a source connected to the power supply and a gate connected to the inverted signal clkref_b of the input reference clock CLKref. While the upper plate of the first capacitor C1 is simultaneously used as the output of the negative phase difference signal DN.

The lower half part of the core circuit consists of a third NMOS switch tube M4, a fourth NMOS switch tube M5, a fifth NMOS switch tube M7, a second PMOS switch tube M6 and a tiny capacitor C2, as shown in the lower part of the figure 3, wherein the capacitance value of the second capacitor C2 is the same as that of the first capacitor C1, so that the charge and discharge of the ultra-high speed (hundreds of GHz,10 picoseconds grade, and the value of C2 is equal to C1) are realized. The connection relation is as follows: the source electrode of the third NMOS switch tube M4 is grounded, the drain electrode of the third NMOS switch tube M5 is connected with the source electrode, and the grid electrode of the third NMOS switch tube M is connected with the reference clock CLKref. The source electrode of the fourth NMOS switch tube M5 is connected with the drain electrode of the third NMOS switch tube M4, the drain electrode is connected with the upper electrode plate of the second capacitor C2, and the grid electrode is connected with the input signal clock CLKvco. The upper electrode plate of the second capacitor C2 is connected with the drain electrode of the fourth NMOS switch tube M5, the drain electrode of the second PMOS switch tube M6 and the source electrode of the fifth NMOS switch tube M7, and the lower electrode plate of the second capacitor C2 is grounded. The source electrode of the second PMOS switch tube M6 is connected to the power supply, the drain electrode is connected to the upper plate of the second capacitor C2, and the gate electrode is connected to the input reference clock CLKref. The source electrode of the fifth NMOS switch tube M7 is connected to the upper electrode plate of the second capacitor C2, the drain electrode of the fourth NMOS switch tube M5, and the drain electrode of the second PMOS switch tube M6, and the drain electrode of the fifth NMOS switch tube M7 is used for outputting the positive phase difference signal UP.

The grid electrode of the upper half part M2 and the grid electrode of the lower half part M5 are commonly connected with the input signal clock signal CLKvco to be detected, the rest parts are independent, and layout positions are adjacently placed to obtain good wiring matching.

The peripheral circuit of the phase detection circuit of the present invention is shown in fig. 4, and the circuit is composed of an inverter, a delay, and an and gate. The input reference clock CLKref outputs an inverted signal clkref_b of CLKref through an inverter 1, the inverted signal clkref_b is input to an input terminal of an and gate 3 through a delay 2, the inverted signal clkref_b is also connected to the input terminal of the and gate 3, the output of the and gate 3 is an inverted delay signal clkref_bd, and the final clkref_b, clkref_bd are input to input ports corresponding to a core circuit of the phase detection circuit. The two output signals of the phase detection circuit are DN and UP respectively. The peripheral circuit is used for generating the above-mentioned inverted signal clkref_b and inverted delay signal clkref_bd through CLKref. The inverter 1, the delay 2 and the and gate 3 are standardized devices in a process standard cell library, and are common devices in the industry and will not be described in detail. While the illustration is made only as a structural reference, the final implementation needs to consider that CLKref and CLKvco and clkref_b are delayed by an and gate delay after clkref_bd is generated (by being input to an and gate output of the same size, the other end of the and gate is input to a fixed high level, and thus the and gate does not implement a logic function and is used only as a delay unit) and then output, because a phase offset of the and gate delay is introduced when clkref_bd is generated, which is equivalent to an inherent offset (offset), so the remaining 3 signals need to be likewise delayed by an and gate delay to cancel the delay offset when clkref_bd is generated.

It should be noted that, unlike the conventional structure (the conventional structure DN and UP are each responsible for a 180 ° half-zone, but for most application scenarios, the half-zone is not necessarily symmetrical), the negative phase difference signal DN is supplied as the main output to the system to adjust the phase difference to 0, it will cover the detection of most of the phase difference interval, while the positive phase difference signal UP is outputted as the auxiliary part, it will cover the detection of the phase difference of the rest of the interval, the whole PFD may still cover the whole phase difference interval of 0 to 2 n, and the interval of general interest is the region of + -30 ° around the zero crossing, which determines the performance influence of the PFD output signal on the whole system, the interval of-300 ° to 0 ° is DN output, 0 ° to +60 ° (the interval of the UP output is determined by the rising edge delay of clkref_bd, the phase interval may be adjusted by adjusting the delay of the delay 3 shown in fig. 4), similarly the interval of-310 ° to 0 ° DN output, and the interval of 0 ° to UP output may also be taken.

The working principle timing diagram of the circuit diagram of the invention is shown in fig. 5, wherein the input signal clocks are CLKref and CLKvco, CLKref represents a reference signal clock, CLKvco represents a signal clock to be detected, and the frequencies of the CLKvco and the reference signal clock are the same. The output signals are UP and DN, the pulse width of UP representing the retard phase difference (or positive phase difference) of CLKvco relative to CLKref and the pulse width of DN representing the advance phase difference (or negative phase difference) of CLKvco relative to CLKref. Clkref_b is obtained from CLKref through an inverter, clkref_bd is obtained from clkref_b through an inverting delay and an and gate. The solid and dashed lines of CLKvco represent the two states of CLKvco relative to CLKref, respectively, the solid line portion represents the advance, at which time the DN signal provides an effective output pulse whose pulse width is equal to the phase delay, i.e., the phase difference, of CLKref and CLKvco, representing a negative phase difference, while the UP output is a low level inactive signal. The dashed line portion represents hysteresis where the UP signal provides an active output pulse having a pulse width equal to the phase delay, i.e., phase difference, of CLKref and CLKvco, representing a positive phase difference, while the DN output is a high inactive signal. It should be noted that, for simplicity of description, the duty cycle of the input signal is shown as 50%, and in practical applications, the duty cycle of the input signal may be different from 50% or even far from 50%.

With reference to fig. 3 and 5, the circuit of the present invention performs the following functions: when CLKvco has a negative phase difference between CLKref and CLKvco before the rising edge of CLKref (CLKvco is ahead of CLKref), DN outputs a low-level pulse while UP is constant low, whose pulse width is equal to the negative phase difference. When CLKvco's rising edge follows CLKref's rising edge (CLKvco lags CLKref), CLKref and CLKvco have a positive phase difference, UP outputs a high pulse while DN is constant high, whose pulse width is equal to the positive phase difference.

With reference to fig. 3 and fig. 4, the specific working principle is as follows: the rising edge of CLKvco is before the rising edge of CLKref for the pulse generation mechanism at negative phase difference of-300 ° to 0 °. For the lower half of fig. 3, M7 is turned on each time, M4 and M5 are both turned on at the same time, M6 is turned off, and the upper plate of C2 is discharged to ground through M4 and M5, at which time the UP output is constant low and refreshed once per clock cycle. For the upper half of fig. 3, when CLKvco's rising edge arrives, CLKref is at low level (because CLKref always enters low level when rising edge arrives), M1, M2 is turned on and M3 is turned off, the upper plate of C1 is discharged from high level through M1, M2 to low level and kept until CLKref's rising edge arrives, M1 is turned off and M inverted signal 3 is turned on, C1 is charged from low level through M3 to high level and kept, a low level pulse is formed until next CLKvco's rising edge arrives, and the upper plate low level duration of C1, that is, pulse width, is the negative phase difference between CLKref and CLKvco, and the pulse width is equal to negative phase difference most of the time (in the range of-180 ° to 0 ° in the phase difference, after exceeding-180 ° the pulse width is the maximum, which is not a problem to be solved for the system) is equal to the delay time between clkco and CLKref. Since clkref_bd is produced by a single rising edge (falling edge remains constant) delay of clkref_b by 60 °, when the negative phase difference of CLKref and CLKvco is between-300 ° and 0 °, for the output of the PFD, DN output is a pulse and UP is constant high.

And a positive phase difference generation mechanism of 0 deg. to 60 deg., namely, the rising edge of CLKvco is after the rising edge of CLKref. For the upper half of fig. 3, since the intersection of clkref_bd and CLKvco being high at the same time is empty at a phase difference of 0 ° to 60 °, i.e., the path of the upper plate of C1 to ground through M1, M2 is constantly turned off, the upper plate of C1 is charged high through M3 and charges are refreshed once every clock cycle, and thus the output of DN at this time is constantly high. For the lower half of fig. 3, when the rising edge of CLKref arrives, the upper plate of C2 has been charged to high level and held through M6 at the previous moment (CLKref is low, M6 is on, M4, M5 is off), at which time M7 just starts to be on, the high voltage on the upper plate of C2 will be conducted through M7 to UP, at which time the output voltage of UP changes from low to high level and held until the rising edge of CLKvco arrives, M4, M5, M7 is on, M6G is off, the upper plate of C2 is discharged to low level and held while the low level is conducted through M7 to UP, at which time the high level of UP is pulled to low level to form a high level pulse until the rising edge of CLKref next time arrives, the width of the pulse is a positive phase difference, the value of which is equal to the delay time of the rising edge of CLKvco to CLKref.

Fig. 6 is a diagram showing a characteristic example of the circuit of the present invention, in which the PFD is described as the relation between the output pulse and the input phase difference, the horizontal axis is CLKref and CLKvco phase difference, CLKref is ahead of CLKvco and indicates a negative phase difference, and the lag indicates a positive phase difference), and the vertical axis is the output pulse width of the PFD (the negative phase difference is indicated by the pulse width of DN only, and the positive phase difference is indicated by the pulse width of UP only). The vertical axis variation curve is obtained from the circuit shown in fig. 3 and 4 and the timing simulation shown in fig. 5, where DN provides an effective output pulse width when the phase difference between the two input clock signals CLKref and CLKvco changes from-300 ° (or-310 °) to 0 °, the lower half of the horizontal axis representing its pulse width change, and when the phase difference changes from-300 ° (or-310 °) to-180 ° (taking a 50% duty cycle input clock as an example), the DN signal consistently outputs a pulse signal having a maximum pulse width of 50% of the signal period, and when the phase difference changes from-180 ° (taking a 50% duty cycle input clock as an example), the pulse width of DN is equal to the phase difference and thus the vertical axis curve changes linearly with the horizontal axis. The UP provides an effective output pulse width when the phase difference of the two input clock signals CLKref and CLKvco varies from 0 deg. to +60 deg. (or +50 deg.), the upper half of the horizontal axis showing its pulse width variation, and the UP pulse width is equal to the phase difference when the phase difference varies from 0 deg. to 60 deg. so that the vertical axis curve varies linearly with the horizontal axis. When the angle exceeds-300 degrees or +60 degrees, the cycle is repeated with the cycle of 2 pi as well. In the vicinity of the zero crossing, the dead zone is negligible because the delayed response of the system is small (typically less than 10 picoseconds, after simple calibration, less than picoseconds, a dead zone of 10 picoseconds may meet most system applications, while a dead zone of 1 picosecond may meet most high performance applications of the system, where the value is much less than the PFD of classical architecture), enabling the dead zone requirements of high speed clocking systems to be met.

Claims

1. A dead zone-free high-speed clock phase detection circuit is characterized by comprising a core circuit and a peripheral circuit; the core circuit includes: an upper half circuit generating a negative phase difference DN output signal and a lower half circuit generating a positive phase difference UP output signal; the upper half circuit consists of a first NMOS switch tube M1, a second NMOS switch tube M2, a first PMOS switch tube M3 and a first capacitor C1, and the connection relation is as follows: the source electrode of the first NMOS switch tube M1 is grounded, the drain electrode is connected with the source electrode of the second NMOS switch tube M2, and the grid electrode is connected with an inverted delay signal CLKref_bd of which the rising edge is delayed by 60 degrees after the inversion of the input reference clock CLKref; the source electrode of the second NMOS switch tube M2 is connected with the drain electrode of the first NMOS switch tube M1, the drain electrode is connected with the upper polar plate of the first capacitor C1, and the grid electrode is connected with the input signal clock CLKvco; the upper polar plate of the first capacitor C1 is connected with the drains of the second NMOS switch tube M2 and the first PMOS switch tube M3 at the same time, and the lower polar plate of the first capacitor C1 is grounded; the source electrode of the first PMOS switch tube M3 is connected with a power supply, and the grid electrode of the first PMOS switch tube M3 is connected with an inverted signal CLKref_b of an input reference clock CLKref; the upper polar plate of the first capacitor C1 is used as the output of the negative phase difference signal DN at the same time;

2. The dead zone free high speed clock phase detection circuit of claim 1 wherein the capacitance of the first capacitor C1 is the same as the capacitance of the second capacitor C2, which is a minimum area representative of the metal finger capacitors in the process library to ensure high speed low power consumption and small area while having sufficient charge storage capacity to accommodate lower frequency use to achieve ultra high speed charge and discharge.

3. The dead-zone-free high-speed clock phase detection circuit of claim 1 wherein the upper half circuit and lower half circuit layout are positioned adjacently to obtain a good trace match.

4. The dead zone free high speed clock phase detection circuit of claim 1 wherein the peripheral circuit is comprised of an inverter, an inverting delay and an and gate; the input reference clock CLKref outputs an inverted signal clkref_b of the CLKref through an inverter, the inverted signal clkref_b is input to an input end of the and gate through an inverted delay device, the inverted signal clkref_b is also connected to an input end of the and gate 3, and the output of the and gate 3 is an inverted delay signal clkref_bd, the inverted signal clkref_b, and the inverted delay signal clkref_bd is input to an input port corresponding to a core circuit of the phase detection circuit.