CN101055759B - Memory access circuit - Google Patents

Memory access circuit Download PDF

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CN101055759B
CN101055759B CN2007101063987A CN200710106398A CN101055759B CN 101055759 B CN101055759 B CN 101055759B CN 2007101063987 A CN2007101063987 A CN 2007101063987A CN 200710106398 A CN200710106398 A CN 200710106398A CN 101055759 B CN101055759 B CN 101055759B
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signal
circuit
delay
reset
produce
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CN101055759A (en
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谢宜政
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Via Technologies Inc
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Via Technologies Inc
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Abstract

The invention provides a memory accessing circuit for generating a pre-charging signal and an accessing actuating signal. The memory accessing circuit of the invention includes: a bolt lock circuit with an input port receiving a high-level inputted signal, when a clock signal is triggerred, the bolt lock circuit outputs a first signal according to the level of the inputted signal; a feedback reset circuit coupled with the bolt lock circuit, receiving the first signal to generate a second signal and a resetting signal, wherein the bolt lock circuit receives the resetting signal and resets the first signal based on the level of the resetting signal; and a door latch circuit coupled to the bolt lock circuit and the feedback reset circuit to generate the pre-charging signal and the accessing actuating signal according to the first signal and the second signal.

Description

Memory access circuit
Technical field
The invention relates to memory circuitry, particularly relevant for memory access circuit.
Background technology
When external circuit desires to read the storage values of certain particular memory location in the storer, must in the static RAM in order to output storage values the first line precharge of bit line (bit line), to keep bit line in certain specific voltage level.Follow the word line that reads address activation Destination Storage Unit (word line), so that the storage values of Destination Storage Unit outputs on the bit line according to external circuit output.Output circuit latchs the magnitude of voltage of reflection storage values on the bit line again, and exports magnitude of voltage to external circuit, so external circuit is read the storage values of Destination Storage Unit.
Because the process need that reads storer is to memory precharge (pre-charge), so storer need produce precharging signal PRE, to trigger the charging of bit line.In addition, because the process of access memory also needs the word line of activation Destination Storage Unit, with by selected target storage unit in numerous storage unit that storer was comprised, so storer also needs to produce access enable signal EN, to trigger choosing of storage unit.Because the precharge of bit line needs could remove the residual voltage that last time read on the bit line in advance early than the choosing of storage unit, allowing the storage values of storage unit export on the bit line, so precharging signal PRE need be enabled earlier.Generally speaking, the time point T1 of precharging signal PRE activation needs the time point T2 (that is T1 is early than T2) early than access enable signal EN activation; In addition the time point T4 of precharging signal PRE disabled need be later than access enable signal EN disabled time point T3 (that is, T4 is later than T3), that is during the activation of precharging signal PRE D1 greater than the activation of access enable signal EN during D2, the maloperation in the time of so just avoiding the memory circuitry access.
The corresponding situation of desirable precharging signal PRE and access enable signal EN as shown in Figure 1.Wherein the time point of precharging signal PRE activation is T1, and the time point of disabled is T4; And the time point of access enable signal EN activation is T2, and the disabled time point is T3.
Summary of the invention
The invention provides a kind of memory access circuit, provide precharging signal and activation access signal, in order to access memory.
The invention provides a kind of memory access circuit, in order to produce precharging signal and access enable signal.Memory access circuit of the present invention includes: latch circuit, and input end receives the input signal of noble potential, and when the clock signal triggering, latch circuit is exported first signal according to the level of input signal; The reset and feedback circuit, be coupled to latch circuit, receive first signal in order to produce secondary signal and reset signal, wherein reverse this first signal of this reset and feedback circuit is to produce this secondary signal, this reset and feedback circuit produces this reset signal with this first signal and the 3rd signal after logical operation, wherein the 3rd signal for postpone and oppositely this secondary signal obtain, wherein latch circuit receives reset signal and according to the level of reset signal first signal of resetting; And door lock deposits circuit, is coupled to latch circuit and reset and feedback circuit, and this door lock is deposited circuit this first signal and this secondary signal are produced precharging signal and access enable signal after logical operation.
The present invention also provides a kind of memory access circuit, in order to produce precharging signal and access enable signal.Memory access circuit of the present invention includes: latch circuit, and input end receives the input signal of noble potential, and when the clock signal triggering, latch circuit is exported first signal according to the level of input signal; Delay circuit receives first signal, and this first signal of this delay circuit sequential delays is to produce secondary signal, the 3rd signal and the 4th signal; The reset and feedback circuit is coupled to latch circuit and delay circuit, receives first signal and the 4th signal, and wherein this reset and feedback circuit produces reset signal with this first signal and the 4th signal after logical operation; Wherein latch circuit receives reset signal and according to the level of reset signal first signal of resetting; And door lock deposits circuit, is coupled to latch circuit and delay circuit, and this door lock is deposited circuit this first signal and this secondary signal, the 3rd signal and the 4th signal are produced precharging signal and access enable signal after logical operation.
For above and other objects of the present invention, feature and advantage can be become apparent, several preferred embodiments cited below particularly, and cooperate appended diagram, be described in detail below.
Description of drawings
Fig. 1 is the block diagram that is used to produce the logical circuit of the precharging signal of static RAM and access enable signal;
Fig. 2 is the calcspar of the present invention's one memory access circuit;
Fig. 3 is the signal timing diagram of Fig. 2 memory access circuit;
Fig. 4 is the calcspar of another memory access circuit of the present invention; And
Fig. 5 is the signal timing diagram of Fig. 4 memory access circuit.
[main element label declaration]
300,400～logical circuit;
314,324,328,512,514,516～delay cell;
302,402～latch circuit;
304,404～reset and feedback circuit;
306,408～door lock is deposited circuit;
318,322,326,510～NAND door;
406～delay circuit; And
522,524～OR door.
Embodiment
Fig. 2 is the calcspar of memory access circuit 300 of the present invention.Memory access circuit 300 comprises as shown in Figure 2: and latch circuit 302 (for example: D flip-flop (D flip-flop)), reset and feedback circuit 304, to deposit circuit 306 with door lock.Wherein, latch circuit 302 receives the input signal V of high level DD, and according to the triggering of clock signal clk with so that signal S 2AKeep V DDHigh level.In addition, latch circuit 302 also receives reset signal S 2D, in order to reset signal S 2AWherein, as reset signal S 2DDuring for low level, latch circuit 302 makes signal S 2AReset to low level.
Wherein above-mentioned described reset signal S 2DBe to utilize with signal S 2AInput to reset and feedback circuit 304 and produce.Its process is as described below.At first utilize first reverser 312 with signal S 2ABe inverted to signal S 2BUtilize first delay cell 314 and second reverser 316 to make signal S afterwards 2BProduce signal S 2CAt last with signal S 2AAnd signal S 2CAfter the logical operation through a NAND logic gate 318, can produce the reset signal S that inputs to latch circuit 302 2DWherein, first delay cell 314 makes signal S 2BProduce the time delay of Td2.In addition, as shown in Figure 2, signal S 2ABefore inputing to reset and feedback circuit 304, can use so that signal S earlier through the 3rd reverser 332 and the 4th reverser 334 2AInput to reset and feedback circuit 304 again after producing delay slightly.
As shown in Figure 2, door lock is deposited circuit 306 and is cross-linked NAND logical circuit.Door lock of the present invention is deposited circuit 306 and is included the 2nd NAND door 322, the 3rd NAND door 326, second delay cell 324, the 3rd delay cell 328 and the 5th reverser 330.Wherein the 2nd NAND door makes signal S 2AAnd precharging signal PRE is through producing signal S after the logical operation 2EUtilize second delay cell 324 to make signal S 2EProduce the delay of Td1 and output signal S 2FUtilize the 5th reverser 330 reverse signal S afterwards 2FIn order to the required activation access signal EN of output access storer.Wherein the 3rd NAND door makes output signal S 2BAnd activation access signal EN is through producing signal S after the logical operation 2GUtilize the 3rd delay cell 328 to make signal S 2GProduce the delay of Td1 and the required precharging signal PRE of output access storer.That is, utilize door lock to deposit circuit 306, make signal S 2AAnd signal S 2BProduce required enable signal EN and the precharging signal PRE of access memory circuit.
Fig. 3 is the signal timing diagram of memory access circuit 300 shown in Figure 2.
As shown in Figure 3, suppose that input signal maintains high level V DDWhen clock signal clk triggers in time point T1, latch circuit 302 is V in time point T1 output-voltage levels DDSignal S 2ABehind process t time delay, produce signal S in time point T2 2AReverse signal S 2BSignal S afterwards 2BDelay and the reverse back of Td2 produce signal S in time point T 3 (T3=T2+Td2) through time delay 2CBecause reset signal S 2DBe by signal S 2AAnd signal S 2CObtain via the NAND logical operation, and the signal S of time point T3 2AAnd signal S 2CBe all high level, so reset signal S 2DWhen time point T 3, be low level.At this moment, as mentioned above, low level reset signal S 2DCan make signal S 2AProduce falling edge (that is signal S in the T4 time point 2ABe reset).Because signal S 2ABehind time point T4 low level, so reset signal S 2DAlso behind time point T4, produce rising edge.Because signal S 2BBe signal S 2AOppositely, therefore through behind the time delay t, signal S 2BProduce rising edge in time point T5.
Because signal S 2GBe by signal S 2BAnd signal S 2FProduce after the process NAND logical operation, and signal S 2BBetween time point T2～T5, be all low level, so no matter signal S 2FLevel why, signal S 2GCan between time point T2～T5, keep high level.And produce after the delay of precharging signal PRE for signal S2G process Td1 time delay, suppose time point T6=T2+Td1, then precharging signal PRE can change into high level at time point T6, and keeps high level at time point T6～T7.
Because signal S 2EBe by signal S 2AAnd produce after the precharging signal PRE process NAND logical operation, and signal S 2AAnd precharging signal PRE is all high level when time point T6, so signal S 2ECan produce falling edge at time point T6.And because signal S 2AWhen time point T4, can change into low level, so signal S 2ECan produce rising edge at time point T4.That is, signal S 2ECan between time point T6～T4, keep low level.And signal S2F is with signal S 2EProduce after the delay through Td1 time delay, suppose time point T8=T6+Td1, then signal S 2FCan produce falling edge at time point T8, and produce rising edge at time point T5, that is signal S 2FT8～T5 keeps low level in time point.Because signal S 2BBehind time point T5 high level, synchronous signal S 2FBehind time point T5, also be high level, so make signal S 2GProduce falling edge in time point T5, and precharging signal PRE also can produce falling edge in time point T7 (supposing T7=T5+Td1).And activation access signal EN is signal S 2FOppositely, so activation access signal EN can keep high level between time point T8～T5.So just, can utilize memory access circuit 300 of the present invention to produce one group of precharging signal PRE and activation access signal EN, in order to access memory.
As shown in Figure 3, precharging signal PRE and activation access signal EN that memory access circuit 300 of the present invention is produced have the good signal corresponding relation, that is the activation time point of precharging signal PRE can be early than the activation time point of activation access signal EN, and the disabled time point of precharging signal PRE can be later than the disabled time point of activation access signal EN.Therefore, but the accessing operation of precharging signal PRE that memory access circuit of the present invention 300 is produced and access enable signal EN triggered as normal storer.
Memory access circuit of the present invention 300 is by reset and feedback circuit 304 regular replacement latch circuits 302, with enable signal S periodically 2AAnd signal S 2BReset and feedback circuit 304 combines with latch circuit, and time delay error that processing procedure drift causes is reduced the influence of circuit.Make addition time delay of signal but the door lock of memory access circuit 300 of the present invention is in addition deposited circuit 306, therefore reduced the time delay of each section delay cell, and reduced the area that memory access circuit 300 integral body occupy.
Fig. 4 is the calcspar of another memory access circuit 400 of the present invention.Memory access circuit 400 comprises that latch circuit 402 (for example: D flip-flop (D flip-flop)), reset and feedback circuit 404, delay circuit 406 to be to deposit circuit 408 with door lock.Wherein, latch circuit 402 receives the input signal V of high level DD, and according to the triggering of clock signal clk with so that signal S 4AKeep V DDHigh level.In addition, latch circuit 302 also receives reset signal S 4E, in order to reset signal S 4AWherein, as reset signal S 4EDuring for high level, latch circuit 402 makes signal S 4AReset to low level.
As shown in Figure 4, delay circuit 406 of the present invention comprises delay cell 512,514, reaches 516.Wherein delay cell 512 is at first with signal S 4ATime delay T D1To obtain signal S 4BThen, delay cell 514 is with signal S 4BTime delay T D2To obtain signal S 4C Last delay cell 516 is with signal S 4CTime delay T D1To obtain signal S 4DReset and feedback circuit 404 comprises NAND door 510 and reverser 511, in order to signal S 4AAnd signal S 4DActuating logic NAND computing is also oppositely to produce reset signal S 4EDoor lock is deposited circuit 408 and is comprised two OR doors 522 and 524, wherein 522 couples of signal S of OR door 4BWith signal S 4CActuating logic OR computing is to obtain access enable signal EN.524 couples of signal S of OR door 4AWith signal S 4DActuating logic OR computing is to obtain precharging signal PRE.
Fig. 5 is the signal timing diagram of memory access circuit 400 shown in Figure 4.
As shown in Figure 5, suppose that input signal maintains high level V DDWhen clock signal clk triggers in time point T1, latch circuit 402 is V in time point T1 output-voltage levels DDSignal S 4AFollow signal S 4B, S 4C, S 4DBe respectively by signal S4A Td1 time delay, (Td1+Td2), (2*Td1+Td2) and produce, therefore as shown in Figure 5, suppose signal S 4B, S 4C, S 4DRespectively at time point T2 (supposing T2=T1+Td1), T3 (supposing T3=T1+Td1+Td2=T2+Td2), and T4 (suppose T4=T1+2*Td1+Td2) generation rising edge.Because reset signal S 4EBe signal S 4AAnd signal S 4DVia logic NAND computing oppositely back generation again, so reset signal S 4ECan produce rising edge at time point T4, make signal S 4AProduce falling edge at time point T5, that is make signal S 4ABetween T1～T5, keep high level.Signal S like this 4BT2～T6 keeps high level at time point; Signal S 4CT3～T7 keeps high level at time point; Signal S 4DT4～T8 keeps high level at time point.
In addition, as shown in Figure 4, precharging signal PRE is by signal S 4AWith signal S 4DCarry out logic OR computing and produce, so precharging signal PRE produces rising edge in time point T1, and produce falling edge in time point T8.That is precharging signal PRE can keep high level between time point T1～T8, as mentioned above, is (3T during the activation of precharging signal PRE D1+ 2T D2).In addition, access enable signal EN is by signal S 4BWith signal S 4CCarry out logic OR computing and produce, so access enable signal EN produces rising edge in time point T2, and produce falling edge in time point T7.That is access enable signal EN can keep high level between time point T2～T7, as mentioned above, is (T during the activation of access enable signal EN D1+ 2T D2).
As shown in Figure 5, precharging signal PRE and activation access signal EN that memory access circuit 400 of the present invention is produced have the good signal corresponding relation, that is the activation time point of precharging signal PRE can be early than the activation time point of activation access signal EN, and the disabled time point of precharging signal PRE can be later than the disabled time point of activation access signal EN.Therefore, but the accessing operation of precharging signal PRE that memory access circuit of the present invention 400 is produced and access enable signal EN triggered as normal storer.
In addition, memory access circuit of the present invention 400 is by reset and feedback circuit 404 regular replacement latch circuits 402, with enable signal S periodically 4A, S 4B, S 4C, S 4D, make time delay error that processing procedure drift causes reduce to the influence of circuit.In addition, by with signal S 4A, S 4B, S 4C, S 4DInput gate latch cicuit 508 is to produce precharging signal PRE and access enable signal EN.Deposit in the circuit 408 at door lock, but therefore addition time delay of signal has reduced the time delay of each section delay cell, and has reduced the area that memory access circuit 400 integral body occupy.
In addition, be the triggering edge of latch circuit though the present invention is a rising edge with clock signal clk, also can use the falling edge of clock signal clk in fact or use the rising edge of clock signal simultaneously and falling edge is the triggering edge of latch circuit.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.

Claims (14)

1. memory access circuit, in order to produce precharging signal and access enable signal, this memory access circuit comprises:
Latch circuit, input end receives the input signal of noble potential, and when the clock signal triggering, this latch circuit is exported first signal according to the level of this input signal;
The reset and feedback circuit, be coupled to this latch circuit, receive this first signal in order to produce secondary signal and reset signal, wherein reverse this first signal of this reset and feedback circuit is to produce this secondary signal, this reset and feedback circuit produces this reset signal with this first signal and the 3rd signal after logical operation, wherein the 3rd signal for postpone and oppositely this secondary signal obtain, wherein this latch circuit receives this reset signal and according to the level of this reset signal this first signal of resetting; And
Door lock is deposited circuit, is coupled to this latch circuit and this reset and feedback circuit, and this door lock is deposited circuit this first signal and this secondary signal are produced this precharging signal and this access enable signal after logical operation.
2. memory access circuit according to claim 1, wherein this reset and feedback circuit comprise first reverser in order to reverse this first signal to produce this secondary signal.
3. memory access circuit according to claim 2, wherein this reset and feedback circuit comprises: first delay cell is connected to this first reverser; Second reverser is connected to this first delay cell; And first logic NAND door be connected to this second reverser; Wherein the delay of this first delay cell and this second reverser and reverse this secondary signal are the 3rd signal; Wherein this first logic NAND door to this first signal and the 3rd signal actuating logic NAND computing to produce this reset signal.
4. memory access circuit according to claim 3, wherein this first delay cell comprised for first time delay, made this secondary signal postpone this first time delay.
5. memory access circuit according to claim 1, wherein this memory access circuit also comprises the output terminal of the 3rd reverser and the 4th reverser polyphone to this latch circuit, in order to twice reverse this first signal.
6. memory access circuit according to claim 1, wherein this door lock is deposited circuit and is comprised: the second logic NAND door, second delay cell, the 5th reverser, the 3rd logic NAND door and the 3rd delay cell; Wherein this second logic NAND door produces the 4th signal according to this first signal and this precharging signal; This second delay units delay the 4th signal is to produce the 5th signal; Reverse the 5th signal of the 5th reverser is to produce this access enable signal; Wherein the 3rd logic NAND produces the 6th signal according to this secondary signal and the 5th signal; The 3rd delay units delay the 6th signal is to produce this precharging signal.
7. memory access circuit according to claim 6, wherein this second delay cell and the 3rd delay cell included for second time delay.
8. memory access circuit according to claim 1, wherein when this reset signal is low level, this latch circuit this first signal of resetting then.
9. memory access circuit, in order to produce precharging signal and access enable signal, this memory access circuit comprises:
Latch circuit, input end receives the input signal of noble potential, and when the clock signal triggering, this latch circuit is exported first signal according to the level of this input signal;
Delay circuit receives this first signal, and this first signal of this delay circuit sequential delays is to produce secondary signal, the 3rd signal and the 4th signal;
The reset and feedback circuit is coupled to this latch circuit and this delay circuit, receives this first signal and the 4th signal, and wherein this reset and feedback circuit produces reset signal with this first signal and the 4th signal after logical operation; Wherein this latch circuit receives this reset signal and according to the level of this reset signal this first signal of resetting; And
Door lock is deposited circuit, is coupled to this latch circuit and this delay circuit, and this door lock is deposited circuit this first signal and this secondary signal, the 3rd signal and the 4th signal are produced this precharging signal and this access enable signal after logical operation.
10. memory access circuit according to claim 9, wherein this delay circuit comprises:
First delay cell is coupled to latch circuit, in order to postpone this first signal to produce this secondary signal;
Second delay cell is coupled to this first delay cell, in order to postpone this secondary signal to produce the 3rd signal; And
The 3rd delay cell is coupled to this second delay cell, in order to postpone the 3rd signal to produce the 4th signal.
11. memory access circuit according to claim 10, wherein this first delay cell included for first time delay, and this second delay cell included for second time delay, and the 3rd delay cell included for the 3rd time delay.
12. memory access circuit according to claim 9, wherein this reset and feedback circuit comprises: logic NAND door and reverser, wherein this logic NAND door and this reverser carry out after the logic NAND computing oppositely this first signal and the 4th signal, to produce this reset signal.
13. memory access circuit according to claim 9, wherein this door lock is deposited circuit and is comprised:
The first logic OR door is coupled to this latch circuit and this delay circuit, in order to this first signal and the 4th signal actuating logic OR computing to produce this precharging signal; And
The second logic OR door is coupled to this delay circuit, in order to this secondary signal and the 3rd signal actuating logic OR computing to produce this access enable signal.
14. memory access circuit according to claim 9, wherein when this reset circuit is logic high, this latch circuit this first signal of resetting then.
CN2007101063987A 2007-05-28 2007-05-28 Memory access circuit Active CN101055759B (en)

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CN105304121B (en) * 2014-07-31 2018-11-16 展讯通信（上海）有限公司 The center control circuit of SRAM memory
CN116913343B (en) * 2023-09-13 2023-12-26 浙江力积存储科技有限公司 Activated precharge feedback circuit and memory

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CN1378112A (en) * 2001-04-03 2002-11-06 华邦电子股份有限公司 Current source device for latching detection
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US6169704B1 (en) * 1998-05-20 2001-01-02 Micron Technology, Inc. Apparatus and method for generating a clock within a semiconductor device and devices and systems including same
CN1378112A (en) * 2001-04-03 2002-11-06 华邦电子股份有限公司 Current source device for latching detection
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