CN104796132A

CN104796132A - Flip-flop circuit

Info

Publication number: CN104796132A
Application number: CN201410268742.2A
Authority: CN
Inventors: 陈祺琦
Original assignee: Individual
Current assignee: Individual
Priority date: 2014-01-22
Filing date: 2014-06-09
Publication date: 2015-07-22
Anticipated expiration: 2034-06-09
Also published as: CN104796132B

Abstract

The invention provides a flip-flop circuit, and belongs to the technical field of semiconductor integrated circuits. The flip-flop circuit comprises a master latch and a secondary latch driven by clocking signals with same phases; the master latch comprises a first logic module for selectively and at least performing AND logic processing on an input data signal and the clock signal, a second logic module for at least performing NOR logic processing on the clock signal and an output signal of a third logic module, and the third logic module for selectively and at least performing the NOR logic processing on the output signal of the first logic module and the output signal of the second logic module so as to output a result to the second logic module; the secondary latch comprises a fourth logic module for at least performing the NOR logic processing on the output signal of the second logic module and the output signal of a fifth logic module, and the fifth logic module for at least performing the AND logic processing on the clock signal and an inversion signal of the output signal of the fourth logic module. The flip-flop circuit is low in dynamic power consumption.

Description

A kind of flip-flop circuit

Technical field

The invention belongs to semiconductor integrated circuit (IC) technical field, relate to the flip-flop circuit realizing low-power consumption.

Background technology

Integration density along with integrated circuit (Integrated Circuit, IC) constantly increases and the improving constantly of its clock operating frequencies, and the power consumption (especially dynamic power consumption) of IC more and more receives publicity.Especially for mancarried electronic aid, its performance and power consumption are paradox, and Ge great manufacturer makes great efforts to reduce its power consumption in the performance improving constantly electronic equipment simultaneously, to improve the service time of the limited electricity of mancarried electronic aid.The application of various high performance IC often because power consumption is too high in mancarried electronic aid receives restriction.

Trigger (Flip-Flop) circuit is the basic function circuit unit in integrated circuit, and it is widely used in various integrated circuit.In some integrated circuit, clock network and trigger consume the dynamic power consumption exceeding half.In traditional flip-flop circuit, latch transmission gate (or triple gate) carries out the collection of data, transmission and preservation in conjunction with clock signal, and these transmission gates (or triple gate) need the clock of two states to drive simultaneously, thus clock needs to produce complementary two phase clock with inverter.Thus no matter whether the state of trigger changes, along with the upset of clock, circuit needs to provide a large amount of power consumption to drive these inverters, transmission gate (or triple gate).

Therefore, the power consumption reducing the flip-flop circuit in integrated circuit will be very beneficial for reducing the power consumption of integrated circuit.

Summary of the invention

The object of the invention is to, reduce the power consumption of trigger.

For realizing above object or other objects, the invention provides a kind of flip-flop circuit, comprising as the first latch of main latch with as the second latch from latch; Under described first latch and the second latch are operated in the clock signal of same phase;

Described first latch comprises the first logic module, the second logic module and the 3rd logic module;

Wherein, the data-signal (D) that described first logic module is used for selectively inputting to major general carries out "AND" logical process with described clock signal (CKN),

Described second logic module is used for carrying out nondisjunction logical process to clock signal described in major general (CKN) and the output signal (S2) of described 3rd logic module,

Described 3rd logic module is used for selectively carrying out nondisjunction logical process to export described second logic module to the output signal (S1) of the first logic module described in major general and the output signal (S0) of described second logic module;

Described second latch comprises the 4th logic module and the 5th logic module;

Wherein, described 4th logic module is used for carrying out nondisjunction logical process to the output signal (S1) of the second logic module described in major general and the output signal (S4) of described 5th logic module,

Described 5th logic module carries out "AND" logical process for the inversion signal (S5) of the output signal (S3) to clock signal described in major general (CKN) and described 4th logic module.

According to the flip-flop circuit of one embodiment of the invention, wherein, described second latch also comprises: for the output signal (S3) of described 4th logic module being carried out the 6th logic module of anti-phase process.

Alternatively, described 6th logic module comprises two the first not gates (X5) and the second not gate (X6) that are arranged in parallel, the output of described first not gate (X5) generates the described inversion signal (S5) being used for described second latch inside, and the output of described second not gate (X6) generates the output signal (Q) of described flip-flop circuit.

According to the flip-flop circuit of further embodiment of this invention, wherein, described first logic module be first with door (X0), described second logic module is the first NOR gate (X1), and described 3rd logic module is the second NOR gate (X2).

Alternatively, described first with door (X0) comprise at least for receive described data-signal (D) first input end, for receive clock signal (CKN) the second input and output to the output of first node (N0);

Described first NOR gate (X1) and the second NOR gate (X2) comprise the output outputting to Section Point (N1) and the 3rd node (N2) respectively, the first input end of described first NOR gate (X1) receives described clock signal (CKN), second input of described first NOR gate (X1) is coupled to described 3rd node (N2), and the first input end of described second NOR gate (X2) and the second input are respectively coupled to described first node (N0) and Section Point (N1).

At the flip-flop circuit of described any embodiment before, wherein,

When clock signal is in high level, the first latch image data signal (D) by its rp state be kept at the 3rd node (N2), the second latch then latched the preceding state of the output signal (Q) of this flip-flop circuit;

When clock signal is in low level, data-signal (D) is transferred to the second latch by Section Point (N1) by the first latch, and the second latch will output signal the state that (Q) is set to current data-signal (D).

According to the flip-flop circuit of further embodiment of this invention, wherein, the first logic module of described first latch, the second logic module and the 3rd logic module at least by first with-or-NOT logic door (241) and with this first with-or first or-NOT logic door (242) that-NOT logic door (241) is connected realize;

4th logic module of described second latch and the 5th logic module are realized by second and-NOT logic door (243).

Particularly, described first and-NOT logic door (241) comprise the first nmos pass transistor (MN0), nmos pass transistor (MN1), the 3rd nmos pass transistor (MN2) and the first PMOS transistor (MP0), the second PMOS transistor (MP1), the 3rd PMOS transistor (MP2);

Wherein, the grid of described first PMOS transistor is defined as Section Point (N1), the drain electrode of described first PMOS transistor is defined as the 3rd node (N2), described second PMOS transistor (MP1) and the 3rd PMOS transistor (MP2) are coupled between the source electrode of power supply and the first PMOS transistor in parallel, the grid of described second PMOS transistor (MP1) accesses described data-signal (D), and the grid of described 3rd PMOS transistor (MP2) accesses described clock signal (CKN);

Wherein, described first nmos pass transistor (MN0) is coupled between the 3rd node (N2) and ground, the grid of described first nmos pass transistor (MN0) is coupled to described Section Point (N1), described second nmos pass transistor (MN1) and the 3rd nmos pass transistor (MN2) are in series coupled between the 3rd node (N2) and ground, the grid of described second nmos pass transistor (MN1) accesses described data-signal (D), and the grid of described 3rd nmos pass transistor (MN2) accesses described clock signal (CKN);

Described first or-NOT logic door (242) comprise the 4th nmos pass transistor (MN3), the 5th nmos pass transistor (MN4) and the 4th PMOS transistor (MP3), the 5th PMOS transistor (MP4);

Wherein, described 4th PMOS transistor (MP3) and the 5th PMOS transistor (MP4) are in series coupled between power supply and described Section Point (N1), the grid of described 4th PMOS transistor (MP3) accesses described clock signal (CKN), and the grid of described 5th PMOS transistor (MP4) is coupled to described 3rd node (N2); Described 4th nmos pass transistor (MN3) and the 5th nmos pass transistor (MN4) are coupled between described Section Point (N1) and ground in parallel, the grid of described 4th nmos pass transistor (MN3) receives described clock signal (CKN), and the grid of described 5th nmos pass transistor (MN4) is coupled to described 3rd node (N2).

Particularly, described second and-NOT logic door (243) comprise the 6th nmos pass transistor (MN5), the 7th nmos pass transistor (MN6), the 8th nmos pass transistor (MN7) and the 6th PMOS transistor (MP5), the 7th PMOS transistor (MP6), the 8th PMOS transistor (MP7);

Wherein, the drain electrode of described 8th PMOS transistor is defined as the 4th node (N3), and grid and the described Section Point (N1) of described 8th PMOS transistor couple; Described 6th PMOS transistor (MP5) and the 7th PMOS transistor (MP6) are coupled between the source electrode of power supply and the 8th PMOS transistor in parallel, grid access output signal (Q) of described 7th PMOS transistor (MP6), the grid of described 6th PMOS transistor (MP5) accesses described clock signal (CKN);

Described 8th nmos pass transistor (MN7) is coupled between the 4th node (N3) and ground, the grid of described 8th nmos pass transistor (MN7) is coupled to described Section Point (N1), described 6th nmos pass transistor (MN5) and the 7th nmos pass transistor (MN6) are in series coupled between the 4th node (N3) and ground, the grid of described 7th nmos pass transistor (MN6) accesses described data-signal (D), and the grid of described 6th nmos pass transistor (MN5) accesses described clock signal (CKN).

Preferably, described second latch also comprises two the first not gates (X5) and the second not gate (X6) be arranged in parallel.

In an also embodiment, first and-NOT logic door be with selection function with-or-NOT logic door.

The flip-flop circuit of an embodiment is gone back according to the present invention, wherein, described flip-flop circuit is the sweep type flip-flop circuit comprising selector (X100), and described selector (X100) is by one of them extremely described first logic module selecting signal (SE) to control with the data-signal (D) optionally exporting its access and sweep signal (SI);

When described selector (X100) exports described data-signal (D), described first logic module is used for the data-signal (D) of input and described clock signal (CKN) to carry out "AND" logical process;

When described selector (X100) exports described sweep signal (SI), described first logic module is used for the sweep signal (SI) of input and described clock signal (CKN) to carry out "AND" logical process.

According to the flip-flop circuit of yet another embodiment of the invention, wherein, described first logic module be first with door (X0), described 3rd logic module is the second NOR gate (X2), first or door (X1 ') and the first NAND gate (X8) form described second logic module, to make described flip-flop circuit, there is asynchronous set function.

Particularly, described first with door (X0) comprise at least for receive described data-signal (D) first input end, for receive clock signal (CKN) the second input and output to the output of first node (N0);

Described first NAND gate (X8) and the second NOR gate (X2) comprise the output outputting to Section Point (N1) and the 3rd node (N2) respectively, described first or the first input end of door (X1 ') receive described clock signal (CKN), described first or the second input of door (X1 ') be coupled to described 3rd node (N2), described first or the output of door (X1 ') be coupled to the first input end of described first NAND gate (X8), second input of described first NAND gate (X8) receives asserts signal (NSET), the first input end of described second NOR gate (X2) and the second input are respectively coupled to described first node (N0) and Section Point (N1).

According to the flip-flop circuit of the present invention's also another embodiment, wherein, described flip-flop circuit also comprises the second NAND gate (X10), and described second NAND gate (X10) is for carrying out NAND logical process with output feedback signal (FB) to described first latch by the output signal (Q) of described flip-flop circuit and described data-signal (D);

Described first latch also comprises the 7th logic module, and it is for carrying out "AND" logical process to export described second logic module to by described feedback signal (FB) and clock signal (CKN).

Particularly, when the output signal (Q) of data-signal (D) and flip-flop circuit is high level, described second NAND gate (X10) exports as low level feedback signal (FB), makes described first latch ignore the upset of described clock signal and keep the constant of the data mode of internal node.

Particularly, when the output signal (Q) of data-signal (D) and flip-flop circuit is not all high level, described second NAND gate (X10) exports the feedback signal (FB) for high level, and described 7th logic module exports described clock signal (CKN), to make described second logic module, this clock signal (CKN) and the output signal (S2) of described 3rd logic module carried out nondisjunction logical process.

In also another embodiment, first logic module of described first latch and the 3rd logic module are realized by first and-NOT logic door, and the second logic module of described first latch and the 7th logic module are realized by the 3rd and-NOT logic door (542);

In also another embodiment, described first and-NOT logic door (241) comprise the first nmos pass transistor (MN0), the second nmos pass transistor (MN1), the 3rd nmos pass transistor (MN2) and the first PMOS transistor (MP0), the second PMOS transistor (MP1), the 3rd PMOS transistor (MP2);

Wherein, the grid of a described PMOS crystal (MP0) is defined as Section Point (N1), the drain electrode of described first PMOS transistor is defined as the 3rd node (N2), described second PMOS transistor (MP1) and the 3rd PMOS transistor (MP2) are coupled between the source electrode of power supply and the first PMOS transistor in parallel, the grid of described second PMOS transistor (MP1) accesses described data-signal (D), and the grid of described 3rd PMOS transistor (MP2) accesses described clock signal (CKN);

Wherein, described first nmos pass transistor (MN0) is coupled between the 3rd node (N2) and ground, the grid of described first nmos pass transistor (MN0) is coupled to described Section Point (N1), described second nmos pass transistor (MN1) and the 3rd nmos pass transistor (MN2) are in series coupled between the 3rd node (N2) and ground, the grid of described nmos pass transistor (MN1) accesses described data-signal (D), and the grid of described 3rd nmos pass transistor (MN2) accesses described clock signal (CKN);

Described 3rd and-NOT logic door (542) comprise the 4th nmos pass transistor (MN3), the 5th nmos pass transistor (MN4), the 9th nmos pass transistor (MN9) and the 4th PMOS transistor (MP3), the 5th PMOS transistor (MP4), the 9th PMOS transistor (MP9);

Wherein, the grid of described 5th PMOS transistor (MP4) is coupled to described 3rd node (N2), the drain electrode of described 5th PMOS transistor (MP4) is coupled to described Section Point (N1), described 4th PMOS transistor (MP3) and described 9th PMOS transistor (MP9) are coupled between the source electrode of power supply and the 5th PMOS crystal (MP4) in parallel, the grid of described 4th PMOS transistor (MP3) accesses described clock signal (CKN), the grid of described 9th PMOS transistor (MP9) accesses described feedback signal (FB),

Wherein, described 5th nmos pass transistor (MN4) is coupled between described Section Point (N2) and ground, the grid of described 5th nmos pass transistor (MN4) couples and described 3rd node (N2), described 4th nmos pass transistor (MN3) and described 9th nmos pass transistor (MN9) are in series coupled between Section Point (N1) and ground, the grid of described 4th nmos pass transistor (MN3) accesses described clock signal (CKN), and the grid of described 9th nmos pass transistor (MN9) accesses described feedback signal (FB).

In also another embodiment, described second and-NOT logic door (243) comprise the 6th nmos pass transistor (MN5), the 7th nmos pass transistor (MN6), the 8th nmos pass transistor (MN7) and the 6th PMOS transistor (MP5), the 7th PMOS transistor (MP6), the 8th PMOS transistor (MP7);

The tristate inverter that the transmission gate that flip-flop circuit provided by the invention does not use clock signal to control controls with the inversion signal of this clock signal, and be work under the clock signal of same phase, there is relatively low dynamic power consumption, and can correctly work, unfailing performance is guaranteed, and realizing circuit structure is relatively simple.

Accompanying drawing explanation

From following detailed description by reference to the accompanying drawings, will make above and other object of the present invention and advantage more complete clear, wherein, same or analogous key element adopts identical label to represent.

Fig. 1 is the basic circuit structure schematic diagram of a kind of flip-flop circuit of prior art.

Fig. 2 is the gate level circuit figure of the flip-flop circuit according to first embodiment of the invention.

Fig. 3 is the level signal change schematic diagram in flip-flop circuit shown in Fig. 2, wherein Fig. 3 (a) is each node when clock signal becomes high level and level corresponding to signal, and Fig. 3 (b) is each node when clock signal becomes low level and level corresponding to signal.

Fig. 4 is the electrical block diagram of the wherein embodiment realizing flip-flop circuit shown in Fig. 3.

Fig. 5 is the equivalent circuit diagram of the flip-flop circuit shown in Fig. 4 when clock signal becomes high level.

Fig. 6 is the equivalent circuit diagram of the flip-flop circuit shown in Fig. 4 when clock signal becomes low level.

Fig. 7 is the gate level circuit figure of the flip-flop circuit according to second embodiment of the invention.

Fig. 8 is the electrical block diagram of the wherein embodiment realizing flip-flop circuit shown in Fig. 7.

Fig. 9 is the gate level circuit figure of the flip-flop circuit according to third embodiment of the invention.

Figure 10 shows that the electrical block diagram of the wherein embodiment realizing flip-flop circuit shown in Fig. 9.

Figure 11 is the gate level circuit figure of the flip-flop circuit according to fourth embodiment of the invention.

Figure 12 is the electrical block diagram of the wherein embodiment realizing flip-flop circuit shown in Figure 11.

Embodiment

Introduce below be of the present invention multiple may some in embodiment, aim to provide basic understanding of the present invention, be not intended to confirm key of the present invention or conclusive key element or limit claimed scope.Easy understand, according to technical scheme of the present invention, do not changing under connotation of the present invention, one of ordinary skill in the art can propose other implementations that can mutually replace.Therefore, following embodiment and accompanying drawing are only the exemplary illustrations to technical scheme of the present invention, and should not be considered as of the present invention all or the restriction be considered as technical solution of the present invention or restriction.

For understanding the progress of flip-flop circuit of the present invention in power consumption better, first detailed example discloses a kind of operation principle of traditional flip-flop circuit and the too high reason of power consumption thereof.

Figure 1 shows that the basic circuit structure schematic diagram of a kind of flip-flop circuit of prior art.With reference to figure 1, in this embodiment, the trigger 10 of prior art is formed primarily of two latchs 11 and 12, complementary clock signal generation circuit 13 and two inverter INV0 and INV3.Particularly, latch 11 is as main latch, and it is formed primarily of the first transmission gate PT1 and the first latch units 112; Wherein, inverter INV1a and tristate inverter INV1b cross-couplings constitute the first latch units 112; Latch 12 conducts are from latch, and it is formed primarily of the second transmission gate PT2 and the second latch units 122, and wherein inverter INV2a and tristate inverter INV2b cross-couplings constitute the second latch units 122.

Complementary clock signal produces circuit 13 and is made up of inverter INV4a and INV4b of two series connection, its effect be to latch 11 and 12 inside transmission gate PT1-PT2, tristate inverter INV1b-INV2b produce complementary clock signal.Such as, inverter INV4a by anti-phase for clock signal C KN with the clock signal producing an opposite logic states further by the effect of next inverter INV4b, a clock signal C KN1 with logic state can be produced again.Apparently, with the clock signal that CKN1 is two logic state complementations.

Inverter INV0 is used to anti-phase for the data-signal (D) of input to produce an anti-phase data-signal and be supplied to latch 11.In latch 11, the first transmission gate PT1 comprises control end and the reception that receives CKN1 signal the inverted control terminals of signal, its output is connected to the first latch units 112; In the first latch units 112, tristate inverter INV1b comprises one the Enable Pin controlled and a CKN1 control invert enable end.Meanwhile, the output of latch 11 is connected to the second transmission gate PT2 of latch 12.

In latch 12, the second transmission gate PT2 comprises a reception the inverted control terminals of the control end of signal and a reception CKN1 signal, its output is connected to the second latch units 122; In the second latch units, tristate inverter INV2b comprises the Enable Pin and that CKN1 controls the invert enable end controlled.Meanwhile, the output of latch 12 is coupled to the input of inverter INV3.

Therefore, at identical CKN1 and under signal is biased, the first transmission gate PT1 is contrary with the operating state of the second transmission gate PT2, and the operating state of tristate inverter INV1b and tristate inverter INV2b is also contrary.

When clock CKN is in high level, inverter INV4a will be reduced to low level, inverter INV4b is driven into high level CKN1 simultaneously.Thus the first transmission gate PT1 conducting also will pass in the first latch units 112.And, be in the CKN1 of high level and be in low level cut off the second transmission gate PT2, and then latch 11 and latch 12 have been kept apart.Meanwhile, the Q of previous state latches by the second latch units 122.

When clock CKN jumps to low level, inverter INV4a handle be driven into high level, inverter INV4b has been reduced to low level CKN1 simultaneously.Thus the first transmission gate PT1 ends and the first latch units 112 is kept apart with input signal D.Meanwhile, the second transmission gate PT2 conducting storing before be transferred to the second latch units 122 from the first latch units 112, be then transferred to the output Q of trigger 10 again by inverter INV3, thus, Q=D.Meanwhile, data-signal be latched in the first latch units 112.

In the trigger 10 of above embodiment, can find out, when circuit working, need by inverter INV4a-INV4b provide simultaneously two anti-phase clock signal C KN1 and i.e. complementary clock signal.Therefore, when clock CKN overturns, these two inverter INV4a-INV4b can produce extra power consumption.And these two complementary clock signals are as the control signal of transmission gate PT1-PT2 and tristate inverter INV1b and INV2b, also transmission gate PT1-PT2 and tristate inverter INV1b and INV2b can be made to produce unnecessary power consumption when clock upset.Therefore, the power consumption of the trigger 10 of this embodiment is larger.

In the trigger that what in ISSCC2011 meeting, the people such as Chen Kong Teh delivered be entitled as disclosed in " A77%Energy-Saving22-Transistor Single-Phase-Clocking D-Flip-Flop withAdaptive-Coupling Configuration in40nm CMOS ", ms filp flop adopts single-phase, can reduce the power consumption of trigger.But it only can keep low-power consumption when low toggle frequency, and when high tumble frequency, power consumption goes up not down; Further, adopting single metal-oxide-semiconductor to transmit data, to be easily subject to technogenic influence comparatively large, so when the larger situation of process shifts and when being operated in again low voltage mode, this trigger just easily overturns failure, thus can not ensure that data are correctly transmitted.

U.S. Patent Application No. is US13/095,641, be entitled as in the patent of " SINGLE-TRIGGERLOW-ENERGY FLIP-FLOP CIRCUIT ", there is disclosed the method for the power consumption reducing trigger; But wherein flip-flop circuit realizes difficulty, need very many metal-oxide-semiconductors to realize, and when high tumble rate, its dynamic power consumption also can increase greatly.

Figure 2 shows that the gate level circuit figure structure schematic representation of the flip-flop circuit according to first embodiment of the invention.In this embodiment, flip-flop circuit 20 realizes with the form of d type flip flop, and particularly, trigger 20 comprises as the first latch 21 of main latch with as the second latch 22 from latch.First latch 21 acts on the main latch be equivalent in trigger, and it comprises one and a door X0 and two NOR gate X1 and X2.Wherein, comprise the input of receive clock signal CKN and receives the input of data-signal D with door X0, also comprise the output of a generation signal S0, this output defined node N0 is also coupled to the input of NOR gate X2.NOR gate X1 comprises two inputs, one of them input receive clock signal CKN, and another input receives the output signal S2 of NOR gate X2; NOR gate X1 comprises one produces signal S1 output at node N1.NOR gate X2 comprises one produces signal S2 output at node N2, and NOR gate X2 comprises two inputs, and one of them receives the input of the output signal S1 of NOR gate X1, and another receives the input with the output signal S0 of door X0.In certain embodiments, be called as " internal signal " at the signal S1 of node N1.Such as, in ensuing specific descriptions, as the first latch 21 latch data signal D (such as when clock signal C KN is high level), internal signal S1 will be reduced to logic low level; And when data-signal D is sent to the second latch 22 by the first latch 21 (such as when clock signal C KN is low level), this internal signal will be configured to the logic state consistent with D.

Second latch 22 effect be equivalent to from latch, it mainly comprise NOR gate X3, with door X4 and not gate X5 and X6.Wherein, NOR gate X3 comprises two inputs, one of them input receives the output signal S1 (i.e. the signal of node N1) of the first latch 21, and another input is coupled to and the output of door X4 (i.e. node N4), from Received signal strength S4; NOR gate X3 comprises one produces signal S3 output at node N3.The output of the input AND OR NOT gate X3 of not gate X6 couples, and its Received signal strength S3 also exports after its logical inversion, thus creates the output signal (Q) of trigger 20.Not gate X5 NAND gate X6 is in parallel, and the signal S3 logical inversion of the output of NOR gate X3 is also produced the Q signal that is used for the second latch 22 inside by it, and namely S5, S5 are substantially identical with output signal Q.Also two inputs and an output is comprised with door X4, one of them input receive clock signal CKN, another input receives the signal Q (i.e. S5) that not gate X5 produces, after signal S5 and clock signal C KN carries out "AND" logical process from output to produce signal S4, this output is coupled to an input of NOR gate X3, and forms node N4.

It is to be appreciated that not gate X5 and X6 is as inverter buffer circuit, in other embodiment, inverter circuit X5 and X6 can replace by some other suitable buffer circuits, in particular cases also can remove at some.And not gate X5 and X6 all produces output signal Q from the signal S3 of node N3.Different, signal Q feeds back to and door X4 by not gate X5, and not gate X6 is then using the output signal (such as output to other circuit or unit) of Q signal as trigger.Like this, be used for the internal signal of the second latch 22 relative to the signal Q of the signal Q that not gate X6 produces, not gate X5 generation, it can be subject to less external noise impact.In another embodiment, also can remove not gate X5, directly the signal Q that not gate X6 produces is connected to the input with door X4.

Figure 3 shows that the level signal change schematic diagram in flip-flop circuit shown in Fig. 2, wherein Fig. 3 (a) is each node when clock signal becomes high level and level corresponding to signal, and Fig. 3 (b) is each node when clock signal becomes low level and level corresponding to signal.The example course of work of trigger 20 is described below in conjunction with Fig. 2 and Fig. 3.

When clock signal CKN is in high level (CKN=1), as shown in Fig. 3 (a), NOR gate X1 will be reduced to node N1 corresponding for its output low level (no matter which kind of signal is S2 correspondence be), i.e. signal S1=0; Meanwhile, with door X0, the state of data-signal D is passed to signal S0, thus S0=D.Because S1 is low level, so NOR gate X2 is by anti-phase for S0 output, create the inversion signal of data-signal D at the node N2 that its output is corresponding be equivalent to D negate, namely like this, when clock signal CKN is high level, the first latch 21 can the state of image data signal D, and stores its inversion signal at node N2 place such as, as D=0, the first latch 21 stores at node N2 place if D=1, the first latch 21 will store at node N2 place

Like this, the logic state of signal S1 and the CKN of high level will be input to the second latch 22.When CKN=1, with door X4 the previous state transfer outputing signal Q to node N4, i.e. signal S4=Q.Because now signal S1 is in low level, NOR gate X3 is anti-phase and output to node N3, i.e. signal by S4 not gate X6 is anti-phase and output to node N6 by S3, namely outputs signal Q.Not gate X5 is also anti-phase by S3 and output to node N5, i.e. S5=Q, thus ensure that the output signal Q being input to and equaling trigger 20 with the signal S5 of door X4.Like this, by latch 22 with door-NOR gate-inverter feedback arrangement, the inversion signal of last Q state be latched at node N3.Unless it should be noted that clock signal C KN jumps to low level from high level, in the second latch 22 with door X4-NOR gate X3-not gate X5 structure by constantly in the value of node N5 place storage signal Q, and to store at node N3 place value.

When clock signal CKN jumps to low level from high level (CKN=0), as shown in Fig. 3 (b), the data-signal D stored before is transferred to the second latch 22 by node N1 by the first latch 21.Particularly, as CKN=0, NOR gate X1 will be stored in the signal at node N2 place anti-phase, and produce the signal equaling D state at node N1 place, i.e. S1=D; Then, S1 will be transferred to the second latch 22 further; Meanwhile, due to CKN=0, low level will be reduced to the output of door X0, i.e. S0=0, so NOR gate X2 is by anti-phase for signal S1 and its inverse value is outputted to node N2, the inversion signal of the data-signal D thus continue to be latched at node N2.Like this, the first latch 21 can be by be latched in N2 and D is latched in N1.Unless it should be noted that clock signal C KN is from low level rebound high level, the NOR gate X1-NOR gate X2 structure in the first latch 21 will store the value of D constantly at node N1 place, and stores at node N2 place value.

To NOR gate X3 be transferred at the D of node N1, and when CKN jumps to low level, can low level be reduced to the output S4 of door X4, and then make NOR gate X3 by the state inversions of S1.So the state of the node N3 that the output of NOR gate X3 is corresponding is set to namely not gate X6 is further by anti-phase for signal S3 output signal output Q, i.e. Q=D.Not gate X5 also can by anti-phase for signal S3 and make it output signal value that S5 is set to D, i.e. S5=D=Q, thus ensure that with the state of the input signal S5 of door X4 and to output signal Q consistent.Like this, by the NOR gate X3 in the first latch 21 and the second latch 22 and not gate X6, the state updating of output signal Q is the state of present input signal D.

As mentioned above, flip-flop circuit 20 is d type flip flops.Wherein, the first latch 21 is as being main latch, and the second latch 22 is as being from latch.When clock signal CKN is from low transition to high level, the first latch 21 is from data terminal D image data, and the preceding state of output signal Q preserved by the second latch 22.When clock signal CKN jumps to low level from high level, the first latch 21 is by the current transfer of data collected from D to the second latch 22, and then this data-signal D is passed to output signal Q by the second latch 22.

In these embodiments, the first latch 21 in flip-flop circuit 20 and the second latch 22 use the clock signal C KN of same phase, namely can be controlled by same clock signal C KN, this means two clock signals not needing to produce the complementation as described in Figure 1 needed for embodiment, thus, trigger 20 does not need clock inversion circuitry (clock inversion circuitry 130 in such as Fig. 1) to produce two complementary clock signals, and correspondingly eliminates the dynamic power consumption (flip-flop circuit in comparison diagram 1) producing two complementary clock signals.Such as, when the clock signal C KN in Fig. 1 overturns between high level and low level at every turn, inverter INV4a-INV4b can carry out charge or discharge accordingly, can produce larger dynamic power consumption like this; And the trigger 20 of correspondence can not produce such dynamic power consumption, because it does not have complementary clock signal to produce circuit.Simultaneously, compare the existing flip-flop circuit 10 shown in Fig. 1, flip-flop circuit 20 in Fig. 2 does not have transmission gate in similar latch 11 and 12 and triple gate unit, the dynamic power consumption in time being omitted transmission gate and triple gate that two complementary clock signals control at switch.Therefore, in dynamic power consumption, the trigger 10 in the relative Fig. 1 of the trigger 20 in Fig. 2 reduces greatly.Further, can correctly work, good reliability.

It will be appreciated that, the clock signal of " same phase " in the present invention refers to the phase place that sequential and phase place are substantially identical, complementary clock signal can not be interpreted as the clock signal of " same phase ", and, the clock signal of " same phase " preferably but be not limited to be same clock signal, such as, can be multiple clock signals that sequential is substantially identical with phase place, the height of the high level between the clock signal of " same phase " be not limited to necessarily identical.

Figure 4 shows that the electrical block diagram of the wherein embodiment realizing flip-flop circuit shown in Fig. 3.The flip-flop circuit 24 i.e. corresponding function realizing flip-flop circuit 20 of this embodiment, divide by function, flip-flop circuit 24 is mainly divided three modules, i.e. the first gate 241, second gate 242 and the 3rd gate 243, certainly not gate X5 and X6 is also comprised, not gate X5 and X6 can adopt existing various circuit structure to realize individually, at this, its circuit structure is no longer shown.In this embodiment, the first gate 241 is functionally and-or-NOT logic door (AOI) structure, and the second gate 242 is functionally or-NOT logic door, and the 3rd gate 243 is also functionally and-or-NOT logic door.And having at least in a kind of embodiment, the first and second gates 241 and 242 in Fig. 4 jointly achieve the 3rd gate 243 NAND gate X5 in the first latch 21, Fig. 4 in Fig. 2 and X6 and combine the second latch 22 achieved in Fig. 2.Particularly, the first gate 241 achieve in Fig. 2 with door X0 and NOR gate X2, the second gate 242 achieves the NOR gate X1 in Fig. 2, the 3rd gate 241 achieve in Fig. 2 with door X4 and NOR gate X3.

Particularly, the first gate 241 comprises nmos pass transistor MN0-MN2 (conducting when grid is high level) and PMOS transistor MP0-MP2 (conducting when grid is low level).Wherein, transistor MN1 and MN2 is in series coupled between node N2 and ground, and meanwhile, transistor MN0 is also coupled between N2 and ground, and like this, transistor MN1 and MN2 and transistor MN0 is arranged in parallel between node N2 and ground; The grid of transistor MN0 is coupled to node N1 (controlling by signal S1), and the grid of transistor MN1 receives data-signal D, transistor MN2 grid receive clock signal CKN.Transistor MP0 and MP2 coupled in series are between node N2 and power vd D between node N2 (controlling by signal S2) and power vd D for transistor MP0 and MP1 coupled in series, and like this, transistor MP2 and MP1 is arranged in parallel.The grid of transistor MP0 is coupled to node N1, and the grid of transistor MP1 receives data-signal D, and the grid receive clock signal CKN of transistor MP2.

Particularly, the second gate 242 comprises nmos pass transistor MN3-MN4, and PMOS transistor MP3-MP4.Transistor MN3 and MN4 is coupled between node N1 and ground in parallel; The grid of the grid receive clock signal CKN of transistor MN3, transistor MN4 is coupled to node N2 (controlling by signal S2); Transistor MP3-MP4 is in series coupled between node N1 and power vd D, and the grid of the grid receive clock signal CKN of transistor MP3, transistor MP4 is coupled to node N2 (controlling by signal S2).

Particularly, the circuit structure of circuit structure first gate 241 of the 3rd gate 243 is similar, and the 3rd gate 243 comprises nmos pass transistor MN5-MN7, and PMOS transistor MP5-MP7.Transistor MN5 and MN6 coupled in series are between node N3 and ground, and meanwhile, transistor MN7 is also coupled between node N3 and ground, and like this, transistor MN6 and MN5 and the transistor MN7 of series connection are arranged in parallel between node N2 and ground.The grid of the grid receive clock signal CKN of transistor MN5, transistor MN6 receives the grid outputing signal Q, transistor MN7 and is coupled to node N1 (controlling by signal S1).Transistor MP5 and MP7 coupled in series between node N3 and power vd D, transistor MP6 and MP7 coupled in series between node N3 and power vd D, like this, transistor MP6 and MP5 coupled in parallel.The grid of the grid receive clock signal CKN of transistor MP5, transistor MP6 receives output signal Q, and the grid of transistor MP7 is coupled to node N1 (controlling by signal S1).

Figure 5 shows that the equivalent circuit diagram of the flip-flop circuit shown in Fig. 4 when clock signal becomes high level.Composition graphs 5 elaborates by an example working method of flip-flop circuit 24.When clock signal CKN is in high level (CKN=1), the first gate 241 can gather the data-signal D of input, and by its inverse value be stored in node N2, the 3rd gate 243 keeps original output signal Q simultaneously.Concrete, as CKN=1, transistor MN2, MN3 and MN5 conducting, and MP2, MP3 and MP5 cut-off (as in figure in 5 shown in dotted transistor).The current potential of node N1 is reduced to earth potential (N1=0) by the MN3 of conducting, so signal S1 is in low level state (S1=0), and then MP0 conducting, MN0 cut-off, form the circuit (MP1, MP0, MN2, MN1 are connected in series the circuit of formation) as dotted line signal in the first gate 241 in Fig. 5, realize the function of inverter, the value of D is anti-phase outputs to node N2 this circuit equivalent thus, when CKN is in high level, the main latch that gate 241-242 is formed will be stored into node N2.

Low level signal S1 transmits the 3rd gate 243 further, because clock signal C KN is in high level, and MN5 conducting and MP5 cut-off; The low level signal S1 conducting MP7 at node N1 place also cuts MN7, form the circuit (MP6, MP7, MN6, MN5 are sequentially connected in series the circuit of formation) as dotted line signal in the 3rd gate 243 in Fig. 5, realize the function of inverter this circuit equivalent, like this, the value of previous output signal Q can be anti-phase, node not gate X5 and X6 by anti-phase for the signal S3 at node N3 place, so maintain the state of the output signal Q of preceding state.

Figure 6 shows that the equivalent circuit diagram of the flip-flop circuit shown in Fig. 4 when clock signal becomes low level.Composition graphs 6 elaborates by an example working method of flip-flop circuit 24.

When clock signal CKN jumps to low level (CKN=0), the second gate 242 by the first gate 241 preserve value pass to the 3rd gate 243, and be the state of present D by the state updating of original output signal Q.Particularly, as CKN=0, transistor MP2, MP3 and MP5 conducting, and transistor MN2, MN3 and MN5 cut-off (as in figure in 6 shown in dotted transistor).The source electrode of transistor MP0 is connected to power vd D by the transistor MP2 of conducting, and the source electrode of transistor MP4 is connected to power vd D by the transistor MP3 of conducting simultaneously, and the source electrode of transistor MP7 is connected to power vd D by the transistor MP5 of conducting.Because transistor MN2 ends, it stops N2 point current potential to be moved to earth potential by the MN1 that D controls, so just ensure that node N2 keeps previous storage always value, and need not worry that it can be subject to the impact of the D value of new input when CKN=0.

Latch at node N2 place be worth by anti-phase (the circuit realiration inverter function of the dotted line signal namely in the second gate 242 of the inverter formed primarily of transistor MN4 and MP4, now MP3, MP4, MN4 are sequentially connected in series, MP3 conducting, MP4 and MN4 controls by S2), and produce signal D at node N1 place.Then, D at node N1 place continues anti-phase (the circuit realiration inverter function of the dotted line signal namely in the first gate 241 of inverter formed by transistor MN0 and MP0, now MP2, MP0, MN0 are sequentially connected in series, MP2 conducting, MP0 and MN0 controls by S1), and output to node N2, so just can keep the state of node N2 to be

Simultaneously, in D also (the circuit realiration inverter function of dotted line signal namely in three gate 243 anti-phase by the inverter be made up of transistor MN7 and MP7 of node N1, now MP5, MP7, MN7 are sequentially connected in series, MP5 conducting, MP7 and MN7 controls by S1), and output to node N3, namely and then anti-phase by not gate X5 and X6, and output signal Q is set to D (i.e. Q=D).Like this, the value of D is sent to the 3rd gate 243 from second gate 242 by low level CKN, simultaneously not by the impact (unless clock signal is from low level rebound high level) of input data signal D saltus step.

Can find from the circuit structure of the trigger of above embodiment, the trigger of first embodiment of the invention can be realized by relatively less MOS transistor, the mos capacitance relevant to clock signal is little, in the process of clock signal C KN upset, be very beneficial for reducing dynamic power consumption, and be easy to realize.Further, as shown in Figure 4, CMOS complementary logic door can be adopted to realize, can effectively ensure data Successful transmissions, even if clock signal C KN is when high tumble frequency, also be, flip-flop circuit 20 works at high frequencies, and its power consumption can't rise too fast; Meanwhile, when power vd D is relatively low, also can correct reliably working.

Be the gate level circuit figure of the flip-flop circuit according to second embodiment of the invention described in Fig. 7.The basic structure of the flip-flop circuit 30 of this embodiment is substantially identical with flip-flop circuit 20 embodiment illustrated in fig. 2, its main distinction is: flip-flop circuit 30 relatively flip-flop circuit 20 adds a selector X100, like this, constitute a sweep type flip-flop circuit, that is, sweep type flip-flop circuit 30.In this embodiment, sweep type flip-flop circuit 30 comprises selector X100, the first latch 21 (identical with Fig. 2) and the second latch 22 (with identical in Fig. 2).This is no longer going to repeat them for the specific implementation of the first latch 21 and the second latch 22.Wherein, two inputs incoming data signal D and sweep signal SI respectively of X100, and comprise the input of input select signal SE, the output of X100 and coupling with an input (this input is in the embodiment depicted in figure 2 for incoming data signal D) of door X0 of the first latch 21.

When selecting signal SE to be in the first state (such as low level), data-signal D is allowed through selector X100 and arrives node N7, be then input to the first latch 21 with door X0; And when selecting signal SE to be in the second state (such as high level), sweep signal SI is allowed through selector X100 and arrives node N7, be then input to the first latch 21.And when clock signal CKN overturns, in the first latch 21 and the second latch 22 operation principle and Fig. 2, the operation principle of flip-flop circuit 20 is similar.

Figure 8 shows that the electrical block diagram of the wherein embodiment realizing flip-flop circuit shown in Fig. 7.With reference to figure 8, flip-flop circuit 34 is one of them embodiment of the flip-flop circuit 30 in Fig. 7, it comprises the first gate 341, second gate 242 (identical with the second gate 242 in Fig. 4) and the 3rd gate 243 (identical with the 3rd gate 243 in Fig. 4), and comprises for the not gate X110 by selecting the anti-phase output of signal SE.For some embodiment, the first gate 341 can be functionally band selection function with-or-NOT logic door; Second gate 242 is functionally or-NOT logic door, and the 3rd gate 243 is also functionally and-or-NOT logic door.Further, at least one embodiment, the first gate 341, second gate 242 in Fig. 8 and not gate X110 achieve selector X100 in Fig. 7 and the first latch 21 jointly; 3rd gate 243 and not gate X5 and X6 achieve the second latch 22 in Fig. 8 jointly.

Not gate X110 receives at input and selects signal SE, and at output reversed-phase output signal NSE.So, select signal SE and NSE to be jointly input in the first gate 341, make it can select the carrying out of data-signal D and sweep signal SI.

First gate 341 comprises nmos pass transistor MN0, MN2 and MN101-MN104, and PMOS transistor MP0, MP2 and MP101-MP104.Compared to embodiment illustrated in fig. 4, it mainly changes and is: transistor MN101-MN104 substitutes transistor MN1, and transistor MP101-MP104 substitutes transistor MP1.

Wherein, transistor MN2, MN101 and MN103 coupled in series is between node N2 and ground, transistor MN2, MN102 and MN104 coupled in series is between node N2 and ground simultaneously, and like this, MN101 and MN103 of series connection is parallel between node N100 and ground with MN102 and MN104 connected.In addition MN0 also coupled in series between node N2 and ground.The grid receive clock signal CKN of transistor MN2, the grid of transistor MN101 receives data-signal D, the grid of MN103 receives the inversion signal NSE selecting signal, the grid of transistor MN102 receives sweep signal SI, the grid of MN104 receives selects signal SE, and the grid of transistor MN0 is coupled to node N1.

Wherein, transistor MP0, MP101 and MP104 coupled in series is between node N2 and power vd D, transistor MP0, MP102 and MP103 coupled in series is between node N2 and power vd D simultaneously, like this, MP101 and MP104 of series connection is parallel between node N101 and power vd D with MP102 and MP103 connected.In addition, transistor MP0 and MP2 also coupled in series between node N2 and power vd D.The grid receive clock signal CKN of transistor MP2, the grid of transistor MP101 receives data-signal D, the grid of MP103 receives the inversion signal NSE selecting signal, the grid of transistor MP102 receives sweep signal SI, the grid of MP104 receives selects signal SE, and the grid of transistor MP0 is coupled to node N1.It should be noted that the selector X100 the first gate 341 in Fig. 8 and not gate X110 logic function achieved in Fig. 7, with door X0 and NOR gate X2.

An example working method of flip-flop circuit 34 is expressed as follows.When selecting signal SE to be low level (SE=0), its complement signal NSE raises as high level (NSE=1) by not gate X110.So, transistor MN103 and MP104 conducting, and transistor MN104 and MP103 ends, result, data-signal D is chosen as collected signal by gate 341.Similar with the flip-flop circuit 24 in Fig. 4, when clock signal CKN is in high level (CKN=1), the first gate 341 pairs input data signal D gathers, and by its inverse value be stored in node N2, the 3rd gate 243 keeps original output signal Q simultaneously; When clock signal CKN jumps to low level (CKN=0), the second gate 242 by the first gate 341 preserve value pass to the 3rd gate 243, and be the state of present D by the state updating of original output signal Q.Its specific works process is see declaratives corresponding to Fig. 5.

When selecting signal SE to be high level (SE=1), NSE is reduced to low level (NSE=0) by not gate X110, so, transistor MN103 and MP104 ends, and transistor MN104 and MP103 conducting, result, sweep signal SI is chosen as collected signal by the first gate 341, and when clock overturns, its working method and above data-signal D similar by situation about selecting.It is noted that when clock signal is high level, sweep signal SI is gathered by gate 341 and by its complement be stored in node N2; And when clock is low level, the state of sweep signal SI is passed to output Q by gate 242-243.

Be the gate level circuit figure of the flip-flop circuit according to third embodiment of the invention described in Fig. 9.With reference to figure 9, which depict the gate level circuit figure that can be used for asynchronous set trigger, in this embodiment, asynchronous set flip-flop circuit 40 comprises the first latch 41 and the second latch 22 (identical with the second latch 22 in Fig. 2).First latch 41 effect be equivalent to main latch, comprise one with door X0, one or an X1 ', a NOR gate X2 and NAND gate X8.Wherein, comprise the input of receive clock signal CKN and the input of data-signal D with door X0, also comprise the output that produces signal S0, this output defined node N0 is also coupled to the input of NOR gate X2.Or door X1 ' comprises one produces the output of signal S8, the input of a receive clock signal CKN and reception NOR gate X2 output signal S2 input at node N8.NAND gate X8 comprises one outputs signal S8 input in the output of node N1 generation signal S1, the input of a reception asserts signal NSET and a reception or door X1 '.NOR gate X2 comprise one node N2 produce signal S2 output, one receive the input that outputs signal S0 with door X0 and one receive the input that NAND gate X8 outputs signal S1.

Therefore, compared to flip-flop circuit 20 embodiment illustrated in fig. 2, its Main Differences is that employing or door X1 ' and NAND gate X8 instead of NOR gate X1, thus can introduce asserts signal NSET from an input of NAND gate X8, can realize asynchronous set function like this.When asserts signal NSET is low level (NSET=0), node N1 is thus lifted to high level by NAND gate X8, and then node N3 is reduced to low level by NOR gate X3, and by the effect of not gate X6, output signal Q is set to high level.When asserts signal NSET is high level (NSET=1), the effect of NAND gate X8 develops into and outputs to node N1 by anti-phase for signal S8, itself and or door X1 ' combine formation NOR-logic, make its working method consistent with NOR gate X1 in flip-flop circuit 20, thus now the working method of flip-flop circuit 41 and the working method of trigger 20 basically identical.

Figure 10 shows that the electrical block diagram of the wherein embodiment realizing flip-flop circuit shown in Fig. 9.With reference to Figure 10, flip-flop circuit 44 i.e. the corresponding function realizing flip-flop circuit 40, divide by function, flip-flop circuit 44 is mainly divided three modules, i.e. the first gate 241 (identical with first gate 241 of Fig. 4), the second gate 442 and the 3rd gate 243 (identical with the 3rd gate 243 of Fig. 4).Be to add PMOS transistor MP8 and nmos pass transistor MN8 compared to the main improvement of the second gate 242, second gate 442 of Fig. 2 institute embodiment.One end of transistor MP8 is connected to node S1, other end access power vd D, and like this, transistor MP8 and transistor MP3 and MP4 connected are in parallel between node N1 and power vd D.Transistor MN8 and MN4 coupled in series are between node N1 and ground, and transistor MN8 and MN3 coupled in series are between node N1 and ground simultaneously, and like this, transistor MN3 and MN4 is arranged in parallel.The grid access asserts signal NSET of transistor MP8 and MN8.

When asserts signal NSET is high level, transistor MP8 ends, and transistor MN8 conducting, its working method is identical with the corresponding working method described of Fig. 5 with Fig. 6 like this; When asserts signal NSET is low level, transistor MP8 conducting, transistor MN8 cut-off simultaneously, node N1 is set to high level, and then, transistor MN7 conducting, node N3 is set to low level, finally, by not gate X5 and X6, output signal Q is set to high level (Q=1), achieves the set operation to flip-flop circuit 44.It should be noted that because of transistor MP8 conducting and MN8 cut-off, no matter which kind of state clock signal C KN is in, and the state of node N1 all can not be subject to the impact of previous stage input signal S2.

Be the gate level circuit figure of the flip-flop circuit according to fourth embodiment of the invention described in Figure 11.

Before flip-flop circuit 50 embodiment illustrated in fig. 11 is described, first get back to embodiment illustrated in fig. 2 in, when former and later two states of the data-signal D inputted are high level entirely, flip-flop circuit 20 can consume extra dynamic power consumption.Such as, when CKN is high level, NOR gate X1 can move node N1 to low level.Meanwhile, because input signal D=1, node N0 is set to high level, so node N2 discharges into low level.So when CKN jumps to low level from high level, node N1 is brought up to high level from low level by NOR gate X1.But output signal Q does not have change state and remains high level.So when the state of existing Q state and next data-signal D is all 1, node N1 may do useless upset between logical zero and 1, and this can consume extra power consumption.

In order to avoid above-mentioned this extra power consumption, the feedback signal FB be similar in Figure 11 can be produced.In this embodiment, the gate leve figure of flip-flop circuit 50 as shown in figure 11.It comprises the first latch 51 and the second latch 22 (identical with the second latch 22 in Fig. 2), also comprises a NAND gate X10.NAND gate X10 gives the first latch 51 for generation of a feedback signal FB.First latch 51 comprises all parts of the first latch 21 in Fig. 2, adds additional one and door X9.Clock signal C KN is couple to and door X9 input, receives with another input of door X9 the feedback signal FB that NAND gate X10 exports, and is coupled to the input of NOR gate X1 with the output defined node N9 of door X9.NAND gate X10 comprises an input of reception data-signal D, another input of reception output signal Q and provides the output of feedback signal FB.

As mentioned above, when the data-signal D outputing signal Q and next input is all high level (Q=D=1), flip-flop circuit 20 can consume extra power consumption, and flip-flop circuit 50 can eliminate this extra power consumption.As shown in figure 11, as Q=D=1, feedback signal FB is set to logical zero (FB=0) by NAND gate X10, no matter which kind of state clock signal C KN is in, all it can be pulled down to low level at the output signal S9 of node N9 with door X9.In this case, because signal S9 is in low level (because D=Q=1), so the value that NOR gate X1 will store at node N2 anti-phase output, so be set to high level at the signal S1 of node N1 always, avoids node N1 may do useless upset between logical zero and 1.Therefore, flip-flop circuit 50 embodiment illustrated in fig. 11 can reduce its power consumption further.

For data-signal D and output signal Q (when Q and D is not high level entirely) of other situations, NAND gate X10 all exports high level to feedback signal FB (i.e. FB=1), thus the value of clock signal C KN can be sent to NOR gate X1 with door X9, now, first latch 51 working method is consistent with the working method of the latch of first in Fig. 2 21, and whole trigger 50 operation principle is in the case identical with the operation principle of the trigger 20 of Fig. 2.

Figure 12 shows that the electrical block diagram of the wherein embodiment realizing flip-flop circuit shown in Figure 11.As shown in figure 12, trigger 54 circuit comprises the first gate 241 (identical with the first gate 241 in Fig. 4), the second gate 542 and the 3rd gate 243 (identical with the 3rd gate 243 in Fig. 4), and comprising NAND gate X10, NAND gate X10 can realize in various custom circuit mode.Relative to flip-flop circuit 24 embodiment illustrated in fig. 4, it mainly improves and is the second gate 542, therefore, mainly introduces the second gate 542 below.

Second gate 542 comprises nmos pass transistor MN3, MN4 and MN9, and PMOS transistor MP3, MP4 and MP9.Transistor MN3 and MN9 coupled in series are between node N1 and ground, and transistor MN4 is also coupled between node N1 and ground simultaneously.The grid receive clock signal CKN of transistor MN3, the grid of transistor MN4 is coupled to node N2, and the grid of MN9 receives the feedback signal FB that NAND gate X10 exports.Transistor MP3 and MP4 coupled in series are between node N1 and power vd D, and transistor MP9 and MP4 coupled in series are between node N1 and power vd D, and like this, transistor MP9 is then in parallel with transistor MP3.The grid receive clock signal CKN of transistor MP3, the grid of transistor MP4 is coupled to node N2, and the grid of MP9 receives the feedback signal FB of NAND gate X10 output.It is noted that gate 542 (i.e. transistor MN3, MN4, MN9 and MP3, MP4, MP9) logic function in Figure 12 constitutes in Figure 11 with the combination of door X9 and NOR gate X1.Compared to flip-flop circuit embodiment illustrated in fig. 4, mainly add and the transistor MP9 of transistor MP3 parallel connection and the transistor MN9 that connects with transistor MN3.

In conjunction with data-signal D and the output signal Q of different input, an example working method of the flip-flop circuit 54 in Figure 12 is below described.

The first situation is that the state of next data-signal D is logical zero and the state of current Q is logical one (i.e. D=0 and Q=1).Due to D=0 and Q=1, feedback signal FB is set to high level by NAND gate X10, so transistor MN9 conducting and transistor MP9 ends, the equivalent circuit diagram that Figure 12 is now corresponding is identical with Fig. 4, and the working method of the second gate 542 is also identical with the working method of the second gate 242 in Fig. 4.Now the course of work of trigger is with reference to declaratives corresponding to figure 5 and Fig. 6.

Second case is that the state of next data-signal D is logical one and the state of current Q is logical zero (i.e. D=1, Q=0).Due to D=1 and Q=0, feedback signal FB is set to high level by NAND gate X10, so transistor MN9 conducting and MP9 transistor cutoff, the equivalent circuit diagram that Figure 12 is now corresponding is identical with Fig. 4, and the working method of the second gate 542 is also identical with the working method of the second gate 242 in Fig. 4.Now the course of work of trigger is with reference to declaratives corresponding to figure 5 and Fig. 6.

The third situation is that the state of next data-signal D is logical one and the state of current output signal Q is also logical one (i.e. D=1 and Q=1).Due to D=1 and Q=1, feedback signal FB is set to low level by NAND gate X10, so transistor MP9 conducting, transistor MN9 end.So as clock signal CKN=1, node N2 is reduced to low level by transistor MN1 and MN2 of conducting; The inverter (now transistor MP9, MP4, MN4 is sequentially connected in series) that low level signal S2 is consisted of transistor MN4 and MP4 is anti-phase, the signal S1 at node N1 place is set to high level, i.e. S1=1; And then transistor MN0 and MN7 conducting, transistor MP0 and MP7 cut-off simultaneously.Due to Q=1, S1=1, CKN=1, transistor MN5-MN7 conducting, transistor MP5-MP7 end, so node N3 is set to low level, and then by non-X6, the high level state of Q are maintained.Like this, the first gate 241 collects data D=1, and the 3rd gate 243 also remain original data Q=1.

Now, when clock signal CKN jumps to low level from high level, CKN=0, transistor MP2, MP3 and MP5 conducting.By transistor MP3, MP4 and MP9 of conducting, remain high level at the signal S1 of node N1, thus transistor MN0 keeps conducting, causes remaining on low level at the signal S2 at node N2 place and (namely latched state ).Because the signal S1 at node N1 place is in high level, transistor MN7 conducting and MP7 cut-off, so by the MN7 of conducting, node N3 remains low level, and then by not gate X6, the state of Q is remained 1, i.e. Q=1.

Therefore, in a third situation, no matter how CKN changes, by transistor MP4 and MP9 of conducting, node N1 remains on high level; And by the MN0 of conducting, node N2 remains on low level, middle node does not have extra energy ezpenditure, thus reduces dynamic power consumption.

4th kind of situation is that the state of next data-signal D is logical zero and the state of current output signal Q is also logical zero (i.e. D=0 and Q=0).Due to D=0 and Q=0, feedback signal FB is set to high level by NAND gate X10, so MN9 conducting and MP9 cut-off, the equivalent circuit diagram that Figure 12 is now corresponding is identical with Fig. 4, and the working method of the second gate 542 is also identical with the working method of the second gate 242 in Fig. 4.Now the course of work of trigger is with reference to declaratives corresponding to figure 5 and Fig. 6.

It will be appreciated that, those skilled in the art can according to the above flip-flop circuit disclosing multiple embodiment, simply combine, improve obtain other situations embodiment (such as, similar for selector 100 embodiment illustrated in fig. 7 joining in flip-flop circuit embodiment illustrated in fig. 9 is formed new flip-flop circuit to improve), this all should be encompassed in the scope of claim of the application.

In the above description, current invention obtains description by some specific embodiments.In addition, this invention also has some other change, it is apparent that these changes are also included within right expression scope of the present invention.These concrete words and chart describe just in order to explain the implementation method of invention instead of limit the interest field of invention.

Be to be understood that, the flip-flop circuit of above embodiment can be applied in various chip circuit, and such as, SOC, is particularly useful for an urgent demand and reduces in the chip of its dynamic power consumption.But the embody rule of the flip-flop circuit of the embodiment of the present invention is not restrictive.

To understand, when it is said parts " connection ", " coupling " or " coupling " to another parts, it can directly connect or be coupled to another parts maybe can exist intermediate member.On the contrary, when it is said parts " direct-coupling ", " directly coupling " or " directly connect " to another parts, then there is not intermediate member.

Above embodiment mainly describes flip-flop circuit of the present invention.Although be only described some of them embodiments of the present invention, those of ordinary skill in the art should understand, and the present invention can implement with other forms many not departing from its purport and scope.Therefore, the example shown and execution mode are regarded as illustrative and not restrictive, when do not depart from as appended each claim define the present invention spirit and scope, the present invention may contain various amendments and replacement.

Claims

1. a flip-flop circuit, comprises as the first latch of main latch with as the second latch from latch; It is characterized in that, under described first latch and the second latch are operated in the clock signal of same phase;

Wherein, described first logic module be used for selectively to major general input data-signal and described clock signal carry out "AND" logical process,

Described second logic module is used for carrying out nondisjunction logical process to the output signal of clock signal described in major general and described 3rd logic module,

Described 3rd logic module is used for selectively carrying out nondisjunction logical process to export described second logic module to the output signal of the first logic module described in major general and the output signal of described second logic module;

Described second latch comprises the 4th logic module and the 5th logic module;

Wherein, described 4th logic module is used for carrying out nondisjunction logical process to the output signal of the second logic module described in major general and the output signal of described 5th logic module,

Described 5th logic module carries out "AND" logical process for the inversion signal of the output signal to clock signal described in major general and described 4th logic module.

2. flip-flop circuit as claimed in claim 1, it is characterized in that, described second latch also comprises: for the output signal of described 4th logic module being carried out the 6th logic module of anti-phase process.

3. flip-flop circuit as claimed in claim 2, it is characterized in that, described 6th logic module comprises two the first not gates and the second not gate that are arranged in parallel, the output of described first not gate generates the described inversion signal being used for described second latch inside, and the output of described second not gate generates the output signal of described flip-flop circuit.

4. the flip-flop circuit as described in claim 1 or 2 or 3, is characterized in that, described first logic module is first and door, and described second logic module is the first NOR gate, and described 3rd logic module is the second NOR gate.

5. flip-flop circuit as claimed in claim 4, is characterized in that, described first with door comprise at least for receive described data-signal first input end, for receive clock signal the second input and output to the output of first node;

Described first NOR gate and the second NOR gate comprise the output outputting to Section Point and the 3rd node respectively, the first input end of described first NOR gate receives described clock signal, second input of described first NOR gate is coupled to described 3rd node, and first input end and second input of described second NOR gate are respectively coupled to described first node and Section Point.

6. flip-flop circuit as claimed in claim 5, is characterized in that,

When clock signal is in high level, its rp state is also kept at the 3rd node by the first latch image data signal, and the second latch then latched the preceding state of the output signal of this flip-flop circuit;

When clock signal is in low level, data-signal is transferred to the second latch by Section Point by the first latch, and output signal is set to the state of current data-signal by the second latch.

7. flip-flop circuit as claimed in claim 1, it is characterized in that, the first logic module of described first latch, the second logic module and the 3rd logic module at least by first with-or-NOT logic door and with this first with-or first or-NOT logic door that-NOT logic door is connected realize;

4th logic module of described second latch and the 5th logic module are realized by second and-NOT logic door.

8. flip-flop circuit as claimed in claim 7, it is characterized in that, described first and-NOT logic door comprise the first nmos pass transistor, the second nmos pass transistor, the 3rd nmos pass transistor and the first PMOS transistor, the second PMOS transistor, the 3rd PMOS transistor;

Wherein, the grid of described first PMOS transistor is defined as Section Point, the drain electrode of described first PMOS transistor is defined as the 3rd node, described second PMOS transistor and the 3rd PMOS transistor are coupled between the source electrode of power supply and the first PMOS transistor in parallel, the grid of described second PMOS transistor accesses described data-signal, and the grid of described 3rd PMOS transistor accesses described clock signal;

Wherein, described first nmos pass transistor is coupled to the 3rd between node and ground, the grid of described first nmos pass transistor is coupled to described Section Point, described second nmos pass transistor and the 3rd nmos pass transistor are in series coupled to the 3rd between node and ground, the grid of described second nmos pass transistor accesses described data-signal, and the grid of described 3rd nmos pass transistor accesses described clock signal;

Described first or-NOT logic door comprise the 4th nmos pass transistor, the 5th nmos pass transistor and the 4th PMOS transistor, the 5th PMOS transistor;

Wherein, described 4th PMOS transistor and the 5th PMOS transistor are in series coupled between power supply and described Section Point, and the grid of described 4th PMOS transistor accesses described clock signal, and the grid of described 5th PMOS transistor is coupled to described 3rd node; Described 4th nmos pass transistor and the 5th nmos pass transistor are coupled between described Section Point and ground in parallel, and the grid of described 4th nmos pass transistor receives described clock signal, and the grid of described 5th nmos pass transistor is coupled to described 3rd node.

9. flip-flop circuit as claimed in claim 8, it is characterized in that, described second and-NOT logic door comprise the 6th nmos pass transistor, the 7th nmos pass transistor, the 8th nmos pass transistor and the 6th PMOS transistor, the 7th PMOS transistor, the 8th PMOS transistor;

Wherein, the drain electrode of described 8th PMOS transistor is defined as the 4th node, and grid and the described Section Point of described 8th PMOS transistor couple; Described 6th PMOS transistor and the 7th PMOS transistor are coupled between the source electrode of power supply and the 8th PMOS transistor in parallel, the grid access output signal of described 7th PMOS transistor, and the grid of described 6th PMOS transistor accesses described clock signal;

Described 8th nmos pass transistor is coupled to the 4th between node and ground, the grid of described 8th nmos pass transistor is coupled to described Section Point, described 6th nmos pass transistor and the 7th nmos pass transistor are in series coupled to the 4th between node and ground, the grid of described 7th nmos pass transistor accesses described data-signal, and the grid of described 6th nmos pass transistor accesses described clock signal.

10. flip-flop circuit as claimed in claim 7, it is characterized in that, described second latch also comprises two the first not gates and the second not gate that are arranged in parallel.

11. flip-flop circuits as described in claim 7 or 8 or 9 or 10, is characterized in that, first and-NOT logic door be with selection function with-or-NOT logic door.

12. flip-flop circuits as described in claim 1 or 2 or 3, it is characterized in that, described flip-flop circuit is the sweep type flip-flop circuit comprising selector, described selector by select signal controlling with optionally export the data-signal of its access and sweep signal one of them to described first logic module;

When described selector exports described data-signal, described first logic module is used for the data-signal of input and described clock signal to carry out "AND" logical process;

When described selector exports described sweep signal, described first logic module is used for the sweep signal of input and described clock signal to carry out "AND" logical process.

13. flip-flop circuits as described in claim 1 or 2 or 3, it is characterized in that, described first logic module is first and door, described 3rd logic module is the second NOR gate, first or door and the first NAND gate form described second logic module, to make described flip-flop circuit, there is asynchronous set function.

14. flip-flop circuits as claimed in claim 13, is characterized in that, described first with door comprise at least for receive described data-signal first input end, for receive clock signal the second input and output to the output of first node;

Described first NAND gate and the second NOR gate comprise the output outputting to Section Point and the 3rd node respectively, described first or the first input end of door receive described clock signal, described first or the second input of door be coupled to described 3rd node, described first or the output of door be coupled to the first input end of described first NAND gate, second input of described first NAND gate receives asserts signal, and first input end and second input of described second NOR gate are respectively coupled to described first node and Section Point.

15. flip-flop circuits as described in claim 1 or 2 or 3, it is characterized in that, described flip-flop circuit also comprises the second NAND gate, and described second NAND gate is used for the output signal of described flip-flop circuit and described data-signal being carried out NAND logical process with output feedback signal to described first latch;

Described first latch also comprises the 7th logic module, and it is for carrying out "AND" logical process to export described second logic module to by described feedback signal and clock signal.

16. flip-flop circuits as claimed in claim 15, it is characterized in that, when the output signal of data-signal and flip-flop circuit is high level, described second NAND gate exports as low level feedback signal, makes described first latch ignore the upset of described clock signal and keep the constant of the data mode of internal node.

17. flip-flop circuits as claimed in claim 15, it is characterized in that, when the output signal of data-signal and flip-flop circuit is not all high level, described second NAND gate exports the feedback signal for high level, and described 7th logic module exports described clock signal, to make described second logic module, the output signal of this clock signal and described 3rd logic module carried out nondisjunction logical process.

18. flip-flop circuits as claimed in claim 15, it is characterized in that, first logic module of described first latch and the 3rd logic module are realized by first and-NOT logic door, and the second logic module of described first latch and the 7th logic module are realized by the 3rd and-NOT logic door;

19. flip-flop circuits as claimed in claim 18, it is characterized in that, described first and-NOT logic door comprise the first nmos pass transistor, the second nmos pass transistor, the 3rd nmos pass transistor and the first PMOS transistor, the second PMOS transistor, the 3rd PMOS transistor;

Described 3rd and-NOT logic door comprise the 4th nmos pass transistor, the 5th nmos pass transistor, the 9th nmos pass transistor and the 4th PMOS transistor, the 5th PMOS transistor, the 9th PMOS transistor;

Wherein, the grid of described 5th PMOS transistor is coupled to described 3rd node, the drain electrode of described 5th PMOS transistor is coupled to described Section Point, described 4th PMOS transistor and described 9th PMOS transistor are coupled between the source electrode of power supply and the 5th PMOS transistor in parallel, the grid of described 4th PMOS transistor accesses described clock signal, and the grid of described 9th PMOS transistor accesses described feedback signal;

Wherein, described 5th nmos pass transistor is coupled between described Section Point and ground, the grid of described 5th nmos pass transistor couples and described 3rd node, described 4th nmos pass transistor and described 9th nmos pass transistor are in series coupled between Section Point and ground, the grid of described 4th nmos pass transistor accesses described clock signal, and the grid of described 9th nmos pass transistor accesses described feedback signal.

20. flip-flop circuits as claimed in claim 19, it is characterized in that, described second and-NOT logic door comprise the 6th nmos pass transistor, the 7th nmos pass transistor, the 8th nmos pass transistor and the 6th PMOS transistor, the 7th PMOS transistor, the 8th PMOS transistor;