CN113472323B - D trigger circuit with strong latch structure - Google Patents
D trigger circuit with strong latch structure Download PDFInfo
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- CN113472323B CN113472323B CN202110921437.9A CN202110921437A CN113472323B CN 113472323 B CN113472323 B CN 113472323B CN 202110921437 A CN202110921437 A CN 202110921437A CN 113472323 B CN113472323 B CN 113472323B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3562—Bistable circuits of the master-slave type
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- H—ELECTRICITY
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- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
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Abstract
The invention discloses a D trigger circuit with a strong latch structure, which comprises four logic input inverters, a strong latch circuit and two transmission gates which are sequentially connected, wherein the strong latch circuit comprises two NMOS transistors and four PMOS transistors, the transistors on the left side are sequentially connected in series, the transistors on the right side are also sequentially connected in series, and the two sides form the strong latch structure; the grid electrode of the PMOS transistor PM6 is connected with the Q node, and the grid electrode of the PMOS transistor PM8 is connected with the Q non-node to form a negative feedback loop; the strong latch circuit receives square wave signals fed by four logic input inverters and is stored in Q and Q NOT nodes, and each conversion can reduce the current of the left side or the right side from VDD to GND, so that dynamic leakage is greatly reduced. The circuit solves the problems of leakage power consumption and large short circuit power consumption in the signal overturning process of the traditional latch, and reduces the power consumption of the whole chip design.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a D trigger circuit with a strong latch structure.
Background
D flip-flops are very widely used in very large scale integration (Very Large Scale Integration, VLSI) circuits, and improving the performance of D flip-flops is one of the most important tasks to enhance the performance of the entire VLSI circuit. As an important application field of the emerging information industry, the trillion-level market of the internet of things is gradually formed, and the equipment and the nodes of the trillion-level are realized through the internet of things technology. Limited by factors such as volume, weight and cost, the internet of things node (such as wearable equipment, intelligent home node, wireless sensor node, environment monitoring node and the like) needs to continuously work for several years or even more than ten years under the condition that a miniature battery is used for supplying power, so that a severe low-power consumption requirement is provided for a chip, a D trigger is a very important part in chip design, and therefore the D trigger for realizing ultra-low power consumption and quick response has very important significance for reducing power consumption of the whole chip design.
The conventional D flip-flop topology consists of an input inverter, two half-latches (master latch and slave latch), and an output inverter. Since there is a strong competing current between the pull-up and pull-down networks with complementary half-latch structures, especially when VDDL is in the subthreshold region, papers and experiments currently show that converting a signal from a subthreshold voltage to a voltage higher than the threshold voltage requires the size of the two NMOS transistors to be amplified by several orders of magnitude to overcome the strength of the pull-up network, resulting in additional consumption of area, which is not practical and acceptable; meanwhile, because the D flip-flop is a half latch, in the transition process, PMOS and NMOS are conducted simultaneously, so that the dynamic power consumption is increased, and the speed of the D flip-flop is also reduced due to the two half latches, so that the extra consumption of the area is also caused.
Disclosure of Invention
The invention aims to provide a D trigger circuit with a strong latch structure, which latches the circuit by adopting a dynamic leakage suppression (DLS, dynamic Leakage Suppression) strong latch structure, so that the area consumption and the power consumption of each conversion are reduced, the response speed is improved, and the power consumption of the whole chip design is reduced.
The invention aims at realizing the following technical scheme:
a D flip-flop circuit of a strong latch structure, the circuit comprising four logic input inverters, a strong latch circuit, two transmission gates connected in sequence, wherein:
the first logic input inverter is composed of an NMOS transistor NM0 and a PMOS transistor PM 0; the source of the PMOS transistor PM0 is connected to the power supply VDD, the source of the NMOS transistor NM0 is connected to the ground GND, the drain of the PMOS transistor PM0 is connected to the drain of the NMOS transistor NM0 as an output signal, and the gate of the PMOS transistor PM0 is connected to the gate of the NMOS transistor NM0 as an input signal;
the second logic input inverter is composed of an NMOS transistor NM1 and a PMOS transistor PM 1; the source of the PMOS transistor PM1 is connected with a power supply VDD, the source of the NMOS transistor NM1 is connected with GND, the drain of the PMOS transistor PM1 is connected with the drain of the NMOS transistor NM1 to serve as an output signal, and the grid of the PMOS transistor PM1 is connected with the grid of the NMOS transistor NM1 to serve as an input signal;
the third logic input inverter is composed of an NMOS transistor NM4 and a PMOS transistor PM 4; the source of the PMOS transistor PM4 is connected to the power supply VDD, the source of the NMOS transistor NM4 is connected to GND, the drain of the PMOS transistor PM4 is connected to the drain of the NMOS transistor NM4 as an output signal, and the gate of the PMOS transistor PM4 is connected to the gate of the NMOS transistor NM4 as an input signal;
the fourth logic input inverter is composed of an NMOS transistor NM5 and a PMOS transistor PM 5; the source of the PMOS transistor PM5 is connected with the power supply VDD, the source of the NMOS transistor NM5 is connected with GND, the drain of the PMOS transistor PM5 is connected with the drain of the NMOS transistor NM5 to serve as an output signal, and the grid of the PMOS transistor PM5 is connected with the grid of the NMOS transistor NM5 to serve as an input signal;
the four logic input inverters are all PMOS drain electrodes and NMOS drain electrodes connected;
the strong latch circuit includes two NMOS transistors NM6 and NM7, four PMOS transistors PM6, PM8, PM7, and PM9, wherein:
PM7, PM6 and NM6 of the left part are sequentially connected in series, PM9, PM8 and NM7 of the right part are also sequentially connected in series, the two side parts form a strong latch structure, only one tube is conducted each time the NMOS transistor NM6 and the PMOS transistor PM7 of the left part are changed, and only one tube is conducted each time the NMOS transistor NM7 and the PMOS transistor PM9 of the right part are changed;
the grid electrode of the PMOS transistor PM6 is connected with the Q node, and the grid electrode of the PMOS transistor PM8 is connected with the Q non-node to form a negative feedback loop;
the strong latch circuit receives square wave signals fed by four logic input inverters and stores the square wave signals in Q and Q non-nodes, and the transistors are utilized to be turned off in the conversion process, so that the current of the left side or the right side part can be reduced from VDD to flow into GND in each conversion, thereby greatly reducing dynamic leakage and reducing power consumption;
the first transmission gate is composed of a PMOS transistor PM2 and an NMOS transistor NM2 and is positioned between the first logic input inverter and the third logic input inverter, and is used as a control signal of a clock CLK, when CLK is always high level, the first transmission gate enables the high level of the first logic input inverter to be input into the third logic input inverter, and when CLK is low level, the first transmission gate is closed and does not enable the signal transmission between the first logic input inverter and the third logic input inverter;
the second transmission gate is composed of a PMOS transistor PM3 and an NMOS transistor NM3, and is located between the second logic input inverter and the fourth logic input inverter, and is used as a control signal of the clock CLK, when CLK is always at a high level, the second transmission gate allows the high level of the second logic input inverter to be input to the fourth logic input inverter, and when CLK is at a low level, the second transmission gate is turned off and does not allow signal transmission between the second logic input inverter and the fourth logic input inverter.
According to the technical scheme provided by the invention, the problem that the traditional latch is large in leakage power consumption and short circuit power consumption in the signal overturning process is solved, the dynamic leakage inhibition strong latch structure is adopted to latch the circuit, the area consumption and the power consumption of each conversion are reduced, the response speed is improved, and the power consumption of the whole chip design is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a D flip-flop circuit with a strong latch structure according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a D flip-flop control circuit according to the prior art;
FIG. 3 is a schematic diagram of a D flip-flop and a prior art D flip-flop control circuit according to an embodiment of the present invention when the input signals D and CLK are changed simultaneously;
fig. 4 is a diagram showing simulation of the D flip-flop and the prior art D flip-flop control circuit according to the embodiment of the present invention when the input signals D and CLK are not changed.
Detailed Description
The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments of the present invention, and this is not limiting to the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
Fig. 1 is a schematic diagram of a D flip-flop circuit with a strong latch structure according to an embodiment of the present invention, where the circuit includes four logic input inverters, a strong latch circuit, and two transmission gates connected in sequence, where:
the first logic input inverter is composed of an NMOS transistor NM0 and a PMOS transistor PM 0; the source of the PMOS transistor PM0 is connected to the power supply VDD, the source of the NMOS transistor NM0 is connected to the ground GND, the drain of the PMOS transistor PM0 is connected to the drain of the NMOS transistor NM0 as an output signal, and the gate of the PMOS transistor PM0 is connected to the gate of the NMOS transistor NM0 as an input signal;
the second logic input inverter is composed of an NMOS transistor NM1 and a PMOS transistor PM 1; the source of the PMOS transistor PM1 is connected with a power supply VDD, the source of the NMOS transistor NM1 is connected with GND, the drain of the PMOS transistor PM1 is connected with the drain of the NMOS transistor NM1 to serve as an output signal, and the grid of the PMOS transistor PM1 is connected with the grid of the NMOS transistor NM1 to serve as an input signal;
the third logic input inverter is composed of an NMOS transistor NM4 and a PMOS transistor PM 4; the source of the PMOS transistor PM4 is connected to the power supply VDD, the source of the NMOS transistor NM4 is connected to GND, the drain of the PMOS transistor PM4 is connected to the drain of the NMOS transistor NM4 as an output signal, and the gate of the PMOS transistor PM4 is connected to the gate of the NMOS transistor NM4 as an input signal;
the fourth logic input inverter is composed of an NMOS transistor NM5 and a PMOS transistor PM 5; the source of the PMOS transistor PM5 is connected with the power supply VDD, the source of the NMOS transistor NM5 is connected with GND, the drain of the PMOS transistor PM5 is connected with the drain of the NMOS transistor NM5 to serve as an output signal, and the grid of the PMOS transistor PM5 is connected with the grid of the NMOS transistor NM5 to serve as an input signal;
the four logic input inverters are all PMOS drain electrodes and NMOS drain electrodes connected;
the strong latch circuit includes two NMOS transistors NM6 and NM7, four PMOS transistors PM6, PM8, PM7, and PM9, wherein:
PM7, PM6 and NM6 of the left part are sequentially connected in series, PM9, PM8 and NM7 of the right part are also sequentially connected in series, the two side parts form a strong latch structure, only one tube is conducted each time the NMOS transistor NM6 and the PMOS transistor PM7 of the left part are changed, and only one tube is conducted each time the NMOS transistor NM7 and the PMOS transistor PM9 of the right part are changed;
the grid electrode of the PMOS transistor PM6 is connected with the Q node, and the grid electrode of the PMOS transistor PM8 is connected with the Q non-node to form a negative feedback loop;
the strong latch circuit receives square wave signals fed by four logic input inverters and stores the square wave signals in Q and Q non-nodes, and the transistors are utilized to be turned off in the conversion process, so that the current of the left side or the right side part can be reduced from VDD to flow into GND in each conversion, thereby greatly reducing dynamic leakage and reducing power consumption;
the first transmission gate is composed of a PMOS transistor PM2 and an NMOS transistor NM2 and is positioned between the first logic input inverter and the third logic input inverter, and is used as a control signal of a clock CLK, when CLK is always high level, the first transmission gate enables the high level of the first logic input inverter to be input into the third logic input inverter, and when CLK is low level, the first transmission gate is closed and does not enable the signal transmission between the first logic input inverter and the third logic input inverter;
the second transmission gate is composed of a PMOS transistor PM3 and an NMOS transistor NM3, and is located between the second logic input inverter and the fourth logic input inverter, and is used as a control signal of the clock CLK, when CLK is always at a high level, the second transmission gate allows the high level of the second logic input inverter to be input to the fourth logic input inverter, and when CLK is at a low level, the second transmission gate is turned off and does not allow signal transmission between the second logic input inverter and the fourth logic input inverter.
In a specific implementation, referring to fig. 1, the connection relationship inside the strong latch circuit is specifically:
the source electrode of the PMOS transistor PM7 is connected with the power supply VDD, and the drain electrode of the PMOS transistor PM7 is connected with the source electrode of the PMOS transistor PM 6;
the drain of the PMOS transistor PM6 is connected to the drain of the NMOS transistor NM6, the source of the NMOS transistor NM6 is connected to GND, and the gate of the NMOS transistor NM6 and the gate of the PMOS transistor PM7 are connected to each other as an input port of the third logic input inverter output;
the drain of the PMOS transistor PM8 and the drain of the NMOS transistor NM7 are connected to the Q point, and the gate of the PMOS transistor PM6 is connected to the Q point;
the substrate of the NMOS transistor NM6 is connected with GND, the substrate of the PMOS transistor PM7 is connected with the power supply VDD, and the substrate of the PMOS transistor PM6 is connected with the power supply VDD;
the source electrode of the PMOS transistor PM9 is connected with the power supply VDD, and the drain electrode of the PMOS transistor PM9 is connected with the source electrode of the PMOS transistor PM 8;
the drain of the PMOS transistor PM8 is connected to the drain of the NMOS transistor NM7, the source of the NMOS transistor NM7 is connected to GND, and the gate of the NMOS transistor NM7 and the gate of the PMOS transistor PM9 are connected to each other as an input port of the output of the fourth logic input inverter;
the drain of the PMOS transistor PM6 and the drain of the NMOS transistor NM6 are connected to Q non-point, and the gate of the PMOS transistor PM8 is connected to Q non-point;
the substrate of the NMOS transistor NM7 is connected to GND, the substrate of the PMOS transistor PM8 is connected to the power supply VDD, and the substrate of the PMOS transistor PM8 is connected to the power supply VDD.
Referring to fig. 1, the connection relationship between the components of the first transmission gate is specifically:
the substrate of the NMOS transistor NM2 is connected with GND, and the substrate of the PMOS transistor PM2 is connected with a power supply VDD;
the drain of the NMOS transistor NM2 is connected to the drain of the PMOS transistor PM2 as an input, while being connected to the output of the first logic input inverter;
the source of the NMOS transistor NM2 is connected to the source of the PMOS transistor PM2 as an output, while being connected to the input of the third logic input inverter;
the gate of the PMOS transistor PM2 is connected to the output of the second logic input inverter;
the gate of the NMOS transistor NM2 is connected to the clock CLK.
Referring to fig. 1, the connection relationship between the components of the second transmission gate is specifically:
the substrate of the NMOS transistor NM3 is connected with GND, and the substrate of the PMOS transistor PM3 is connected with a power supply VDD;
the drain of the NMOS transistor NM3 is connected to the drain of the PMOS transistor PM3 as an input, and is connected to a D input signal (i.e., a square wave signal input from the outside);
the source of the NMOS transistor NM3 is connected to the source of the PMOS transistor PM3 as an output, while being connected to the input of the fourth logic input inverter;
the gate of the PMOS transistor PM3 is connected to the output of the second logic input inverter;
the gate of the NMOS transistor NM3 is connected to the clock CLK.
Based on the D trigger circuit structure, the circuit principle is specifically as follows:
the first logic input inverter has inputs connected to the gates of PM0 and NM0 and outputs connected to the drains of PM0 and NM0 such that the D signal input produces a D non-signal output. The second logic input inverter has inputs connected to the gates of PM1 and NM1 and outputs connected to the drains of PM1 and NM1, such that the CLK signal input produces a CLK non-signal output. The first transmission gate D is not input to the junction of the drain of the PMOS transistor PM2 and the drain of the NMOS transistor NM2, the source of the PMOS transistor PM2 is connected to the source of the NMOS transistor NM2 as an output, the CLK is not input to the gate of the PMOS transistor PM2, the CLK is input to the gate of the NMOS transistor NM2, the input of the third logic input inverter is pulled down if D is not at a low level by the control of the transmission of the CLK signal, and the input of the third logic input inverter is pulled up if D is not at a high level. The second transmission gate D signal is input to the junction of the drain of the PMOS transistor PM3 and the drain of the NMOS transistor NM3, the source of the PMOS transistor PM3 is connected to the source of the NMOS transistor NM3 as an output, the CLK signal is input to the gate of the PMOS transistor PM3, the CLK signal is input to the gate of the NMOS transistor NM3, the input of the fourth logic input inverter is pulled down if D is low, and the input of the fourth logic input inverter is pulled up if D is high by the transmission of the control D signal of the CLK signal.
The third logic input inverter is a D non-signal input connected to the gates of the PMOS transistor PM4 and the NMOS transistor NM4, the connection of the drain of the PMOS transistor PM4 and the drain of the NMOS transistor NM4 being an output port IN, connected to the strong latch circuit; the third logic input inverter is mainly aimed at increasing the drive. The fourth logic input inverter is that a D signal input is connected to the gate of the PMOS transistor PM5 and the gate of the NMOS transistor NM5, the connection of the drain of the PMOS transistor PM5 and the drain of the NMOS transistor NM5 is used as an output port INB, and is connected to a strong latch circuit, and the fourth logic input inverter is mainly aimed at increasing driving.
The principle of the strong latch circuit described above is as follows:
when the input signal IN is low and INB is high, NM6 is IN an off state, PM7 is IN an on state, NM7 is IN an on state, the voltage at Q is pulled down, PM9 is IN an off state, since the voltage at Q is pulled down to cause PM6 to become IN an on state, and the voltage at Q is not pulled up to cause PM8 to be IN an off state;
when the input signal IN is at a high level and the input signal INB is at a low level, the NM7 is IN an off state, the PM9 is IN an on state, the NM6 is IN an on state, the PM7 is IN an off state, and the voltage at the Q non-place is pulled down, so that the PM8 is IN an on state, and the voltage at the Q place is pulled up;
when the input signal IN is high and INB is high, NM6 is on, PM7 is off, NM7 is on, PM9 is off, and both Q and Q are pulled low, which is a clear state.
When the input signal IN is low and INB is low, the NM6 is IN an off state, the PM7 is IN an on state, the NM7 is IN an off state, the PM9 is IN an on state, if Q is high, Q is not low, the PM8 is IN an on state, the PM6 is IN an off state, Q is high, Q is not low, if Q is low, Q is not high, the PM8 is IN an off state, the PM6 is IN an on state, Q is low, and Q is not high, which is a hold state.
Fig. 2 is a schematic diagram of a comparison circuit of a D flip-flop according to the prior art, wherein the comparison circuit is a DFF flip-flop formed by an RS flip-flop, and is configured to determine whether R and S are high or low by conducting a power supply VDD to a ground GND through a CLK clock, and then control and adjust RB and SB signals by externally inputting a square wave D signal, and finally store the RB and SB signals by a latch, thereby completing the DFF function.
As shown in fig. 3, the simulation diagrams of the D flip-flop and the prior art D flip-flop comparison circuit provided in the embodiment of the present invention when the input signals D and CLK are changed simultaneously are shown, Q and QB are the outputs of the circuit in the embodiment of the present invention, RB and SB are the outputs of the prior art comparison circuit, and it can be seen from fig. 3: the external input signals D, CLK are changed simultaneously, while at the same time, it is seen that Q and QB can collect and hold signals well, while RB and SB cannot.
Fig. 4 is a simulation diagram of the D flip-flop and the prior art D flip-flop comparison circuit provided by the embodiment of the present invention when the input signals D and CLK are different, where GND (2) is the current change condition of the circuit ground of the present invention in fig. 1, and GND (1) is the current change condition of the circuit ground of the prior art in fig. 2, as can be seen from fig. 4: the external input signals D and CLK are not changed at the same time, Q and QB, RB and SB can well collect and store signals, GND (2) can well control the current, and GND (1) cannot reduce the current.
The following table 1 shows the comparison of power consumption data of the D flip-flop according to the embodiment of the present invention and the D flip-flop control circuit according to the prior art when the input signals D and CLK are not changed, and the test simulation is performed under the condition that the VDD power supply is 1.2V, the temperature is 27 ℃, and the process angle is TT.
| Voltage (V) | Temperature [ ] 0 C) | Technological angle | Average power consumption (W) | |
| The invention is that | 1.2 | 27 | TT | 228.498n |
| Control circuit | 1.2 | 27 | TT | 181.534u |
As can be seen from table 1 above: the average power consumption of the circuit is 228.498nw; whereas the average power consumption of the control circuit in the prior art is 181.534uw, the power consumption is approximately 794.5 times less.
It is noted that what is not described in detail in the embodiments of the present invention belongs to the prior art known to those skilled in the art.
In summary, the circuit according to the embodiment of the present invention controls the transmission of the D signal input by the CLK signal, and inputs the signal to the strong latch, but each side of the latch cannot be completely turned on from VDD to GND every time the latch is inverted, because the change of the other side is required on one side every time the latch is converted, so that the energy consumption is further reduced, and meanwhile, the response speed of the D flip-flop is increased because the number of latches is reduced, so that the power consumption of the whole chip design is reduced.
The foregoing is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims. The information disclosed in the background section herein is only for enhancement of understanding of the general background of the invention and is not to be taken as an admission or any form of suggestion that this information forms the prior art already known to those of ordinary skill in the art.
Claims (4)
1. The utility model provides a D trigger circuit of strong latch structure which characterized in that, the circuit includes four logic input inverters, strong latch circuit, two transmission gates that connect gradually, wherein:
the first logic input inverter is composed of an NMOS transistor NM0 and a PMOS transistor PM 0; the source of the PMOS transistor PM0 is connected to the power supply VDD, the source of the NMOS transistor NM0 is connected to the ground GND, the drain of the PMOS transistor PM0 is connected to the drain of the NMOS transistor NM0 as an output signal, and the gate of the PMOS transistor PM0 is connected to the gate of the NMOS transistor NM0 as an input signal;
the second logic input inverter is composed of an NMOS transistor NM1 and a PMOS transistor PM 1; the source of the PMOS transistor PM1 is connected with a power supply VDD, the source of the NMOS transistor NM1 is connected with GND, the drain of the PMOS transistor PM1 is connected with the drain of the NMOS transistor NM1 to serve as an output signal, and the grid of the PMOS transistor PM1 is connected with the grid of the NMOS transistor NM1 to serve as an input signal;
the third logic input inverter is composed of an NMOS transistor NM4 and a PMOS transistor PM 4; the source of the PMOS transistor PM4 is connected to the power supply VDD, the source of the NMOS transistor NM4 is connected to GND, the drain of the PMOS transistor PM4 is connected to the drain of the NMOS transistor NM4 as an output signal, and the gate of the PMOS transistor PM4 is connected to the gate of the NMOS transistor NM4 as an input signal;
the fourth logic input inverter is composed of an NMOS transistor NM5 and a PMOS transistor PM 5; the source of the PMOS transistor PM5 is connected with the power supply VDD, the source of the NMOS transistor NM5 is connected with GND, the drain of the PMOS transistor PM5 is connected with the drain of the NMOS transistor NM5 to serve as an output signal, and the grid of the PMOS transistor PM5 is connected with the grid of the NMOS transistor NM5 to serve as an input signal;
the four logic input inverters are all PMOS drain electrodes and NMOS drain electrodes connected;
the strong latch circuit includes two NMOS transistors NM6 and NM7, four PMOS transistors PM6, PM8, PM7, and PM9, wherein:
PM7, PM6 and NM6 of the left part are sequentially connected in series, PM9, PM8 and NM7 of the right part are also sequentially connected in series, the two side parts form a strong latch structure, only one tube is conducted each time the NMOS transistor NM6 and the PMOS transistor PM7 of the left part are changed, and only one tube is conducted each time the NMOS transistor NM7 and the PMOS transistor PM9 of the right part are changed;
the grid electrode of the PMOS transistor PM6 is connected with the Q node, and the grid electrode of the PMOS transistor PM8 is connected with the Q non-node to form a negative feedback loop;
the strong latch circuit receives square wave signals fed by four logic input inverters and stores the square wave signals in Q and Q non-nodes, and the transistors are utilized to be turned off in the conversion process, so that the current of the left side or the right side part can be reduced from VDD to flow into GND in each conversion, thereby greatly reducing dynamic leakage and reducing power consumption;
the first transmission gate is composed of a PMOS transistor PM2 and an NMOS transistor NM2 and is positioned between the first logic input inverter and the third logic input inverter, and is used as a control signal of a clock CLK, when CLK is always high level, the first transmission gate enables the high level of the first logic input inverter to be input into the third logic input inverter, and when CLK is low level, the first transmission gate is closed and does not enable the signal transmission between the first logic input inverter and the third logic input inverter;
the second transmission gate is composed of a PMOS transistor PM3 and an NMOS transistor NM3, and is located between the second logic input inverter and the fourth logic input inverter, and is used as a control signal of the clock CLK, when CLK is always at a high level, the second transmission gate allows the high level of the second logic input inverter to be input to the fourth logic input inverter, and when CLK is at a low level, the second transmission gate is turned off and does not allow signal transmission between the second logic input inverter and the fourth logic input inverter.
2. The D flip-flop circuit of claim 1, wherein the connection relationship inside the strong latch circuit is specifically:
the source electrode of the PMOS transistor PM7 is connected with the power supply VDD, and the drain electrode of the PMOS transistor PM7 is connected with the source electrode of the PMOS transistor PM 6;
the drain of the PMOS transistor PM6 is connected to the drain of the NMOS transistor NM6, the source of the NMOS transistor NM6 is connected to GND, and the gate of the NMOS transistor NM6 and the gate of the PMOS transistor PM7 are connected to each other as an input port of the third logic input inverter output;
the drain of the PMOS transistor PM8 and the drain of the NMOS transistor NM7 are connected to the Q point, and the gate of the PMOS transistor PM6 is connected to the Q point;
the substrate of the NMOS transistor NM6 is connected with GND, the substrate of the PMOS transistor PM7 is connected with the power supply VDD, and the substrate of the PMOS transistor PM6 is connected with the power supply VDD;
the source electrode of the PMOS transistor PM9 is connected with the power supply VDD, and the drain electrode of the PMOS transistor PM9 is connected with the source electrode of the PMOS transistor PM 8;
the drain of the PMOS transistor PM8 is connected to the drain of the NMOS transistor NM7, the source of the NMOS transistor NM7 is connected to GND, and the gate of the NMOS transistor NM7 and the gate of the PMOS transistor PM9 are connected to each other as an input port of the output of the fourth logic input inverter;
the drain of the PMOS transistor PM6 and the drain of the NMOS transistor NM6 are connected to Q non-point, and the gate of the PMOS transistor PM8 is connected to Q non-point;
the substrate of the NMOS transistor NM7 is connected to GND, the substrate of the PMOS transistor PM8 is connected to the power supply VDD, and the substrate of the PMOS transistor PM8 is connected to the power supply VDD.
3. The D flip-flop circuit of claim 1 wherein said first pass gate has a connection relationship of components comprising:
the substrate of the NMOS transistor NM2 is connected with GND, and the substrate of the PMOS transistor PM2 is connected with a power supply VDD;
the drain of the NMOS transistor NM2 is connected to the drain of the PMOS transistor PM2 as an input, while being connected to the output of the first logic input inverter;
the source of the NMOS transistor NM2 is connected to the source of the PMOS transistor PM2 as an output, while being connected to the input of the third logic input inverter;
the gate of the PMOS transistor PM2 is connected to the output of the second logic input inverter;
the gate of the NMOS transistor NM2 is connected to the clock CLK.
4. The D flip-flop circuit of claim 1 wherein said second pass gate has a connection relationship of components comprising:
the substrate of the NMOS transistor NM3 is connected with GND, and the substrate of the PMOS transistor PM3 is connected with a power supply VDD;
the drain of the NMOS transistor NM3 is connected to the drain of the PMOS transistor PM3 as an input, and is connected to the D input signal;
the source of the NMOS transistor NM3 is connected to the source of the PMOS transistor PM3 as an output, while being connected to the input of the fourth logic input inverter;
the gate of the PMOS transistor PM3 is connected to the output of the second logic input inverter;
the gate of the NMOS transistor NM3 is connected to the clock CLK.
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