CN206237376U - Difference type based on floating-gate MOS tube is unilateral along T triggers - Google Patents
Difference type based on floating-gate MOS tube is unilateral along T triggers Download PDFInfo
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- CN206237376U CN206237376U CN201621371111.4U CN201621371111U CN206237376U CN 206237376 U CN206237376 U CN 206237376U CN 201621371111 U CN201621371111 U CN 201621371111U CN 206237376 U CN206237376 U CN 206237376U
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Abstract
The utility model discloses that a kind of difference type in floating-gate MOS tube is unilateral along T triggers, including input control structure, the master flip-flop of differential configuration and differential configuration slave flipflop.The beneficial effects of the utility model are：Input control structure is made up of simple combinational logic circuit.Circuit make use of easily controllable this natural quality of the threshold value that floating-gate MOS tube has, without increasing special circuit, it is only necessary to just can easily control the switch of circuit by increasing an input in N-shaped floating-gate MOS tube.The trigger of differential configuration is due to having the advantages that complementary output, low-power consumption, simple structure, and the nMOS logic circuits in traditional difference D-flip flop are instead of with N-shaped floating-gate MOS tube pulldown network, pulldown network structure is simplified, so as to further reduce the power consumption of circuit.
Description
Technical field
The utility model is related to difference type unilateral along T triggers, more particularly to a kind of difference type list based on floating-gate MOS tube
Edge T triggers.
Background technology
Trigger is basic component in digital integrated electronic circuit, and they are decide including power consumption, delay, area, reliability
Deng the performance of circuit.In all of trigger, the trigger of differential configuration is due to complementary output, low-power consumption, simple
The advantages of structure, therefore application is than wide.Differential flip-flops can play a part of amplifier, therefore they can be in low pendulum
Worked well under width voltage signal.They can also set up various logic function to reduce sequencing expense in trigger.
Utility model content
For the problem that above-mentioned prior art is present, the utility model provides a kind of low in energy consumption and simple structure based on floating
The difference type of grid metal-oxide-semiconductor is unilateral along T triggers.
To achieve these goals, the technical solution adopted in the utility model is：Difference type based on floating-gate MOS tube is unilateral
Along T triggers, including the slave flipflop for being input into control structure, the master flip-flop of differential configuration and differential configuration；
The input control structure is made up of combinational logic circuit, and XOR gate XOR1 constitutes F1 input structures, XOR gate
XOR2 and not gate I1 constitutes F2 input structures；XOR1 is output as F1；XOR2 is output as the input of I1, and I1 is output as F2；
The master flip-flop is input into N-shaped floating-gate MOS by the two PMOS m3 and m4 and two three that constitute differential configuration
Pipe m1 and m2 are constituted；
The slave flipflop is by constituting two PMOS m7 and m8, two three input N-shaped floating-gate MOS tube m5 of differential configuration
Constituted with m6 and two phase inverter INV1 and INV2；
PMOS m3, m4, m7 and m8 source class meet operating voltage VDD, the three input N-shaped floating-gate MOS tubes m1, m2,
The source class ground connection of m5 and m6；
Two drain electrodes of PMOS m3 and m4 that differential configuration is constituted in the master flip-flop are input into N-shapeds with two three respectively
The drain electrode connection of floating-gate MOS tube m1 and m2, and produce the output of master flip-flopAnd x；Difference is constituted in the slave flipflop
Drain electrode of the drain electrode of two PMOSs m7 and m8 of structure respectively with two three input N-shaped floating-gate MOS tubes m5 and m6 is connected, and leads to
Cross two phase inverters INV1 and INV2 be connected to output end Q and
The beneficial effects of the utility model are：Input control structure is made up of simple combinational logic circuit.Circuit is utilized
Threshold value easily controllable this natural quality that floating-gate MOS tube has, without increasing special circuit, it is only necessary to by N-shaped
Increasing an input in floating-gate MOS tube just can easily control the switch of circuit.The trigger of differential configuration is due to having
The advantages of complementary output, low-power consumption, simple structure, and instead of traditional difference type with N-shaped floating-gate MOS tube pulldown network
NMOS logic circuits in trigger, simplify pulldown network structure, so as to further reduce the power consumption of circuit.
Brief description of the drawings
Fig. 1 is N-shaped and p-type multi input floating-gate MOS tube symbol and capacitor model；
Fig. 2 is the utility model circuit theory diagrams.
Specific embodiment
The utility model is described further with reference to embodiment.The explanation of following embodiments is only intended to help and manages
Solution the utility model.It should be pointed out that for those skilled in the art, not departing from the utility model principle
On the premise of, some improvement and modification can also be carried out to the utility model, these are improved and modification also falls into the utility model
In scope of the claims.
Multi input floating-gate MOS tube be propose in recent years it is a kind of with feature it is strong, threshold value control is flexible the features such as it is new
Type device, people have carried out further investigation in application of the multiple fields to it such as simulation, numeral and neutral nets.This device
Processing technology it is completely compatible with the double level polysilicon CMOS technology of standard, its symbol is represented and its capacitor model such as Fig. 1 institutes
Show.It has multiple input grid and a floating gates, and wherein floating boom is formed by ground floor polysilicon, and multiple input control gate is then
Formed by second layer polysilicon.Coupled by electric capacity realization between input and floating boom.V in figureFRepresent the voltage on floating boom, V0
It is underlayer voltage, V1、V2、……、VnIt is applied signal voltage.C0It is the coupled capacitor between floating boom and substrate, it is mainly by grid
Oxidation layer capacitance CoxConstitute, C1、C2、……、CnIt is the coupled capacitor between each input grid and floating boom.D and S difference table in figure
Show drain electrode and source electrode.Net charge Q on floating boomFIt is given by：
For n-channel floating-gate MOS tube, Substrate ground, therefore V0=0.Assuming that the initial charge on floating boom is zero, according to electricity
Lotus law of conservation, as available from the above equation:
If VTIt is the threshold voltage of the pipe seen into by floating boom end, then works as VF>VTShi Guanzi is turned on.By formula (2) and (3)
As can be seen that multi input floating-gate MOS tube can go control to each grid input signal weighted sum with the summed result being calculated
The "ON" and "Off" of metal-oxide-semiconductor processed.The sum operation with coefficient for noticing all input signals that it is carried out on floating boom is using electricity
Hold what coupling effect was carried out with voltage mode, have the low-power consumption more more excellent than current-mode summation technology special which show it
Property.If with V1Used as input, other inputs then have as control end：
So, by V1The threshold voltage V of the pipe that end is seen into* t1Can be expressed as:
Above formula shows, without adjusting VTIf, by changing the proportionate relationship between coupled capacitor or changing control end electricity
Pressure ViFloating-gate MOS tube can just be changed relative to input signal V1Threshold voltage, so as to control the conducting and cut-off of metal-oxide-semiconductor.It is right
In p-channel floating-gate MOS tube, substrate generally meets circuit maximum voltage sources (such as VDD), therefore V in formula (1)0=VDD, formula (2)-(5) need
Make corresponding amendment.
A kind of structure of difference type Master-Slave JK Flip-Flop circuit based on floating-gate MOS tube of the present utility model as shown in Fig. 2
Including：The slave flipflop of input control structure, the master flip-flop of differential configuration and differential configuration.
The input control structure is made up of combinational logic circuit, and XOR gate XOR1 constitutes F1 input structures, XOR gate
XOR2, not gate I1 constitute F2 input structures；The master flip-flop by constitute differential configuration two PMOSs m3 and m4, two three
Input N-shaped floating-gate MOS tube m1 and m2 are constituted；The slave flipflop by constitute differential configuration two PMOSs m7 and m8, two
Three input N-shaped floating-gate MOS tube m5 and m6, two phase inverters INV1 and INV2 are constituted.
PMOS m3, m4, m7, m8 source class meet operating voltage VDD, the three input N-shaped floating-gate MOS tubes m1, m2,
The source class ground connection of m5, m6.
In the input control structure, XOR1 is output as F1；The input of the output I1 of XOR2, I1 is output as F2.
Two drain electrodes of PMOS m3 and m4 that differential configuration is constituted in the master flip-flop are input into N-shapeds with two three respectively
The drain electrode connection of floating-gate MOS tube m1 and m2, and produce the output of master flip-flopAnd x；Difference is constituted in the slave flipflop
Drain electrode of the drain electrode of two PMOSs m7 and m8 of structure respectively with two three input N-shaped floating-gate MOS tubes m5 and m6 is connected, and leads to
Cross two phase inverters INV1 and INV2 be connected to output end Q and
Three input floating-gate MOS tube m1 employed in the design input (V1=F1,V3=GND) weight
It is identical, i.e. C1=C2=C3=C；Three input floating-gate MOS tube m2 employed in the design input (V1=F2,
V3=GND) weight is identical, i.e. C1=C2=C3=C；Input (the V1 of three input floating-gate MOS tube m5 employed in the design
=x, V2=clk, V3=0) weight it is identical, i.e. C1=C2=C3=C；Three input floating-gate MOS tubes employed in the design
The input of m6V2=clk, V3=0) weight it is identical, i.e. C1=C2=C3=C.
According to formula (4)：
For m1, only need
M1 is turned on,
I.e.
For m2, only need
M2 is turned on,
I.e.
For m5, only need
M5 is turned on,
I.e.
For m6, only need
M6 is turned on,
I.e.
In input control structure, outer input signal J and K and output feedback signal (the existing state of trigger) QnWithWith input F1
Relation with F2 is as follows：
From formula (10) and (11),
With outer input and the difference of the existing state of trigger, the state for being input into F1 and F2 is as shown in the table：
The flip-flop operation state is as follows：
In clk low levels, according to formula (6) and (7), the V2=1 in m1 and m2, the master flip-flop receives input letter
Number, when it is high level to be input into F1, F2 is low level, m1 conductings and m2 ends, master flip-flop output x andRespectively 1 and 0；
When it is low level to be input into F1, F2 is high level, m2 conductings and m1 ends, master flip-flop output x andRespectively 0 and 1；Now
According to formula (8) and (9), m5 and m6 end, and slave flipflop is closed, output Q andKeep constant；In clk rising edges, according to
Formula (6) and (7), the V2=0 in m1 and m2, master flip-flop close, slave flipflop open, the output x of master flip-flop andCertainly
Surely output Q andWhen x be high level when, m5 conducting and m6 end, output Q andIt is 1 and 0；When x is low level, m6 conductings
And m5 end, output Q andIt is 0 and 1.
Arbitrary value is represented with φ.According to the course of work above, a kind of difference based on floating-gate MOS tube can be summed up
The unilateral working condition along T flip-flop circuits of parting is as shown in the table：
Claims (1)
1. a kind of difference type based on floating-gate MOS tube is unilateral along T triggers, it is characterised in that：Including input control structure, difference
The master flip-flop of structure and the slave flipflop of differential configuration；
It is described input control structure be made up of combinational logic circuit, XOR gate XOR1 constitute F1 input structures, XOR gate XOR2 and
Not gate I1 constitutes F2 input structures；XOR1 is output as F1；XOR2 is output as the input of I1, and I1 is output as F2；
The master flip-flop is input into N-shaped floating-gate MOS tube m1 by the two PMOS m3 and m4 and two three that constitute differential configuration
Constituted with m2；
The slave flipflop is by constituting two PMOS m7 and m8, two three input N-shaped floating-gate MOS tubes m5 and m6 of differential configuration
And two phase inverters INV1 and INV2 are constituted；
PMOS m3, m4, m7 and m8 source class meet operating voltage VDD, described three input N-shaped floating-gate MOS tube m1, m2, m5 and
The source class ground connection of m6；
Two drain electrodes of PMOS m3 and m4 that differential configuration is constituted in the master flip-flop are input into N-shaped floating booms with two three respectively
The drain electrode connection of metal-oxide-semiconductor m1 and m2, and produce the output of master flip-flopAnd x；Differential configuration is constituted in the slave flipflop
Two drain electrodes of PMOS m7 and m8 are connected with two three drain electrodes for being input into N-shaped floating-gate MOS tube m5 and m6 respectively, and by two
Phase inverter INV1 and INV2 be connected to output end Q and
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621371111.4U CN206237376U (en) | 2016-12-14 | 2016-12-14 | Difference type based on floating-gate MOS tube is unilateral along T triggers |
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| CN201621371111.4U CN206237376U (en) | 2016-12-14 | 2016-12-14 | Difference type based on floating-gate MOS tube is unilateral along T triggers |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113346894A (en) * | 2021-06-08 | 2021-09-03 | 李世杰 | Logic operation circuit, differential amplification circuit, and electronic device |
| CN113346894B (en) * | 2021-06-08 | 2024-05-31 | 李世杰 | Logic operation circuit and electronic device |
-
2016
- 2016-12-14 CN CN201621371111.4U patent/CN206237376U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113346894A (en) * | 2021-06-08 | 2021-09-03 | 李世杰 | Logic operation circuit, differential amplification circuit, and electronic device |
| WO2022257246A1 (en) * | 2021-06-08 | 2022-12-15 | 李世杰 | Logic operation circuit, differential amplification circuit, and electronic device |
| CN113346894B (en) * | 2021-06-08 | 2024-05-31 | 李世杰 | Logic operation circuit and electronic device |
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Granted publication date: 20170609 Termination date: 20181214 |