CN202435379U - SET/MOS (single-electron transistor/ Metal Oxide Semiconductor) mixed structure multiplier unit based on threshold logic - Google Patents
SET/MOS (single-electron transistor/ Metal Oxide Semiconductor) mixed structure multiplier unit based on threshold logic Download PDFInfo
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- CN202435379U CN202435379U CN2012200014458U CN201220001445U CN202435379U CN 202435379 U CN202435379 U CN 202435379U CN 2012200014458 U CN2012200014458 U CN 2012200014458U CN 201220001445 U CN201220001445 U CN 201220001445U CN 202435379 U CN202435379 U CN 202435379U
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Abstract
The utility model relates to the technical field of integrated circuits, and in particular relates to an SET/MOS (Single-Electron Transistor/Metal Oxide Semiconductor) mixed structure multiplier unit based on a threshold logic. The SET/MOS mixed structure multiplier unit based on the threshold logic comprises a first signal source, a second signal source, a third signal source, a fourth signal source, a fourth input threshold logic gate, a fifth input threshold logic gate and a phase inverter; and three PMOS (P-channel Metal Oxide Semiconductor) tubes, three NMOS (N-channel Metal Oxide Semiconductor) tubes and two SETs are used up. A simulation result of HSPICE (Hyper Simulation Program with Integrated Circuit Emphasis) shows that a circuit is adopted to effectively realize a logic function of the multiplier unit and the average power consumption of the whole circuit is only 12nW. Compared with a CMOS (Complementary Metal-Oxide-Semiconductor) multiplier unit based on a Boolean logic, the number of tubes is greatly reduced, the power consumption is obviously reduced, and the circuit structure is further simplified, so that the area of a chip is saved, and the integration level of the circuit is improved.
Description
Technical field
The utility model relates to technical field of integrated circuits, particularly a kind of SET/MOS mixed structure multiplier unit of being made up of nano-device based on voting logic.
Background technology
Multiplier is a kind of common combinational logic circuit, in microprocessor, digital signal processor and image engine, important use is arranged.Traditional CMOS multiplier constitutes by multistage full adder with door, and its schematic diagram is as shown in Figure 1.This multiplier need consume more CMOS transistor.Along with constantly dwindling of CMOS characteristic size, the CMOS technology faces very big challenge, and a lot of problems has appearred in electric properties of devices and reliability, like short-channel effect, and high-field effect, drain electrode causes potential barrier decline effect etc.At this moment, based on the raising of the transistorized multiplier of CMOS along with the complexity of the increase of computing figure place and circuit, aspects such as its arithmetic speed, integrated level, reliability, power consumption have received very big restriction, can not satisfy the requirement of new capability.
Summary of the invention
The purpose of the utility model provides a kind of SET/MOS mixed structure multiplier unit based on voting logic.
The utility model adopts following scheme to realize: a kind of SET/MOS mixed structure multiplier unit based on voting logic is characterized in that: comprise first, second, third and fourth signal source, four input Threshold Logic Gate, five input Threshold Logic Gate and inverters; Said first signal source is connected with the first input end of said four input Threshold Logic Gate, the first input end of five input Threshold Logic Gate; Said secondary signal source is connected with second input of said four input Threshold Logic Gate, second input of five input Threshold Logic Gate; Said the 3rd signal source is connected with the 3rd input of said four input Threshold Logic Gate, the 3rd input of five input Threshold Logic Gate; Said the 4th signal source is connected with the four-input terminal of said four input Threshold Logic Gate, the four-input terminal of five input Threshold Logic Gate; The output of said four input Threshold Logic Gate is connected through the five terminal of said inverter with said five input Threshold Logic Gate; Said four, five input Threshold Logic Gate are made up of the SET/MOS hybrid circuit.
In the utility model one embodiment, described SET/MOS hybrid circuit comprises: PMOS pipe, its source electrode connects power end
V DdOne NMOS pipe, its drain electrode is connected with the drain electrode of said PMOS pipe; And a SET pipe, it is connected with source electrode that said NMOS manages.
The utility model has been realized the multiplier unit based on voting logic based on coulomb blockade oscillation effect and multiple-grid input characteristics that the SET/MOS mixed structure has.The logic function that voting logic is powerful makes it realize complicated logic function effectively by enough less pipes.The multiplier unit based on voting logic of the utility model only is made up of 2 Threshold Logic Gate and 1 inverter, consumes 3 PMOS pipes altogether, 3 NMOS pipes and 2 SET.The simulation result of HSPICE shows that this circuit can realize the logic function of multiplier unit effectively, and the average power consumption of entire circuit is merely 12 nW.Compare with the CMOS multiplier unit based on Boolean logic, number of tubes significantly reduces, and power consumption significantly reduces, and circuit structure has obtained further simplification, helps saving area of chip, improves the integrated level of circuit.
Description of drawings
Fig. 1 is the circuit structure principle schematic of traditional multiplier.
Fig. 2 is the Threshold Logic Gate sketch map.
Fig. 3 is multiple-grid input SET/MOS hybrid circuit schematic diagram.
Fig. 4 is the multiplier unit schematic diagram of SET/MOS mixed structure.
Fig. 5 is the simulated properties curve of multiplier unit.
Embodiment
Below in conjunction with accompanying drawing and embodiment the utility model is further specified.
As shown in Figure 3, the utility model provides a kind of SET/MOS mixed structure multiplier unit based on voting logic, comprises first, second, third and fourth signal source, four input Threshold Logic Gate, five input Threshold Logic Gate and inverters; Said first signal source
a 1Be connected with the first input end of said four input Threshold Logic Gate, the first input end of five input Threshold Logic Gate; Said secondary signal source
a 2Be connected with second input of said four input Threshold Logic Gate, second input of five input Threshold Logic Gate; Said the 3rd signal source
s iBe connected with the 3rd input of said four input Threshold Logic Gate, the 3rd input of five input Threshold Logic Gate; Said the 4th signal source
c iBe connected with the four-input terminal of said four input Threshold Logic Gate, the four-input terminal of five input Threshold Logic Gate; The output of said four input Threshold Logic Gate is connected through the five terminal of said inverter with said five input Threshold Logic Gate; Said four, five input Threshold Logic Gate are made up of the SET/MOS hybrid circuit, and its threshold value is 1.5, and its output logic is to calculate total input value according to the weighted value of importing; And total input value and said threshold value compared; More than or equal to said threshold value, then be output as 1, otherwise be output as 0.
The utility model adopts single-electronic transistor, and (Single electron transistor SET) carries out the design of multiplier unit with the mode that metal-oxide-semiconductor mixes mutually.As typical case's representative of nano electron device of new generation, SET has remarkable advantages at aspects such as power consumption, operating rates with respect to traditional microelectronic component, is considered to make low-power consumption of future generation, the desirable basic device of high density very lagre scale integrated circuit (VLSIC).Single-electronic transistor can be compatible mutually with the CMOS silicon technology; The SET/MOS hybrid circuit possesses the superior function of SET and metal-oxide-semiconductor; Show extremely low power consumption, extra small device size, stronger driving force and bigger output voltage swing, obtained using widely at aspects such as MULTI-VALUED LOGIC CIRCUIT, D and D/A converter circuit, memory circuitries.In addition, the SET/MOS hybrid circuit can be realized the method for designing based on voting logic.The logical process of voting logic is more complicated than Boolean logic, can more effectively realize logic function.Therefore,, be expected to the function of intensifier circuit, improve the integrated level of circuit based on the circuit design of voting logic.
The utility model is based on the voting logic design.The cardinal principle of voting logic is that the weight calculation according to input goes out total input value, total input value and threshold value is compared draw output logic.If total input value then is output as 1, otherwise is 0 more than or equal to threshold value.The logical equation that voting logic will satisfy is:
Wherein
W iBe input
X iCorresponding weight,
nBe the number of input,
θBe threshold value.The sketch map of Threshold Logic Gate is as shown in Figure 2.
This a unit of full adder in the multiplier of the utility model and one and door primordial utilizes the powerful logic function of voting logic, has realized the simplification of circuit structure and the raising of integrated level.Being input as of the basic multiplier unit of choosing
a 1,
a 2,
s i,
c i, corresponding being output as
s I+1,
c I+1The logic function that this multiplier unit need be realized is as shown in table 1,
Table 1
The voting logic expression formula that can obtain multiplier output by table 1 is suc as formula (2); (3) shown in, wherein
is
through the output valve behind the inverter.
The utility model adopts the SET/MOS hybrid circuit of multiple-grid input to realize the logic function of multiplier unit.The SET/MOS hybrid circuit of multiple-grid input is as shown in Figure 3.This circuit is managed by a PMOS, and the SET of a NMOS pipe and a multiple-grid input is in series.The PMOS pipe is that entire circuit provides bias current as constant-current source in the circuit.Because the electric current of SET operate as normal is very little, is generally the nA order of magnitude, so the PMOS pipe should be operated in sub-threshold region.The grid bias V of NMOS pipe
NgFix, its value is slightly larger than the threshold voltage of NMOS pipe
V Th, the drain voltage of SET is fixed as
V Ng-
V ThGrid voltage
V 1,
V 2...,
V nBe capacitively coupled on the Coulomb island, SET is mainly worked by the electromotive force of grid voltage control Coulomb island.The SET/MOS hybrid circuit also possesses the characteristics of multiple-grid input, allows a plurality of input voltages and is coupled on the Coulomb island.Through suitable circuit parameter is set, the SET/MOS hybrid circuit can be realized the function of Threshold Logic Gate.Schematic diagram based on the multiplier unit of voting logic is as shown in Figure 4, and this circuit only is made up of 2 Threshold Logic Gate and 1 inverter, and wherein inverter is realized by traditional CMOS transistor.Input
a 1,
a 2,
s i,
c iBe directly connected to the input of SET/MOS hybrid circuit, the weight of input is embodied by the input coupling capacitance.
The utility model utilizes HSPICE that the multiplier unit based on voting logic is carried out the function simulating checking.The model of SET is the macro model (Compact macromodel) widely-used at present, that precision is high.This model with the formal definition of electronic circuit in SPICE.The model of metal-oxide-semiconductor uses the Predicting Technique model (Predictive technology model) of 22 nm that generally acknowledge at present.In the multiplier unit circuit, except unit input coupling capacitance (
C 1,
C 2) and back of the body gate bias voltage (
V Ctrl1,
V Ctrl2) outside, two Threshold Logic Gate have identical simulation parameter, wherein
C 1,
V Ctrl1Corresponding to output
c I+1Threshold Logic Gate,
C 2,
V Ctrl2Corresponding to output
s I+1Threshold Logic Gate.In circuit, supply voltage
V DdBe set to 0.80 V, the breadth length ratio of PMOS pipe and NMOS pipe (
W/
L) all being made as 1/7, main circuit simulation parameter is as shown in table 2.
Table 2
The characteristic curve that emulation obtains is as shown in Figure 5.In Fig. 5, input signal
a 1,
a 2,
s i,
c iAll be made as square wave, added waveform satisfies 16 kinds of logical combinations of 4 inputs, and 0.8 V and 0 V are set to high level and the low level imported respectively.The output waveform that emulation obtains is low level and high level with 0.07 V and 0.75 V all.As can be seen from the figure, this output waveform satisfies multiplier unit truth table (table 1), explains that this circuit can realize the logic function that multiplier unit is corresponding.
What be noted that the utility model requirement protection here is the connection features of hardware circuit, just is used to let those skilled in the art better understand the utility model as for other relevant design algorithmic descriptions.
The above is merely the preferred embodiment of the utility model, and all equalizations of being done according to the utility model claim change and modify, and all should belong to the covering scope of the utility model.
Claims (2)
1. the SET/MOS mixed structure multiplier unit based on voting logic is characterized in that: comprise first, second, third and fourth signal source, four input Threshold Logic Gate, five input Threshold Logic Gate and inverters;
Said first signal source is connected with the first input end of said four input Threshold Logic Gate, the first input end of five input Threshold Logic Gate;
Said secondary signal source is connected with second input of said four input Threshold Logic Gate, second input of five input Threshold Logic Gate;
Said the 3rd signal source is connected with the 3rd input of said four input Threshold Logic Gate, the 3rd input of five input Threshold Logic Gate;
Said the 4th signal source is connected with the four-input terminal of said four input Threshold Logic Gate, the four-input terminal of five input Threshold Logic Gate;
The output of said four input Threshold Logic Gate is connected through the five terminal of said inverter with said five input Threshold Logic Gate; Said four, five input Threshold Logic Gate are made up of the SET/MOS hybrid circuit.
2. the SET/MOS mixed structure multiplier unit based on voting logic according to claim 1, it is characterized in that: described SET/MOS hybrid circuit comprises:
One PMOS pipe, its source electrode connects power end
V Dd
One NMOS pipe, its drain electrode is connected with the drain electrode of said PMOS pipe; And
One SET pipe, its source electrode with said NMOS pipe is connected.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102571071A (en) * | 2012-01-05 | 2012-07-11 | 福州大学 | Single electron transistor (SET)/metal oxide semiconductor (MOS) mixed structure multiplier unit based on threshold logic |
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2012
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102571071A (en) * | 2012-01-05 | 2012-07-11 | 福州大学 | Single electron transistor (SET)/metal oxide semiconductor (MOS) mixed structure multiplier unit based on threshold logic |
| CN102571071B (en) * | 2012-01-05 | 2014-03-26 | 福州大学 | Single electron transistor (SET)/metal oxide semiconductor (MOS) mixed structure multiplier unit based on threshold logic |
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Granted publication date: 20120912 Termination date: 20180105 |