CN102571076B - Threshold logic-based 7-3 counter with SET (single-electron transistors)/MOS (metal-oxide-semiconductor) mixed structure - Google Patents

Abstract

The invention relates to the technical field of integrated circuits, and particularly relates to a threshold logic-based 7-3 counter with an SET (single-electron transistors)/MOS (metal-oxide-semiconductor) mixed structure. The 7-3 counter comprises a seven-input threshold logic gate, an eight-input threshold logic gate and a nine-input threshold logic gate; and a circuit only consists of three threshold logic gates and two inverters, and totally consumes five PMOS (P-channel Metal Oxide Semiconductor) tubes, five NMOS (N-channel metal oxide semiconductor) tubes and three SETs (single-electron transistors). A Boolean logic-based CMOS7-3 counter consumes 194 transistors. The average power consumption of the whole circuit is only 6.92 nW. In contrast, as the 7-3 counter provided by the invention is used, the number of the tubes is greatly reduced, the power consumption of the circuit is significantly lowered, and the structure of the circuit is further simplified, therefore, the 7-3 counter is expected to be applied to multipliers, multi-input adders and digital signal processors.

Description

Based on the 7-3 counter of the SET/MOS mixed structure of voting logic

Technical field

The present invention relates to technical field of integrated circuits, particularly a kind of 7-3 counter of the SET/MOS mixed structure based on voting logic be made up of nano-device.

Background technology

7-3 counter, as basic digital circuit unit, can calculate the number of high level in input signal, is encoded to the binary number of 3.7-3 counter is widely used in multiplier, multi input adder and digital signal processor.Existing 7-3 counter is formed primarily of traditional CMOS transistor.7-3 counter circuit structure based on cmos device is complicated, needs to consume more transistor, and circuit power consumption is comparatively large, and integrated level is not high.

Summary of the invention

The object of this invention is to provide a kind of 7-3 counter of the SET/MOS mixed structure based on voting logic.

The present invention adopts following scheme to realize: a kind of 7-3 counter of the SET/MOS mixed structure based on voting logic, comprises one seven input Threshold Logic Gate, eight input Threshold Logic Gate and one nine input Threshold Logic Gate; The 8th input that the output of described seven input Threshold Logic Gate inputs Threshold Logic Gate through the 8th input, nine that the first inverter and described eight inputs Threshold Logic Gate is connected; The 9th input that the output of described eight input Threshold Logic Gate inputs Threshold Logic Gate through the second inverter and described nine is connected; Described seven, eight, nine input Threshold Logic Gate are made up of SET/MOS hybrid circuit, and its threshold value is 1.5, and its output logic calculates total input value according to the weighted value of input, and total input value and described threshold value are compared, be more than or equal to described threshold value, then exporting is 1, otherwise output is 0.

In an embodiment of the present invention, the voting logic of described seven, eight, nine input Threshold Logic Gate meets logical equation:

Wherein w _ifor input x _icorresponding weight, nfor the number of input, θfor threshold value.

In an embodiment of the present invention, described SET/MOS hybrid circuit comprises: a PMOS, and its source electrode connects power end v _dd; One NMOS tube, its drain electrode is connected with the drain electrode of described PMOS; And one SET pipe, it is connected with the source electrode of described NMOS tube.

In an embodiment of the present invention, described PMOS M ₁parameter meet: channel width w _pbe 22 nm, channel length l _pbe 154 nm, grid voltage v _pgfor 0.4V; Described NMOS tube M ₂parameter meet: channel width w _nbe 22 nm, channel length l _nbe 154 nm, grid voltage v _ngbe 0.4 V; The parameter of described SET pipe meets: tunnel junctions electric capacity c _s, c _dbe 0.1 aF; Tunnel junctions resistance r _s, r _dbe 600 K Ω; Back gate voltage v _ctrlbe 0.762 V, backgate electric capacity c _ctrlbe 0.1050 aF, coupling capacitance c ₂be 0.0150 aF, coupling capacitance c ₁be 0.0095 aF; Coupling capacitance c ₀be 0.0080 aF.

The Coulomb blockade oscillation effect that the present invention utilizes single-electronic transistor and metal-oxide-semiconductor mixed structure to have and multiple-grid input characteristics, achieve the 7-3 counter of the SET/MOS mixed structure based on voting logic.Due to the logic function that voting logic is powerful, this circuit is only made up of 3 Threshold Logic Gate and 2 inverters, consumes 5 PMOS altogether, 5 NMOS tube and 3 SET.CMOS 7-3 counter based on Boolean logic then will consume 194 transistors.The simulation architecture of HSPICE shows that this circuit can realize the function of 7-3 counter, and the average power consumption of whole circuit is only 19.7 nW.Comparatively speaking, the 7-3 counter number of tubes that the present invention proposes greatly reduces, and circuit power consumption significantly reduces, and circuit structure obtains further simplification, is expected to be applied in the circuit such as multiplier, multi input adder and digital signal processor.

Accompanying drawing explanation

Fig. 1 is Threshold Logic Gate schematic diagram.

Fig. 2 is SET/MOS mixed structure 7-3 counter principle figure.

Fig. 3 is multiple-grid input SET/MOS hybrid circuit schematic diagram.

Fig. 4 is the input-output characteristic curve of SET/MOS hybrid circuit.

Fig. 5 a and Fig. 5 b is SET/MOS mixed structure 7-3 counter simulated properties curve.

Embodiment

Below in conjunction with drawings and Examples, the present invention will be further described.

As shown in Figure 2, the invention provides a kind of 7-3 counter of the SETMOS mixed structure based on voting logic, comprise one seven input Threshold Logic Gate, eight input Threshold Logic Gate and one nine input Threshold Logic Gate; The 8th input that the output of described seven input Threshold Logic Gate inputs Threshold Logic Gate through the 8th input, nine that the first inverter and described eight inputs Threshold Logic Gate is connected; The 9th input that the output of described eight input Threshold Logic Gate inputs Threshold Logic Gate through the second inverter and described nine is connected; Described seven, eight, nine input Threshold Logic Gate are made up of SET/MOS hybrid circuit, and its threshold value is 1.5, and its output logic calculates total input value according to the weighted value of input, and total input value and described threshold value are compared, be more than or equal to described threshold value, then exporting is 1, otherwise output is 0.

Specifically, the present invention adopts single-electronic transistor (Single electron transistor, SET) to carry out the design of 7-3 counter with the mode that metal-oxide-semiconductor mixes mutually.Single-electronic transistor is nano electron device of new generation, has unique coulomb blockade and coulomb oscillations effect.SET has extra small device size and ultralow circuit power consumption, in power consumption, operating rate etc., relative to traditional microelectronic component, there is obvious advantage, be expected to become and manufacture the desirable basic device of low-power consumption of future generation, high density very lagre scale integrated circuit (VLSIC).Single-electronic transistor can be mutually compatible with CMOS silicon technology simultaneously, and the advantage being conducive to making full use of existing CMOS technology carries out circuit design.This makes SET/MOS mixed structure become an important research direction of single-electronic transistor.SET/MOS hybrid circuit possesses the superior function of SET and metal-oxide-semiconductor, shows extremely low power consumption, extra small device size, stronger driving force and larger output voltage swing, is widely used in digital circuit.

In addition, SET/MOS hybrid circuit can not follow traditional method for designing based on Boolean logic, and adopts voting logic to carry out the design of circuit.Because voting logic has the logical process more complicated than Boolean logic, more effectively logic function can be realized.Therefore based on the circuit design of the SET/MOS mixed structure of voting logic, be expected to the function of intensifier circuit, improve the integrated level of circuit.

The cardinal principle of voting logic of the present invention goes out total input value according to the weight calculation of input, total input value and threshold value compared and draw output logic.If total input value is more than or equal to threshold value, then exporting is 1, otherwise is 0.The logical equation that voting logic will meet as the formula (1), wherein w _ifor input x _icorresponding weight, nfor the number of input, θfor threshold value.The schematic diagram of Threshold Logic Gate as shown in Figure 1.First circuit design based on voting logic will determine the voting logic expression formula of circuit, and key determines the weight of each input and the threshold value of circuit in circuit.

(1)

7-3 counter of the present invention can calculate the number of logical one in input signal, exports with the form of the binary number of 3.Continue referring to Fig. 2, this 7-3 counter is made up of 3 Threshold Logic Gate and two inverters, and 7 are input as v ₀- v ₆, export and be v _out0- v _out2.This structure can realize the calculating of logical one number in input, and exports 3 bits.3 export voting logic expression formulas such as formula shown in (2), (3), (4), , , for exporting, , for , through the output valve of inverter.The SET/MOS hybrid circuit that each Threshold Logic Gate in Fig. 2 inputs by a multiple-grid is formed, and its schematic diagram as shown in Figure 3.This circuit is by 1 PMOS, and the SET of 1 NMOS tube and 1 multiple-grid input is in series.In circuit PMOS as constant-current source for whole circuit provides bias current.The electric current normally worked due to SET is all very little, is generally the nA order of magnitude, so PMOS should be operated in sub-threshold region.The grid bias of NMOS tube v _ngbe fixing, its value is slightly larger than the threshold voltage of NMOS tube v _th, the drain voltage of SET is fixed as v _ng- v _th.Grid voltage v ₁, v ₂..., v _nbe capacitively coupled on coulomb island.Coupling capacitance constitutes the array of an electric capacity, for calculating total input value.According to the definition of voting logic, just corresponding output logic can be obtained by more total input voltage with circuit threshold value.When total input voltage is greater than threshold value, export as high level (logical one); When total input voltage is less than threshold value, export as low level (logical zero).By arranging suitable circuit parameter, input and output that SET/MOS hybrid circuit is corresponding ( v _in- v _out) characteristic curve as shown in Figure 4.Output voltage changes along with the change of input voltage.When input voltage exceedes certain numerical value (i.e. the threshold value of circuit, the 400mV as in Fig. 4), export the saltus step realized from low level to high level.By the back gate voltage of biased SET ( v _ctrl), different threshold values can be obtained.Therefore, SET/MOS hybrid circuit can realize the function of Threshold Logic Gate.

(2)

(3)

(4)

The present invention utilizes HSPICE to carry out the simulating, verifying of function to the 7-3 counter based on voting logic.The model of SET be widely use at present, macro model (Compact macromodel) that precision is high.This model with the formal definition of electronic circuit in SPICE.The model of metal-oxide-semiconductor uses the Predicting Technique model (Predictive technology model) of 22 nm generally acknowledged at present.In the circuit of 7-3 counter, except unit input coupling capacitance ( c ₀, c ₁, c ₂) outward, 3 Threshold Logic Gate have identical simulation parameter, wherein c ₀, c ₁, c ₂correspond respectively to produce and export v _out0, v _out1, v _out2threshold Logic Gate.In circuit, supply voltage v _ddbe set to 0.80V, the breadth length ratio of PMOS and NMOS tube ( w/ l) being all set to 1/7, main circuit simulation parameter is as shown in table 1.

Table 1

The characteristic curve that emulation obtains as shown in figure 5 a and 5b.In fig 5 a, input signal is all set to square wave, and the low and high level of input is respectively 0.8 V and 0 V.Emulate the number that the output waveform obtained can calculate logical one in input, the form being binary number with 3 exports, as shown in Figure 5 b.Therefore the structure that the present invention proposes can realize the function of 7-3 counter effectively.

The foregoing is only preferred embodiment of the present invention, all equalizations done according to the present patent application the scope of the claims change and modify, and all should belong to covering scope of the present invention.

Claims (1)

1., based on a 7-3 counter for the SET/MOS mixed structure of voting logic, comprise one seven input Threshold Logic Gate, eight input Threshold Logic Gate and one nine input Threshold Logic Gate; The 8th input that the output of described seven input Threshold Logic Gate inputs Threshold Logic Gate through the 8th input, nine that the first inverter and described eight inputs Threshold Logic Gate is connected; The 9th input that the output of described eight input Threshold Logic Gate inputs Threshold Logic Gate through the second inverter and described nine is connected; Described seven, eight, nine input Threshold Logic Gate are made up of SET/MOS hybrid circuit, and its threshold value is 1.5, and its output logic calculates total input value according to the weighted value of input, and total input value and described threshold value are compared, be more than or equal to described threshold value, then exporting is 1, otherwise output is 0; The voting logic of described seven, eight, nine input Threshold Logic Gate meets logical equation:

$F\left(x\right)=\mathrm{sgn}(\underset{i=1}{\overset{n}{\mathrm{\Σ}}}{W}_i{X}_i-\mathrm{\θ})=\left\{\begin{array}{cc}1,\mathrm{if}& \underset{i=1}{\overset{n}{\mathrm{\Σ}}}{W}_i{X}_i\≥\mathrm{\θ}\\ 0,& \mathrm{otherwise}\end{array}\right.$

Wherein W _ifor input X _icorresponding weight, n is the number of input, and θ is threshold value;

The obituary that this 7-3 counter realizes logical one number in input is calculated, and exports 3 bits; 3 export voting logic expression formulas such as formula shown in (2), (3), (4), O ₂, O ₁, O ₀for exporting, for O ₂, O ₁through the output valve of inverter;

$O_2=\mathrm{sgn}(\underset{i=0}{\overset{6}{\mathrm{\Σ}}}{X}_i-3.5)---\left(2\right)$

$O_1=\mathrm{sgn}(\underset{i=0}{\overset{6}{\mathrm{\Σ}}}{X}_i+4\stackrel{\‾}{O_2}-5.5)---\left(3\right)$

$O_0=\mathrm{sgn}(\underset{i=0}{\overset{6}{\mathrm{\Σ}}}{X}_i+4\stackrel{\‾}{O_2}+2\stackrel{\‾}{O_1}-6.5)---\left(4\right)$

Described SET/MOS hybrid circuit comprises:

One PMOS, its source electrode meets power end V _dd;

One NMOS tube, its drain electrode is connected with the drain electrode of described PMOS; And

One SET pipe, it is connected with the source electrode of described NMOS tube;

Described PMOS M ₁parameter meet: channel width W _pfor 22nm, channel length L _pfor 154nm, grid voltage V _pgfor 0.4V; Described NMOS tube M ₂parameter meet: channel width W _nfor 22nm, channel length L _nfor 154nm, grid voltage V _ngfor 0.4V; The parameter of described SET pipe meets: tunnel junctions electric capacity C _s, C _dfor 0.1aF; Tunnel junctions resistance R _s, R _dfor 600K Ω; Back gate voltage V _ctrlfor 0.762V, backgate electric capacity C _ctr1for 0.1050aF, coupling capacitance C ₂for 0.0150aF, coupling capacitance C ₁for 0.0095aF; Coupling capacitance C ₀for 0.0080aF.