CN202453865U - Threshold logic-based SET/MOS hybrid structure 2 bit multiplier - Google Patents
Threshold logic-based SET/MOS hybrid structure 2 bit multiplier Download PDFInfo
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- CN202453865U CN202453865U CN2012200014960U CN201220001496U CN202453865U CN 202453865 U CN202453865 U CN 202453865U CN 2012200014960 U CN2012200014960 U CN 2012200014960U CN 201220001496 U CN201220001496 U CN 201220001496U CN 202453865 U CN202453865 U CN 202453865U
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Abstract
The utility model relates to the technical field of integrated circuits, especially, relates to a threshold logic-based SET (Single-electron transistor)/MOS (Metal Oxide Semiconductor) hybrid structure 2 bit multiplier. The multiplier is composed of 5 threshold logic gates, one phase inverter and one exclusive OR gate only, and consumes 7 PMOS (P-channel Metal Oxide Semiconductor) tubes, 7 NMOS (N-channel Mental-oxide-semiconductor) tubes and 6 SETs in all. The average power consumption of the whole circuit is only 46nW. In comparison with a Boolean logic-based CMOS (Complementary Metal-Oxide-Semiconductor), the number of tubes is reduced greatly, the power consumption is lowered obviously, and the circuit structure is further simplified, which is helpful for saving chip area and improving the integration level of the circuit, so that the multiplier can be widely used in microprocessors, digital signal processors and image engines, hopefully.
Description
Technical field
The utility model relates to technical field of integrated circuits, particularly a kind of 2 multipliers of SET/MOS mixed structure based on voting logic of being made up of nano-device.
Background technology
Along with the characteristic dimension entering deep-submicron of integrated circuit, the resistance that further develops not only derives from manufacturing process, more is the integrated physical restriction of bringing of small size, high density, like short-channel effect, and high-field effect, drain electrode causes potential barrier decline effect etc.Multiplier is widely used in microprocessor, digital signal processor and image engine as a kind of important combinational logic circuit.Traditional multiplier based on the CMOS technology constitutes by multistage full adder with door, need to consume more CMOS transistor, and circuit structure is complicated, and integrated level is not high.These characteristics make traditional Multiplier Design method can not satisfy the performance requirement of the integrated circuit that improves day by day.
Summary of the invention
The purpose of the utility model provides a kind of 2 multipliers of SET/MOS mixed structure based on voting logic.
The utility model adopts following scheme to realize: a kind of 2 multipliers of SET/MOS mixed structure based on voting logic is characterized in that: comprise an XOR gate, a phase inverter, four signal sources, three two input Threshold Logic Gate, three input Threshold Logic Gate and one four input Threshold Logic Gate; First signal source of described four signal sources is connected with first end of said the one or two input Threshold Logic Gate, first end of the three or two input Threshold Logic Gate, first end of four input Threshold Logic Gate; The secondary signal source is connected with second end of said the one or two input Threshold Logic Gate, second end of the two or two input Threshold Logic Gate, second end of four input Threshold Logic Gate; The 3rd signal source is connected with first end of said the two or two input Threshold Logic Gate, first end of three input Threshold Logic Gate; The 4th signal source is connected with second end of said the 3rd input Threshold Logic Gate, second end of three input Threshold Logic Gate, the 4th end of four input Threshold Logic Gate; The output terminal of said the one or two input Threshold Logic Gate is connected through the 3rd input end of said phase inverter with said three input Threshold Logic Gate; Said two, three, four input Threshold Logic Gate are made up of the SET/MOS hybrid circuit.
In the utility model one embodiment, described SET/MOS hybrid circuit comprises: PMOS pipe, its source electrode meets power end V
DdOne NMOS pipe, its drain electrode is connected with the drain electrode of said PMOS pipe; And a SET pipe, it is connected with source electrode that said NMOS manages.
The utility model is only by 5 Threshold Logic Gate, and 1 phase inverter and 1 XOR gate constitute, and consumes 7 PMOS pipes altogether, 7 NMOS pipes and 6 SET.The average power consumption of entire circuit is merely 46nW.Compare with CMOS multiplier based on Boolean logic; Number of tubes significantly reduces; Power consumption significantly reduces, and circuit structure has obtained further simplification, helps saving area of chip; Improve the integrated level of circuit, be expected in microprocessor, digital signal processor and image engine, be widely used.
Description of drawings
Fig. 1 is the Threshold Logic Gate synoptic diagram.
Fig. 2 is multiple-grid input SET/MOS hybrid circuit schematic diagram.
Fig. 3 is the SET/MOS multiplier schematic diagram based on voting logic.
Fig. 4 a and Fig. 4 b are the simulated properties curve of multiplier.
Embodiment
Below in conjunction with accompanying drawing and embodiment the utility model is further specified.
As shown in Figure 3; Present embodiment provides a kind of 2 multipliers of SETMOS mixed structure based on voting logic, it is characterized in that: comprise an XOR gate, a phase inverter, four signal sources, three two input Threshold Logic Gate, three input Threshold Logic Gate and one four input Threshold Logic Gate; The first signal source A of described four signal sources
0Be connected with first end of said the one or two input Threshold Logic Gate, first end of the three or two input Threshold Logic Gate, first end of four input Threshold Logic Gate; Secondary signal source B
0Be connected with second end of said the one or two input Threshold Logic Gate, second end of the two or two input Threshold Logic Gate, second end of four input Threshold Logic Gate; The 3rd signal source A
1Be connected with first end of said the two or two input Threshold Logic Gate, first end of three input Threshold Logic Gate; The 4th signal source B
1Be connected with second end of said the 3rd input Threshold Logic Gate, second end of three input Threshold Logic Gate, the 4th end of four input Threshold Logic Gate; The output terminal of said the one or two input Threshold Logic Gate is connected through the 3rd input end of said phase inverter with said three input Threshold Logic Gate; Said two, three, four input Threshold Logic Gate are made up of the SET/MOS hybrid circuit, and its threshold value is 1.5, and its output logic is to calculate total input value according to the weighted value of importing; And total input value and said threshold value compared; More than or equal to said threshold value, then be output as 1, otherwise be output as 0.
The utility model is based on the design that voting logic is carried out multiplier.The logical process of voting logic is more complicated than Boolean logic, can realize complicated more logic function by enough less pipes.Based on the circuit design of voting logic, be expected to the function of intensifier circuit, improve the integrated level of circuit.Because many novel nano electron devices can be supported the method for designing based on voting logic well, the utility model has been chosen single-electronic transistor, and (Single electron transistor SET) designs multiplier.As typical case's representative of nano electron device of new generation, SET has remarkable advantages at aspects such as power consumption, operating rates with respect to traditional microelectronic component, is considered to make low-power consumption of future generation, the desirable basic device of high density VLSI (very large scale integrated circuits).Single-electronic transistor can be compatible mutually with the CMOS silicon technology characteristics; Make the SET/MOS hybrid circuit possess the superior function of SET and metal-oxide-semiconductor; Show extremely low power consumption, extra small device size, stronger driving force and bigger output voltage swing, obtained using widely at aspects such as MULTI-VALUED LOGIC CIRCUIT, D and D/A converter circuit, memory circuitries.Simultaneously, the SET/MOS hybrid circuit can be realized the design of threshold logic cirtuic preferably, can further simplify circuit structure, reduces power consumption, improves the performance of circuit.
The cardinal principle of voting logic is that the weight calculation according to input goes out total input value, total input value and threshold value is compared draw output logic.If total input value then is output as 1, otherwise is 0 more than or equal to threshold value.The logical equatiion that voting logic will satisfy is:
Wherein
W iBe input
X iCorresponding weight,
nBe the number of input,
θBe threshold value.The synoptic diagram of Threshold Logic Gate is as shown in Figure 1.To confirm at first that based on the circuit design of voting logic the voting logic expression formula of circuit, key are to confirm the weight of each input in the circuit and the threshold value of circuit.
In the present embodiment, 2 multipliers be input as A
1A
0And B
1B
0, be output as O
0, O
1, O
2And O
3, its logic function that satisfies is shown in truth table (table one).The logical expression that can be obtained each output by truth table is suc as formula (2), and (3) are shown in (4).O
3, O
2And O
0Be linear function, can directly realize by threshold logic cirtuic.Therefore, O
0, O
2And O
3The voting logic expression formula suc as formula (6), (7) are shown in (8).O
1Realization can be through calculating earlier A
1B
0And A
0B
1, then with A
1B
0And A
0B
1Result of calculation be connected to an XOR gate and realize.
(5)
(7)
Table one
The utility model is used for realizing that the SET/MOS hybrid circuit of voting logic is as shown in Figure 2.This circuit is managed by a PMOS, and the SET of a NMOS pipe and a multiple-grid input is in series.The PMOS pipe is that entire circuit provides bias current as constant current source in the circuit.Because the electric current of SET operate as normal is very little, is generally the nA order of magnitude, so the PMOS pipe should be operated in sub-threshold region.The grid bias V of NMOS pipe
NgFix, its value is slightly larger than the threshold voltage V of NMOS pipe
Th, make the drain voltage of SET be fixed as V
Ng-V
ThGrid voltage V
1, V
2..., V
nBe capacitively coupled on the Coulomb island, SET is mainly worked by the electromotive force of grid voltage control Coulomb island.The SET/MOS hybrid circuit also possesses the characteristics of multiple-grid input, allows a plurality of input voltages and is coupled on the Coulomb island.Through suitable circuit parameter is set, the SET/MOS hybrid circuit can be realized the function of Threshold Logic Gate.Schematic diagram based on 2 multipliers of voting logic is as shown in Figure 3, and this circuit only is made up of 5 Threshold Logic Gate and 1 XOR gate, and wherein XOR gate also is to be made up of the SET/MOS hybrid circuit among Fig. 2.Input is directly connected to the input of SET/MOS hybrid circuit, and the weight of input is embodied by the input coupling capacitance.
The utility model utilizes the HSPICE emulator that 2 multipliers based on voting logic are carried out the function simulating checking.The model of SET is the macro model (Compact macromodel) widely-used at present, that precision is high.This model with the formal definition of electronic circuit in SPICE.The model of metal-oxide-semiconductor uses the forecasting techniques model (Predictive technology model) of 22 nm that generally acknowledge at present.In multiplier circuit, except coupling capacitance and back of the body gate bias voltage, 5 Threshold Logic Gate have identical circuit parameter shown in table two.Coupling capacitance C
3, C
2, C
1, C
0With back of the body gate bias voltage V
Ctrl3,V
Ctrl2, V
Ctrl1, V
Ctrl0Correspond respectively to output O
3, O
2, O
1, O
0C
3, C
2, C
1, C
0Numerical value be respectively 0.026aF, 0.035aF, 0.0525aF, 0.0525aF; V
Ctrl3, V
Ctrl2, V
Ctrl1, V
Ctrl0Be placed as 0.5V respectively, 0.54V, 0.6V, 0.6V.For output O
1In the exclusive or logic gate that uses, the major parameter of its SET is: C
s=C
d=0.1aF, R
s=R
d=350 K Ω, C
g=0.1aF, C
Ctrl=0.2aF, V
Ctrl=0.43V.
Table two
The family curve that emulation obtains is as shown in Figure 4.In Fig. 4 (a), input signal A
1, A
0, B
1, B
0All be made as square wave, added waveform satisfies 16 kinds of logical combinations of 4 inputs, and 0.8 V and 0 V are set to high level and the low level imported respectively.The output waveform that emulation obtains is low level and high level with 0.03V and 0.77V all, shown in Fig. 4 (b).As can be seen from the figure, this output waveform satisfies the truth table (table one) of 2 multipliers, explains that this circuit can realize the logic function of multiplier effectively.
What be noted that the utility model requirement protection here is the connection features of hardware circuit, just is used to let those skilled in the art better understand the utility model as for other relevant design algorithmic descriptions.
The above is merely the preferred embodiment of the utility model, and all equalizations of being done according to the utility model claim change and modify, and all should belong to the covering scope of the utility model.
Claims (2)
1. 2 multipliers of SET/MOS mixed structure based on voting logic is characterized in that: comprise an XOR gate, a phase inverter, four signal sources, three two input Threshold Logic Gate, three input Threshold Logic Gate and one four input Threshold Logic Gate;
First signal source of described four signal sources is connected with first end of said the one or two input Threshold Logic Gate, first end of the three or two input Threshold Logic Gate, first end of four input Threshold Logic Gate;
The secondary signal source is connected with second end of said the one or two input Threshold Logic Gate, second end of the two or two input Threshold Logic Gate, second end of four input Threshold Logic Gate;
The 3rd signal source is connected with first end of said the two or two input Threshold Logic Gate, first end of three input Threshold Logic Gate;
The 4th signal source is connected with second end of said the 3rd input Threshold Logic Gate, second end of three input Threshold Logic Gate, the 4th end of four input Threshold Logic Gate;
The output terminal of said the one or two input Threshold Logic Gate is connected through the 3rd input end of said phase inverter with said three input Threshold Logic Gate; Said two, three, four input Threshold Logic Gate are made up of the SET/MOS hybrid circuit.
2. 2 multipliers of SET/MOS mixed structure based on voting logic according to claim 1, it is characterized in that: described SET/MOS hybrid circuit comprises:
One PMOS pipe, its source electrode connects power end
V Dd
One NMOS pipe, its drain electrode is connected with the drain electrode of said PMOS pipe; And
One SET pipe, its source electrode with said NMOS pipe is connected.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102545881A (en) * | 2012-01-05 | 2012-07-04 | 福州大学 | Semiconductor field-effect transistor/metal-oxide-semiconductor (SET/MOS) mixed structure 2-bit multiplier based on threshold logic |
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2012
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102545881A (en) * | 2012-01-05 | 2012-07-04 | 福州大学 | Semiconductor field-effect transistor/metal-oxide-semiconductor (SET/MOS) mixed structure 2-bit multiplier based on threshold logic |
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