CN102545881B - Semiconductor field-effect transistor/metal-oxide-semiconductor (SET/MOS) mixed structure 2-bit multiplier based on threshold logic - Google Patents
Semiconductor field-effect transistor/metal-oxide-semiconductor (SET/MOS) mixed structure 2-bit multiplier based on threshold logic Download PDFInfo
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Abstract
The invention relates to the technical field of integrated circuits, in particular to a semiconductor field-effect transistor/metal-oxide-semiconductor (SET/MOS) mixed structure 2-bit multiplier which only comprises five threshold logic gates, one phase inverter and one exclusive-OR gate, and consumes a total of seven P-channel metal oxide semiconductor (PMOS) tubes, seven N-channel metal oxide semiconductor (NMOS) tubes and six semiconductor field-effect transistors (SETs). The average power consumption of a whole circuit is only 46nW. Compared with a complementary metal-oxide-semiconductor (CMOS) multiplier based on Boolean logic, the number of tubes is greatly reduced, the power consumption is significantly reduced, the structure of the circuit is further simplified, the area of a chip is favorably saved, the integration of the circuit is improved, and the SET/MOS mixed structure 2-bit multiplier based on threshold logic is expected to be widely applied to microprocessors, digital signal processors and image engines.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly a kind of 2 multipliers of the SETMOS mixed structure based on voting logic that formed by nano-device.
Background technology
Along with the characteristic dimension of integrated circuit enters deep-submicron, the resistance further developing not only derives from manufacturing process, is more the physical restriction that small size, High Density Integration bring, as short-channel effect, and high-field effect, drain electrode causes potential barrier decline effect etc.Multiplier, as a kind of important combinational logic circuit, is widely used in microprocessor, digital signal processor and image engine.Traditional multiplier based on CMOS technology forms by multistage full adder with door, need to consume more CMOS transistor, and circuit structure is complicated, and integrated level is not high.These features make traditional Multiplier Design method can not meet the performance requirement of the integrated circuit day by day improving.
Summary of the invention
The object of this invention is to provide 2 multipliers of a kind of SET/MOS mixed structure based on voting logic.
The present invention adopts following scheme to realize: 2 multipliers of a kind of SET/MOS mixed structure based on voting logic, is characterized in that: comprise an XOR gate, a phase inverter, four signal sources, three two input Threshold Logic Gate, three input Threshold Logic Gate and one four input Threshold Logic Gate; The first signal source of four described signal sources is connected with the first end of described the one or two input Threshold Logic Gate, the first end of the first end of the three or two input Threshold Logic Gate, four input Threshold Logic Gate; Secondary signal source is connected with the second end of described the one or two input Threshold Logic Gate, the second end of the second end of the two or two input Threshold Logic Gate, four input Threshold Logic Gate; The 3rd signal source is connected with the first end of described the two or two input Threshold Logic Gate, the first end of three input Threshold Logic Gate; The 4th signal source is connected with the second end of described the 3rd input Threshold Logic Gate, the 4th end of the second end of three input Threshold Logic Gate, four input Threshold Logic Gate; The output terminal of described the one or two input Threshold Logic Gate is connected with the 3rd input end of described three input Threshold Logic Gate through described phase inverter; Described two, three, four input Threshold Logic Gate consist of SET/MOS hybrid circuit, and its threshold value is 1.5, and its output logic is to calculate total input value according to the weighted value of input, and total input value and described threshold value are compared, be more than or equal to described threshold value, be output as 1, otherwise be output as 0.
In an embodiment of the present invention, the voting logic of described two, three, four input Threshold Logic Gate meets logical equatiion:
Wherein
w ifor input
x icorresponding weight,
nfor the number of input,
θfor threshold value.
In an embodiment of the present invention, described SET/MOS hybrid circuit comprises: a PMOS pipe, its source electrode meets power end V
dd; One NMOS pipe, its drain electrode is connected with the drain electrode of described PMOS pipe; And a SET pipe, it is connected with the source electrode of described NMOS pipe.
In an embodiment of the present invention, the parameter of described PMOS pipe meets: channel width W
pbe 22 nm, channel length L
pbe 66 nm, grid voltage V
pgbe 0.4 V; The parameter of described NMOS pipe meets: channel width W
nbe 22 nm, channel length L
nbe 66 nm, grid voltage V
ngbe 0.4 V; The parameter of described SET pipe meets: tunnel junctions capacitor C
s, C
dbe 0.1 aF, tunnel junctions resistance R
s, R
dbe 150 K Ω, back of the body gate capacitance C
ctrlbe 0.1050 aF.
The present invention only consists of 5 Threshold Logic Gate and 1 XOR gate, consumes altogether 7 PMOS pipes, 7 NMOS pipes and 6 SET.The average power consumption of whole circuit is only 46nW.Compare with the CMOS multiplier based on Boolean logic, number of tubes greatly reduces, power consumption significantly reduces, circuit structure has obtained further simplification, be conducive to save the area of chip, the integrated level that improves circuit, is expected to be widely used in microprocessor, digital signal processor and image engine.
Accompanying drawing explanation
Fig. 1 is Threshold Logic Gate schematic diagram.
Fig. 2 is multiple-grid input SET/MOS hybrid circuit schematic diagram.
Fig. 3 is the SET/MOS multiplier schematic diagram based on voting logic.
The simulated properties curve that Fig. 4 a and Fig. 4 b are multiplier.
Embodiment
Below in conjunction with drawings and Examples, the present invention will be further described.
As shown in Figure 3, the present embodiment provides a kind of SET/MOS mixed structure based on voting logic 2 multipliers, it is characterized in that: comprise an XOR gate, four signal sources, three two input Threshold Logic Gate, three input Threshold Logic Gate and one four input Threshold Logic Gate; The first signal source A of four described signal sources
0be connected with the first end of described the one or two input Threshold Logic Gate, the first end of the first end of the three or two input Threshold Logic Gate, four input Threshold Logic Gate; Secondary signal source B
0be connected with the second end of described the one or two input Threshold Logic Gate, the second end of the second end of the two or two input Threshold Logic Gate, four input Threshold Logic Gate; The 3rd signal source A
1be connected with the first end of described the two or two input Threshold Logic Gate, the first end of three input Threshold Logic Gate; The 4th signal source B
1be connected with the second end of described the 3rd input Threshold Logic Gate, the 4th end of the second end of three input Threshold Logic Gate, four input Threshold Logic Gate; The output terminal of described the one or two input Threshold Logic Gate is connected with the 3rd input end of described three input Threshold Logic Gate through described phase inverter; Described two, three, four input Threshold Logic Gate consist of SET/MOS hybrid circuit, and its threshold value is 1.5, and its output logic is to calculate total input value according to the weighted value of input, and total input value and described threshold value are compared, be more than or equal to described threshold value, be output as 1, otherwise be output as 0.
The present invention carries out the design of multiplier based on voting logic.The logical process of voting logic is more complicated than Boolean logic, can realize more complicated logic function by enough less pipes.Circuit design based on voting logic, is expected to the function of intensifier circuit, improves the integrated level of circuit.Because many novel nano electron devices can be supported the method for designing based on voting logic well, the present invention has chosen single-electronic transistor (Single electron transistor, SET) and has designed multiplier.As the Typical Representative of nano electron device of new generation, SET has obvious advantage at aspects such as power consumption, operating rates with respect to traditional microelectronic component, is considered to manufacture low-power consumption of future generation, the desirable basic device of high density VLSI (very large scale integrated circuit).Single-electronic transistor can with CMOS silicon technology compatible feature mutually, make SET/MOS hybrid circuit possess the superior function of SET and metal-oxide-semiconductor, show extremely low power consumption, extra small device size, stronger driving force and larger output voltage swing, at aspects such as MULTI-VALUED LOGIC CIRCUIT, D and D/A converter circuit, memory circuitries, be widely used.Meanwhile, SET/MOS hybrid circuit can be realized the design of threshold logic cirtuic preferably, can further simplify circuit structure, reduces power consumption, improves the performance of circuit.
The cardinal principle of voting logic is to go out total input value according to the weight calculation of input, and total input value and threshold value are compared and draw output logic.If total input value is more than or equal to threshold value, is output as 1, otherwise is 0.Voting logic will be satisfied logical equatiion be:
(1)
Wherein
w ifor input
x icorresponding weight,
nfor the number of input,
θfor threshold value.The schematic diagram of Threshold Logic Gate as shown in Figure 1.First circuit design based on voting logic will determine the voting logic expression formula of circuit, and key is to determine the weight of each input and the threshold value of circuit in circuit.
In the present embodiment, 2 multipliers be input as A
1a
0and B
1b
0, be output as O
0, O
1, O
2and O
3, its satisfied logic function is as shown in truth table (table one).By truth table, can be obtained the logical expression of each output suc as formula (2), (3), shown in (4).O
3, O
2and O
0for linear function, can directly by threshold logic cirtuic, be realized.Therefore, O
0, O
2and O
3voting logic expression formula suc as formula (6), (7), shown in (8).O
1realization can be by first calculating A
1b
0and A
0b
1, then by A
1b
0and A
0b
1result of calculation be connected to an XOR gate and realize.
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Table one
The SET/MOS hybrid circuit that the present invention is used for realizing voting logic as shown in Figure 2.This circuit is managed by a PMOS, and the SET of a NMOS pipe and a multiple-grid input is in series.In circuit, PMOS pipe provides bias current as constant current source for whole circuit.Because the electric current of the normal work of SET is very little, be generally the nA order of magnitude, so PMOS pipe should be operated in sub-threshold region.The grid bias V of NMOS pipe
ngfix, its value is slightly larger than the threshold voltage V of NMOS pipe
th, make the drain voltage of SET be fixed as V
ng-V
th.Grid voltage V
1, V
2..., V
nbe capacitively coupled on coulomb island, SET is mainly worked by the electromotive force on grid voltage control coulomb island.SET/MOS hybrid circuit also possesses the feature of multiple-grid input, has allowed a plurality of input voltages to be coupled on coulomb island.By suitable circuit parameter is set, SET/MOS hybrid circuit can be realized the function of Threshold Logic Gate.As shown in Figure 3, this circuit only consists of 5 Threshold Logic Gate and 1 XOR gate the schematic diagram of 2 multipliers based on voting logic, and wherein XOR gate is also that SET/MOS hybrid circuit in Fig. 2 forms.Input is directly connected to the input of SET/MOS hybrid circuit, and the weight of input embodies by inputting coupling capacitance.
The present invention utilizes HSPICE emulator to carry out the simulating, verifying of function based on 2 multipliers of voting logic.The model of SET be widely used at present, macro model (Compact macromodel) that precision is high.This model with the formal definition of electronic circuit in SPICE.The model of metal-oxide-semiconductor is used the forecasting techniques model (Predictive technology model) of 22 nm that generally acknowledge at present.In multiplier circuit, except coupling capacitance and back of the body gate bias voltage, 5 Threshold Logic Gate have identical circuit parameter as shown in Table 2.Coupling capacitance C
3, C
2, C
1, C
0with back of the body gate bias voltage V
ctrl3,v
ctrl2, V
ctrl1, V
ctrl0correspond respectively to output O
3, O
2, O
1, O
0.C
3, C
2, C
1, C
0numerical value be respectively 0.026aF, 0.035aF, 0.0525aF, 0.0525aF; V
ctrl3, V
ctrl2, V
ctrl1, V
ctrl0be placed as respectively 0.5V, 0.54V, 0.6V, 0.6V.For output O
1in the exclusive or logic gate that uses, the major parameter of its SET is: C
s=C
d=0.1aF, R
s=R
d=350 K Ω, C
g=0.1aF, C
ctrl=0.2aF, V
ctrl=0.43V.
Table two
The family curve that emulation obtains as shown in Figure 4.In Fig. 4 (a), input signal A
1, A
0, B
1, B
0all be made as square wave, added waveform meets 16 kinds of logical combinations of 4 inputs, and 0.8 V and 0 V are set to respectively high level and the low level of input.It is low level and high level that the output waveform that emulation obtains all be take 0.03V and 0.77V, as shown in Fig. 4 (b).As can be seen from the figure, this output waveform meets the truth table (table one) of 2 multipliers, illustrates that this circuit can realize the logic function of multiplier effectively.
The foregoing is only preferred embodiment of the present invention, all equalizations of doing according to the present patent application the scope of the claims change and modify, and all should belong to covering scope of the present invention.
Claims (2)
1. 2 multipliers of the SET/MOS mixed structure based on voting logic, is characterized in that: comprise an XOR gate, a phase inverter, four signal sources, the one or two input Threshold Logic Gate, the two or two input Threshold Logic Gate, the three or two input Threshold Logic Gate, three input Threshold Logic Gate and one four input Threshold Logic Gate;
The first signal source of four described signal sources is connected with the first end of described the one or two input Threshold Logic Gate, the first end of the first end of the three or two input Threshold Logic Gate, four input Threshold Logic Gate;
Secondary signal source is connected with the second end of described the one or two input Threshold Logic Gate, the second end of the second end of the two or two input Threshold Logic Gate, four input Threshold Logic Gate;
The 3rd signal source is connected with the first end of described the two or two input Threshold Logic Gate, the first end of three input Threshold Logic Gate;
The 4th signal source is connected with the second end of described the three or two input Threshold Logic Gate, the 4th end of the second end of three input Threshold Logic Gate, four input Threshold Logic Gate;
The output terminal of described the one or two input Threshold Logic Gate is connected with the 3rd input end of described three input Threshold Logic Gate through described phase inverter; Described the one or two input Threshold Logic Gate, the two or two input Threshold Logic Gate, the three or two input Threshold Logic Gate, three input Threshold Logic Gate and four input Threshold Logic Gate form by SET/MOS hybrid circuit, its threshold value is 1.5, its output logic is to calculate total input value according to the weighted value of input, and total input value and described threshold value are compared, be more than or equal to described threshold value, be output as 1, otherwise be output as 0;
The voting logic of described the one or two input Threshold Logic Gate, the two or two input Threshold Logic Gate, the three or two input Threshold Logic Gate, three input Threshold Logic Gate and four input Threshold Logic Gate meets logical equatiion:
Wherein
w ifor input
x icorresponding weight,
nfor the number of input,
θfor threshold value;
Described SET/MOS hybrid circuit comprises:
One PMOS pipe, its source electrode connects power end
v dd;
One NMOS pipe, its drain electrode is connected with the drain electrode of described PMOS pipe; And
One SET pipe, it is connected with the source electrode of described NMOS pipe.
2. 2 multipliers of the SET/MOS mixed structure based on voting logic according to claim 1, is characterized in that: the parameter of described PMOS pipe meets: channel width
w pbe 22 nm, channel length
l pbe 66 nm, grid voltage
v pgbe 0.4 V; The parameter of described NMOS pipe meets: channel width
w nbe 22 nm, channel length
l nbe 66 nm, grid voltage
v ngbe 0.4 V; The parameter of described SET pipe meets: tunnel junctions electric capacity
c s,
c dbe 0.1 aF, tunnel junctions resistance
r s,
r dbe 150 K Ω, back of the body gate capacitance
c ctrlbe 0.1050 aF.
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