CN203675093U - Dynamic exclusive-OR gate design based on floating gate technology - Google Patents

Dynamic exclusive-OR gate design based on floating gate technology Download PDF

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CN203675093U
CN203675093U CN 201420010075 CN201420010075U CN203675093U CN 203675093 U CN203675093 U CN 203675093U CN 201420010075 CN201420010075 CN 201420010075 CN 201420010075 U CN201420010075 U CN 201420010075U CN 203675093 U CN203675093 U CN 203675093U
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complementary
exclusive
circuit
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output
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胡晓慧
刘承成
杭国强
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浙江大学城市学院
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Abstract

The utility model discloses a dynamic exclusive-OR gate design based on a floating gate technology. The dynamic exclusive-OR gate design based on the floating gate technology comprises a complementary and operational output circuit and a complementary exclusive or operational output circuit. The complementary and operational output circuit generates the complementary output signals (x*y) and (anti-(x*y)), and the complementary exclusive or operational output circuit generates the complementary output signals (x xor y) and (anti-(x xor y)), and the (anti-(x*y)) signal is used as an input signal of the complementary exclusive or operational output circuit. The beneficial effects of the utility model are that: the circuits utilize the natural attribute that the threshold value possesses by an MOS transistor is easy to control, the application of the general MOS transistors and the interconnection lines in the circuits is reduced greatly, the structure of the circuits is simplified and the power consumption is reduced; by the logic minimization, the AND operation output signal (anti-(x*y)) is applied as a control end to control the complementary exclusive or operational output circuit, thereby increasing the relational degree of the whole circuits, and simplifying the circuits; meanwhile, with the application of dynamic technology, the work processes and states of the circuits are controlled flexibly further, and the power consumption of the circuits is reduced.

Description

基于浮栅技术的动态异或门设计 Dynamic floating gate-based design XOR gate

技术领域 FIELD

[0001] 本实用新型涉及一种动态异或门设计,更具体说,它涉及一种基于浮栅技术的动态异或门设计。 [0001] The present invention relates to a dynamic XOR gate design, and more particularly, it relates to a dynamic art floating gate XOR gate design.

背景技术 Background technique

[0002] 随着便携式设备的增多,集成电路对于体积和功耗的要求也更加严格。 [0002] With the increase in portable devices, integrated circuits and more stringent requirements for size and power consumption. 在实现低功耗的方法中,动态电路引起越来越多的关注。 In the process to achieve low power consumption, the dynamic circuit caused more and more attention. 在动态电路中,动态能耗控制是一项极为重要的功能,它针对电路器件是否在使用及使用的程度,通过开关来控制器件,使得不需要工作的器件关闭,从而不消耗能量。 In the dynamic circuit, the dynamic power control is a vital function, whether it is in use and the degree of use, for the circuit to control the device through the switching device, so that the device does not need to work off, so does not consume energy. 同时动态电路在速度、芯片面积等方面也比静态电路有优势。 Meanwhile dynamic circuits in speed and area advantage over static chips circuit.

[0003] 多输入浮栅MOS器件是一种具有复杂功能的MOS管,它具有多个输入栅极和一个浮栅极,大大增强了单个晶体管的功能,从而有效地降低了整个电路的复杂度,大大减少了互连线数。 [0003] The multi-input floating gate MOS devices is a complex function having a MOS transistor, having a plurality of input gate and a floating gate, greatly enhancing the function of a single transistor, thereby effectively reduces the complexity of the overall circuit , greatly reducing the number of interconnections. 另一方面,由于多输入浮栅MOS管对栅极电平的加权求和是通过输入栅与浮栅间的电容耦合来实现的,因此具有极低功耗的特点。 On the other hand, since the multi-input floating gate MOS transistor gate weighted sum level is achieved by capacitive coupling between the input gate and the floating gate, thus with very low power consumption.

发明内容 SUMMARY

[0004] 本实用新型的目的是克服现有技术中的不足,提供一种结构合理简化,功耗低和工作状态可控的基于浮栅技术的动态异或门设计。 [0004] The object of the present invention is to overcome the disadvantages of the prior art, to provide a reasonable simplifying a structure and low power operating state controlled based on a dynamic floating gate XOR gate design.

[0005] 这种基于浮栅技术的动态异或门设计,包括互补与运算输出电路和互补异或运算输出电路; [0005] Based on this dynamic floating gate XOR gate design techniques, including complementary to the arithmetic circuit output and the complementary output of the exclusive OR operation circuit;

[0006] 所述互补与运算输出电路产生互补的输出信号X *y和ϋ,所述互补异或运算输 [0006] The complementary output of the operational circuit generates a complementary output signal X * y and ϋ, said complementary input exclusive OR operation

出电路产生互补的输出信号;c田和,同时信号作为所述互补异或运算输出电路的一个输入信号; Circuit generates complementary output signals; C fields and, at the same time as the complementary signal output circuit of the exclusive OR operation an input signal;

[0007] 所述互补与运算输出电路包含:时钟动态控制电路,包括pMOS管m3和m7,nM0S管m6和m4 ;两个稳压箝位电路,包括pMOS管m2和普通反相器INVl,pM0S管m8和普通反相器INV2 ;输入控制电路,包括三输入浮栅nMOS管ml和普通nMOS管m5 ; [0007] The complementary output of the operational circuit comprising: a clock dynamic control circuit comprising pMOS transistor m3 and m7, nM0S tube m6 and M4; two regulator clamping circuit comprising pMOS transistor m2 and ordinary inverters INVl, pM0S m8 tube ordinary inverter INV2; an input control circuit comprises a three-input floating gate of the nMOS transistor and the common nMOS transistor M5 ml;

[0008] 所述互补异或运算输出电路包含:时钟动态控制电路,包括pMOS管mil和ml5,nMOS管ml2和ml4 ;两个稳压箝位电路,包括pMOS管mlO和普通反相器INV3,pMOS管ml6和普通反相器INV4 ;输入控制电路,包括四输入浮栅nMOS管m9和普通nMOS管ml3 ; [0008] The complementary output of the exclusive OR operation circuit comprising: a clock dynamic control circuit comprising pMOS transistor mil and ml5, nMOS tube ml2 and ML4; two zener clamp circuit comprises a pMOS transistor and an ordinary inverter mlO and INV3, ml6 pMOS transistor and the inverter INV4 is normal; input control circuit, including a four-input floating gate of the nMOS transistor m9 and ML3 ordinary nMOS transistor;

[0009]所述 pMOS 管m3、m7、m2、m8、mll、ml5、ml0 和ml6 的源级接工作电压VDD,所述nMOS管m4和ml2的源级接地; [0009] The pMOS transistor m3, m7, m2, m8, mll, ml5, ml0 and a source connected to the operating voltage level of VDD ml6, the nMOS source electrode is grounded and m4 ml2 the tube;

[0010] 所述时钟动态控制端,包括pMOS管m3和m7, nMOS管m6和m4及pMOS管mil和ml5, nMOS管ml2和ml4的栅极接时钟信号elk ;所述三输入nMOS管ml的三个输入分别接 [0010] The dynamic clock control terminal, and comprises a pMOS transistor M7 m3, m4, and m6 of the nMOS and pMOS transistor mil and ML5, and the gate of the nMOS ml2 to the clock signal elk ml4; said three-input of the nMOS ml three inputs are connected

X、y、GND ;所述普通反相器INVl和INV2的输出分别接与运算输出信号xy和.XY所述四输入nMOS管m9的四个输入分别接x、y、^和GND,其中i的权重是其余三个输入权重的2倍;所述普通反相器INV3和INV4的输出分别接异或运算输出信号;^©丨和^ ;所 X, y, GND; the normal output of inverter INVl and INV2 are respectively connected to the four input and output of the operational signal xy .XY the four-input are respectively connected to the nMOS transistor m9 x, y, ^ and GND, where i 2 times the weight of the heavy weight of the remaining three inputs; the output of the inverter INV3 and INV4 common are respectively connected the output signal of the exclusive oR operation; and Shu ^ © ^; the

述稳压箝位电路中pMOS管m2、m8、ml0、ml6的栅极分别接输出信号xy和χ.ν χ㊉V和 Said clamp circuits pMOS transistor regulator m2, m8, ml0, a gate connected to the output signal are ml6 xy and χ.ν χ㊉V and

[0011] 本实用新型的有益效果是:电路利用了浮栅MOS管所具有的阈值易于控制这一自然属性,极大的减少了电路中普通MOS管和互联线的运用,简化了电路结构,减小了功耗; [0011] The present invention has the advantages that: a circuit using the floating gate MOS transistor has a threshold that is easy to control the natural properties, greatly reducing the use of the ordinary MOS transistor and interconnect lines circuit, simplifying the circuit configuration, power consumption is reduced;

通过逻辑化简,运用与运算输出&作为一个控制端来控制互补异或运算输出电路,增加 By simplification logic, the output of the operational use as a & complementary control terminal to control the output of the exclusive OR operation circuit, increasing

了整个电路的关联度,简化了电路。 Association of the entire circuit, simplifying the circuit. 同时动态技术的运用,进一步灵活的控制了电路的工作过程和状态,降低了电路功耗。 While the use of dynamic technology, more flexible control of the process and the working state of the circuit, the circuit reduces power consumption.

附图说明 BRIEF DESCRIPTION

[0012] 图1为η型和P型多输入浮栅MOS管符号和电容模型; [0012] FIG. 1 is a P-type and η-type multi-input floating-gate MOS transistor and a capacitor model symbols;

[0013] 图2为本实用新型电路原理图。 [0013] FIG. 2 is a schematic circuit diagram invention.

具体实施方式 Detailed ways

[0014] 下面结合附图和实施例对本实用新型做进一步描述。 Figures and examples further describe the present invention do [0014] The following binding. 虽然本实用新型将结合较佳实施例进行描述,但应知道,并不表示本实用新型限制在所述实施例中。 Although the present invention will be described in conjunction with preferred embodiments, it should be understood, it does not mean to limit the present invention in the embodiment. 相反,本实用新型将涵盖可包含在有附后权利要求书限定的本实用新型的范围内的替换物、改进型和等同物。 In contrast, the present disclosure is to cover may be included within the scope of the present invention, the appended claims books defined alternatives, modification, and equivalents thereof.

[0015] 多输入浮栅MOS管是近年来提出的一种具有功能性强、阈值控制灵活等特点的新型器件,人们已在模拟、数字和神经网络等多个领域对它的应用开展了深入研究。 [0015] The multi-input floating gate MOS transistor is recently proposed a functional, flexible control characteristics of the threshold value of the new device, it has been in many areas of its analog, digital, and neural network applications have conducted in-depth the study. 这种器件的加工工艺与标准的双层多晶硅CMOS工艺完全兼容,它的符号表示及其电容模型如图1所示。 Processing of such devices with the standard double poly CMOS process is fully compatible with, and its sign indicates capacitance model shown in Fig. 它具有多个输入栅极和一个浮栅极,其中浮栅由第一层多晶硅形成,多个输入控制栅则由第二层多晶硅形成。 Having a plurality of input gate and a floating gate, wherein the floating gate is formed from a first polysilicon layer, a plurality of input control gate formed by the second polysilicon layer. 输入端与浮栅之间通过电容实现耦合。 Between the input terminal and the floating gate through capacitive coupling achieved. 图中Vf表示浮栅上的电压, FIG Vf represents the voltage on the floating gate,

Vtl为衬底电压,VpV2'......、vn为输入信号电压。 A substrate voltage Vtl, VpV2 '......, vn is the input signal voltage. Ctl是浮栅与衬底之间的稱合电容,它主要 Ctl is called combined capacitance between the floating gate and the substrate, it is mainly

由栅氧化层电容Cm构成,C1Xy……、Cn为各个输入栅与浮栅之间的耦合电容。 Is constituted by the gate oxide capacitance Cm, C1Xy ......, Cn is the coupling capacitance between each input gate and the floating gate. 图中D和S分别表示漏极和源极。 D and S in FIG drain and source, respectively. 浮栅上的净电荷Qf由下式给出: Qf net charge on the floating gate is given by:

[0016] [0016]

Figure CN203675093UD00041

[0017] 对于n沟道浮栅MOS管,衬底接地,因此Vtl=O15假设浮栅上的初始电荷为零,根据电荷守恒定律,由上式可得: [0017] For the n-channel floating gate MOS transistor, the substrate is grounded, so Vtl = O15 assume that the initial zero charge on the floating gate, the charge conservation law, the above equation can be obtained:

Figure CN203675093UD00042
Figure CN203675093UD00051

[0020] 设Vt为由浮栅端看进去的管子的阈值电压,则当VF>VT时管子导通。 [0020] Vt provided by looking into the end of the floating gate threshold voltage of the tube, then when VF> VT is turned tube. 由式(2)和 By the formula (2), and

(3)可以看出,多输入浮栅MOS管能够对各栅极输入信号加权求和,用计算得到的求和结果去控制MOS管的“开”和“关”。 (3) It can be seen, a multi-input floating gate MOS transistor can be input to each gate signal weighted summation with the summation result to the calculated control MOS transistor "on" and "off." 注意到它在浮栅上进行的所有输入信号的加权求和运算是利用电容耦合效应以电压模式来进行的,这显示了它具有比电流模式求和技术更优秀的低功耗特性。 Note that all the weighted summation of the input signal which is carried on the floating gate by capacitive coupling effect is in the mode for voltage, which shows that it has better than a current summing mode of low power consumption technology. 如果以Vl作为输入端,其他输入端作为控制端,则有: If Vl as an input to the other input terminal as the control terminal, there are:

[0021] [0021]

Figure CN203675093UD00052

[0022] 这样,由V1端看进去的管子的阈值电压V*tl可以表示为: [0022] Thus, to see the inside of the tube end V1 of the threshold voltage V * tl may be expressed as:

[0023] [0023]

Figure CN203675093UD00053

[0024] 上式表明,无需调整Vt,只要通过改变耦合电容之间的比例关系或改变控制端电压Vi就可以改变浮栅MOS管相对于输入信号V1的阈值电压,从而控制MOS管的导通和截止。 [0024] The above equations show no adjustment Vt of, as long as it can change the floating gate MOS transistor with by changing the proportional relationship between the coupling capacitance or change the control terminal voltage Vi to the input threshold voltage signal V1, thereby controlling the conduction of MOS tube and off. 对于P沟道浮栅MOS管,衬底通常接电路最高电压源(如VDD),因此式(I)中Vci=Vdd,式 For P-channel floating gate MOS transistor, the substrate is typically connected to the highest voltage source circuit (e.g., the VDD), thus the formula (I), Vci = Vdd, formula

(2)- (5)需作相应修正。 (2) - (5) need to be amended accordingly.

[0025] 本发明的一种基于浮栅技术的动态异或门电路如图2所示。 One kind of [0025] the present invention is based on floating gate technology dynamic exclusive OR gate circuit shown in Fig.

[0026] 包括互补与运算输出电路和互补异或运算输出电路。 [0026] The output circuit comprises complementary to the arithmetic operation and the complementary output of the exclusive OR circuit.

[0027] 所述互补与运算输出电路产生互补的输出信号X *y和;所述互补异或运算输 [0027] The complementary output of the operational circuit generates a complementary output signal X * y and; said complementary input exclusive OR operation

出电路产生互补的信号I© !;和,同时V信号作为所述互补异或运算输出电路的一个输入信号。 Complementary signal generating circuit I ©;! And, at the same time as the complementary signal V exclusive OR operation of the output circuit of an input signal.

[0028] 所述互补与运算输出电路包含:时钟动态控制电路,包括pMOS管m3和m7,nM0S管m6和m4 ;两个稳压箝位电路,包括pMOS管m2和普通反相器INVl,pM0S管m8和普通反相器INV2 ;输入控制电路,包括三输入浮栅nMOS管ml和普通nMOS管m5。 [0028] The complementary output of the operational circuit comprising: a clock dynamic control circuit comprising pMOS transistor m3 and m7, nM0S tube m6 and M4; two regulator clamping circuit comprising pMOS transistor m2 and ordinary inverters INVl, pM0S m8 tube ordinary inverter INV2; an input control circuit comprises a three-input floating gate of the nMOS transistor ml and the nMOS normal m5.

[0029] 所述互补异或运算输出电路包含:时钟动态控制电路,包括pMOS管mil和ml5,nMOS管ml2和ml4 ;两个稳压箝位电路,包括pMOS管mlO和普通反相器INV3,pMOS管ml6和普通反相器INV4 ;输入控制电路,包括四输入浮栅nMOS管m9和普通nMOS管ml3。 [0029] The complementary output of the exclusive OR operation circuit comprising: a clock dynamic control circuit comprising pMOS transistor mil and ml5, nMOS tube ml2 and ML4; two zener clamp circuit comprises a pMOS transistor and an ordinary inverter mlO and INV3, ml6 pMOS transistor and the inverter INV4 is normal; input control circuit, including a four-input floating gate of the nMOS transistor m9 and the nMOS general ml3.

[0030]所述 pMOS 管m3、m7、m2、m8、mll、ml5、ml0 和ml6 的源级接工作电压VDD,所述nMOS管m4和ml2的源级接地。 [0030] The pMOS transistor m3, m7, a source electrode connected to the operating voltage VDD m2, m8, mll, ml5, ml0 and ml6 of the nMOS transistor and the source electrode is grounded ml2 of m4.

[0031] 所述时钟动态控制端,包括pMOS管m3和m7, nMOS管m6和m4及pMOS管mil和ml5, nMOS管ml2和ml4的栅极接时钟信号elk ;所述三输入nMOS管ml的三个输入分别接 [0031] The dynamic clock control terminal, and comprises a pMOS transistor M7 m3, m4, and m6 of the nMOS and pMOS transistor mil and ML5, and the gate of the nMOS ml2 to the clock signal elk ml4; said three-input of the nMOS ml three inputs are connected

X、Y、GND ;所述普通反相器INVl和INV2的输出分别接与运算输出信号xy和ϋ.所述 X, Y, GND; the normal inverters INVl and INV2 are respectively connected to the output of the output operation of the signal xy, and ϋ.

9四输入nMOS管m9的四个输入分别接x、y、^和GND,其中G的权重是其余三个输入权重的2倍;所述普通反相器INV3和INV4的输出分别接异或运算输出信号χΘ)/和W ;所述稳压箝位电路中pMOS管m2、m8、mlO、ml6的栅极分别接输出信号xy和τ..ν、λ 9 ι和x® y 9 four-input four inputs respectively connected to the nMOS transistor m9 x, y, ^ and GND, wherein the weight G of the heavy weight is twice the remaining three input power; the common output of the inverter INV3 and INV4 are respectively connected with an exclusive OR operation output signal χΘ) / and W is; the pMOS transistor regulator clamping circuit m2, m8, mlO, a gate connected to the output signal are ml6 xy and τ..ν, λ 9 ι and x® y

[0032] 本设计中所采用的三输入浮栅MOS管ml的输入端(Vl=x、V2=y、V3=GND)权重相同,即C1=C2=C3=C ; [0032] The design used in the three-input floating gate MOS transistor of the input terminal ml (Vl = x, V2 = y, V3 = GND) the same weight, i.e. C1 = C2 = C3 = C;

[0033] 根据公式(4)只需 [0033] According to Equation (4) only

[0034] [0034]

Figure CN203675093UD00061

[0037] 本设计中所采用的四输入浮栅MOS管的m9的输入端(Vl=x、V2=y、V3=GND、V4=^7)的权重为:C1=C2=C3=C,C4=2C ; [0037] The input terminal of a four-input floating gate MOS transistor m9 in the present design employed in (Vl = x, V2 = y, V3 = GND, V4 = ^ 7) a weight of: C1 = C2 = C3 = C, C4 = 2C;

[0038] 根据公式(4),只需 [0038] According to Equation (4), only

Figure CN203675093UD00062

[0042] 当elk为低电平时,1113、1]17、1]111、1]115导通,所述一种基于浮栅技术的动态异或门电 [0042] When elk is low, 1113,1] 17,1] 111,1] 115 is turned on, the floating gate technology based on dynamic XOR gate electrically

路处于预充电状态,时钟动态控制电路将输出X *y、W、预置为低电平,同时箝位电路将输出电压进一步稳定。 Road precharged state, the dynamic control circuit outputs the clock X * y, W, preset low while the output voltage clamp circuit further stabilized.

[0043] 当elk为高电平时,m4、m6、ml2、ml4导通,所述一种基于浮栅技术的动态异或门电路处于运算求值状态,此时互补与运算输出电路和互补异或运算输出电路的工作状态分别为: [0043] When elk is high, m4, m6, ml2, ml4 turned on, the floating gate technology based on dynamic exclusive OR gate circuit is in the operation state is evaluated, this time with the complementary output of the operational circuit and the complementary iso or the operating state of the output circuit operation are as follows:

[0044] 输入X、y通过三输入nMOS浮栅管ml决定xy的输出,并通过m5管决定 [0044] The input X, y by a three-input floating gate nMOS ml tube xy decision output, and through the tube decision m5

状态,根据公式(6):当X、y均为高电平,ml导通,xy为高电平,m5截止,.ν..ι.为低电平;当x、y中至少有一个为低电平时,ml截止,m5导通,Xy为低电平"ι力高电平。 State, according to the equation (6): When X, y are high, turned ml, XY is high, m5 off, .ν..ι is low; and when x, y at least one of is low, ml oFF, m5 is turned on, Xy low "ι high force.

[0045] 输入X、y、XV通过四输入nMOS浮栅管m9决定x®.)"的状态,并通过ml3管决定χθ ν的状态,根据公式(7):当^为I时,x、y中只要有一个为1,m9导通,λ® ,为高电平,ml3截止,.χΆν保持低电平;当1.}为O时,无论X、y的状态怎样,m9均截止,x®y为低电平,ml3导通,为高电平。 Status [0045] The input X, y, XV by a four-input floating gate nMOS tube m9 decision x®) "and determine the status ml3 χθ ν tube, according to the equation (7): When ^ when I, x, y as long as there is a 1, m9 is turned on, λ®, is high, ML3 off, .χΆν remain low; when O is 1}, regardless of X, y what state, M9 are turned off, x®y low, ML3 turned high.

[0046] 以φ表示任意值。 [0046] represents any value φ. 根据上面的工作过程,可以总结出所述一种基于浮栅技术的动态异或门电路的工作状态如下表所示: The above working process, it can be concluded based on the technique of dynamic floating gate exclusive OR gate circuit of the operating state as follows:

[0047] [0047]

Figure CN203675093UD00071

Claims (1)

1.一种基于浮栅技术的动态异或门设计,其特征在于:包括互补与运算输出电路和互补异或运算输出电路; 所述互补与运算输出电路产生互补的输出信号Xy和 A floating gate technology based on dynamic XOR gate design, wherein: the arithmetic output includes a complementary circuit and the complementary output of the exclusive OR operation circuit; Xy an output signal of the complementary output of the operational circuit to generate complementary and
Figure CN203675093UC00021
,所述互补异或运算输出电路产生互补的输出信号xΘy和 The complementary output of the exclusive OR operation circuit generates an output signal and the complementary xΘy
Figure CN203675093UC00022
,同时 ,Simultaneously
Figure CN203675093UC00023
信号作为所述互补异或运算输出电路的一个输入信号; 所述互补与运算输出电路包含:时钟动态控制电路,包括PMOS管m3和m7,nMOS管m6和m4 ;两个稳压箝位电路,包括pMOS管m2和普通反相器INVl,pMOS管m8和普通反相器INV2 ;输入控制电路,包括三输入浮栅nMOS管ml和普通nMOS管m5 ; 所述互补异或运算输出电路包含:时钟动态控制电路,包括PMOS管ml I和ml5,nMOS管ml2和ml4 ;两个稳压箝位电路,包括pMOS管mlO和普通反相器INV3,pMOS管ml6和普通反相器INV4 ;输入控制电路,包括四输入浮栅nMOS管m9和普通nMOS管ml3 ; 所述口pmoa管1113、1117、1112、1118、11111、11115、11110 和ml6 的源级接工作电压VDD,所述nMOS 管m4和ml2的源级接地; 所述时钟动态控制端,包括pMOS管m3和m7, nMOS管m6和m4及pMOS管mil和ml5,nMOS管ml2和ml4的栅极接时钟信号elk ;所述三输入nMOS管ml的三个输入分别接x、y、GND ;所述普通反相器I Signal as an input signal of the complementary output of the exclusive OR operation circuit; said complementary output of the operational circuit comprising: a clock dynamic control circuit comprises a PMOS transistor m3 and m7, nMOS tube m6 and M4; two regulator clamping, m2 and comprises a pMOS transistor of the inverter INVL general, and the pMOS transistor m8 ordinary inverter INV2; an input control circuit comprises a three-input floating gate of the nMOS transistor and the common nMOS transistor M5 ml; exclusive oR operation of the complementary output circuit comprising: a clock dynamic control circuitry, and comprises a PMOS transistor ml I ml5, nMOS tube ml2 and ML4; two zener clamp circuit comprises a pMOS transistor and an ordinary inverter mlO and INV3, and the pMOS transistor ml6 inverter INV4 is normal; input control circuit , including four-input floating gate of the nMOS transistor m9 and ML3 ordinary nMOS transistor; the source port connected to the operating voltage level VDD pmoa tube 1113,1117,1112,1118,11111,11115,11110 and ml6 of the nMOS transistor m4 and ml2 the source electrode is grounded; dynamic control of the clock terminal, and comprises a pMOS transistor M7 m3, m4, and m6 of the nMOS and pMOS transistor mil and ML5, and the gate of the nMOS ml2 to the clock signal elk ml4; said three-input nMOS transistor three inputs respectively connected ml x, y, GND; the normal inverter I NVl和INV2的输出分别接与运算输出信号x *y和 NVl and INV2 are connected to the output of the operational output signal and x * y
Figure CN203675093UC00024
所述四输入nMOS管m9的四个输入分别接x、y、 The four-input four inputs respectively connected to the nMOS transistor m9 x, y,
Figure CN203675093UC00025
with
Figure CN203675093UC00026
其中的权重是其余三个输入权重的2倍;所述普通反相器INV3和INV4的输出分别接异或运算输出信号Y ㊉ V和⑥.所述稳压箝位电路中pMOS管m2、m8、ml0、ml6的栅极分别接输出信号xy和 Wherein the weights are 2 times the weight of the remaining three input power; the common output of the inverter INV3 and INV4 are respectively connected to the output signal of the exclusive OR operation Y ㊉ V and the voltage regulator clamp circuit ⑥ pMOS transistor m2, m8. , ml0, a gate connected to the output signal are ml6 xy and
Figure CN203675093UC00027
、x㊉y和x㊉y;;。 , X㊉y and x㊉y ;;.
CN 201420010075 2014-01-07 2014-01-07 Dynamic exclusive-OR gate design based on floating gate technology CN203675093U (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10347283B2 (en) 2017-11-02 2019-07-09 Kandou Labs, S.A. Clock data recovery in multilane data receiver
US10355852B2 (en) 2016-08-31 2019-07-16 Kandou Labs, S.A. Lock detector for phase lock loop
WO2019148014A1 (en) * 2018-01-26 2019-08-01 Kandou Labs, S.A. Dynamically weighted exclusive or gate having weighted output segments for phase detection and phase interpolation
US10374787B2 (en) 2016-04-22 2019-08-06 Kandou Labs, S.A. High performance phase locked loop
US10411922B2 (en) 2016-09-16 2019-09-10 Kandou Labs, S.A. Data-driven phase detector element for phase locked loops

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10374787B2 (en) 2016-04-22 2019-08-06 Kandou Labs, S.A. High performance phase locked loop
US10355852B2 (en) 2016-08-31 2019-07-16 Kandou Labs, S.A. Lock detector for phase lock loop
US10411922B2 (en) 2016-09-16 2019-09-10 Kandou Labs, S.A. Data-driven phase detector element for phase locked loops
US10347283B2 (en) 2017-11-02 2019-07-09 Kandou Labs, S.A. Clock data recovery in multilane data receiver
WO2019148014A1 (en) * 2018-01-26 2019-08-01 Kandou Labs, S.A. Dynamically weighted exclusive or gate having weighted output segments for phase detection and phase interpolation

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