CN103279322B - The threshold logic type carry lookahead adder that SET/MOS hybrid circuit is formed - Google Patents

Abstract

The Coulomb blockade oscillation effect that the present invention utilizes single-electronic transistor and metal-oxide-semiconductor mixed structure to have and multiple-grid input characteristics, achieve the carry lookahead adder based on voting logic.Due to the logic function that voting logic is powerful, this circuit is only made up of 10 Threshold Logic Gate, and whole circuit only consumes 30 devices.With traditional pure CMOS carry lookahead adder Comparatively speaking, the circuit structure of this threshold logic type carry lookahead adder simplifies greatly, and number of tubes significantly reduces, and circuit power consumption declines further.This threshold logic type carry lookahead adder is expected to be applied in the field such as microprocessor, digital signal processor, is conducive to reducing circuit power consumption further, saving chip area, improves the integrated level of circuit.

Description

The threshold logic type carry lookahead adder that SET/MOS hybrid circuit is formed

Technical field

The present invention relates to microelectronics technology, particularly a kind of threshold logic type carry lookahead adder of SET/MOS hybrid circuit formation.

Background technology

Totalizer is the vitals of microprocessor, digital signal processor, is mainly positioned in its critical path, directly affects the speed of processor.Additive operation is the most basic most important computing, and all other computing (subtract, multiplication and division) finally all can be summed up as additive operation.In additive operation, there is carry, make drawing of certain result of calculation relevant with all positions lower than it.This is the arithmetic speed of totalizer with regard to extreme influence.In order to reduce the time that carry propagate consumes, improve computing velocity, polytype totalizer is arisen at the historic moment.

In recent years, along with the development of microelectric technique, processor, machine word length increase exponentially, and long totalizer becomes study hotspot gradually.The main target of long totalizer optimal design realizes high speed, low-power consumption and high integration, and its key adopts high speed, efficiently carry algorithm and structure.Carry look ahead, as the most basic high speed, efficiently bit method, is the basis of many carry algorithms.Therefore, carry lookahead adder has the advantages such as speed is fast, low in energy consumption, structural module, in the research of high speed, low-power consumption totalizer, occupy critical role.

At present, carry lookahead adder mainly designs based on traditional CMOS technology.But, along with CMOS technology enters nm regime, when the characteristic dimension of device is close to physics limit, utilize traditional reduction of device size inapplicable gradually to the method realizing low-power consumption and reduction area.Now, how to change circuit structure, adopt the nano electron device day by day risen to carry out circuit design, become the critical problem in carry lookahead adder research process.

Summary of the invention

The object of this invention is to provide the threshold logic type carry lookahead adder that a kind of SET/MOS hybrid circuit is formed, can circuit structure be simplified, reduce power consumption, improve the integrated level of circuit.

The present invention realizes in the following ways: the threshold logic type carry lookahead adder that a kind of SET/MOS hybrid circuit is formed, and it is characterized in that: by carry look ahead logic module, the first additive operation module and the second additive operation module composition;

Described first additive operation module comprises signal input part x ₀, y ₀, c ₀, output terminal s ₀, p ₀, g ₀, first and second two input SET/MOS hybrid circuit, the one or three input SET/MOS hybrid circuit and the one or four input SET/MOS hybrid circuit; Described first liang, second liang, the one or three, first and second input end of the one or four input SET/MOS hybrid circuit is connected respectively described signal input part x ₀, y ₀, the 3rd input end of described one or three input SET/MOS hybrid circuit is connected to described signal input part c ₀, the output terminal of described one or three input SET/MOS hybrid circuit is connected with described one or four four-input terminal inputting SET/MOS hybrid circuit; Input the output terminal corresponding and described output end p respectively of SET/MOS hybrid circuit for described first liang, second liang, the one or four ₀, g ₀, s ₀connect;

Described second additive operation module comprises signal input part x ₁, y ₁, c ₁, output terminal s ₁, p ₁, g ₁, third and fourth two input SET/MOS hybrid circuit, the two or three input SET/MOS hybrid circuit and the two or four input SET/MOS hybrid circuit; Described 3rd liang, the 4th liang, the two or three, first and second input end of the two or four input SET/MOS hybrid circuit is connected respectively described signal input part x ₁, y ₁, the 3rd input end of described two or three input SET/MOS hybrid circuit is connected to described signal input part c ₁, the output terminal of described two or three input SET/MOS hybrid circuit is connected with described two or four four-input terminal inputting SET/MOS hybrid circuit; Input the output terminal corresponding and described output end p respectively of SET/MOS hybrid circuit for described 3rd liang, the 4th liang, the two or four ₁, g ₁, s ₁connect;

Described carry look ahead logic module is made up of the three or three input SET/MOS hybrid circuit and five input SET/MOS hybrid circuits, and first, second and third input end of the 33, five input SET/MOS hybrid circuits is connected respectively described signal input part c ₀, output end p ₀, g ₀; Fourth, fifth input end of described five input SET/MOS hybrid circuits is connected respectively described output end p ₁, g ₁; The output terminal of described 33, five input SET/MOS hybrid circuits is connected respectively signal input part c ₁, c ₂.

In an embodiment of the present invention, the logic of described SET/MOS hybrid circuit meets logical equatiion:

$F\left(x\right)=\mathrm{sgn}\left(\underset{i=1}{\overset{n}{\Σ}}{W}_i{X}_i-\mathrm{\θ}\right)=\left\{\begin{array}{cc}1,& \begin{array}{cc}if& \underset{i=1}{\overset{n}{\Σ}}{W}_i{X}_i\≥\mathrm{\θ}\end{array}\\ 0,& otherwise\end{array}\right.$

Wherein W _ifor input X _icorresponding weight, n is the number of input, and θ is threshold value.

In an embodiment of the present invention, described threshold logic type carry lookahead adder energy topology arrives the carry lookahead adder of N position, the carry c of wherein kth position generation _k+1be expressed as:

c _k+1＝g _k+p _k·c _k

Wherein, g _kand p _kthe carry being respectively kth position produces function and propagator; If kth position produces carry, then a g _kbe 1, with input carry c _kirrelevant; If an input carry propagates through this position, then p _kbe 1; By launching c _kc can be eliminated _k+1to c _kdependence:

c _k+1＝g _k+p _k·(g _k-1+p _k-1·c _k-1)

Then c _kcomplete expansion is:

c _k+1＝g _k+p _k·(g _k-1+p _k-1·(...+p ₁·(g ₀+p ₀c ₀)...))。

In an embodiment of the present invention, described SET/MOS hybrid circuit comprises:

One PMOS, its source electrode meets power end V _dd;

One NMOS tube, its drain electrode is connected with the drain electrode of described PMOS; And

One SET pipe, is connected with the source electrode of described NMOS tube.

In an embodiment of the present invention, described PMOS meets parameter: W _pfor 22nm; L _pfor 66nm; V _pgfor 0.4V; Described NMOS meets parameter: W _nfor 22nm; L _nfor 66nm; V _ngfor 0.4V; The parameter that described SET pipe meets: C _s, C _dfor 0.1aF; R _s, R _dfor 150K Ω; C _ctrlfor 0.105aF; C _infor 0.105aF.

The voting logic function that the present invention utilizes SET/MOS mixed structure to realize, devises the carry lookahead adder of two.This circuit is only made up of 10 Threshold Logic Gate, consumes 10 PMOS altogether, 10 NMOS tube and 10 SET.Relative to traditional pure CMOS carry lookahead adder, the structure of this threshold logic type carry lookahead adder simplifies greatly, and power consumption obviously declines, and further reduces the area consumption of circuit.This threshold logic type carry lookahead adder is expected to be applied in the field such as microprocessor, digital signal processor, is conducive to reducing circuit power consumption, saving chip area, improves the integrated level of circuit.

Accompanying drawing explanation

Fig. 1 a is multiple-grid input SET/MOS hybrid circuit schematic diagram.

Fig. 1 b is SET/MOS hybrid circuit threshold logic unit schematic diagram.

Fig. 2 is carry lookahead adder schematic diagram.

Fig. 3 is additive operation module principle figure.

Fig. 4 is carry look ahead logic module schematic diagram.

Fig. 5 a is c ₂voting logic family curve.

Fig. 5 b is c ₂transient response curve.

Fig. 6 is the input-output characteristic curve of carry lookahead adder.

Embodiment

Below in conjunction with drawings and Examples, the present invention will be further described.

The method for designing that the threshold logic type carry lookahead adder that the SET/MOS hybrid circuit that the present invention proposes is formed adopts single-electronic transistor (Singleelectrontransistor, SET) to mix mutually with metal-oxide-semiconductor.Single-electronic transistor has obvious advantage relative to traditional microelectronic component in power consumption, operating rate etc., is the Typical Representative of nano electron device of new generation.Single-electronic transistor can be mutually compatible with CMOS silicon technology, SET/MOS hybrid circuit possesses the superior function of SET and metal-oxide-semiconductor, show extremely low power consumption, extra small device size, stronger driving force and larger output voltage swing, be expected to be widely used in MULTI-VALUED LOGIC CIRCUIT, D and D/A converter circuit, memory circuitry etc.

Refer to Fig. 2, the threshold logic type carry lookahead adder that the present embodiment provides a kind of SET/MOS hybrid circuit to form, it is characterized in that: by carry look ahead logic module, the first additive operation module and the second additive operation module composition;

Described first additive operation module comprises signal input part x ₀, y ₀, c ₀, output terminal s ₀, p ₀, g ₀, first and second two input SET/MOS hybrid circuit, the one or three input SET/MOS hybrid circuit and the one or four input SET/MOS hybrid circuit; Described first liang, second liang, the one or three, first and second input end of the one or four input SET/MOS hybrid circuit is connected respectively described signal input part x ₀, y ₀, the 3rd input end of described one or three input SET/MOS hybrid circuit is connected to described signal input part c ₀, the output terminal of described one or three input SET/MOS hybrid circuit is connected with described one or four four-input terminal inputting SET/MOS hybrid circuit; Input the output terminal corresponding and described output end p respectively of SET/MOS hybrid circuit for described first liang, second liang, the one or four ₀, g ₀, s ₀connect;

Described second additive operation module comprises signal input part x ₁, y ₁, c ₁, output terminal s ₁, p ₁, g ₁, third and fourth two input SET/MOS hybrid circuit, the two or three input SET/MOS hybrid circuit and the two or four input SET/MOS hybrid circuit; Described 3rd liang, the 4th liang, the two or three, first and second input end of the two or four input SET/MOS hybrid circuit is connected respectively described signal input part x ₁, y ₁, the 3rd input end of described two or three input SET/MOS hybrid circuit is connected to described signal input part c ₁, the output terminal of described two or three input SET/MOS hybrid circuit is connected with described two or four four-input terminal inputting SET/MOS hybrid circuit; Input the output terminal corresponding and described output end p respectively of SET/MOS hybrid circuit for described 3rd liang, the 4th liang, the two or four ₁, g ₁, s ₁connect;

Described carry look ahead logic module is made up of the three or three input SET/MOS hybrid circuit and five input SET/MOS hybrid circuits, and first, second and third input end of the 33, five input SET/MOS hybrid circuits is connected respectively described signal input part c ₀, output end p ₀, g ₀; Fourth, fifth input end of described five input SET/MOS hybrid circuits is connected respectively described output end p ₁, g ₁; The output terminal of described 33, five input SET/MOS hybrid circuits is connected respectively signal input part c ₁, c ₂.

In order to allow those skilled in the art better understand the present invention, below each several part circuit of the present invention is described further.Threshold logic type carry lookahead adder of the present invention make use of SET/MOS hybrid circuit and can not, based on the feature of Boolean logic, adopt voting logic to carry out the design of circuit.Because the function of voting logic is better than Boolean logic, based on the carry lookahead adder of voting logic, can circuit structure be simplified, reduce power consumption, improve the integrated level of circuit.The cardinal principle of voting logic goes out total input value according to the weight calculation of input, total input value and threshold value compared and draw output logic.If total input value is more than or equal to threshold value, then exporting is 1, otherwise is 0.The logical equatiion that voting logic will meet such as formula shown in (1), wherein W _ifor input X _icorresponding weight, n is the number of input, and θ is threshold value.Voting logic expression formula also can be expressed as such as formula the form shown in (2).First circuit design based on voting logic will determine the voting logic expression formula of circuit, and key determines the weight of each input and the threshold value of circuit in circuit.

$F\left(x\right)=\mathrm{sgn}\left(\underset{i=1}{\overset{n}{\Σ}}{W}_i{X}_i-\mathrm{\θ}\right)=\left\{\begin{array}{cc}1,& \begin{array}{cc}if& \underset{i=1}{\overset{n}{\Σ}}{W}_i{X}_i\≥\mathrm{\θ}\end{array}\\ 0,& otherwise\end{array}\right.---\left(1\right)$

F(x)＝(X ₁，X ₂，...，X _n)＝[W ₁，W ₂，...，W _n；θ](2)

The SET/MOS hybrid circuit structure of multiple-grid input as shown in Figure 1a.This circuit is by 1 PMOS, and 1 NMOS tube and 1 SET are in series.Input voltage is capacitively coupled on coulomb island, and the weight of input is embodied in its coupling capacitance.In circuit PMOS as constant current source for whole circuit provides bias current.The electric current normally worked due to SET is all very little, is generally the nA order of magnitude, so PMOS should be operated in sub-threshold region.The grid bias V of NMOS tube _ngbe fixing, its value is slightly larger than the threshold voltage V of NMOS tube _th, make the drain voltage of SET be fixed as V _ng-V _th.Grid voltage V ₁, V ₂..., V _nbe capacitively coupled on coulomb island.By arranging suitable circuit parameter, SET/MOS hybrid circuit can realize the function of Threshold Logic Gate, its form threshold logic unit as shown in Figure 1 b, wherein x ₁, x ₂..., x _nfor input end, w ₁, w ₂..., w _nfor input weight, θ is threshold value.In the design process of threshold logic type carry lookahead adder, should according to concrete circuit module, definite threshold logical expression.

Carry lookahead adder can eliminate the effect of cascaded carry, and therefore this totalizer is quicker in calculating process.For the carry lookahead adder of a N position, the carry c that its kth position produces _k+1can be expressed as:

c _k+1＝g _k+p _k·c _k(3)

Wherein, g _kand p _kthe carry being respectively kth position produces function and propagator.If kth position produces carry, then a g _kbe 1, with input carry c _kirrelevant; If an input carry propagates through this position, then p _kbe 1.By launching c _kc can be eliminated _k+1to c _kdependence:

c _k+1＝g _k+p _k·(g _k-1+p _k-1·c _k-1)(4)

C _kcomplete expansion is:

c _k+1＝g _k+p _k·(g _k-1+p _k-1·(...+p ₁·(g ₀+p ₀c ₀)...))(5)

The carry lookahead adder of a N position can be realized by formula (5).The output of each carry and " with " output of position all has nothing to do with position above, thus effectively eliminates cascaded carry effect.Therefore, time and the figure place of carry lookahead adder have nothing to do, and drastically increase the arithmetic speed of totalizer.

The schematic diagram of carry lookahead adder as shown in Figure 2.This structure is the carry lookahead adder of two, forms primarily of carry look ahead logic module and additive operation module (Bit1, Bit0).X ₀, y ₀, x ₁, y ₁, c ₀for input, s ₁, s ₀, c ₂for final output.The schematic diagram of additive operation module as shown in Figure 3.For i-th unit, this additive operation module is to input signal x _i, y _i, c _iprocess, produce s _i, p _i, g _i, its logic function expresses formula such as formula (6), and (7), shown in (8).By formula (6), (7), (8) are converted to voting logic expression formula respectively such as formula (9), (10), shown in (11), and wherein s _ivoting logic expression formula by t _iand x _i, y _i, c _icommon realization, t _icorresponding voting logic expression formula is such as formula shown in (12).

p _i＝x _i+y _i(6)

g _i＝x _i·y _i(7)

$s_i=x_i\⊕y_i\⊕c_i---\left(8\right)$

p _i＝(x _i，y _i)＝[1，1；0.5](9)

g _i＝(x _i，y _i)＝[1，1；1.5](10)

s _i＝(x _i，y _i，c _i，t _i)＝[1，1，1，2；2.5](11)

t _i＝(x _i，y _i，c _i)＝[1，1，1；1.5](12)

The schematic diagram of carry look ahead logic module as shown in Figure 4.Carry look ahead logic module is mainly used in producing the final carry c of circuit fast ₂, and do not require that all additive operation modules all to complete after calculating just output carry, thus decrease the transmission time of carry, improve the speed of totalizer.From formula (5), c ₁, c ₂realize logic function such as formula (13), shown in (14).

c ₁＝g ₀+p ₀·c ₀(13)

c ₂＝g ₁+p ₁·(g ₀+p ₀·c ₀)＝g ₁+p ₁·g ₀+p ₁·p ₀·c ₀(14)

C ₁, c ₂corresponding voting logic expression formula such as formula (15), shown in (16).

c ₁＝(c ₀，p ₀，g ₀)＝[1，1，2；1.5](15)

c ₂＝(c ₀，p ₀，g ₀，p ₁，g ₁)＝[1，1，2，3，5；4.5](16)

The present invention is to realize c ₂for example, introduce and utilize SET/MOS mixed structure to realize the method for designing of voting logic.C ₂there are five input ends, need the SET/MOS design of hybrid circuits of five inputs to realize.For the ease of analysis circuit characteristic, five input ends can be equivalent to one-input terminal.Be capacitively coupled to the identical principle of the charge number on coulomb island according to input end, have V ₁c ₁+ V ₂c ₂+ V ₃c ₃+ V ₄c ₄+ V ₅c ₅=V _inc _in, wherein V ₁, V ₂, V ₃, V ₄, V ₅be respectively 5 input end c ₀, p ₀, g ₀, p ₁, g ₁corresponding input voltage, C ₁, C ₂, C ₃, C ₄, C ₅be respectively the electric capacity that 5 input ends are coupled to coulomb island, V _inand C _inbe respectively the single ended input voltage after equivalence and coupling capacitance.Therefore V _in=(V ₁c ₁+ V ₂c ₂+ V ₃c ₃+ V ₄c ₄+ V ₅c ₅)/C _in.In SET/MOS mixed structure, the weight of input end is embodied by the coupling capacitance of input end.From formula (16), c ₀, p ₀, g ₀, p ₁, g ₁weight be respectively 1,1,2,3,5.Therefore, input capacitance should meet C ₁=C ₂=C _in/ 12, C ₃=C _in/ 6, C ₄=C _in/ 4, C ₅=5C _in/ 12 V _in=(V ₁+ V ₂+ 2V ₃+ 3V ₄+ 5V ₅)/12, formula can realize five inputs being equivalent to an input V thus _in.Therefore, the input-output characteristic curve of five input SET/MOS hybrid circuits just can be equivalent to the V of single input _in-V _outfamily curve.From formula (16), c ₂threshold value be 4.5, then the V of single ended input _in-V _outit is 4.5 that family curve meets threshold value.

Single ended input family curve after equivalence as shown in Figure 5 a, input voltage V _inbiasing range be 0V to 0.8V.

Then c ₂threshold value 4.5 correspond to input voltage and should be 0.3V (0.8V*4.5/12=0.3V).From Fig. 5 (a), there is saltus step in output voltage near 0.3V, meets the requirement of voting logic.Fig. 5 b is on the SET/MOS hybrid circuit basis of single ended input, designs the c obtained ₂transient response curve.Input signal is square wave, and the low and high level of input signal is respectively 0.8V and 0V, as can be seen from transient response curve, exports c ₂meet the requirement of formula (16), illustrate that the five SET/MOS hybrid circuits inputted can realize c ₂logic function.For other voting logic modules, in like manner realization can be designed.

The present invention, after sub-module has designed, emulates whole circuit in conjunction with each several part, mainly based on HSPICE, threshold logic type carry lookahead adder is carried out to the simulating, verifying of function.The model of SET be widely use at present, Compactmacromodel that precision is high.This model with the formal definition of electronic circuit in SPICE.The model of metal-oxide-semiconductor uses the forecasting techniques model (Predictivetechnologymodel) of the 22nm generally acknowledged at present.Supply voltage V in circuit _ddbe set to 0.80V, the breadth length ratio (W/L) of PMOS and NMOS tube is all set to 1/3, and main circuit simulation parameter is as shown in table 1.Wherein, c is produced ₁, c ₂, g ₀(g ₁), p ₀(p ₁), s ₀(s ₁), t ₀(t ₁) control end voltage V corresponding to SET/MOS pipe hybrid circuit _ctrlbe respectively 0.9V, 0.9V, 0.6V, 1V, 0.8V, 0.8V.

Table 1

The input-output curve of circuit as shown in Figure 6.Input signal x ₀, y ₀, x ₁, y ₁, c ₀consider all possibilities, the low and high level of input is respectively 0.8V and 0V.Wherein in order to increase c ₂output voltage swing, at c ₂end adds an impact damper.S ₁, s ₀, c ₂all with 0.05V and 0.75V for low level and high level.The Output rusults of Fig. 6 meets the function of two carry lookahead adders.Therefore, the structure that the present invention proposes can realize the carry lookahead adder of two.

The foregoing is only preferred embodiment of the present invention, all equalizations done according to the present patent application the scope of the claims change and modify, and all should belong to covering scope of the present invention.

Claims (3)

1. a threshold logic type carry lookahead adder for SET/MOS hybrid circuit formation, is characterized in that: by carry look ahead logic module, the first additive operation module and the second additive operation module composition;

Described first additive operation module comprises signal input part x ₀, y ₀, c ₀, output terminal s ₀, p ₀, g ₀, first and second two input SET/MOS hybrid circuit, the one or three input SET/MOS hybrid circuit and the one or four input SET/MOS hybrid circuit; Described first liang, second liang, the one or three, first and second input end of the one or four input SET/MOS hybrid circuit is connected respectively described signal input part x ₀, y ₀, the 3rd input end of described one or three input SET/MOS hybrid circuit is connected to described signal input part c ₀, the output terminal of described one or three input SET/MOS hybrid circuit is connected with described one or four four-input terminal inputting SET/MOS hybrid circuit; Input the output terminal corresponding and described output end p respectively of SET/MOS hybrid circuit for described first liang, second liang, the one or four ₀, g ₀, s ₀connect;

Described second additive operation module comprises signal input part x ₁, y ₁, c ₁, output terminal s ₁, p ₁, g ₁, third and fourth two input SET/MOS hybrid circuit, the two or three input SET/MOS hybrid circuit and the two or four input SET/MOS hybrid circuit; Described 3rd liang, the 4th liang, the two or three, first and second input end of the two or four input SET/MOS hybrid circuit is connected respectively described signal input part x ₁, y ₁, the 3rd input end of described two or three input SET/MOS hybrid circuit is connected to described signal input part c ₁, the output terminal of described two or three input SET/MOS hybrid circuit is connected with described two or four four-input terminal inputting SET/MOS hybrid circuit; Input the output terminal corresponding and described output end p respectively of SET/MOS hybrid circuit for described 3rd liang, the 4th liang, the two or four ₁, g ₁, s ₁connect;

Described carry look ahead logic module is made up of the three or three input SET/MOS hybrid circuit and five input SET/MOS hybrid circuits, and first, second and third input end of the 33, five input SET/MOS hybrid circuits is connected respectively described signal input part c ₀, output end p ₀, g ₀; Fourth, fifth input end of described five input SET/MOS hybrid circuits is connected respectively described output end p ₁, g ₁; The output terminal of described 33, five input SET/MOS hybrid circuits is connected respectively signal input part c ₁, c ₂;

Described SET/MOS hybrid circuit comprises: a PMOS, and its source electrode meets power end Vdd; One NMOS tube, its drain electrode is connected with the drain electrode of described PMOS; And one SET pipe, be connected with the source electrode of described NMOS tube;

The logic of described SET/MOS hybrid circuit meets logical equatiion:

Wherein W _ifor input X _icorresponding weight, n is the number of input, and θ is threshold value.

2. the threshold logic type carry lookahead adder of SET/MOS hybrid circuit formation according to claim 1, is characterized in that: described threshold logic type carry lookahead adder energy topology arrives the carry lookahead adder of N position, the carry c of wherein kth position generation _k+1be expressed as:

c _k+1＝g _k+p _k·c _k

Wherein, g _kand p _kthe carry being respectively kth position produces function and propagator; If kth position produces carry, then a g _kbe 1, with input carry c _kirrelevant; If an input carry propagates through this position, then p _kbe 1; By launching c _kc can be eliminated _k+1to c _kdependence:

c _k+1＝g _k+p _k·(g _k-1+p _k-1·c _k-1)

Then c _kcomplete expansion is:

c _k+1＝g _k+p _k·(g _k-1+p _k-1·(...+p ₁·(g ₀+p ₀c ₀)...))。

3. the threshold logic type carry lookahead adder of SET/MOS hybrid circuit formation according to claim 1, is characterized in that: levy and be: described PMOS meets parameter: W _pfor 22nm; L _pfor 66nm; V _pgfor 0.4V; Described NMOS meets parameter: W _nfor 22nm; L _nfor 66nm; V _ngfor 0.4V; The parameter that described SET pipe meets: C _s, C _dfor 0.1aF; R _s, R _dfor 150K Ω; C _ctrlfor 0.105aF; C _infor 0.105aF.