CN206237375U - Difference type Master-Slave JK Flip-Flop based on floating-gate MOS tube - Google Patents

Abstract

The utility model discloses a kind of difference type Master-Slave JK Flip-Flop based on floating-gate MOS tube, including the slave flipflop for being input into control structure, the master flip-flop of differential configuration and differential configuration.The beneficial effects of the utility model are：Circuit make use of easily controllable this natural quality of the threshold value that floating-gate MOS tube has, without increasing special circuit, it is only necessary to just can easily control the switch of circuit by increasing an input in N-shaped floating-gate MOS tube.The trigger of differential configuration is due to having the advantages that complementary output, low-power consumption, simple structure, and the nMOS logic circuits in traditional difference D-flip flop are instead of with N-shaped floating-gate MOS tube pulldown network, pulldown network structure is simplified, so as to further reduce the power consumption of circuit.

Description

Difference type Master-Slave JK Flip-Flop based on floating-gate MOS tube

Technical field

The utility model is related to difference type Master-Slave JK Flip-Flop, more particularly to a kind of difference type master based on floating-gate MOS tube From JK flip-flop.

Background technology

Trigger is basic component in digital integrated electronic circuit, and they are decide including power consumption, delay, area, reliability Deng the performance of circuit.In all of trigger, the trigger of differential configuration is due to complementary output, low-power consumption, simple The advantages of structure, therefore application is than wide.Differential flip-flops can play a part of amplifier, therefore they can be in low pendulum Worked well under width voltage signal.They can also set up various logic function to reduce sequencing expense in trigger.

Utility model content

For the problem that above-mentioned prior art is present, the utility model provides a kind of low in energy consumption based on floating-gate MOS tube Difference type Master-Slave JK Flip-Flop.

To achieve these goals, the technical solution adopted in the utility model is：Difference type principal and subordinate based on floating-gate MOS tube JK flip-flop, including it is input into the slave flipflop of control structure, the master flip-flop of differential configuration and differential configuration；

The input control structure is made up of basic gate circuit, and it is defeated that not gate I1 and door N1 and door N2 and OR gate A1 constitutes f1 Enter structure, not gate I2 and door N3 and door N4, OR gate A2 and not gate I3 constitute f2 input structures；The output of I1 is used as one of N2 Input, the output of N1 and N2 as A1 two inputs, A1 is output as f1；I2 is exported as an input of N3, N3 and N4 Output as two of A2 inputs, the output of A2 as I3 input, I3 is output as f2；

The master flip-flop by constitute the PMOS m3 of differential configuration, PMOS m4, three input N-shaped floating-gate MOS tube m1 and Three input N-shaped floating-gate MOS tube m2 are constituted；

The slave flipflop is by constituting the PMOS m7 of differential configuration, PMOS m8, three input N-shaped floating-gate MOS tube m5, three Input N-shaped floating-gate MOS tube m6, phase inverter INV1 and phase inverter INV2 are constituted；

PMOS m3, m4, m7, m8 source class meet operating voltage VDD, the three input N-shaped floating-gate MOS tubes m1, m2, The source class ground connection of m5, m6；

Two drain electrodes of PMOS m3 and m4 that differential configuration is constituted in the master flip-flop are input into N-shapeds with two three respectively The drain electrode connection of floating-gate MOS tube m1 and m2, and produce the output of master flip-flopAnd x；Difference is constituted in the slave flipflop Drain electrode of the drain electrode of two PMOSs m7 and m8 of structure respectively with two three input N-shaped floating-gate MOS tubes m5 and m6 is connected, and leads to Cross two phase inverters INV1 and INV2 be connected to output end Q and

The beneficial effects of the utility model are：Circuit make use of the threshold value that floating-gate MOS tube has it is easily controllable this from Right attribute, without increasing special circuit, it is only necessary to just can be convenient by increasing an input in N-shaped floating-gate MOS tube Control the switch of circuit.The trigger of differential configuration is transported due to having the advantages that complementary output, low-power consumption, simple structure The nMOS logic circuits in traditional difference D-flip flop are instead of with N-shaped floating-gate MOS tube pulldown network, pulldown network is simplified Structure, so as to further reduce the power consumption of circuit.

Brief description of the drawings

Fig. 1 is N-shaped and p-type multi input floating-gate MOS tube symbol and capacitor model；

Fig. 2 is the utility model circuit theory diagrams.

Specific embodiment

The utility model is described further with reference to embodiment.The explanation of following embodiments is only intended to help and manages Solution the utility model.It should be pointed out that for those skilled in the art, not departing from the utility model principle On the premise of, some improvement and modification can also be carried out to the utility model, these are improved and modification also falls into the utility model In scope of the claims.

Multi input floating-gate MOS tube be propose in recent years it is a kind of with feature it is strong, threshold value control is flexible the features such as it is new Type device, people have carried out further investigation in application of the multiple fields to it such as simulation, numeral and neutral nets.This device Processing technology it is completely compatible with the double level polysilicon CMOS technology of standard, its symbol is represented and its capacitor model such as Fig. 1 institutes Show.It has multiple input grid and a floating gates, and wherein floating boom is formed by ground floor polysilicon, and multiple input control gate is then Formed by second layer polysilicon.Coupled by electric capacity realization between input and floating boom.V in figure_FRepresent the voltage on floating boom, V₀ It is underlayer voltage, V₁、V₂、……、V_nIt is applied signal voltage.C₀It is the coupled capacitor between floating boom and substrate, it is mainly by grid Oxidation layer capacitance C_oxConstitute, C₁、C₂、……、C_nIt is the coupled capacitor between each input grid and floating boom.D and S difference table in figure Show drain electrode and source electrode.Net charge Q on floating boom_FIt is given by：

For n-channel floating-gate MOS tube, Substrate ground, therefore V₀=0.Assuming that the initial charge on floating boom is zero, according to electricity Lotus law of conservation, as available from the above equation:

If V_TIt is the threshold voltage of the pipe seen into by floating boom end, then works as V_F>V_TShi Guanzi is turned on.By formula (2) and (3) As can be seen that multi input floating-gate MOS tube can go control to each grid input signal weighted sum with the summed result being calculated The "ON" and "Off" of metal-oxide-semiconductor processed.The sum operation with coefficient for noticing all input signals that it is carried out on floating boom is using electricity Hold what coupling effect was carried out with voltage mode, have the low-power consumption more more excellent than current-mode summation technology special which show it Property.If with V₁Used as input, other inputs then have as control end：

So, by V₁The threshold voltage V of the pipe that end is seen into^* _t1Can be expressed as:

Above formula shows, without adjusting V_TIf, by changing the proportionate relationship between coupled capacitor or changing control end electricity Pressure V_iFloating-gate MOS tube can just be changed relative to input signal V₁Threshold voltage, so as to control the conducting and cut-off of metal-oxide-semiconductor.It is right In p-channel floating-gate MOS tube, substrate generally meets circuit maximum voltage sources (such as V_DD), therefore V in formula (1)₀=V_DD, formula (2)-(5) need Make corresponding amendment.

A kind of structure of difference type Master-Slave JK Flip-Flop circuit based on floating-gate MOS tube of the invention is as shown in Fig. 2 bag Include：The slave flipflop of input control structure, the master flip-flop of differential configuration and differential configuration.

It is described input control structure be made up of basic gate circuit, not gate I1, two with door N1 and N2, OR gate A1 composition f1 it is defeated Enter structure, not gate I2, two and door N3 and N4, OR gate A2, not gate I3 constitute f2 input structures；The master flip-flop is by constituting difference Two PMOSs m3 and m4 of separation structure, two three input N-shaped floating-gate MOS tube m1 and m2 are constituted；The slave flipflop is by constituting Two PMOSs m7 and m8 of differential configuration, two three input N-shaped floating-gate MOS tube m5 and m6, two phase inverters INV1 and INV2 Constitute.

PMOS m3, m4, m7, m8 source class meet operating voltage VDD, the three input N-shaped floating-gate MOS tubes m1, m2, The source class ground connection of m5, m6.

In the input control structure, the output of I1 as N2 an input, the output of N1 and N2 is used as two of A1 Input, A1 is output as f1；I2 is exported as one of N3 input, the output of N3 and N4 as A2 two inputs, A2's is defeated Go out as the input of I3, I3 is output as f2.

Two drain electrodes of PMOS m3 and m4 that differential configuration is constituted in the master flip-flop are input into N-shapeds with two three respectively The drain electrode connection of floating-gate MOS tube m1 and m2, and produce the output of master flip-flopAnd x；Difference knot is constituted in the slave flipflop Drain electrode of the drain electrode of two PMOSs m7 and m8 of structure respectively with two three input N-shaped floating-gate MOS tubes m5 and m6 is connected, and passes through Two phase inverters INV1 and INV2 be connected to output end Q and

Three input floating-gate MOS tube m1 employed in the design input (V1=f1,V3=GND) weight It is identical, i.e. C1=C2=C3=C；Three input floating-gate MOS tube m2 employed in the design input (V1=f2, V3=GND) weight is identical, i.e. C1=C2=C3=C；Input (the V1 of three input floating-gate MOS tube m5 employed in the design =x, V2=clk, V3=0) weight it is identical, i.e. C1=C2=C3=C；Three input floating-gate MOS tubes employed in the design M6 input (V2=clk, V3=0) weight it is identical, i.e. C1=C2=C3=C.

According to formula (4)：

For m1, only need

M1 is turned on,

I.e.

For m2, only need

M2 is turned on,

I.e.

For m5, only need

M5 is turned on,

I.e.

For m6, only need

M6 is turned on,

I.e.

In input control structure, outer input signal J and K and output feedback signal (the existing state of trigger) QⁿWithWith input f1 Relation with f2 is as follows：

From formula (10) and (11),

With outer input and the difference of the existing state of trigger, the state for being input into f1 and f2 is as follows：

The flip-flop operation state is as follows：

In clk low levels, according to formula (6) and (7), the V2=1 in m1 and m2, the master flip-flop receives input letter Number, when it is high level to be input into f1, f2 is low level, m1 conductings and m2 ends, master flip-flop output x andRespectively 1 and 0；When When input f1 is low level, f2 is high level, m2 conductings and m1 ends, master flip-flop output x andRespectively 0 and 1；Now root According to formula (8) and (9), m5 and m6 end, and slave flipflop is closed, output Q andKeep constant；In clk rising edges, according to public affairs Formula (6) and (7), the V2=0 in m1 and m2, master flip-flop close, slave flipflop open, the output x of master flip-flop andDetermine defeated Go out Q andWhen x be high level when, m5 conducting and m6 end, output Q andIt is 1 and 0；When x is low level, m6 is turned on and m5 Cut-off, output Q andIt is 0 and 1.

Arbitrary value is represented with φ.According to the course of work above, a kind of difference based on floating-gate MOS tube can be summed up The working condition of parting Master-Slave JK Flip-Flop circuit is as shown in the table：

Claims (1)

1. a kind of difference type Master-Slave JK Flip-Flop based on floating-gate MOS tube, it is characterised in that：Including input control structure, difference The master flip-flop of structure and the slave flipflop of differential configuration；

The input control structure is made up of basic gate circuit, and not gate I1 and door N1 and door N2 and OR gate A1 constitutes f1 input knots Structure, not gate I2 and door N3 and door N4, OR gate A2 and not gate I3 constitute f2 input structures；The output of I1 is defeated as one of N2 Enter, the output of N1 and N2 as A1 two inputs, A1 is output as f1；I2 is exported as an input of N3, N3's and N4 Export as two of A2 inputs, the output of A2 as I3 input, I3 is output as f2；

The master flip-flop is defeated by constituting the PMOS m3 of differential configuration, PMOS m4, three input N-shaped floating-gate MOS tube m1 and three Enter N-shaped floating-gate MOS tube m2 compositions；

The slave flipflop is by constituting the PMOS m7 of differential configuration, PMOS m8, three input N-shaped floating-gate MOS tube m5, three inputs N-shaped floating-gate MOS tube m6, phase inverter INV1 and phase inverter INV2 are constituted；

PMOS m3, m4, m7, m8 source class meet operating voltage VDD, described three input N-shaped floating-gate MOS tubes m1, m2, m5, m6 Source class ground connection；

Two drain electrodes of PMOS m3 and m4 that differential configuration is constituted in the master flip-flop are input into N-shaped floating booms with two three respectively The drain electrode connection of metal-oxide-semiconductor m1 and m2, and produce the output of master flip-flopAnd x；Differential configuration is constituted in the slave flipflop Two drain electrodes of PMOS m7 and m8 are connected with two three drain electrodes for being input into N-shaped floating-gate MOS tube m5 and m6 respectively, and by two Phase inverter INV1 and INV2 be connected to output end Q and