CN103716014B - A kind of difference type dual-edge trigger based on neuron mos pipe designs - Google Patents

Abstract

The invention discloses the design of a kind of difference type dual-edge trigger based on neuron mos pipe, comprise the slave flipflop of the master flip-flop 1 of differential configuration, master flip-flop 2 and a differential configuration; Described master flip-flop 1 is by the PMOS m3 and the PMOS m4 that form differential configuration, and three input N-shaped floating-gate MOS tube m1 and three input N-shaped floating-gate MOS tube m2 are formed; Described master flip-flop 2 is by the PMOS m7 and the PMOS m8 that form differential configuration, and three input N-shaped floating-gate MOS tube m5 and three input N-shaped floating-gate MOS tube m6 are formed; Described slave flipflop is by the PMOS m9 and the PMOS m10 that form differential configuration, three input N-shaped floating-gate MOS tube m11, three input N-shaped floating-gate MOS tube m12, three input N-shaped floating-gate MOS tube m13 and three input N-shaped floating-gate MOS tube m14, inverter INV1 and inverter INV2 is formed.The invention has the beneficial effects as follows: there is the advantages such as complementary output, low-power consumption, simple structure, simplify pulldown network structure, thus further reduce the power consumption of circuit.

Description

A kind of difference type dual-edge trigger based on neuron mos pipe designs

Technical field

The present invention relates to the design of a kind of difference type dual-edge trigger, more specifically, it relates to the design of a kind of difference type dual-edge trigger based on neuron mos pipe.

Background technology

Trigger is component basic in digital integrated circuit, and they decide the performance comprising the circuit such as power consumption, delay, area, reliability.In all triggers, the trigger of differential configuration is owing to having the advantages such as complementary output, low-power consumption, simple structure, and therefore Application comparison is extensive.Differential flip-flops can play the effect of amplifier, and therefore they well can work under low amplitude of oscillation voltage signal.They can also set up various logic function to reduce order-checking expense in trigger.

Dual-edge trigger can both sample input signal on clock signal rising edge edge and trailing edge edge, thus upgrades output state.Therefore, under the condition keeping legacy data process frequency, use dual-edge trigger can make the frequency halving of clock signal, thus decrease the dynamic power consumption of clock network.But the dual-edge trigger circuit structure of prior art is complicated, and power consumption is undesirable, and function is dumb.

Summary of the invention

The object of the invention is to overcome deficiency of the prior art, provide a kind of rational in infrastructure, low in energy consumption, control to design based on the difference type dual-edge trigger of neuron mos pipe flexibly.

This difference type dual-edge trigger based on neuron mos pipe designs, and comprises the slave flipflop of the master flip-flop 1 of differential configuration, master flip-flop 2 and a differential configuration; Described master flip-flop 1 is by the PMOS m3 and the PMOS m4 that form differential configuration, and three input N-shaped floating-gate MOS tube m1 and three input N-shaped floating-gate MOS tube m2 are formed; Described master flip-flop 2 is by the PMOS m7 and the PMOS m8 that form differential configuration, and three input N-shaped floating-gate MOS tube m5 and three input N-shaped floating-gate MOS tube m6 are formed; Described slave flipflop is by the PMOS m9 and the PMOS m10 that form differential configuration, three input N-shaped floating-gate MOS tube m11, three input N-shaped floating-gate MOS tube m12, three input N-shaped floating-gate MOS tube m13 and three input N-shaped floating-gate MOS tube m14, inverter INV1 and inverter INV2 is formed;

The source electrode of described PMOS m3, m4, m7, m8, m9 and m10 meets operating voltage VDD, the source electrode of described three input N-shaped floating-gate MOS tube m1, m2, m5, m6 and an input all ground connection, the source ground of described three input N-shaped floating-gate MOS tube m11, m12, m13, m14;

The drain electrode of two the PMOS m3 and m4 that form differential configuration in described master flip-flop 1 inputs N-shaped floating-gate MOS tube m1 and m2 respectively drain electrode with two three is connected, and produces the output of master flip-flop 1 and x1; The drain electrode of two the PMOS m7 and m8 that form differential configuration in described master flip-flop 2 inputs N-shaped floating-gate MOS tube m5 and m6 respectively drain electrode with two three is connected, and produces the output of master flip-flop 2 and x2;

The output x1 of described master flip-flop 1 and connect an input of three input N-shaped floating-gate MOS tube m11 and m14 in slave flipflop respectively, the output x2 of described master flip-flop 2 and connect an input of three input N-shaped floating-gate MOS tube m12 and m13 in slave flipflop respectively;

The drain electrode of two the PMOS m9 and m10 that form differential configuration in described slave flipflop inputs N-shaped floating-gate MOS tube m11 and m12 with two three respectively, the drain electrode of m13 and m14 is connected, and is connected to output by two inverter INV1 and INV2;

When clk rising edge, the output x1 of described master flip-flop 1 and be transferred to output by m11 and m14, the output x2 of described master flip-flop 2 and determine by input D; When clk trailing edge, the output x2 of described master flip-flop 2 and be transferred to output by m12 and m13, the output x1 of described master flip-flop 1 and determine by input D; Three input N-shaped floating-gate MOS tube m11 and m12 are provided with asynchronous set end S, and three input N-shaped floating-gate MOS tube m13 and m14 are provided with asynchronous resetting end R.

The invention has the beneficial effects as follows: circuit make use of the threshold value that neuron mos pipe has and is easy to control this natural quality, without the need to increasing special circuit, only needing just can the switch of control circuit easily by increasing an input in N-shaped floating-gate MOS tube.The trigger of differential configuration is owing to having the advantages such as complementary output, low-power consumption, simple structure, and use N-shaped floating-gate MOS tube pulldown network to instead of nMOS logical circuit in traditional difference type trigger, simplify pulldown network structure, thus further reduce the power consumption of circuit.And by the utilization of floating-gate MOS tube, the set end in trigger and reset terminal can realize very easily.Dual-edge trigger can both sample input signal on clock signal rising edge edge and trailing edge edge, improves the efficiency of clock signal, decreases the dynamic power consumption of clock network.Asynchronous set and adding of asynchronous resetting end make the function of trigger more flexible.

Accompanying drawing explanation

Fig. 1 is N-shaped and p-type multi input floating-gate MOS tube symbol and capacitor model;

Fig. 2 is circuit theory diagrams of the present invention;

Fig. 3 is the one encapsulation connecting circuit of the embodiment of the present invention;

Fig. 4 is the transient state functional simulation performance plot of circuit shown in Fig. 3 under 25MHz clock frequency, and abscissa is the time, and unit is ns, and ordinate is voltage, and unit is V.

Embodiment

Below in conjunction with drawings and Examples, the present invention is described further.Although the present invention will be described in conjunction with preferred embodiment, should know, and not represent and limit the invention in described embodiment.On the contrary, the present invention will contain can be included in attached claims limit scope of the present invention in alternative, modified model and equivalent.

Multi input floating-gate MOS tube is the new device that propose in recent years a kind of has that functional strong, threshold value controls the feature such as flexible, and people have carried out further investigation in the application of multiple field to it such as simulation, numeral and neural nets.The processing technology of this device and the double level polysilicon CMOS technology of standard completely compatible, its symbol represent and capacitor model as shown in Figure 1.It has multiple input grid and a floating boom pole, and wherein floating boom is formed by ground floor polysilicon, and multiple input control grid are then formed by second layer polysilicon.Realize being coupled by electric capacity between input with floating boom.V in Fig. 1 _frepresent the voltage on floating boom, V ₀for underlayer voltage, V ₁, V ₂..., V _nfor applied signal voltage.C ₀be the coupling capacitance between floating boom and substrate, it is primarily of gate oxide capacitance C _oxform, C ₁, C ₂..., C _nfor the coupling capacitance between each input grid and floating boom.In Fig. 1, D and S represents drain electrode and source electrode respectively.Net charge Q on floating boom _fprovided by following formula:

$Q_F=\underset{i=0}{\overset{n}{\Σ}}{C}_i(V_F-V_i)=V_F\underset{i=0}{\overset{n}{\Σ}}{C}_i-\underset{i=0}{\overset{n}{\Σ}}{C}_i{V}_i;---\left(1\right)$

For n raceway groove floating-gate MOS tube, Substrate ground, therefore V ₀=0.Suppose that the initial charge on floating boom is zero, according to law of conservation of charge, can be obtained fom the above equation:

$V_F=\underset{i=1}{\overset{n}{\Σ}}{w}_i{V}_i;---\left(2\right)$

$w_i=\frac{C_i}{C_0+\underset{j=1}{\overset{n}{\Σ}}{C}_j};---\left(3\right)$

If V _tfor the threshold voltage of pipe seen into by floating boom end, then work as V _f>V _tshi Guanzi conducting.As can be seen from formula (2) and (3), multi input floating-gate MOS tube to the weighted sum of each grid input signal, can go by the summed result calculated the "ON" and the "Off" that control metal-oxide-semiconductor.Notice that the sum operation with coefficient of all input signals that it carries out on floating boom utilizes capacitance coupling effect to carry out with voltage mode, which show it and there is the low power consumption characteristic more outstanding than current-mode summation technology.If with V ₁as input, other inputs as control end, then have:

$V_1>\frac{\underset{i=0}{\overset{n}{\Σ}}{C}_i}{C_1}{V}_T-\frac{C_2}{C_1}{V}_2-L-\frac{C_n}{C_1}{V}_n;---\left(4\right)$

Like this, by V ₁hold the threshold voltage V of the pipe seen into ^* _t1can be expressed as:

$V_{t1}^{*}=\frac{\underset{i=0}{\overset{n}{\Σ}}{C}_i}{C_1}{V}_T-\frac{C_2}{C_1}{V}_2-L-\frac{C_n}{C_1}{V}_n;---\left(5\right)$

Above formula shows, without the need to adjusting V _tif, by the proportionate relationship between change coupling capacitance or change control end voltage V _ijust can change floating-gate MOS tube relative to input signal V ₁threshold voltage, thus control the conducting of metal-oxide-semiconductor and cut-off.For p raceway groove floating-gate MOS tube, the usual connection circuit maximum voltage sources of substrate is (as V _dD), therefore V in formula (1) ₀=V _dD, corresponding correction need be done in formula (2)-(5).

The structure of a kind of difference type dual-edge trigger circuit based on neuron mos pipe of the present invention as shown in Figure 2, comprising: the master flip-flop circuit (1,2) of two differential configurations and the slave flipflop circuit of a differential configuration.

Described master flip-flop 1 by forming two PMOS m3 and m4 of differential configuration, two three input N-shaped floating-gate MOS tube m1 and m2 form; Described master flip-flop 2 by forming two PMOS m7 and m8 of differential configuration, two three input N-shaped floating-gate MOS tube m5 and m6 form; Described slave flipflop by forming two PMOS m9 and m10 of differential configuration, two three input N-shaped floating-gate MOS tube m11, m12, m13 and m14, two inverter INV1 and INV2 form.

The source electrode of described PMOS m3, m4, m7, m8, m9 and m10 meets operating voltage VDD, the source electrode of described three input N-shaped floating-gate MOS tube m1, m2, m5, m6 and an input all ground connection, the source ground of described three input N-shaped floating-gate MOS tube m11, m12, m13, m14.

The drain electrode of two the PMOS m3 and m4 that form differential configuration in described master flip-flop 1 inputs N-shaped floating-gate MOS tube m1 and m2 respectively drain electrode with two three is connected, and produces the output of master flip-flop 1 and x1; The drain electrode of two the PMOS m7 and m8 that form differential configuration in described master flip-flop 2 inputs N-shaped floating-gate MOS tube m5 and m6 respectively drain electrode with two three is connected, and produces the output of master flip-flop 2 and x2.

The output x1 of described master flip-flop 1 and connect an input of three input N-shaped floating-gate MOS tube m11 and m14 in slave flipflop respectively, the output x2 of described master flip-flop 2 and connect an input of three input N-shaped floating-gate MOS tube m12 and m13 in slave flipflop respectively.

The drain electrode of two the PMOS m9 and m10 that form differential configuration in described slave flipflop inputs N-shaped floating-gate MOS tube m11 and m12 with two three respectively, the drain electrode of m13 and m14 is connected, and is connected to output by two inverter INV1 and INV2.

When clk rising edge, the output x1 of described master flip-flop 1 and be transferred to output by m11 and m14, the output x2 of described master flip-flop 2 and determine by input D; When clk trailing edge, the output x2 of described master flip-flop 2 and be transferred to output by m12 and m13, the output x1 of described master flip-flop 1 and determine by input D.S and R realizes asynchronous set and the asynchronous resetting function of trigger respectively.

Input (V1, V2, V3) weight of the three input floating-gate MOS tubes adopted in the design is identical, i.e. C1=C2=C3.Only need according to formula (4) $\frac{V1*C1+V2*C2+V3*C3}{C1+C2+C3}\≥V_T=\frac{V_H}{2};$ Namely $\frac{V1+V2+V3}{3}\≥V_T=\frac{V_H}{2}.$ V _hi.e. high level.

Described m1 (V1=D, V2=clk, V3=0) and m2 ( v2=clk, V3=0), when clk is high level, because V2=V3=0, so m1 and m2 ends, and exports hold mode is in x1; When clk is low level, V2=V _h, V3=0, works as V1=V _htime, pipe conducting, as V1=0, pipe ends, the at this moment output of m1 and m2 determine by inputting D with x1; Therefore master flip-flop 1 is operated in clk low level state.

In like manner, master flip-flop 2 is operated in clk high level state to the course of work of M5 and m6.

Described m11 (V1=x1, V2=clk, V3=S) and m14 ( v2=clk, V3=R), when clear terminal and set end do not act on, i.e. S=R=0; When clk is low level, because V2=V3=0, so m11 and m14 ends, with x1 transmission less than output; When clk is high level, V2=V _h, V3=0, works as V1=V _htime, pipe conducting, as V1=0, pipe ends, with x1 determine current trigger output Q and therefore during clk rising edge master flip-flop 1 output x1 and determine the output of described a kind of difference type dual-edge trigger based on neuron mos pipe.

The course of work of m12 and m13 in like manner, during clk trailing edge master flip-flop 2 output x2 and determine the output of described a kind of difference type dual-edge trigger based on neuron mos pipe.

Adopt TSMC0.35 μm of double level polysilicon CMOS technology parameter, and the voltage VDD=1.5V of power taking source VDD, when clock frequency is 25MHz frequency, Fig. 4 gives and simulates through HSPICE the voltage transmission curve obtained.Analog result shows its correct functional characteristic, indicates a kind of practicality of the difference type dual-edge trigger circuit based on neuron mos pipe.

Claims (1)

1. the difference type dual-edge trigger based on neuron mos pipe designs, and it is characterized in that: the slave flipflop comprising the master flip-flop 1 of differential configuration, master flip-flop 2 and a differential configuration; Described master flip-flop 1 is by the PMOS m3 and the PMOS m4 that form differential configuration, and three input N-shaped floating-gate MOS tube m1 and three input N-shaped floating-gate MOS tube m2 are formed; Described master flip-flop 2 is by the PMOS m7 and the PMOS m8 that form differential configuration, and three input N-shaped floating-gate MOS tube m5 and three input N-shaped floating-gate MOS tube m6 are formed; Described slave flipflop is by the PMOS m9 and the PMOS m10 that form differential configuration, three input N-shaped floating-gate MOS tube m11, three input N-shaped floating-gate MOS tube m12, three input N-shaped floating-gate MOS tube m13 and three input N-shaped floating-gate MOS tube m14, inverter INV1 and inverter INV2 is formed;

The source electrode of described PMOS m3, m4, m7, m8, m9 and m10 meets operating voltage VDD, the source electrode of described three input N-shaped floating-gate MOS tube m1, m2, m5, m6 and an input all ground connection, the source ground of described three input N-shaped floating-gate MOS tube m11, m12, m13, m14;

The drain electrode of two the PMOS m3 and m4 that form differential configuration in described master flip-flop 1 inputs N-shaped floating-gate MOS tube m1 and m2 respectively drain electrode with two three is connected, and produces the output of master flip-flop 1 and x1; The drain electrode of two the PMOS m7 and m8 that form differential configuration in described master flip-flop 2 inputs N-shaped floating-gate MOS tube m5 and m6 respectively drain electrode with two three is connected, and produces the output of master flip-flop 2 and x2;

The output x1 of described master flip-flop 1 and connect an input of three input N-shaped floating-gate MOS tube m11 and m14 in slave flipflop respectively, the output x2 of described master flip-flop 2 and connect an input of three input N-shaped floating-gate MOS tube m12 and m13 in slave flipflop respectively;

The drain electrode of two the PMOS m9 and m10 that form differential configuration in described slave flipflop inputs N-shaped floating-gate MOS tube m11 and m12 with two three respectively, the drain electrode of m13 and m14 is connected, and is connected to output by two inverter INV1 and INV2;

When clk rising edge, the output x1 of described master flip-flop 1 and be transferred to output by three input N-shaped floating-gate MOS tube m11 and m14, the output x2 of described master flip-flop 2 and determine by input D; When clk trailing edge, the output x2 of described master flip-flop 2 and be transferred to output by m12 and m13, the output x1 of described master flip-flop 1 and determine by input D; Three input N-shaped floating-gate MOS tube m11 and m12 are provided with asynchronous set end S, and three input N-shaped floating-gate MOS tube m13 and m14 are provided with asynchronous resetting end R.