CN110798201B - High-speed voltage-resistant level conversion circuit - Google Patents
High-speed voltage-resistant level conversion circuit Download PDFInfo
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- CN110798201B CN110798201B CN201911197548.9A CN201911197548A CN110798201B CN 110798201 B CN110798201 B CN 110798201B CN 201911197548 A CN201911197548 A CN 201911197548A CN 110798201 B CN110798201 B CN 110798201B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention discloses a high-speed voltage-resistant level conversion circuit, which comprises a level conversion core circuit, an output inverter and the like. The invention adopts 6 MOS tubes such as NMOS tube M1, NMOS tube M2, NMOS tube M3, NMOS tube M4, PMOS tube M11, PMOS tube M12 and the like as input driving tubes, and adopts the technology that a latch is formed by cross coupling pair transistors PMOS tube M7 and PMOS tube M8 and the like to realize high-speed conversion performance, adopts a MOS tube stack structure to improve the voltage withstand performance of a circuit, and simultaneously, the source electrode of the PMOS tube M15 in the output inverter is connected with an external high power supply 2VDD and the source electrode of the NMOS tube M16 is connected with an external low power supply VDD, thereby realizing a high-speed voltage withstand level conversion circuit.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a high-speed voltage-resistant level conversion circuit.
Background
With the rapid development of microelectronic integrated circuit technology, system on Chip (SoC) functions are becoming more and more powerful, and analog integrated circuits and digital integrated circuits are integrated on the same Chip. Different functional modules in the SoC operate at non-operating supply voltages, so that data exchange between different voltage domains requires level shifting circuitry, and the performance of the level shifting circuitry can affect the performance characteristics of the SoC.
Fig. 1 is a conventional level shift circuit, in which the external power supply VDDH voltage is higher than the external power supply VDDL voltage, when the input voltage of the input terminal Vin is the external power supply VDDL voltage, the NMOS tube MN1 is turned on, the NMOS tube MN2 is turned off, the NMOS tube MN1 pulls the potential of the node a low, so that the PMOS tube MP2 is turned on and charges the node B to the external power supply VDDH voltage to turn off the PMOS tube MP1, thereby keeping the node a at a low potential, and meanwhile, the low potential voltage of the node a forms an inverter through the NMOS tube MN4 and the PMOS tube MP4 to enable the output terminal Vout to obtain the external power supply VDDH voltage. Similarly, when the input voltage of the input end Vin is at a low level, the NMOS transistor MN1 is turned off, the NMOS transistor MN2 is turned on, and the node B discharges through the NMOS transistor MN2, so that the PMOS transistor MP1 is turned on and charges the node a to the external power supply VDDH voltage, and the node a voltage forms an inverter through the NMOS transistor MN4 and the PMOS transistor MP4, so that the output end Vout of the circuit obtains a low level.
The conventional level conversion circuit has a simple structure and is easy to realize, but can only work in a specific range, the working power supply voltage must be in the withstand voltage range of a single transistor, and the conversion of a small logic level to a high level requires an NMOS (N-channel metal oxide semiconductor) transistor with a large channel width to length ratio to provide a large current for pulling down the potentials of the node A and the node B, which leads to the increase of propagation delay.
Disclosure of Invention
The present invention is directed to solving the above problems of the prior art. A high-speed withstand voltage level converting circuit is provided.
The technical scheme of the invention is as follows:
a high-speed withstand voltage level shift circuit, comprising: the device comprises a level conversion core circuit and an output inverter, wherein the signal output end of the level conversion core circuit is connected with the signal input end of the output inverter; the level conversion core circuit adopts 4 NMOS tubes and 2 PMOS tubes as input driving tubes, adopts cross-coupled PMOS tubes to form a latch, thereby realizing the high-speed conversion performance of the level conversion circuit, and adopts an MOS tube stack structure to improve the voltage resistance of the circuit; the source electrode of the PMOS tube M15 in the output inverter is connected with an external high power supply 2VDD, and the source electrode of the NMOS tube M16 in the output inverter is connected with an external low power supply VDD; the level shift core circuit mainly functions when the external input terminal Vin is the voltage V of the external low power supply VDD dd When the voltage of the node B is changed to V dd And to maintain the voltage of node B at V dd When the external input terminal Vin is low level 0, the voltage of the node B is quickly changed to the voltage 2V of the external high power supply 2VDD dd And the voltage of the node B is kept to be 2V dd The method comprises the steps of carrying out a first treatment on the surface of the The main function of the output inverter is that when the voltage of the node B is V dd When the voltage of the output terminal Vout is 2V dd When the voltage of the node B is 2V dd When the voltage of the output terminal Vout is V dd Thereby realizing that the voltage of the output end Vout is V when the voltage of the input end Vin is 0 dd The voltage at the input terminal Vin is V dd The voltage at the output terminal Vout is 2V dd Equal level conversion function。
Further, the level shift core circuit includes: NMOS tube M1, NMOS tube M2, NMOS tube M3, NMOS tube M4, PMOS tube M5, PMOS tube M6, PMOS tube M7, PMOS tube M8, NMOS tube M9, NMOS tube M10, PMOS tube M11, PMOS tube M12, PMOS tube M13 and NMOS tube M14, wherein the source of PMOS tube M7 is connected with the source of PMOS tube M8 and external high power supply 2VDD respectively, the grid of PMOS tube M7 is connected with the source of NMOS tube M10, the source of PMOS tube M6, the drain of PMOS tube M8, the grid of PMOS tube M15 and the grid of PMOS tube M16 respectively, the drain of PMOS tube M7 is connected with the source of NMOS tube M9, the grid of PMOS tube M8 and the source of PMOS tube M5 respectively, the grid of PMOS tube M5 is connected with the grid of PMOS tube M6, the source of PMOS tube M13 and external low power supply 2VDD respectively, the drain of PMOS tube M5 is connected with the drain of NMOS tube M3 respectively, the grid electrode of the NMOS tube M3 is respectively connected with the grid electrode of the PMOS tube M11, the grid electrode of the PMOS tube M13, the grid electrode of the NMOS tube M14, the grid electrode of the NMOS tube M2 and the external input end Vin, the source electrode of the NMOS tube M3 is connected with the grid electrode of the NMOS tube M1, the grid electrode of the NMOS tube M1 is respectively connected with the grid electrode of the PMOS tube M13, the grid electrode of the NMOS tube M14, the grid electrode of the PMOS tube M12 and the grid electrode of the NMOS tube M4, the source electrode of the NMOS tube M1 is respectively connected with the source electrode of the NMOS tube M14, the source electrode of the NMOS tube M2 and the external ground GND, the source electrode of the PMOS tube M11 is respectively connected with the source electrode of the PMOS tube M12 and the external low power supply VDD, the grid electrode of the NMOS tube M9 is respectively connected with the grid electrode of the NMOS tube M10 and the external high power supply 2, the drain electrode of the NMOS tube M12 is connected with the drain electrode of the NMOS tube M10, the drain electrode of the PMOS tube M6 is connected with the drain electrode of the NMOS tube M4, and the source electrode of the NMOS tube M4 is connected with the drain electrode of the NMOS tube M2.
Further, in the level conversion core circuit, 6 MOS tubes, namely, the NMOS tube M1, the NMOS tube M2, the NMOS tube M3, the NMOS tube M4, the PMOS tube M11 and the PMOS tube M12, are combined into an input driving tube, the PMOS tube M7 and the PMOS tube M8 are cross-coupled tubes, and meanwhile, the PMOS tube M7 and the PMOS tube M8 form a latch, so that the high-speed conversion performance of the level conversion circuit is realized; the PMOS tube M5 and the NMOS tube M3, the PMOS tube M6 and the NMOS tube M4, the PMOS tube M11 and the NMOS tube M9, the PMOS tube M12 and the NMOS tube M10 respectively form a stack structure, the grid electrode of the NMOS tube M9 and the grid electrode of the NMOS tube M10 are connected with an external high power supply 2VDD, whereinThe voltage of the external high power supply 2VDD is 2V dd The grid electrode M5 of the PMOS tube and the grid electrode of the PMOS tube M6 are both provided with an external low power supply VDD, wherein the voltage of the external low power supply VDD is V dd Ensure that each MOS tube works at V in different states dd To improve the withstand voltage characteristics of the level shifter circuit.
Further, the output inverter includes: the PMOS tube M15 and the NMOS tube M16, wherein the source electrode of the PMOS tube M15 is connected with the external high power supply 2VDD, the drain electrode of the PMOS tube M15 is respectively connected with the drain electrode of the NMOS tube M16 and the output end Vout, and the source electrode of the NMOS tube M16 is connected with the external low power supply VDD.
Further, the external input terminal Vin is an external low power supply VDD voltage V dd When the NMOS transistor M2 and the NMOS transistor M3 are turned on, the NMOS transistor M1, the NMOS transistor M4 and the PMOS transistor M11 are turned off, the cascade branch where the PMOS transistor M12 and the NMOS transistor M10 are located is turned on, and the voltage of the node B is changed into V rapidly dd The PMOS tube M6 is cut off, the voltage of the node B is 2V through the inverter formed by the PMOS tube M15 and the NMOS tube M16 and the voltage of the output end Vout dd Wherein 2V dd The voltage of the external high power supply 2VDD is reached, and the PMOS tube M7 is turned on, the voltage of the node A becomes 2V dd The PMOS tube M8 is cut off, and the pull-up capability of the PMOS tube M8 is reduced; similarly, when the input terminal Vin is at low level 0, the NMOS transistor M1 and the NMOS transistor M4 are turned on, the NMOS transistor M2, the NMOS transistor M3 and the PMOS transistor M12 are turned off, the cascade branch where the PMOS transistor M11 and the NMOS transistor M9 are located is turned on, and the voltage of the node A is changed into V rapidly dd The PMOS tube M8 is turned on, and the voltage of the node B becomes 2V dd The voltage of the node B is V through an inverter formed by a PMOS tube M15 and an NMOS tube M16 and then the voltage of the output end Vout dd Meanwhile, the voltage of the node B enables the PMOS tube M7 to be cut off, and the pull-up capability of the PMOS tube M7 is reduced.
The invention has the advantages and beneficial effects as follows:
the present invention provides a high-speed withstand voltage level converting circuit, comprising: the device comprises a level conversion core circuit and an output inverter, wherein the signal output end of the level conversion core circuit is connected with the signal input end of the output inverter; the level conversion core circuit adopts a technology that 6 MOS tubes such as an NMOS tube M1, an NMOS tube M2, an NMOS tube M3, an NMOS tube M4, a PMOS tube M11, a PMOS tube M12 and the like are used as input driving tubes to replace the traditional 2 NMOS tubes as input driving tubes, a PMOS tube M7 and a PMOS tube M8 are cross-coupled pairs, and meanwhile, the PMOS tube M7 and the PMOS tube M8 form a latch, so that the high-speed conversion performance of the level conversion circuit is realized; the level conversion core circuit also adopts a stack structure formed by a PMOS tube M5 and an NMOS tube M3, a PMOS tube M6 and an NMOS tube M4, a PMOS tube M11 and an NMOS tube M9, and a PMOS tube M12 and an NMOS tube M10 respectively, so that the voltage resistance of the level conversion circuit is improved; the source electrode of the MOS tube M15 in the output inverter is connected with an external high power supply 2VDD, and the source electrode of the NMOS tube M16 is connected with an external low power supply VDD, so that a high-speed voltage-resistant level conversion circuit is realized.
Drawings
FIG. 1 is a schematic diagram of a conventional level shifting circuit in accordance with a preferred embodiment of the present invention;
FIG. 2 is a schematic diagram of a high-speed voltage-tolerant level-shifting circuit according to a preferred embodiment of the present invention;
fig. 3 is a simulation diagram of the input-output relationship of a high-speed voltage-withstanding level conversion circuit according to a preferred embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and specifically described below with reference to the drawings in the embodiments of the present invention. The described embodiments are only a few embodiments of the present invention.
The technical scheme for solving the technical problems is as follows:
in the embodiment of the application, the level conversion core circuit adopts the technologies of using 4 NMOS tubes and 2 PMOS tubes as input driving tubes, forming latches by cross coupling pair tubes and the like to realize high-speed conversion performance, and adopts the MOS tube stack structure to improve the voltage withstand performance of the circuit, so that the level conversion circuit with high-speed voltage withstand is realized.
In order to better understand the above technical solutions, the following detailed description will refer to the accompanying drawings and specific embodiments.
Examples
A high-speed withstand voltage level switching circuit, as shown in fig. 2, includes a level switching core circuit 1, an output inverter 2;
wherein, the signal output end of the level conversion core circuit 1 is connected with the signal input end of the output inverter 2; the level conversion core circuit 1 adopts the technologies of using 4 NMOS tubes and 2 PMOS tubes as input driving tubes, forming latches by cross coupling tubes and the like to realize high-speed conversion performance, and adopts a MOS tube stack structure to improve the voltage withstand performance of the circuit, thereby realizing the high-speed voltage withstand level conversion circuit.
As a preferred embodiment, as shown in fig. 2, the level shift core circuit 1 includes: NMOS tube M1, NMOS tube M2, NMOS tube M3, NMOS tube M4, PMOS tube M5, PMOS tube M6, PMOS tube M7, PMOS tube M8, NMOS tube M9, NMOS tube M10, PMOS tube M11, PMOS tube M12, PMOS tube M13 and NMOS tube M14, wherein the source of PMOS tube M7 is connected with the source of PMOS tube M8 and external high power supply 2VDD respectively, the grid of PMOS tube M7 is connected with the source of NMOS tube M10, the source of PMOS tube M6, the drain of PMOS tube M8, the grid of PMOS tube M15 and the grid of PMOS tube M16 respectively, the drain of PMOS tube M7 is connected with the source of NMOS tube M9, the grid of PMOS tube M8 and the source of PMOS tube M5 respectively, the grid of PMOS tube M5 is connected with the grid of PMOS tube M6, the source of PMOS tube M13 and external low power supply 2VDD respectively, the drain of PMOS tube M5 is connected with the drain of NMOS tube M3 respectively, the grid electrode of the NMOS tube M3 is respectively connected with the grid electrode of the PMOS tube M11, the grid electrode of the PMOS tube M13, the grid electrode of the NMOS tube M14, the grid electrode of the NMOS tube M2 and the external input end Vin, the source electrode of the NMOS tube M3 is connected with the drain electrode of the NMOS tube M1, the grid electrode of the NMOS tube M1 is respectively connected with the drain electrode of the PMOS tube M13, the drain electrode of the NMOS tube M14, the grid electrode of the PMOS tube M12 and the grid electrode of the NMOS tube M4, the source electrode of the NMOS tube M1 is respectively connected with the source electrode of the NMOS tube M14, the source electrode of the NMOS tube M2 and the external ground GND, the source electrode of the PMOS tube M11 is respectively connected with the source electrode of the PMOS tube M12 and the external low power supply VDD, the grid electrode of the NMOS tube M9 is respectively connected with the grid electrode of the NMOS tube M10 and the external high power supply 2, the drain electrode of the NMOS tube M12 is connected with the drain electrode of the NMOS tube M10, the drain electrode of the PMOS tube M6 is connected with the drain electrode of the NMOS tube M4, and the source electrode of the NMOS tube M4 is connected with the drain electrode of the NMOS tube M2;
the output inverter 2 includes: the PMOS tube M15 and the NMOS tube M16, wherein the source electrode of the PMOS tube M15 is connected with the external high power supply 2VDD, the drain electrode of the PMOS tube M15 is respectively connected with the drain electrode of the NMOS tube M16 and the output end Vout, and the source electrode of the NMOS tube M16 is connected with the external low power supply VDD.
In the level conversion core circuit 1, 6 MOS tubes such as an NMOS tube M1, an NMOS tube M2, an NMOS tube M3, an NMOS tube M4, a PMOS tube M11, a PMOS tube M12 and the like form an input driving tube, and a PMOS tube M7 and a PMOS tube M8 are cross-coupled to each other and form a latch, so that the high-speed conversion performance of the level conversion circuit is realized; the PMOS tube M5 and the NMOS tube M3, the PMOS tube M6 and the NMOS tube M4, the PMOS tube M11 and the NMOS tube M9, the PMOS tube M12 and the NMOS tube M10 respectively form a stack structure, the grid electrode of the NMOS tube M9 and the grid electrode of the NMOS tube M10 are connected with an external high power supply 2VDD, wherein the voltage of the external high power supply 2VDD is 2V dd The grid electrode M5 of the PMOS tube and the grid electrode of the PMOS tube M6 are both provided with an external low power supply VDD, wherein the voltage of the external low power supply VDD is V dd Ensure that each MOS tube works at V in different states dd To improve the withstand voltage characteristics of the level shifter circuit.
The external input terminal Vin is the voltage V of the external low power supply VDD dd When the NMOS transistor M2 and the NMOS transistor M3 are turned on, the NMOS transistor M1, the NMOS transistor M4 and the PMOS transistor M11 are turned off, the cascade branch where the PMOS transistor M12 and the NMOS transistor M10 are located is turned on, and the voltage of the node B is changed into V rapidly dd The PMOS tube M6 is cut off, the voltage of the node B is 2V through the inverter formed by the PMOS tube M15 and the NMOS tube M16 and the voltage of the output end Vout dd At the same time, the PMOS tube M7 is turned on, and the voltage of the node A becomes 2V dd The PMOS tube M8 is cut off, and the pull-up capability of the PMOS tube M8 is reduced; similarly, when the input terminal Vin is at low level 0, the NMOS transistor M1 and the NMOS transistor M4 are turned on, the NMOS transistor M2, the NMOS transistor M3 and the PMOS transistor M12 are turned off, the cascade branch where the PMOS transistor M11 and the NMOS transistor M9 are located is turned on, and the voltage of the node A is changed into V rapidly dd The PMOS tube M8 is turned on, and the voltage of the node B becomes 2V dd The voltage of the node B is V through an inverter formed by a PMOS tube M15 and an NMOS tube M16 and then the voltage of the output end Vout dd Meanwhile, the voltage of the node B enables the PMOS tube M7 to be cut off, thereby reducingPull-up capability of PMOS transistor M7.
FIG. 3 is a diagram showing the simulation of the input-output relationship of the high-speed voltage-withstanding level conversion circuit of the present invention. Simulation results show that the high-speed voltage-withstanding level conversion circuit effectively realizes level conversion, improves conversion speed and improves voltage-withstanding characteristics.
In the above embodiments of the present application, a high-speed withstand voltage level conversion circuit includes a level conversion core circuit and an output inverter. According to the embodiment of the application, the technology of using 4 NMOS tubes and 2 PMOS tubes as input driving tubes, forming latches by cross coupling pairs and the like is adopted to achieve high-speed conversion performance, and the MOS tube stack structure is adopted to improve the voltage withstand performance of the circuit, so that the high-speed voltage withstand level conversion circuit is achieved.
The above examples should be understood as illustrative only and not limiting the scope of the invention. Various changes and modifications to the present invention may be made by one skilled in the art after reading the teachings herein, and such equivalent changes and modifications are intended to fall within the scope of the invention as defined in the appended claims.
Claims (4)
1. A high-speed withstand voltage level shift circuit, comprising: the device comprises a level conversion core circuit (1) and an output inverter (2), wherein the signal output end of the level conversion core circuit (1) is connected with the signal input end of the output inverter (2); the level conversion core circuit (1) adopts 4 NMOS tubes and 2 PMOS tubes as input driving tubes, and adopts cross-coupled PMOS tubes to form a latch, so that the high-speed conversion performance of the level conversion circuit is realized, and the level conversion core circuit (1) also adopts an MOS tube stack structure to improve the voltage withstand performance of the circuit; in the output inverter (2), a source electrode of the PMOS tube M15 is connected with an external high power supply 2VDD, and a source electrode of the NMOS tube M16 is connected with an external low power supply VDD;
the level shift core circuit (1) is used for providing a voltage V of an external low power supply VDD when an external input terminal Vin is dd When the voltage of the node B is changed to V dd And to maintain the voltage of node B at V dd When the external input terminal Vin is low level 0, makeThe voltage of the node B rapidly changes to the voltage 2V of the external high power supply 2VDD dd And the voltage of the node B is kept to be 2V dd The method comprises the steps of carrying out a first treatment on the surface of the The output inverter (2) is used for when the voltage of the node B is V dd When the voltage of the output terminal Vout is 2V dd When the voltage of the node B is 2V dd When the voltage of the output terminal Vout is V dd Thereby realizing that the voltage of the output end Vout is V when the voltage of the input end Vin is 0 dd The voltage at the input Vin is V dd The voltage at the output terminal Vout is 2V dd An equilevel conversion function;
the level shift core circuit (1) includes: NMOS tube M1, NMOS tube M2, NMOS tube M3, NMOS tube M4, PMOS tube M5, PMOS tube M6, PMOS tube M7, PMOS tube M8, NMOS tube M9, NMOS tube M10, PMOS tube M11, PMOS tube M12, PMOS tube M13 and NMOS tube M14, wherein the source of PMOS tube M7 is connected with the source of PMOS tube M8 and external high power supply 2VDD respectively, the grid of PMOS tube M7 is connected with the source of NMOS tube M10, the source of PMOS tube M6, the drain of PMOS tube M8, the grid of PMOS tube M15 and the grid of PMOS tube M16 respectively, the drain of PMOS tube M7 is connected with the source of NMOS tube M9, the grid of PMOS tube M8 and the source of PMOS tube M5 respectively, the grid of PMOS tube M5 is connected with the grid of PMOS tube M6, the source of PMOS tube M13 and external low power supply 2VDD respectively, the drain of PMOS tube M5 is connected with the drain of NMOS tube M3 respectively, the grid electrode of the NMOS tube M3 is respectively connected with the grid electrode of the PMOS tube M11, the grid electrode of the PMOS tube M13, the grid electrode of the NMOS tube M14, the grid electrode of the NMOS tube M2 and the external input end Vin, the source electrode of the NMOS tube M3 is connected with the grid electrode of the NMOS tube M1, the grid electrode of the NMOS tube M1 is respectively connected with the grid electrode of the PMOS tube M13, the grid electrode of the NMOS tube M14, the grid electrode of the PMOS tube M12 and the grid electrode of the NMOS tube M4, the source electrode of the NMOS tube M1 is respectively connected with the source electrode of the NMOS tube M14, the source electrode of the NMOS tube M2 and the external ground GND, the source electrode of the PMOS tube M11 is respectively connected with the source electrode of the PMOS tube M12 and the external low power supply VDD, the grid electrode of the NMOS tube M9 is respectively connected with the grid electrode of the NMOS tube M10 and the external high power supply 2, the drain electrode of the NMOS tube M12 is connected with the drain electrode of the NMOS tube M10, the drain electrode of the PMOS tube M6 is connected with the drain electrode of the NMOS tube M4, and the source electrode of the NMOS tube M4 is connected with the drain electrode of the NMOS tube M2.
2. The high-speed voltage-resistant level conversion circuit according to claim 1, wherein in the level conversion core circuit (1), 6 MOS tubes including an NMOS tube M1, an NMOS tube M2, an NMOS tube M3, an NMOS tube M4, a PMOS tube M11 and a PMOS tube M12 are combined into an input driving tube, a PMOS tube M7 and a PMOS tube M8 form a cross-coupled pair tube, and a PMOS tube M7 and a PMOS tube M8 form a latch, thereby realizing high-speed conversion performance of the level conversion circuit; the PMOS tube M5 and the NMOS tube M3, the PMOS tube M6 and the NMOS tube M4, the PMOS tube M11 and the NMOS tube M9, the PMOS tube M12 and the NMOS tube M10 respectively form a stack structure, the grid electrode of the NMOS tube M9 and the grid electrode of the NMOS tube M10 are connected with an external high power supply 2VDD, wherein the voltage of the external high power supply 2VDD is 2V dd The grid electrode M5 of the PMOS tube and the grid electrode of the PMOS tube M6 are both provided with an external low power supply VDD, wherein the voltage of the external low power supply VDD is V dd Ensure that each MOS tube works at V in different states dd To improve the withstand voltage characteristics of the level shifter circuit.
3. A high-speed withstand voltage level converting circuit according to one of claims 1-2, characterized in that the output inverter (2) comprises: the PMOS tube M15 and the NMOS tube M16, wherein the source electrode of the PMOS tube M15 is connected with the external high power supply 2VDD, the drain electrode of the PMOS tube M15 is respectively connected with the drain electrode of the NMOS tube M16 and the output end Vout, and the source electrode of the NMOS tube M16 is connected with the external low power supply VDD.
4. A high-speed voltage-withstanding level conversion circuit according to claim 3, wherein the external input terminal Vin is a voltage V of an external low power supply VDD dd When the NMOS transistor M2 and the NMOS transistor M3 are turned on, the NMOS transistor M1, the NMOS transistor M4 and the PMOS transistor M11 are turned off, the cascade branch where the PMOS transistor M12 and the NMOS transistor M10 are located is turned on, and the voltage of the node B is changed into V rapidly dd The PMOS tube M6 is cut off, the voltage of the node B is 2V through the inverter formed by the PMOS tube M15 and the NMOS tube M16 and the voltage of the output end Vout dd Wherein 2V dd The voltage of the external high power supply 2VDD is reached, and the PMOS tube M7 is turned on, the voltage of the node A becomes 2V dd So that the PMOS tube M8 is cut off and the PMOS tube is reducedPull-up capability of M8; similarly, when the input terminal Vin is at low level 0, the NMOS transistor M1 and the NMOS transistor M4 are turned on, the NMOS transistor M2, the NMOS transistor M3 and the PMOS transistor M12 are turned off, the cascade branch where the PMOS transistor M11 and the NMOS transistor M9 are located is turned on, and the voltage of the node A is changed into V rapidly dd The PMOS tube M8 is turned on, and the voltage of the node B becomes 2V dd The voltage of the node B is V through an inverter formed by a PMOS tube M15 and an NMOS tube M16 and then the voltage of the output end Vout dd Meanwhile, the voltage of the node B enables the PMOS tube M7 to be cut off, and the pull-up capability of the PMOS tube M7 is reduced.
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| US5241225A (en) * | 1990-12-26 | 1993-08-31 | Fujitsu Limited | Level conversion circuit having improved control and speed of switching from high to low level converter outputs |
| CN101562441A (en) * | 2008-10-08 | 2009-10-21 | 西安电子科技大学 | Ultrahigh-speed comparator with low offset |
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| CN104124957A (en) * | 2014-08-14 | 2014-10-29 | 灿芯半导体(上海)有限公司 | Level switching circuit |
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| CN101562441A (en) * | 2008-10-08 | 2009-10-21 | 西安电子科技大学 | Ultrahigh-speed comparator with low offset |
| CN102331807A (en) * | 2011-09-30 | 2012-01-25 | 电子科技大学 | Low-dropout (LDO) linear regulator of integrated slew rate enhancing circuit |
| CN104124957A (en) * | 2014-08-14 | 2014-10-29 | 灿芯半导体(上海)有限公司 | Level switching circuit |
| CN108847841A (en) * | 2018-07-04 | 2018-11-20 | 电子科技大学 | Level shifting circuit |
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